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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / wdk / timer_test.c
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6fa3eb70
S		 1#include <linux/init.h>
2#include <linux/module.h>
3#include <linux/kernel.h>
4#include <linux/rtpm_prio.h>
5#include <linux/version.h>
6#include <linux/kernel.h>
7#include <linux/sched.h>
8#include <linux/kthread.h>
9#include <linux/delay.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/proc_fs.h>
13#include <linux/string.h>
14#include <linux/uaccess.h>
15#include <linux/spinlock.h>
16#include <linux/rtpm_prio.h>
17#include <linux/rtc.h>
18#include <linux/cpu.h>
19#include <linux/hrtimer.h>
20
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/spinlock.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/proc_fs.h>
29#include <linux/syscore_ops.h>
30#include <asm/sched_clock.h>
31#include <linux/version.h>
32
33#include <mach/mt_reg_base.h>
34#include <mach/mt_gpt.h>
35#include <mach/mt_timer.h>
36#include <mach/irqs.h>
37#include <mach/mt_cpuxgpt.h>
38
39#ifdef CONFIG_LOCAL_WDT
40extern int nr_cpu_ids;
41#else
42#define nr_cpu_ids 1
43#endif
44
45
46//extern int nr_cpu_ids;
47//int enable_clock(int id, unsigned char *name);
48static int test_case = 0;
49
50static int ts_msleep = 0;
51static int msleep_times = 0;
52
53static int ts_mdelay = 0;
54static int mdelay_times = 0;
55
56static int ts_udelay = 0;
57static int udelay_times = 0;
58
59static long ts_hrtimer_sec = 0;
60static unsigned long ts_hrtimer_nsecs = 0;
61static int ts_hrtimer_times = 0;
62
63static struct hrtimer hrtimer_test;
64u64 hr_t1=0;
65u64 hr_t2=0;
66
67module_param(test_case, int, 00664);
68
69module_param(ts_msleep, int, 00664);
70module_param(msleep_times, int, 00664);
71
72module_param(ts_mdelay, int, 00664);
73module_param(mdelay_times, int, 00664);
74
75module_param(ts_udelay, int, 00664);
76module_param(udelay_times, int, 00664);
77
78module_param(ts_hrtimer_sec, int, 00664);
79module_param(ts_hrtimer_nsecs, int, 00664);
80module_param(ts_hrtimer_times, int, 00664);
81
82static DEFINE_SPINLOCK(wdt_test_lock0);
83static DEFINE_SPINLOCK(wdt_test_lock1);
84static struct task_struct *wk_tsk[2];// cpu: 2
85static int data;
86
87static int hrtimer_test_case();
88
89static int __cpuinit
90cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
91{
92 int hotcpu = (unsigned long)hcpu;
93
94 switch (action) {
95 case CPU_UP_PREPARE:
96 case CPU_UP_PREPARE_FROZEN:
97// watchdog_prepare_cpu(hotcpu);
98 break;
99 case CPU_ONLINE:
100 case CPU_ONLINE_FROZEN:
101//
102 if(hotcpu < nr_cpu_ids)
103 {
104 kthread_bind(wk_tsk[hotcpu], hotcpu);
105 wake_up_process(wk_tsk[hotcpu]);
106 printk("[WDK-test]cpu %d plug on ", hotcpu);
107 }
108 break;
109#ifdef CONFIG_HOTPLUG_CPU
110 case CPU_UP_CANCELED:
111 case CPU_UP_CANCELED_FROZEN:
112 case CPU_DEAD:
113 case CPU_DEAD_FROZEN:
114 printk("[WDK-test]:start Stop CPU:%d\n", hotcpu);
115
116 break;
117#endif /* CONFIG_HOTPLUG_CPU */
118 }
119
120 /*
121 * hardlockup and softlockup are not important enough
122 * to block cpu bring up. Just always succeed and
123 * rely on printk output to flag problems.
124 */
125 return NOTIFY_OK;
126}
127
128static struct notifier_block __cpuinitdata cpu_nfb = {
129 .notifier_call = cpu_callback
130};
131
132
133static int msleep_test(int length, int times)
134{
135
136 u64 t1=0;
137 u64 t2=0;
138 int i =0;
139 t1 = sched_clock();
140 for(i=0; i<times; i++)
141 {
142 msleep(length);
143 }
144 t2 = sched_clock();
145 printk("msleep_test, msleep(%d) test %d times\n", length,times);
146 printk("msleep_test: t1 =%lld, t2=%lld, delta=%lld\n", t1,t2, t2-t1);
147
148}
149
150static int udelay_test(int length, int times)
151{
152
153 u64 t1=0;
154 u64 t2=0;
155 int i =0;
156 t1 = sched_clock();
157 for(i=0; i<times; i++)
158 {
159 udelay(length);
160 }
161 t2 = sched_clock();
162 printk("udelay_test, udelay_test(%d) test %d times\n", length,times);
163
164 printk("udelay_test :t1 =%lld, t2=%lld, delta=%lld\n", t1,t2, t2-t1);
165
166}
167
168static int mdelay_test(int length, int times)
169{
170
171 u64 t1=0;
172 u64 t2=0;
173 int i =0;
174 t1 = sched_clock();
175 for(i=0; i<times; i++)
176 {
177 mdelay(length);
178 }
179 t2 = sched_clock();
180 printk("mdelay_test, mdelay_test(%d) test %d times\n", length,times);
181
182 printk("mdelay_test:t1 =%lld, t2=%lld, delta=%lld\n", t1,t2, t2-t1);
183
184}
185
186
187#define read_cntpct(cntpct_lo, cntpct_hi) \
188do { \
189 __asm__ __volatile__( \
190 "MRRC p15, 0, %0, %1, c14\n" \
191 :"=r"(cntpct_lo), "=r"(cntpct_hi) \
192 : \
193 :"memory"); \
194} while (0)
195static int phycical_count_test()
196{
197 unsigned int cntpct_lo1 = 0;
198 unsigned int cntpct_hi1 = 0;
199 unsigned int cntpct_lo2 = 0;
200 unsigned int cntpct_hi2 = 0;
201 printk("phycical_count_test start\n");
202 while(1)
203 {
204 read_cntpct(cntpct_lo1, cntpct_hi1);
205 read_cntpct(cntpct_lo2, cntpct_hi2);
206 if(cntpct_hi2 == cntpct_hi1)
207 {
208 if(cntpct_lo2 < cntpct_lo1)
209 {
210 if(0xffff == cntpct_lo1)
211 {
212 printk("fwq 0 by pass bug cntpct_hi1=%u,cntpct_lo1=%u, cntpct_hi2=%u,cntpct_lo2=%u \n",cntpct_hi1,cntpct_lo1,cntpct_hi2,cntpct_lo2 );
213 continue;
214 }
215 printk("fwq 1 cntpct_hi1=%d,cntpct_lo1=%d, cntpct_hi2=%d,cntpct_lo2=%d \n",cntpct_hi1,cntpct_lo1,cntpct_hi2,cntpct_lo2 );
216 //break;
217 }
218 }
219 if(cntpct_hi2 < cntpct_hi1)
220 {
221 printk("fwq 2 cntpct_hi1=%d,cntpct_lo1=%d, cntpct_hi2=%d,cntpct_lo2=%d \n",cntpct_hi1,cntpct_lo1,cntpct_hi2,cntpct_lo2 );
222 //break;
223 }
224 }
225 printk("phycical_count_test end\n");
226
227}
228#define GPT_IRQEN (APXGPT_BASE + 0x0000)
229#define GPT_IRQSTA (APXGPT_BASE + 0x0004)
230#define GPT_IRQACK (APXGPT_BASE + 0x0008)
231static int dump_gpt_reg(void)
232{
233 printk("IRQ STA %x \n", DRV_Reg32(GPT_IRQSTA));
234 printk("IRQ EN %x \n", DRV_Reg32(GPT_IRQEN));
235 printk("IRQ ACK %x \n", DRV_Reg32(GPT_IRQACK));
236 printk("GPT3 clk %x \n", DRV_Reg32(0xF0008034));
237 printk("GPT3 con %x \n", DRV_Reg32(0xF0008030));
238 printk("GPT3 count %x \n", DRV_Reg32(0xF0008038));
239 printk("GPT3 cmp %x \n", DRV_Reg32(0xF000803c));
240}
241
242static int dump_gpt1_reg(void)
243{
244 printk("IRQ STA %x \n", DRV_Reg32(GPT_IRQSTA));
245 printk("IRQ EN %x \n", DRV_Reg32(GPT_IRQEN));
246 printk("IRQ ACK %x \n", DRV_Reg32(GPT_IRQACK));
247 printk("GPT3 clk %x \n", DRV_Reg32(0xF0008014));
248 printk("GPT3 con %x \n", DRV_Reg32(0xF0008010));
249 printk("GPT3 count %x \n", DRV_Reg32(0xF0008018));
250 printk("GPT3 cmp %x \n", DRV_Reg32(0xF000801c));
251}
252
253
254u64 cpuxgpt_t1=0;
255u64 cpuxgpt_t2=0;
256int g_cpuxgpt0_called=0;
257int g_cpuxgpt1_called=0;
258int g_cpuxgpt2_called=0;
259static irqreturn_t cpuxgpt_test_irq_handler(int irq, void *dev_id)
260{
261 cpuxgpt_t2 = sched_clock();
262 g_cpuxgpt0_called=1;
263 printk("cpuxgpt irq:%d called \n", irq);
264 printk("cpuxgpt t2(%lld),t1(%lld),delta(%lld) \n",cpuxgpt_t2,cpuxgpt_t1,cpuxgpt_t2-cpuxgpt_t1);
265 return IRQ_HANDLED;
266}
267
268#if 1
269static irqreturn_t cpuxgpt1_test_irq_handler(int irq, void *dev_id)
270{
271 g_cpuxgpt1_called=1;
272 printk("cpuxgpt1 irq called \n");
273 return IRQ_HANDLED;
274}
275
276static irqreturn_t cpuxgpt2_test_irq_handler(int irq, void *dev_id)
277{
278 g_cpuxgpt2_called=1;
279 printk("cpuxgpt2 irq called \n");
280 return IRQ_HANDLED;
281}
282
283static irqreturn_t cpuxgpt3_test_irq_handler(int irq, void *dev_id)
284{
285 printk("cpuxgpt3 irq called \n");
286 return IRQ_HANDLED;
287}
288
289static irqreturn_t cpuxgpt4_test_irq_handler(int irq, void *dev_id)
290{
291 printk("cpuxgpt4 irq called \n");
292 return IRQ_HANDLED;
293}
294
295static irqreturn_t cpuxgpt5_test_irq_handler(int irq, void *dev_id)
296{
297 printk("cpuxgpt5 irq called \n");
298 return IRQ_HANDLED;
299}
300
301static irqreturn_t cpuxgpt6_test_irq_handler(int irq, void *dev_id)
302{
303 printk("cpuxgpt6 irq called \n");
304 return IRQ_HANDLED;
305}
306
307static irqreturn_t cpuxgpt7_test_irq_handler(int irq, void *dev_id)
308{
309 printk("cpuxgpt7 irq called \n");
310 return IRQ_HANDLED;
311}
312#endif
313
314void generic_timer_ppi_check(void)
315{
316 disable_cpuxgpt();
317 cpu_xgpt_set_init_count(0x80000000,0xffffff00);
318 enable_cpuxgpt();
319}
320
321static cpuxgpt_X_interrupt_test(int cpu)
322{
323 disable_cpuxgpt();
324 cpu_xgpt_set_init_count(0x80000000,0xffffff00);
325
326 //cpu_xgpt_register_timer(cpu,cpuxgpt_test_irq_handler);
327 cpu_xgpt_register_timer(1,cpuxgpt1_test_irq_handler);
328 cpu_xgpt_register_timer(2,cpuxgpt2_test_irq_handler);
329 cpu_xgpt_register_timer(3,cpuxgpt3_test_irq_handler);
330 cpu_xgpt_register_timer(4,cpuxgpt4_test_irq_handler);
331 cpu_xgpt_register_timer(5,cpuxgpt5_test_irq_handler);
332 cpu_xgpt_register_timer(6,cpuxgpt6_test_irq_handler);
333 cpu_xgpt_register_timer(7,cpuxgpt7_test_irq_handler);
334
335 //
336 cpu_xgpt_set_cmp_HL(cpu,0x80000001,0x00000100);
337 cpuxgpt_t1 = sched_clock();
338 enable_cpuxgpt();
339 /*wait for interrupt trigger, timeout:(0,0x80000001,0x00000100) - (0x80000000,0xffffff00)*/
340 msleep(20);
341}
342
343static cpuxgpt_interrupt_test(void)
344{
345 int i = 0;
346 //for(i = 0; i < 8; i++)
347 //{
348 cpuxgpt_X_interrupt_test(i);
349 //}
350 //test_case = 0;
351}
352
353static void cpuxgpt_frequency_test(void)
354{
355 //long long delta1 = 0;
356 //long long delta2 = 0;
357 //div1
358 #define TIMEOUT (13000000) // 1s = 13M
359 set_cpuxgpt_clk(CLK_DIV2);
360 disable_cpuxgpt();
361 cpu_xgpt_set_init_count(0x00000000,0x00000000);
362 //set_cpuxgpt_clk(CLK_DIV1);
363 cpu_xgpt_register_timer(0,cpuxgpt_test_irq_handler);
364 cpu_xgpt_set_cmp_HL(0,0x00000000,TIMEOUT);
365 cpuxgpt_t1 = sched_clock();
366 set_cpuxgpt_clk(CLK_DIV1);
367 enable_cpuxgpt();
368
369 while(0 == g_cpuxgpt0_called)
370 {
371 msleep(10);
372 printk("busy wait \n");
373 }
374 g_cpuxgpt0_called=0;
375 printk("cpuxgpt0-div1 t2(%lld),t1(%lld),delta(%lld) \n",cpuxgpt_t2,cpuxgpt_t1,cpuxgpt_t2-cpuxgpt_t1);
376
377#if 1
378 msleep(1000);
379 //div2
380 disable_cpuxgpt();
381 cpu_xgpt_set_init_count(0x00000000,0x00000000);
382 //set_cpuxgpt_clk(CLK_DIV2);
383 cpu_xgpt_set_cmp_HL(0,0x00000000,TIMEOUT);
384 cpuxgpt_t1 = sched_clock();
385 set_cpuxgpt_clk(CLK_DIV2);
386 enable_cpuxgpt();
387 while(0 == g_cpuxgpt0_called)
388 {
389 msleep(10);
390 printk("busy wait \n");
391 }
392 g_cpuxgpt0_called=0;
393 printk("cpuxgpt0-div2 t2(%lld),t1(%lld),delta(%lld) \n",cpuxgpt_t2,cpuxgpt_t1,cpuxgpt_t2-cpuxgpt_t1);
394
395 msleep(1000);
396 //div3
397 disable_cpuxgpt();
398 cpu_xgpt_set_init_count(0x00000000,0x00000000);
399 //set_cpuxgpt_clk(CLK_DIV4);
400 cpu_xgpt_set_cmp_HL(0,0x00000000,TIMEOUT);
401 cpuxgpt_t1 = sched_clock();
402 set_cpuxgpt_clk(CLK_DIV4);
403 enable_cpuxgpt();
404 while(0 == g_cpuxgpt0_called)
405 {
406 msleep(10);
407 printk("busy wait \n");
408 }
409 g_cpuxgpt0_called=0;
410 printk("cpuxgpt0-div4 t2(%lld),t1(%lld),delta(%lld) \n",cpuxgpt_t2,cpuxgpt_t1,cpuxgpt_t2-cpuxgpt_t1);
411#endif
412}
413
414void cpuxgpt_halt_on_debug_test(void)
415{
416 unsigned int cntpct_lo1 = 0;
417 unsigned int cntpct_hi1 = 0;
418
419 disable_cpuxgpt();
420 cpu_xgpt_set_init_count(0x00000000,0x00000000);
421 set_cpuxgpt_clk(CLK_DIV1);
422 enable_cpuxgpt();
423 cpu_xgpt_halt_on_debug_en(1);
424
425/*
426 read_cntpct(cntpct_lo1, cntpct_hi1);
427 localtimer_get_phy_count();
428 read_cntpct(cntpct_lo1, cntpct_hi1);
429 localtimer_get_phy_count();
430 printk("11111 ca7 counter(%u,%u) == %lld\n", cntpct_hi1,cntpct_lo1,localtimer_get_phy_count() );
431
432
433 read_cntpct(cntpct_lo1, cntpct_hi1);
434 printk("22222 ca7 counter(%u,%u) == %lld\n", cntpct_hi1,cntpct_lo1,localtimer_get_phy_count() );
435 read_cntpct(cntpct_lo1, cntpct_hi1);
436 printk("33333 ca7 counter(%u,%u) == %lld\n", cntpct_hi1,cntpct_lo1,localtimer_get_phy_count() );
437 read_cntpct(cntpct_lo1, cntpct_hi1);
438 printk("44444 ca7 counter(%u,%u) == %lld\n", cntpct_hi1,cntpct_lo1,localtimer_get_phy_count() );
439*/
440
441}
442
443static void cpuxgpt_test_case_help(void)
444{
445 printk("1:cpuxgpt_interrupt_test\n");
446 printk("2:cpuxgpt_frequency_test\n");
447 printk("3: cpuxgpt_halt_on_debug_test\n");
448
449}
450
451void cpuxgpt_run_case(int testcase)
452{
453 switch(testcase)
454 {
455 case 0:
456 cpuxgpt_test_case_help();
457 break;
458 case 1:
459 cpuxgpt_interrupt_test();
460 break;
461 case 2:
462 cpuxgpt_frequency_test();
463 break;
464 case 3:
465 cpuxgpt_halt_on_debug_test();
466 break;
467 case 4:
468 generic_timer_ppi_check();
469 break;
470 default:
471 printk("[%s] invalid testcase\n", __FUNCTION__);
472 }
473 test_case = 0;
474}
475
476static int idx =0;
477static int ktimer_thread_test(void *arg)
478{
479 struct sched_param param = { .sched_priority = RTPM_PRIO_WDT};
480 int cpu;
481 unsigned int flags;
482 int ret=0;
483 unsigned int cntpct_lo1 = 0;
484 unsigned int cntpct_hi1 = 0;
485 static unsigned int last_cntpct_lo1 = 0;
486 static unsigned int last_cntpct_hi1 = 0;
487 int i=0;
488
489 sched_setscheduler(current, SCHED_FIFO, &param);
490
491 set_current_state(TASK_INTERRUPTIBLE);
492
493
494
495
496 for(;;){
497
498 spin_lock(&wdt_test_lock0);
499 cpu = smp_processor_id();
500 spin_unlock(&wdt_test_lock0);
501 printk("timer test debug start, cpu:%d\n", cpu);
502 //phycical_count_test();
503 cpuxgpt_run_case(test_case);
504
505 if(ts_msleep != 0)
506 {
507 //printk("CPU:%d, msleep(%d) test\n", cpu,ts_msleep);
508 if(0 != msleep_times)
509 {
510 msleep_test(ts_msleep,msleep_times);
511 }
512 else
513 {
514 msleep_test(ts_msleep,1);
515 }
516
517 }
518
519 if(ts_mdelay != 0)
520 {
521 //printk("CPU:%d, mdelay(%d) test\n", cpu,ts_mdelay);
522 if(0 != mdelay_times)
523 {
524 mdelay_test(ts_mdelay,mdelay_times);
525 }
526 else
527 {
528 mdelay_test(ts_mdelay,1);
529 }
530
531 }
532
533 if(ts_udelay != 0)
534 {
535 //printk("CPU:%d, udelay(%d) test\n", cpu,ts_udelay);
536 if(0 != udelay_times)
537 {
538 udelay_test(ts_udelay,udelay_times);
539 }
540 else
541 {
542 udelay_test(ts_udelay,1);
543 }
544
545 }
546
547 if(ts_hrtimer_nsecs !=0 || ts_hrtimer_sec !=0)
548 {
549 hrtimer_test_case();
550 }
551
552 msleep(5*1000);//5s
553
554 read_cntpct(cntpct_lo1, cntpct_hi1);
555 printk("ca7 counter(%u,%u) == %lld\n", cntpct_hi1,cntpct_lo1,localtimer_get_phy_count() );
556
557 //printk("cpuxgpt(%d) set 100ms timer,idx=%d\n" ,idx%8,idx);
558 //cpu_xgpt_set_timer(idx%8,100000000);
559 //idx++;
560
561 printk("timer test debug end, cpu:%d\n", cpu);
562 #if 0
563 printk("fwq2 before set\n" );
564 dump_gpt_reg();
565 printk("set gpt3 5s oneshot\n" );
566
567 DRV_WriteReg32( 0xF0008000, 0x7);
568 DRV_WriteReg32( 0xF0008030, 0x0);
569
570 DRV_WriteReg32( 0xF0008038, 0x0);
571 DRV_WriteReg32( 0xF0008034, 0x0);
572 DRV_WriteReg32( 0xF000803c, 0x1c9c380);
573
574 DRV_WriteReg32( 0xF0008030, 0x3);
575
576 read_cntpct(cntpct_lo1, cntpct_hi1);
577 if(cntpct_hi1==last_cntpct_hi1 && cntpct_lo1==last_cntpct_lo1)
578 {
579 printk("fwq local count error !!! \n");
580 }
581 last_cntpct_hi1 = cntpct_hi1;
582 last_cntpct_lo1 = cntpct_lo1;
583 printk("ca7 counter(%u,%u), cpu:%d\n", cntpct_hi1,cntpct_lo1);
584 printk("timer test debug end, cpu:%d\n", cpu);
585 #endif
586 }
587 return 0;
588}
589
590static enum hrtimer_restart hrtimer_test_func(struct hrtimer *timer)
591{
592
593 hr_t2 = sched_clock();
594 printk("[hrtimer_test_func] t1=%lld,t2 =%lld \n",hr_t1, hr_t2);
595
596 printk("[hrtimer_test_func] delta=%lld, \n",hr_t2-hr_t1);
597 return HRTIMER_NORESTART;
598}
599
600static int hrtimer_test_case()
601{
602 int ret =0;
603 int value =0; //Unit ms
604 printk("hrtimer_test_case:ts_hrtimer_sec=%ld, ts_hrtimer_nsecs=%ld\n", ts_hrtimer_sec,ts_hrtimer_nsecs);
605 hr_t1 = sched_clock();
606 hrtimer_start(&hrtimer_test,
607 ktime_set(ts_hrtimer_sec, ts_hrtimer_nsecs),
608 HRTIMER_MODE_REL);
609
610}
611static int start_kicker(void)
612{
613
614 int i;
615 unsigned char name[15] = {0};
616
617 hrtimer_init(&hrtimer_test, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
618 hrtimer_test.function = hrtimer_test_func;
619
620 for(i = 0; i < 1; i++){
621 sprintf(name, "timer-test%d", i);
622 printk("[Timer]:thread name: %s\n", name);
623 wk_tsk[i] = kthread_create(ktimer_thread_test, &data, name);
624 if (IS_ERR(wk_tsk[i])) {
625 int ret = PTR_ERR(wk_tsk[i]);
626 wk_tsk[i] = NULL;
627 return ret;
628 }
629 kthread_bind(wk_tsk[i], i);
630 wake_up_process(wk_tsk[i]);
631}
632 return 0;
633}
634static int __init test_init(void)
635{
636 //enable_clock(12, "Vfifo");
637
638 //register_cpu_notifier(&cpu_nfb);
639 start_kicker();
640 return 0;
641}
642
643static void __init test_exit(void)
644{
645
646}
647#if 0
648int TimerUT_proc_init(void) {
649
650 struct proc_dir_entry *de = create_proc_entry(PROC_WK, 0660, 0);
651
652 printk("[WDK] Initialize proc\n");
653
654 de->read_proc = wk_proc_cmd_read;
655 de->write_proc = wk_proc_cmd_write;
656
657 return 0 ;
658}
659
660
661void TimerUT_proc_exit(void)
662{
663
664 remove_proc_entry(PROC_WK, NULL);
665
666}
667#endif
668module_init(test_init);
669module_exit(test_exit);
kernel source for telekom puls (alcatel/mediatek)