[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gyroscope / mpu3050c / mpu3050c.h

/* mpu3000.h
 *
 * (C) Copyright 2008 
 * MediaTek <www.mediatek.com>
 *
 * mpu300 head file for MT65xx
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef MPU3000_H
#define MPU3000_H
	 
#include <linux/ioctl.h>
	 
#define MPU3000_I2C_SLAVE_ADDR		0xD0
#define MPU3000_FIXED_DEVID			0xD0


/* MPU3000 Register Map  (Please refer to MPU3000 Specifications) */
#define MPU3000_REG_DEVID			         0x00
#define MPU3000_REG_OFS_XH			0x0C
#define MPU3000_REG_OFS_XL		         0x0D
#define MPU3000_REG_OFS_YH			0x0E
#define MPU3000_REG_OFS_YL			0x0F
#define MPU3000_REG_OFS_ZH			0x10
#define MPU3000_REG_OFS_ZL			0x11
#define MPU3000_REG_FIFO_EN			0x12
#define MPU3000_REG_AUX_VDD			0x13
#define MPU3000_REG_AUX_ID		         0x14
#define MPU3000_REG_SAMRT_DIV		0x15
#define MPU3000_REG_DATA_FMT			0x16   //set external sync, full-scale range and sample rate, low pass filter bandwidth
#define MPU3000_REG_INT_EN			0x17
#define MPU3000_REG_AUX_ADDR   		0x18
#define MPU3000_REG_INT_STA			0x1A

#define MPU3000_REG_TEMP_OUTH		0x1B
#define MPU3000_REG_TEMP_OUTL	         0x1C
#define MPU3000_REG_GYRO_XH			0x1D
#define MPU3000_REG_GYRO_XL			0x1E
#define MPU3000_REG_GYRO_YH			0x1F
#define MPU3000_REG_GYRO_YL			0x20
#define MPU3000_REG_GYRO_ZH			0x21
#define MPU3000_REG_GYRO_ZL			0x22
#define MPU3000_REG_AUX_XH			0x23
#define MPU3000_REG_AUX_XL			0x24
#define MPU3000_REG_AUX_YH			0x25
#define MPU3000_REG_AUX_YL			0x26
#define MPU3000_REG_AUX_ZH			0x27
#define MPU3000_REG_AUX_ZL			0x28
#define MPU3000_REG_FIFO_CNTH		0x3A
#define MPU3000_REG_FIFO_CNTL		0x3B
#define MPU3000_REG_FIFO_DATA		0x3C
#define MPU3000_REG_FIFO_CTL			0x3D
#define MPU3000_REG_PWR_CTL			0x3E

	 
/*MPU3000 Register Bit definitions*/ 
#define MPU3000_I2C_DIS					0x80	//disable I2C access mode
#define MPU3000_DEVID_MASK			0x7E	//I2C address mask of the device

#define MPU3000_FIFO_TEMP_EN			0x80	//insert the termperature data into FIFO
#define MPU3000_FIFO_GYROX_EN		0x40	//insert the X Gyro data into FIFO
#define MPU3000_FIFO_GYROY_EN		0x20	//insert the Y Gyro data into FIFO
#define MPU3000_FIFO_GYROZ_EN		0x10	//insert the Z Gyro data into FIFO
#define MPU3000_FIFO_AUXX_EN			0x08	//insert the X Accelerometer data into FIFO
#define MPU3000_FIFO_AUXY_EN			0x04	//insert the Y Accelerometer data into FIFO
#define MPU3000_FIFO_AUXZ_EN			0x02	//insert the Z Accelerometer data into FIFO
#define MPU3000_FIFO_FOOTER_EN		0x01	//insert the FIFO data into FIFO

#define MPU3000_AUX_VDDIO_EN			0x04	//enable VDD level for the secondary I2C bus clock and data lines
#define MPU3000_AUX_VDDIO_DIS			0x00	//disable VDD level for the secondary I2C bus clock and data lines
#define MPU3000_AUX_ID_MASK			0x7F	//AUX ID mask
#define MPU3000_AUX_CLKOUT_EN		0x80	//enable reference clock output at CLKOUT pin

#define MPU3000_EXT_SYNC				0x05	//captue the state of external frame sync input pin to insert into LSB of registers
#define MPU3000_SYNC_NONE 			0x00
#define MPU3000_SYNC_TEMP			0x01
#define MPU3000_SYNC_GYROX			0x02
#define MPU3000_SYNC_GYROY			0x03
#define MPU3000_SYNC_GYROZ			0x04
#define MPU3000_SYNC_AUXX			0x05
#define MPU3000_SYNC_AUXY			0x06
#define MPU3000_SYNC_AUXZ			0x07

#define MPU3000_FS_RANGE			0x03	//set the full-scale range of the gyro sensors
#define MPU3000_FS_250 				0x00
#define MPU3000_FS_500				0x01
#define MPU3000_FS_1000				0x02
#define MPU3000_FS_2000				0x03
#define MPU3000_FS_MAX				0x03

#define MPU3000_FS_250_LSB			131		// LSB/(o/s)
#define MPU3000_FS_500_LSB			66
#define MPU3000_FS_1000_LSB			33
#define MPU3000_FS_2000_LSB			16
#define MPU3000_FS_MAX_LSB			131


#define MPU3000_SAM_RATE_MASK		0x07	//set sample rate and low padd filter configuration
#define MPU3000_RATE_8K_LPFB_256HZ 	0x00
#define MPU3000_RATE_1K_LPFB_188HZ	0x01
#define MPU3000_RATE_1K_LPFB_98HZ 	0x02
#define MPU3000_RATE_1K_LPFB_42HZ 	0x03
#define MPU3000_RATE_1K_LPFB_20HZ 	0x04
#define MPU3000_RATE_1K_LPFB_10HZ 	0x05
#define MPU3000_RATE_1K_LPFB_5HZ 	0x06


#define MPU3000_INT_ACTL				0x80	//logic level for INT out pin(low level)
#define MPU3000_INT_OPEN				0x40	//drvier type for INT out pin(open drain)
#define MPU3000_INT_LATCH_EN			0x20	//latch mode(latch until clear INT)
#define MPU3000_INT_CLR_BYRD			0x10	//clear INT by reading any register
#define MPU3000_MPU_RDY_EN			0x04	//enable INT when device is ready
#define MPU3000_DMP_DONE_EN			0x02	//enable INT when DMP is done
#define MPU3000_RAW_RDY_EN			0x01	//enable INT when data is available

#define MPU3000_INTS_MPU_RDY			0x04	//PLL is ready
#define MPU3000_INTS_DMP_DONE		0x02	//digital motion processor(DMP) is done
#define MPU3000_INTS_RAW_RDY			0x01	//raw data or FIFO data is ready

#define MPU3000_FIFO_CNT_H			0x03	//high bits of FIFO data 	number
#define MPU3000_FIFO_CNT_L				0xFF	//low bits of FIFO data number
#define MPU3000_FIFOSIZE				512

#define MPU3000_FIFO_EN				0x40	//enable FIFO operation for sensor data
#define MPU3000_AUX_IF_EN				0x20	//enable AUX interface via I2C
#define MPU3000_AUX_IF_RST			0x08	//reset AUX interface function
#define MPU3000_FIFO_RST				0x02	//reset FIFO function
#define MPU3000_GYRO_RST				0x01	//reset gyro analog and digital functions

#define MPU3000_H_SET					0x80	//reset device and internal registers to default settings
#define MPU3000_SLEEP					0x40	//enable low power sleep mode
#define MPU3000_STBY_XG				0x20	//put gyro Z in standby mode
#define MPU3000_STBY_YG				0x10	//put gyro Z in standby mode
#define MPU3000_STBY_ZG				0x08	//put gyro Z in standby mode

#define MPU3000_CLK_SEL_MASK			0x07	//select device clock device
#define MPU3000_CLK_INTER_OSC		0x00
#define MPU3000_CLK_PLL_GYROX		0x01
#define MPU3000_CLK_PLL_GYROY		0x02
#define MPU3000_CLK_PLL_GYROZ		0x03
#define MPU3000_CLK_PLL_32K			0x04
#define MPU3000_CLK_PLL_19M			0x05
#define MPU3000_CLK_PLL_RESV			0x06
#define MPU3000_CLK_STOP_MASK		0x07

	 
#define MPU3000_SUCCESS				    0
#define MPU3000_ERR_I2C				  -1
#define MPU3000_ERR_STATUS			  -3
#define MPU3000_ERR_SETUP_FAILURE	  -4
#define MPU3000_ERR_GETGSENSORDATA  -5
#define MPU3000_ERR_IDENTIFICATION	  -6
	 

/*
typedef enum  {
    MPU3000_SYNC_NONE = 0x0,
    MPU3000_SYNC_TEMP,
    MPU3000_SYNC_GYROX,
    MPU3000_SYNC_GYROY,
    MPU3000_SYNC_GYROZ,
    MPU3000_SYNC_AUXX,
    MPU3000_SYNC_AUXY,
    MPU3000_SYNC_AUXZ,
} MPU3000_EXT_SYNC_SEL;

typedef enum  {
    MPU3000_FS_250 = 0x0,
    MPU3000_FS_500,
    MPU3000_FS_1000,
    MPU3000_FS_2000,
    MPU3000_FS_MAX = 0x3,
} MPU3000_FS_SEL;

typedef enum  {
    MPU3000_RATE_8K_LPFB_256HZ = 0x0,
    MPU3000_RATE_1K_LPFB_188HZ,
    MPU3000_RATE_1K_LPFB_98HZ,
    MPU3000_RATE_1K_LPFB_42HZ,
    MPU3000_RATE_1K_LPFB_20HZ,
    MPU3000_RATE_1K_LPFB_10HZ,
    MPU3000_RATE_1K_LPFB_5HZ,
} MPU3000_SAMRATE_SEL;
*/

#define MPU3000_BUFSIZE 60

// 1 rad = 180/PI degree, MAX_LSB = 131,
// 180*131/PI = 7506
#define DEGREE_TO_RAD	7506
	 
#endif //MPU3000_H
Commit	Line	Data
6fa3eb70 S	1	/* mpu3000.h
	2	*
	3	* (C) Copyright 2008
	4	* MediaTek <www.mediatek.com>
	5	*
	6	* mpu300 head file for MT65xx
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22	#ifndef MPU3000_H
	23	#define MPU3000_H
	24
	25	#include <linux/ioctl.h>
	26
	27	#define MPU3000_I2C_SLAVE_ADDR 0xD0
	28	#define MPU3000_FIXED_DEVID 0xD0
	29
	30
	31	/* MPU3000 Register Map (Please refer to MPU3000 Specifications) */
	32	#define MPU3000_REG_DEVID 0x00
	33	#define MPU3000_REG_OFS_XH 0x0C
	34	#define MPU3000_REG_OFS_XL 0x0D
	35	#define MPU3000_REG_OFS_YH 0x0E
	36	#define MPU3000_REG_OFS_YL 0x0F
	37	#define MPU3000_REG_OFS_ZH 0x10
	38	#define MPU3000_REG_OFS_ZL 0x11
	39	#define MPU3000_REG_FIFO_EN 0x12
	40	#define MPU3000_REG_AUX_VDD 0x13
	41	#define MPU3000_REG_AUX_ID 0x14
	42	#define MPU3000_REG_SAMRT_DIV 0x15
	43	#define MPU3000_REG_DATA_FMT 0x16 //set external sync, full-scale range and sample rate, low pass filter bandwidth
	44	#define MPU3000_REG_INT_EN 0x17
	45	#define MPU3000_REG_AUX_ADDR 0x18
	46	#define MPU3000_REG_INT_STA 0x1A
	47
	48	#define MPU3000_REG_TEMP_OUTH 0x1B
	49	#define MPU3000_REG_TEMP_OUTL 0x1C
	50	#define MPU3000_REG_GYRO_XH 0x1D
	51	#define MPU3000_REG_GYRO_XL 0x1E
	52	#define MPU3000_REG_GYRO_YH 0x1F
	53	#define MPU3000_REG_GYRO_YL 0x20
	54	#define MPU3000_REG_GYRO_ZH 0x21
	55	#define MPU3000_REG_GYRO_ZL 0x22
	56	#define MPU3000_REG_AUX_XH 0x23
	57	#define MPU3000_REG_AUX_XL 0x24
	58	#define MPU3000_REG_AUX_YH 0x25
	59	#define MPU3000_REG_AUX_YL 0x26
	60	#define MPU3000_REG_AUX_ZH 0x27
	61	#define MPU3000_REG_AUX_ZL 0x28
	62	#define MPU3000_REG_FIFO_CNTH 0x3A
	63	#define MPU3000_REG_FIFO_CNTL 0x3B
	64	#define MPU3000_REG_FIFO_DATA 0x3C
65	#define MPU3000_REG_FIFO_CTL 0x3D
66	#define MPU3000_REG_PWR_CTL 0x3E
67
68
69
70	/MPU3000 Register Bit definitions/
71	#define MPU3000_I2C_DIS 0x80 //disable I2C access mode
72	#define MPU3000_DEVID_MASK 0x7E //I2C address mask of the device
73
74	#define MPU3000_FIFO_TEMP_EN 0x80 //insert the termperature data into FIFO
75	#define MPU3000_FIFO_GYROX_EN 0x40 //insert the X Gyro data into FIFO
76	#define MPU3000_FIFO_GYROY_EN 0x20 //insert the Y Gyro data into FIFO
77	#define MPU3000_FIFO_GYROZ_EN 0x10 //insert the Z Gyro data into FIFO
78	#define MPU3000_FIFO_AUXX_EN 0x08 //insert the X Accelerometer data into FIFO
79	#define MPU3000_FIFO_AUXY_EN 0x04 //insert the Y Accelerometer data into FIFO
80	#define MPU3000_FIFO_AUXZ_EN 0x02 //insert the Z Accelerometer data into FIFO
81	#define MPU3000_FIFO_FOOTER_EN 0x01 //insert the FIFO data into FIFO
82
83	#define MPU3000_AUX_VDDIO_EN 0x04 //enable VDD level for the secondary I2C bus clock and data lines
84	#define MPU3000_AUX_VDDIO_DIS 0x00 //disable VDD level for the secondary I2C bus clock and data lines
85	#define MPU3000_AUX_ID_MASK 0x7F //AUX ID mask
86	#define MPU3000_AUX_CLKOUT_EN 0x80 //enable reference clock output at CLKOUT pin
87
88	#define MPU3000_EXT_SYNC 0x05 //captue the state of external frame sync input pin to insert into LSB of registers
89	#define MPU3000_SYNC_NONE 0x00
90	#define MPU3000_SYNC_TEMP 0x01
91	#define MPU3000_SYNC_GYROX 0x02
92	#define MPU3000_SYNC_GYROY 0x03
93	#define MPU3000_SYNC_GYROZ 0x04
94	#define MPU3000_SYNC_AUXX 0x05
95	#define MPU3000_SYNC_AUXY 0x06
96	#define MPU3000_SYNC_AUXZ 0x07
97
98	#define MPU3000_FS_RANGE 0x03 //set the full-scale range of the gyro sensors
99	#define MPU3000_FS_250 0x00
100	#define MPU3000_FS_500 0x01
101	#define MPU3000_FS_1000 0x02
102	#define MPU3000_FS_2000 0x03
103	#define MPU3000_FS_MAX 0x03
104
105	#define MPU3000_FS_250_LSB 131 // LSB/(o/s)
106	#define MPU3000_FS_500_LSB 66
107	#define MPU3000_FS_1000_LSB 33
108	#define MPU3000_FS_2000_LSB 16
109	#define MPU3000_FS_MAX_LSB 131
110
111
112	#define MPU3000_SAM_RATE_MASK 0x07 //set sample rate and low padd filter configuration
113	#define MPU3000_RATE_8K_LPFB_256HZ 0x00
114	#define MPU3000_RATE_1K_LPFB_188HZ 0x01
115	#define MPU3000_RATE_1K_LPFB_98HZ 0x02
116	#define MPU3000_RATE_1K_LPFB_42HZ 0x03
117	#define MPU3000_RATE_1K_LPFB_20HZ 0x04
118	#define MPU3000_RATE_1K_LPFB_10HZ 0x05
119	#define MPU3000_RATE_1K_LPFB_5HZ 0x06
120
121
122	#define MPU3000_INT_ACTL 0x80 //logic level for INT out pin(low level)
123	#define MPU3000_INT_OPEN 0x40 //drvier type for INT out pin(open drain)
124	#define MPU3000_INT_LATCH_EN 0x20 //latch mode(latch until clear INT)
125	#define MPU3000_INT_CLR_BYRD 0x10 //clear INT by reading any register
126	#define MPU3000_MPU_RDY_EN 0x04 //enable INT when device is ready
127	#define MPU3000_DMP_DONE_EN 0x02 //enable INT when DMP is done
128	#define MPU3000_RAW_RDY_EN 0x01 //enable INT when data is available
129
130	#define MPU3000_INTS_MPU_RDY 0x04 //PLL is ready
131	#define MPU3000_INTS_DMP_DONE 0x02 //digital motion processor(DMP) is done
132	#define MPU3000_INTS_RAW_RDY 0x01 //raw data or FIFO data is ready
133
134	#define MPU3000_FIFO_CNT_H 0x03 //high bits of FIFO data number
135	#define MPU3000_FIFO_CNT_L 0xFF //low bits of FIFO data number
136	#define MPU3000_FIFOSIZE 512
137
138	#define MPU3000_FIFO_EN 0x40 //enable FIFO operation for sensor data
139	#define MPU3000_AUX_IF_EN 0x20 //enable AUX interface via I2C
140	#define MPU3000_AUX_IF_RST 0x08 //reset AUX interface function
141	#define MPU3000_FIFO_RST 0x02 //reset FIFO function
142	#define MPU3000_GYRO_RST 0x01 //reset gyro analog and digital functions
143
144	#define MPU3000_H_SET 0x80 //reset device and internal registers to default settings
145	#define MPU3000_SLEEP 0x40 //enable low power sleep mode
146	#define MPU3000_STBY_XG 0x20 //put gyro Z in standby mode
147	#define MPU3000_STBY_YG 0x10 //put gyro Z in standby mode
148	#define MPU3000_STBY_ZG 0x08 //put gyro Z in standby mode
149
150	#define MPU3000_CLK_SEL_MASK 0x07 //select device clock device
151	#define MPU3000_CLK_INTER_OSC 0x00
152	#define MPU3000_CLK_PLL_GYROX 0x01
153	#define MPU3000_CLK_PLL_GYROY 0x02
154	#define MPU3000_CLK_PLL_GYROZ 0x03
155	#define MPU3000_CLK_PLL_32K 0x04
156	#define MPU3000_CLK_PLL_19M 0x05
157	#define MPU3000_CLK_PLL_RESV 0x06
158	#define MPU3000_CLK_STOP_MASK 0x07
159
160
161	#define MPU3000_SUCCESS 0
162	#define MPU3000_ERR_I2C -1
163	#define MPU3000_ERR_STATUS -3
164	#define MPU3000_ERR_SETUP_FAILURE -4
165	#define MPU3000_ERR_GETGSENSORDATA -5
166	#define MPU3000_ERR_IDENTIFICATION -6
167
168
169	/*
170	typedef enum {
171	MPU3000_SYNC_NONE = 0x0,
172	MPU3000_SYNC_TEMP,
173	MPU3000_SYNC_GYROX,
174	MPU3000_SYNC_GYROY,
175	MPU3000_SYNC_GYROZ,
176	MPU3000_SYNC_AUXX,
177	MPU3000_SYNC_AUXY,
178	MPU3000_SYNC_AUXZ,
179	} MPU3000_EXT_SYNC_SEL;
180
181	typedef enum {
182	MPU3000_FS_250 = 0x0,
183	MPU3000_FS_500,
184	MPU3000_FS_1000,
185	MPU3000_FS_2000,
186	MPU3000_FS_MAX = 0x3,
187	} MPU3000_FS_SEL;
188
189	typedef enum {
190	MPU3000_RATE_8K_LPFB_256HZ = 0x0,
191	MPU3000_RATE_1K_LPFB_188HZ,
192	MPU3000_RATE_1K_LPFB_98HZ,
193	MPU3000_RATE_1K_LPFB_42HZ,
194	MPU3000_RATE_1K_LPFB_20HZ,
195	MPU3000_RATE_1K_LPFB_10HZ,
196	MPU3000_RATE_1K_LPFB_5HZ,
197	} MPU3000_SAMRATE_SEL;
198	*/
199
200	#define MPU3000_BUFSIZE 60
201
202	// 1 rad = 180/PI degree, MAX_LSB = 131,
203	// 180*131/PI = 7506
204	#define DEGREE_TO_RAD 7506
205
206	#endif //MPU3000_H
207