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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / connectivity / combo / drv_wlan / mt6630 / wlan / os / windows / ce / hif / spi / colibri.c
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6fa3eb70
S		 1/*
2** $Id: //Department/DaVinci/BRANCHES/MT6620_WIFI_DRIVER_V2_3/os/windows/ce/hif/spi/colibri.c#1 $
3*/
4
5/*! \file "colibri.c"
6 \brief Colibri platform specific functions
7
8*/
9
10
11
12/*
13** $Log: colibri.c $
14**
15** 09 17 2012 cm.chang
16** [BORA00002149] [MT6630 Wi-Fi] Initial software development
17** Duplicate source from MT6620 v2.3 driver branch
18** (Davinci label: MT6620_WIFI_Driver_V2_3_120913_1942_As_MT6630_Base)
19 *
20 * 07 08 2010 cp.wu
21 *
22 * [WPD00003833] [MT6620 and MT5931] Driver migration - move to new repository.
23 *
24 * 06 06 2010 kevin.huang
25 * [WPD00003832][MT6620 5931] Create driver base
26 * [MT6620 5931] Create driver base
27** \main\maintrunk.MT6620WiFiDriver_Prj\2 2009-04-29 20:13:47 GMT mtk01104
28** Fix bug. It needs OR, not AND in insteaGPIOConfigBackup() and GPIOConfigRestore()
29** \main\maintrunk.MT6620WiFiDriver_Prj\1 2009-04-24 21:13:20 GMT mtk01104
30** Initial version
31*/
32
33/******************************************************************************
34* C O M P I L E R F L A G S
35*******************************************************************************
36*/
37
38/******************************************************************************
39* E X T E R N A L R E F E R E N C E S
40*******************************************************************************
41*/
42#include "gl_os.h"
43LINT_EXT_HEADER_BEGIN \v
44#include <ceddk.h>
45 LINT_EXT_HEADER_END
46#include "hif.h"
47#include "colibri.h"
48/******************************************************************************
49* C O N S T A N T S
50*******************************************************************************
51*/
52/* Colibri custom IOCTL */
53#define GPIO_EDGE_RISING 1
54#define GPIO_EDGE_FALLING 2
55/* For Interrupt GPIO to sysIRQ */
56#define IOCTL_HAL_GPIO2IRQ \
57 CTL_CODE(FILE_DEVICE_HAL, 2048, METHOD_BUFFERED, FILE_ANY_ACCESS)
58#define IOCTL_HAL_IRQEDGE \
59 CTL_CODE(FILE_DEVICE_HAL, 2050, METHOD_BUFFERED, FILE_ANY_ACCESS)
60/******************************************************************************
61* D A T A T Y P E S
62*******************************************************************************
63*/
64/******************************************************************************
65* P U B L I C D A T A
66*******************************************************************************
67*/
68/* volatile OST_Timer* pVOSTRegs = NULL; */
69volatile CLK_MGR * pVClkMgr = NULL;
70volatile SSP_REG *pVSsp = NULL;
71volatile GPIO_REG *pVMem = NULL;
72
73/* For backup GPIO config */
74UINT_32 Fun_GAFR0_U;
75UINT_32 IO_GPDR0;
76
77/******************************************************************************
78* P R I V A T E D A T A
79*******************************************************************************
80*/
81
82/******************************************************************************
83* M A C R O S
84*******************************************************************************
85*/
86
87/******************************************************************************
88* F U N C T I O N D E C L A R A T I O N S
89*******************************************************************************
90*/
91
92/*----------------------------------------------------------------------------*/
93/*!
94* \brief This routine is to used for register access.
95*
96* \param[in] u4Cmd The Read/Write command use the MT5921 defined.
97* \param[in] u4Offset The register address
98* \param[in] pU4Value The read / wite buffer pointer
99*
100* \return None
101*
102*/
103/*----------------------------------------------------------------------------*/
104VOID SpiSendCmd32(UINT_32 u4Cmd, UINT_32 u4Offset, UINT_32 *pU4Value)
105{
106 UINT_32 u4CmdRespBuff = u4Cmd | (4 << 16) | u4Offset;
107#if CONFIG_SPI_8_BIT_MODE
108 UINT_32 i;
109 PUINT_8 pucBuff = (PUINT_8) &u4CmdRespBuff;
110#endif
111 UINT_32 u4Value = 0;
112
113 ASSERT(pU4Value);
114
115 WAIT_BUS_CLEAR(u4CmdRespBuff);
116
117#if CONFIG_SPI_8_BIT_MODE
118 i = 0;
119 while (i < 4) {
120 WAIT_BUS_READY_TX();
121 pVSsp->ssdr = pucBuff[i++]; /* for write cmd */
122 WAIT_BUS_READY_RX(u4Value);
123 if (u4Value != 0) {
124 (void)pVSsp->ssdr;
125 }
126 }
127
128 if (u4Cmd & BIT(31)) { /* write */
129 pucBuff = (PUINT_8) pU4Value;
130 i = 0;
131 while (i < 4) {
132 WAIT_BUS_READY_TX();
133 pVSsp->ssdr = pucBuff[i++]; /* write data */
134 }
135 } else { /* read */
136 i = 0;
137 while (i < 4) {
138 WAIT_BUS_READY_TX();
139 pVSsp->ssdr = 0xff; /* for rsp */
140 WAIT_BUS_READY_RX(u4Value);
141 pucBuff[i++] = (UINT_8) pVSsp->ssdr;
142 }
143 pucBuff = (PUINT_8) pU4Value;
144 i = 0;
145 while (i < 4) {
146 WAIT_BUS_READY_TX();
147 pVSsp->ssdr = 0xff; /* for write data */
148 WAIT_BUS_READY_RX(u4Value);
149 pucBuff[i++] = (UINT_8) pVSsp->ssdr;
150 }
151 }
152
153#else
154
155 WAIT_BUS_READY_TX();
156 pVSsp->ssdr = u4CmdRespBuff; /* write cmd */
157 WAIT_BUS_READY_RX(u4Value);
158 if (u4Value != 0) {
159 (void)pVSsp->ssdr;
160 } else {
161 ASSERT(FALSE);
162 }
163
164 if (u4Cmd & BIT(31)) { /* write */
165 WAIT_BUS_READY_TX();
166 pVSsp->ssdr = pU4Value[0]; /* write data */
167 } else { /* read */
168 WAIT_BUS_READY_TX();
169 pVSsp->ssdr = 0xffffffff;
170 WAIT_BUS_READY_RX(u4Value);
171 if (u4Value != 0) {
172 u4CmdRespBuff = pVSsp->ssdr;
173 } else {
174 ASSERT(FALSE);
175 }
176
177 WAIT_BUS_READY_TX();
178 pVSsp->ssdr = 0xffffffff;
179 WAIT_BUS_READY_RX(u4Value);
180 if (u4Value != 0) {
181 pU4Value[0] = pVSsp->ssdr;
182 } else {
183 ASSERT(FALSE);
184 }
185 }
186#endif
187
188 WAIT_BUS_DONE();
189
190}
191
192
193/*----------------------------------------------------------------------------*/
194/*!
195* \brief This routine is to used for port data access.
196*
197* \param[in] u4Cmd The Read/Write command use the MT5921 defined.
198* \param[in] u4Offset The register address
199* \param[in] pU4Value The read / wite buffer pointer
200* \param[in] u4Size The read / wite buffer size
201*
202* \return None
203*
204*/
205/*----------------------------------------------------------------------------*/
206void SpiReadWriteData32(UINT_32 u4Cmd, UINT_32 u4Offset, UINT_8 *pucDataBuff, UINT_32 u4Size)
207{
208 UINT_32 u4CmdRespBuff = u4Cmd | (u4Size << 16) | u4Offset;
209 UINT_32 u4Value = 0;
210 UINT_32 i = 0, j = 0, temp = 0;
211 UINT_32 u4Len32bit = (u4Size >> 2);
212 UINT_32 *pu4DataBuff;
213#if CONFIG_SPI_8_BIT_MODE
214 UINT_32 k = 0;
215 PUINT_8 pucBuff = (PUINT_8) &u4CmdRespBuff;
216#endif
217
218 ASSERT(pucDataBuff);
219
220 pu4DataBuff = (UINT_32 *) pucDataBuff;
221
222 WAIT_BUS_CLEAR(u4CmdRespBuff);
223
224#if CONFIG_SPI_8_BIT_MODE
225
226 k = 0;
227 while (k < SPI_LOOP_COUNT) {
228 WAIT_BUS_READY_TX();
229 pVSsp->ssdr = pucBuff[k++]; /* write cmd */
230
231 WAIT_BUS_READY_RX(u4Value);
232 (void)pVSsp->ssdr; /* for write cmd */
233 }
234 /* Data, use double word size */
235 if (u4Cmd & BIT(31)) { /* write */
236 pucBuff = (PUINT_8) pucDataBuff;
237 if ((u4Len32bit >> 4) > 0) {
238 for (i = 0; i < (u4Len32bit >> 4); i++) {
239 for (k = 0; k < SPI_LOOP_COUNT; k++) {
240 WAIT_BUS_READY_TX();
241 pVSsp->ssdr = pucBuff[j];
242 WAIT_BUS_READY_TX();
243 pVSsp->ssdr = pucBuff[j + 1];
244 WAIT_BUS_READY_TX();
245 pVSsp->ssdr = pucBuff[j + 2];
246 WAIT_BUS_READY_TX();
247 pVSsp->ssdr = pucBuff[j + 3];
248 WAIT_BUS_READY_TX();
249 pVSsp->ssdr = pucBuff[j + 4];
250 WAIT_BUS_READY_TX();
251 pVSsp->ssdr = pucBuff[j + 5];
252 WAIT_BUS_READY_TX();
253 pVSsp->ssdr = pucBuff[j + 6];
254 WAIT_BUS_READY_TX();
255 pVSsp->ssdr = pucBuff[j + 7];
256
257 WAIT_BUS_READY_TX();
258 pVSsp->ssdr = pucBuff[j + 8];
259 WAIT_BUS_READY_TX();
260 pVSsp->ssdr = pucBuff[j + 9];
261 WAIT_BUS_READY_TX();
262 pVSsp->ssdr = pucBuff[j + 10];
263 WAIT_BUS_READY_TX();
264 pVSsp->ssdr = pucBuff[j + 11];
265 WAIT_BUS_READY_TX();
266 pVSsp->ssdr = pucBuff[j + 12];
267 WAIT_BUS_READY_TX();
268 pVSsp->ssdr = pucBuff[j + 13];
269 WAIT_BUS_READY_TX();
270 pVSsp->ssdr = pucBuff[j + 14];
271 WAIT_BUS_READY_TX();
272 pVSsp->ssdr = pucBuff[j + 15];
273 j += 16;
274 }
275 }
276 }
277
278 if ((u4Len32bit & 0x8) != 0) {
279 for (k = 0; k < SPI_LOOP_COUNT; k++) {
280 WAIT_BUS_READY_TX();
281 pVSsp->ssdr = pucBuff[j];
282 WAIT_BUS_READY_TX();
283 pVSsp->ssdr = pucBuff[j + 1];
284 WAIT_BUS_READY_TX();
285 pVSsp->ssdr = pucBuff[j + 2];
286 WAIT_BUS_READY_TX();
287 pVSsp->ssdr = pucBuff[j + 3];
288 WAIT_BUS_READY_TX();
289 pVSsp->ssdr = pucBuff[j + 4];
290 WAIT_BUS_READY_TX();
291 pVSsp->ssdr = pucBuff[j + 5];
292 WAIT_BUS_READY_TX();
293 pVSsp->ssdr = pucBuff[j + 6];
294 WAIT_BUS_READY_TX();
295 pVSsp->ssdr = pucBuff[j + 7];
296 j += 8;
297 }
298 }
299
300 if ((u4Len32bit & 0x4) != 0) {
301 for (k = 0; k < SPI_LOOP_COUNT; k++) {
302 WAIT_BUS_READY_TX();
303 pVSsp->ssdr = pucBuff[j];
304 WAIT_BUS_READY_TX();
305 pVSsp->ssdr = pucBuff[j + 1];
306 WAIT_BUS_READY_TX();
307 pVSsp->ssdr = pucBuff[j + 2];
308 WAIT_BUS_READY_TX();
309 pVSsp->ssdr = pucBuff[j + 3];
310 j += 4;
311 }
312 }
313
314 temp = (u4Len32bit & 0x3);
315 while (temp--) {
316 for (k = 0; k < SPI_LOOP_COUNT; k++) {
317 WAIT_BUS_READY_TX();
318 pVSsp->ssdr = pucBuff[j++];
319 }
320 }
321
322 } else { /* read */
323
324 for (k = 0; k < SPI_LOOP_COUNT; k++) {
325 WAIT_BUS_READY_TX();
326 pVSsp->ssdr = 0xff; /* rsp */
327 WAIT_BUS_READY_RX(u4Value);
328 (void)pVSsp->ssdr; /* for rsp */
329 }
330 pucBuff = (PUINT_8) &pu4DataBuff[0];
331 if ((u4Len32bit >> 4) > 0) {
332 for (i; i < (u4Len32bit >> 4); i++) {
333 for (k = 0; k < SPI_LOOP_COUNT; k++) {
334 WAIT_BUS_READY_TX();
335 pVSsp->ssdr = 0xFFFFFFFF;
336 pVSsp->ssdr = 0xFFFFFFFF;
337 pVSsp->ssdr = 0xFFFFFFFF;
338 pVSsp->ssdr = 0xFFFFFFFF;
339 pVSsp->ssdr = 0xFFFFFFFF;
340
341 pVSsp->ssdr = 0xFFFFFFFF;
342 pVSsp->ssdr = 0xFFFFFFFF;
343 pVSsp->ssdr = 0xFFFFFFFF;
344 pVSsp->ssdr = 0xFFFFFFFF;
345 pVSsp->ssdr = 0xFFFFFFFF;
346
347 pVSsp->ssdr = 0xFFFFFFFF;
348 pVSsp->ssdr = 0xFFFFFFFF;
349 pVSsp->ssdr = 0xFFFFFFFF;
350 pVSsp->ssdr = 0xFFFFFFFF;
351 pVSsp->ssdr = 0xFFFFFFFF;
352
353 pVSsp->ssdr = 0xFFFFFFFF;
354
355 WAIT_BUS_READY_RX(u4Value);
356 pucBuff[j] = (UINT_8) pVSsp->ssdr;
357 WAIT_BUS_READY_RX(u4Value);
358 pucBuff[j + 1] = (UINT_8) pVSsp->ssdr;
359 WAIT_BUS_READY_RX(u4Value);
360 pucBuff[j + 2] = (UINT_8) pVSsp->ssdr;
361 WAIT_BUS_READY_RX(u4Value);
362 pucBuff[j + 3] = (UINT_8) pVSsp->ssdr;
363 WAIT_BUS_READY_RX(u4Value);
364 pucBuff[j + 4] = (UINT_8) pVSsp->ssdr;
365
366 WAIT_BUS_READY_RX(u4Value);
367 pucBuff[j + 5] = (UINT_8) pVSsp->ssdr;
368 WAIT_BUS_READY_RX(u4Value);
369 pucBuff[j + 6] = (UINT_8) pVSsp->ssdr;
370 WAIT_BUS_READY_RX(u4Value);
371 pucBuff[j + 7] = (UINT_8) pVSsp->ssdr;
372 WAIT_BUS_READY_RX(u4Value);
373 pucBuff[j + 8] = (UINT_8) pVSsp->ssdr;
374 WAIT_BUS_READY_RX(u4Value);
375 pucBuff[j + 9] = (UINT_8) pVSsp->ssdr;
376
377 WAIT_BUS_READY_RX(u4Value);
378 pucBuff[j + 10] = (UINT_8) pVSsp->ssdr;
379 WAIT_BUS_READY_RX(u4Value);
380 pucBuff[j + 11] = (UINT_8) pVSsp->ssdr;
381 WAIT_BUS_READY_RX(u4Value);
382 pucBuff[j + 12] = (UINT_8) pVSsp->ssdr;
383 WAIT_BUS_READY_RX(u4Value);
384 pucBuff[j + 13] = (UINT_8) pVSsp->ssdr;
385 WAIT_BUS_READY_RX(u4Value);
386 pucBuff[j + 14] = (UINT_8) pVSsp->ssdr;
387
388 WAIT_BUS_READY_RX(u4Value);
389 pucBuff[j + 15] = (UINT_8) pVSsp->ssdr;
390 j += 16;
391 }
392 }
393 }
394
395 if ((u4Len32bit & 0x8) != 0) {
396 for (k = 0; k < SPI_LOOP_COUNT; k++) {
397 WAIT_BUS_READY_TX();
398 pVSsp->ssdr = 0xFFFFFFFF;
399 pVSsp->ssdr = 0xFFFFFFFF;
400 pVSsp->ssdr = 0xFFFFFFFF;
401 pVSsp->ssdr = 0xFFFFFFFF;
402 pVSsp->ssdr = 0xFFFFFFFF;
403
404 pVSsp->ssdr = 0xFFFFFFFF;
405 pVSsp->ssdr = 0xFFFFFFFF;
406 pVSsp->ssdr = 0xFFFFFFFF;
407
408 WAIT_BUS_READY_RX(u4Value);
409 pucBuff[j] = (UINT_8) pVSsp->ssdr;
410 WAIT_BUS_READY_RX(u4Value);
411 pucBuff[j + 1] = (UINT_8) pVSsp->ssdr;
412 WAIT_BUS_READY_RX(u4Value);
413 pucBuff[j + 2] = (UINT_8) pVSsp->ssdr;
414 WAIT_BUS_READY_RX(u4Value);
415 pucBuff[j + 3] = (UINT_8) pVSsp->ssdr;
416 WAIT_BUS_READY_RX(u4Value);
417 pucBuff[j + 4] = (UINT_8) pVSsp->ssdr;
418
419 WAIT_BUS_READY_RX(u4Value);
420 pucBuff[j + 5] = (UINT_8) pVSsp->ssdr;
421 WAIT_BUS_READY_RX(u4Value);
422 pucBuff[j + 6] = (UINT_8) pVSsp->ssdr;
423 WAIT_BUS_READY_RX(u4Value);
424 pucBuff[j + 7] = (UINT_8) pVSsp->ssdr;
425 j += 8;
426 }
427 }
428
429 if ((u4Len32bit & 0x4) != 0) {
430 for (k = 0; k < SPI_LOOP_COUNT; k++) {
431 WAIT_BUS_READY_TX();
432 pVSsp->ssdr = 0xFFFFFFFF;
433 pVSsp->ssdr = 0xFFFFFFFF;
434 pVSsp->ssdr = 0xFFFFFFFF;
435 pVSsp->ssdr = 0xFFFFFFFF;
436
437 WAIT_BUS_READY_RX(u4Value);
438 pucBuff[j] = (UINT_8) pVSsp->ssdr;
439 WAIT_BUS_READY_RX(u4Value);
440 pucBuff[j + 1] = (UINT_8) pVSsp->ssdr;
441 WAIT_BUS_READY_RX(u4Value);
442 pucBuff[j + 2] = (UINT_8) pVSsp->ssdr;
443 WAIT_BUS_READY_RX(u4Value);
444 pucBuff[j + 3] = (UINT_8) pVSsp->ssdr;
445 j += 4;
446 }
447 }
448
449 temp = (u4Len32bit & 0x3);
450 while (temp--) {
451 for (k = 0; k < SPI_LOOP_COUNT; k++) {
452 WAIT_BUS_READY_TX();
453 pVSsp->ssdr = 0xFF;
454 WAIT_BUS_READY_RX(u4Value);
455 pucBuff[j++] = (UINT_8) pVSsp->ssdr;
456 }
457 }
458 }
459
460#else /* 32-bit mode */
461 WAIT_BUS_READY_TX();
462 pVSsp->ssdr = u4CmdRespBuff; /* write cmd */
463
464 WAIT_BUS_READY_RX(u4Value);
465 u4Value = pVSsp->ssdr; /* for write cmd */
466
467 /* Data, use double word size */
468 if (u4Cmd & BIT(31)) { /* write */
469 if ((u4Len32bit >> 4) > 0) {
470 for (i = 0; i < (u4Len32bit >> 4); i++) {
471 WAIT_BUS_READY_TX();
472 pVSsp->ssdr = pu4DataBuff[j];
473 WAIT_BUS_READY_TX();
474 pVSsp->ssdr = pu4DataBuff[j + 1];
475 WAIT_BUS_READY_TX();
476 pVSsp->ssdr = pu4DataBuff[j + 2];
477 WAIT_BUS_READY_TX();
478 pVSsp->ssdr = pu4DataBuff[j + 3];
479 WAIT_BUS_READY_TX();
480 pVSsp->ssdr = pu4DataBuff[j + 4];
481 WAIT_BUS_READY_TX();
482 pVSsp->ssdr = pu4DataBuff[j + 5];
483 WAIT_BUS_READY_TX();
484 pVSsp->ssdr = pu4DataBuff[j + 6];
485 WAIT_BUS_READY_TX();
486 pVSsp->ssdr = pu4DataBuff[j + 7];
487 WAIT_BUS_READY_TX();
488 pVSsp->ssdr = pu4DataBuff[j + 8];
489 WAIT_BUS_READY_TX();
490 pVSsp->ssdr = pu4DataBuff[j + 9];
491 WAIT_BUS_READY_TX();
492 pVSsp->ssdr = pu4DataBuff[j + 10];
493 WAIT_BUS_READY_TX();
494 pVSsp->ssdr = pu4DataBuff[j + 11];
495 WAIT_BUS_READY_TX();
496 pVSsp->ssdr = pu4DataBuff[j + 12];
497 WAIT_BUS_READY_TX();
498 pVSsp->ssdr = pu4DataBuff[j + 13];
499 WAIT_BUS_READY_TX();
500 pVSsp->ssdr = pu4DataBuff[j + 14];
501 WAIT_BUS_READY_TX();
502 pVSsp->ssdr = pu4DataBuff[j + 15];
503 j += 16;
504 }
505 }
506
507 if ((u4Len32bit & 0x8) != 0) {
508 WAIT_BUS_READY_TX();
509 pVSsp->ssdr = pu4DataBuff[j];
510 WAIT_BUS_READY_TX();
511 pVSsp->ssdr = pu4DataBuff[j + 1];
512 WAIT_BUS_READY_TX();
513 pVSsp->ssdr = pu4DataBuff[j + 2];
514 WAIT_BUS_READY_TX();
515 pVSsp->ssdr = pu4DataBuff[j + 3];
516 WAIT_BUS_READY_TX();
517 pVSsp->ssdr = pu4DataBuff[j + 4];
518 WAIT_BUS_READY_TX();
519 pVSsp->ssdr = pu4DataBuff[j + 5];
520 WAIT_BUS_READY_TX();
521 pVSsp->ssdr = pu4DataBuff[j + 6];
522 WAIT_BUS_READY_TX();
523 pVSsp->ssdr = pu4DataBuff[j + 7];
524 j += 8;
525 }
526
527 if ((u4Len32bit & 0x4) != 0) {
528 WAIT_BUS_READY_TX();
529 pVSsp->ssdr = pu4DataBuff[j];
530 WAIT_BUS_READY_TX();
531 pVSsp->ssdr = pu4DataBuff[j + 1];
532 WAIT_BUS_READY_TX();
533 pVSsp->ssdr = pu4DataBuff[j + 2];
534 WAIT_BUS_READY_TX();
535 pVSsp->ssdr = pu4DataBuff[j + 3];
536 j += 4;
537 }
538
539 temp = (u4Len32bit & 0x3);
540 while (temp--) {
541 WAIT_BUS_READY_TX();
542 pVSsp->ssdr = pu4DataBuff[j++];
543 }
544
545 } else { /* read */
546
547 WAIT_BUS_READY_TX();
548 pVSsp->ssdr = 0xffffffff; /* rsp */
549 WAIT_BUS_READY_RX(u4Value);
550 u4Value = pVSsp->ssdr; /* for rsp */
551
552 if ((u4Len32bit >> 4) > 0) {
553 for (i; i < (u4Len32bit >> 4); i++) {
554 WAIT_BUS_READY_TX();
555 pVSsp->ssdr = 0xFFFFFFFF;
556 pVSsp->ssdr = 0xFFFFFFFF;
557 pVSsp->ssdr = 0xFFFFFFFF;
558 pVSsp->ssdr = 0xFFFFFFFF;
559 pVSsp->ssdr = 0xFFFFFFFF;
560
561 pVSsp->ssdr = 0xFFFFFFFF;
562 pVSsp->ssdr = 0xFFFFFFFF;
563 pVSsp->ssdr = 0xFFFFFFFF;
564 pVSsp->ssdr = 0xFFFFFFFF;
565 pVSsp->ssdr = 0xFFFFFFFF;
566
567 pVSsp->ssdr = 0xFFFFFFFF;
568 pVSsp->ssdr = 0xFFFFFFFF;
569 pVSsp->ssdr = 0xFFFFFFFF;
570 pVSsp->ssdr = 0xFFFFFFFF;
571 pVSsp->ssdr = 0xFFFFFFFF;
572
573 pVSsp->ssdr = 0xFFFFFFFF;
574
575 WAIT_BUS_READY_RX(u4Value);
576 pu4DataBuff[j] = pVSsp->ssdr;
577 WAIT_BUS_READY_RX(u4Value);
578 pu4DataBuff[j + 1] = pVSsp->ssdr;
579 WAIT_BUS_READY_RX(u4Value);
580 pu4DataBuff[j + 2] = pVSsp->ssdr;
581 WAIT_BUS_READY_RX(u4Value);
582 pu4DataBuff[j + 3] = pVSsp->ssdr;
583 WAIT_BUS_READY_RX(u4Value);
584 pu4DataBuff[j + 4] = pVSsp->ssdr;
585
586 WAIT_BUS_READY_RX(u4Value);
587 pu4DataBuff[j + 5] = pVSsp->ssdr;
588 WAIT_BUS_READY_RX(u4Value);
589 pu4DataBuff[j + 6] = pVSsp->ssdr;
590 WAIT_BUS_READY_RX(u4Value);
591 pu4DataBuff[j + 7] = pVSsp->ssdr;
592 WAIT_BUS_READY_RX(u4Value);
593 pu4DataBuff[j + 8] = pVSsp->ssdr;
594 WAIT_BUS_READY_RX(u4Value);
595 pu4DataBuff[j + 9] = pVSsp->ssdr;
596
597 WAIT_BUS_READY_RX(u4Value);
598 pu4DataBuff[j + 10] = pVSsp->ssdr;
599 WAIT_BUS_READY_RX(u4Value);
600 pu4DataBuff[j + 11] = pVSsp->ssdr;
601 WAIT_BUS_READY_RX(u4Value);
602 pu4DataBuff[j + 12] = pVSsp->ssdr;
603 WAIT_BUS_READY_RX(u4Value);
604 pu4DataBuff[j + 13] = pVSsp->ssdr;
605 WAIT_BUS_READY_RX(u4Value);
606 pu4DataBuff[j + 14] = pVSsp->ssdr;
607
608 WAIT_BUS_READY_RX(u4Value);
609 pu4DataBuff[j + 15] = pVSsp->ssdr;
610 j += 16;
611 }
612 }
613
614 if ((u4Len32bit & 0x8) != 0) {
615 WAIT_BUS_READY_TX();
616 pVSsp->ssdr = 0xFFFFFFFF;
617 pVSsp->ssdr = 0xFFFFFFFF;
618 pVSsp->ssdr = 0xFFFFFFFF;
619 pVSsp->ssdr = 0xFFFFFFFF;
620 pVSsp->ssdr = 0xFFFFFFFF;
621
622 pVSsp->ssdr = 0xFFFFFFFF;
623 pVSsp->ssdr = 0xFFFFFFFF;
624 pVSsp->ssdr = 0xFFFFFFFF;
625
626 WAIT_BUS_READY_RX(u4Value);
627 pu4DataBuff[j] = pVSsp->ssdr;
628 WAIT_BUS_READY_RX(u4Value);
629 pu4DataBuff[j + 1] = pVSsp->ssdr;
630 WAIT_BUS_READY_RX(u4Value);
631 pu4DataBuff[j + 2] = pVSsp->ssdr;
632 WAIT_BUS_READY_RX(u4Value);
633 pu4DataBuff[j + 3] = pVSsp->ssdr;
634 WAIT_BUS_READY_RX(u4Value);
635 pu4DataBuff[j + 4] = pVSsp->ssdr;
636
637 WAIT_BUS_READY_RX(u4Value);
638 pu4DataBuff[j + 5] = pVSsp->ssdr;
639 WAIT_BUS_READY_RX(u4Value);
640 pu4DataBuff[j + 6] = pVSsp->ssdr;
641 WAIT_BUS_READY_RX(u4Value);
642 pu4DataBuff[j + 7] = pVSsp->ssdr;
643 j += 8;
644 }
645 if ((u4Len32bit & 0x4) != 0) {
646 WAIT_BUS_READY_TX();
647 pVSsp->ssdr = 0xFFFFFFFF;
648 pVSsp->ssdr = 0xFFFFFFFF;
649 pVSsp->ssdr = 0xFFFFFFFF;
650 pVSsp->ssdr = 0xFFFFFFFF;
651
652 WAIT_BUS_READY_RX(u4Value);
653 pu4DataBuff[j] = pVSsp->ssdr;
654 WAIT_BUS_READY_RX(u4Value);
655 pu4DataBuff[j + 1] = pVSsp->ssdr;
656 WAIT_BUS_READY_RX(u4Value);
657 pu4DataBuff[j + 2] = pVSsp->ssdr;
658 WAIT_BUS_READY_RX(u4Value);
659 pu4DataBuff[j + 3] = pVSsp->ssdr;
660 j += 4;
661 }
662
663 temp = (u4Len32bit & 0x3);
664 while (temp--) {
665 WAIT_BUS_READY_TX();
666 pVSsp->ssdr = 0xFFFFFFFF;
667 WAIT_BUS_READY_RX(u4Value);
668 pu4DataBuff[j++] = pVSsp->ssdr;
669 }
670
671 }
672#endif
673
674 WAIT_BUS_DONE();
675}
676
677/*----------------------------------------------------------------------------*/
678/*!
679* \brief This routine is used to set spi bus width.
680*
681* \param[in] u4BusSize - Bus size.
682*
683* \retval 0 TRUE
684* \retval -1 FALSE
685*/
686/*----------------------------------------------------------------------------*/
687static INT_32 SpiSetBusWidth(UINT_32 u4BusSize)
688{
689 /* if size is not valid, return with size unchanged */
690 /* if (u4BusSize > 32 || u4BusSize < 4) */
691 if (u4BusSize != 32 && u4BusSize != 8)
692 return -1;
693
694 /* 1) disable port */
695 pVSsp->sscr0 &= ~SSCR0_SSE;
696
697 /* 2) clear size field */
698 pVSsp->sscr0 &= ~(SSCR0_DSS_32BIT | SSCR0_EDSS);
699
700 /* MUST restore SSCR1 value after disable SSE */
701 pVSsp->sscr1 = SSCR1_SPH | SSCR1_SPO | (3 << 6) | (0 << 10);
702
703 /* 3) set size and enable port */
704 pVSsp->sscr0 |= (SSCR0_DSS_SIZE(u4BusSize) | SSCR0_SSE);
705
706 return 0;
707} /* SpiSetBusWidth */
708
709
710/*----------------------------------------------------------------------------*/
711/*!
712* \brief This routine is used to set operation mode to n-bit mode and Endian.
713*
714* \param[in] u4BusSize - Bus size.
715*
716* \return none
717*/
718/*----------------------------------------------------------------------------*/
719static VOID SpiSetOpMode(VOID)
720{
721#if !CONFIG_SPI_8_BIT_MODE
722 UINT_32 u4Value = 0;
723#endif
724
725 /* Set bus to 32-bit mode */
726#if CONFIG_SPI_8_BIT_MODE
727 if (SpiSetBusWidth(8) != 0) {
728 ASSERT(FALSE);
729 return;
730 }
731 DBGLOG(INIT, TRACE, ("Set bus to 8-bit mode\n"));
732#else
733 if (SpiSetBusWidth(32) != 0) {
734 ASSERT(FALSE);
735 return;
736 }
737 DBGLOG(INIT, TRACE, ("Set bus to 32-bit mode\n"));
738#endif
739
740#if !CONFIG_SPI_8_BIT_MODE
741 /* SPI CSR set from 8 bit mode to 32 bit mode, notice the byte order */
742 /* Set this after set bus to 32-bit mode */
743 WAIT_BUS_READY_TX();
744 pVSsp->ssdr = SPICSR_32BIT_MODE_ADDR;
745 WAIT_BUS_READY_RX(u4Value);
746 if (u4Value != 0) {
747 (void)pVSsp->ssdr;
748 } else {
749 ASSERT(FALSE);
750 }
751
752 WAIT_BUS_READY_TX();
753 pVSsp->ssdr = SPICSR_32BIT_MODE_DATA;
754 WAIT_BUS_READY_RX(u4Value);
755 if (u4Value != 0) {
756 (void)pVSsp->ssdr;
757 } else {
758 ASSERT(FALSE);
759 }
760#endif
761
762} /* SpiSetOpMode */
763
764
765/*----------------------------------------------------------------------------*/
766/*!
767* \brief Modify GP DDR For Input Direction
768* aGpioPinArray[] = array of GPIO pins,
769* aGpioPinArray[0] = size of array
770*
771* \param[in] aGpioPinArray[] - rray of GPIO pins.
772*
773* \return none
774*/
775/*----------------------------------------------------------------------------*/
776static VOID GpioSetDirectionIn(P_GPIO_REG prGPIO, UINT_32 au4GpioPinArray[]
777 )
778{
779 UINT_32 u4GpioPinMask;
780 UINT_32 u4SizeArray;
781 UINT_32 u4Mask0, u4Mask1, u4Mask2, u4Mask3;
782 BOOL fgSet0, fgSet1, fgSet2, fgSet3;
783 UINT_32 i;
784
785 ASSERT(prGPIO);
786 ASSERT(au4GpioPinArray);
787
788 /* determine size of array */
789 u4SizeArray = au4GpioPinArray[0];
790 u4Mask0 = u4Mask1 = u4Mask2 = u4Mask3 = 0;
791 fgSet0 = fgSet1 = fgSet2 = fgSet3 = FALSE;
792
793 for (i = 1; i <= u4SizeArray; i++) {
794 u4GpioPinMask = 0x1u << (au4GpioPinArray[i] & 0x1F);
795 if (au4GpioPinArray[i] > 95) {
796 u4Mask3 |= u4GpioPinMask;
797 fgSet3 = TRUE;
798 } else if (au4GpioPinArray[i] > 63) {
799 u4Mask2 |= u4GpioPinMask;
800 fgSet2 = TRUE;
801 } else if (au4GpioPinArray[i] > 31) {
802 u4Mask1 |= u4GpioPinMask;
803 fgSet1 = TRUE;
804 } else {
805 u4Mask0 |= u4GpioPinMask;
806 fgSet0 = TRUE;
807 }
808
809 }
810
811 if (fgSet3) {
812 prGPIO->GPDR3 = ((prGPIO->GPDR3 & ~u4Mask3) & ~GPIO_PIN_RESERVED_BITS);
813 }
814 if (fgSet2) {
815 prGPIO->GPDR2 = ((prGPIO->GPDR2) & ~u4Mask2);
816 }
817 if (fgSet1) {
818 prGPIO->GPDR1 = ((prGPIO->GPDR1) & ~u4Mask1);
819 }
820 if (fgSet0) {
821 prGPIO->GPDR0 = ((prGPIO->GPDR0) & ~u4Mask0);
822 }
823} /* GpioSetDirectionIn */
824
825
826/*----------------------------------------------------------------------------*/
827/*!
828* \brief Modify GP DDR For Output Direction,
829* aGpioPinArray[]=array of GPIO pins,
830* aGpioPinArray[0] = size of array
831*
832* \param[in] aGpioPinArray[] - array of GPIO pins
833*
834* \return none
835*/
836/*----------------------------------------------------------------------------*/
837static VOID GpioSetDirectionOut(P_GPIO_REG prGPIO, UINT_32 au4GpioPinArray[]
838 )
839{
840 UINT_32 u4GpioPinMask;
841 UINT_32 u4SizeArray;
842 UINT_32 u4Mask0, u4Mask1, u4Mask2, u4Mask3;
843 BOOL fgSet0, fgSet1, fgSet2, fgSet3;
844 UINT_32 i;
845
846 ASSERT(prGPIO);
847 ASSERT(au4GpioPinArray);
848
849 /* determine size of array */
850 u4SizeArray = au4GpioPinArray[0];
851 u4Mask0 = u4Mask1 = u4Mask2 = u4Mask3 = 0;
852 fgSet0 = fgSet1 = fgSet2 = fgSet3 = FALSE;
853
854 for (i = 1; i <= u4SizeArray; i++) {
855 u4GpioPinMask = 0x1u << (au4GpioPinArray[i] & 0x1F);
856 if (au4GpioPinArray[i] > 95) {
857 u4Mask3 |= u4GpioPinMask;
858 fgSet3 = TRUE;
859 } else if (au4GpioPinArray[i] > 63) {
860 u4Mask2 |= u4GpioPinMask;
861 fgSet2 = TRUE;
862 } else if (au4GpioPinArray[i] > 31) {
863 u4Mask1 |= u4GpioPinMask;
864 fgSet1 = TRUE;
865 } else {
866 u4Mask0 |= u4GpioPinMask;
867 fgSet0 = TRUE;
868 }
869 }
870 if (fgSet3) {
871 prGPIO->GPDR3 = ((prGPIO->GPDR3 | u4Mask3) & ~GPIO_PIN_RESERVED_BITS);
872 }
873 if (fgSet2) {
874 prGPIO->GPDR2 = ((prGPIO->GPDR2) | u4Mask2);
875 }
876 if (fgSet1) {
877 prGPIO->GPDR1 = ((prGPIO->GPDR1) | u4Mask1);
878 }
879 if (fgSet0) {
880 prGPIO->GPDR0 = ((prGPIO->GPDR0) | u4Mask0);
881 }
882} /* GpioSetDirectionOut */
883
884
885/*----------------------------------------------------------------------------*/
886/*!
887* \brief Set GPIO pins alternate function values,
888* aGpioPinArray[]=array of GPIO pins,
889* aGpioPinArray[0] = size of array
890*
891* aAfValueArray[]=array of GPIO pins alternate function values,
892* aAfValueArray[0] = size of array
893* \param[in] aGpioPinArray[] - array of GPIO pins
894* \param[in] aAfValueArray[] - array of GPIO pins alternate function values
895*
896* \return none
897* \note: IMPORTANT:THE ORDER OF aAfValueArray[] HAS TO MATCH THE ORDER OF aGpioPinArray[]
898*/
899/*----------------------------------------------------------------------------*/
900static VOID GpioSetAlternateFn(P_GPIO_REG prGPIO, UINT_32 au4GpioPinArray[], UINT_32 aAfValueArray[]
901 )
902{
903 UINT_32 u4GpioPinAFMask;
904 UINT_32 u4GpioPinAFValue;
905 UINT_32 u4SizeArray;
906 UINT_32 u4Mask0_U, u4Mask0_L, u4Mask1_U, u4Mask1_L;
907 UINT_32 u4Mask2_U, u4Mask2_L, u4Mask3_U, u4Mask3_L;
908 UINT_32 u4AFnV0_U, u4AFnV0_L, u4AFnV1_U, u4AFnV1_L;
909 UINT_32 u4AFnV2_U, u4AFnV2_L, u4AFnV3_U, u4AFnV3_L;
910 BOOL fgSet0_U, fgSet0_L, fgSet1_U, fgSet1_L;
911 BOOL fgSet2_U, fgSet2_L, fgSet3_U, fgSet3_L;
912 UINT_32 i;
913
914 ASSERT(prGPIO);
915 ASSERT(au4GpioPinArray);
916 ASSERT(aAfValueArray);
917
918 /* determine size of array */
919 u4SizeArray = au4GpioPinArray[0];
920 u4Mask0_U = u4Mask0_L = u4Mask1_U = u4Mask1_L = 0;
921 u4Mask2_U = u4Mask2_L = u4Mask3_U = u4Mask3_L = 0;
922 u4AFnV0_U = u4AFnV0_L = u4AFnV1_U = u4AFnV1_L = 0;
923 u4AFnV2_U = u4AFnV2_L = u4AFnV3_U = u4AFnV3_L = 0;
924 fgSet0_U = fgSet0_L = fgSet1_U = fgSet1_L = FALSE;
925 fgSet2_U = fgSet2_L = fgSet3_U = fgSet3_L = FALSE;
926
927 for (i = 1; i <= u4SizeArray; i++) {
928 u4GpioPinAFMask = 0x3u << ((au4GpioPinArray[i] & 0xF) * 2);
929 u4GpioPinAFValue = aAfValueArray[i] << ((au4GpioPinArray[i] & 0xF) * 2);
930 if (au4GpioPinArray[i] > 111) {
931 u4AFnV3_U |= u4GpioPinAFValue;
932 u4Mask3_U |= u4GpioPinAFMask;
933 fgSet3_U = TRUE;
934 } else if (au4GpioPinArray[i] > 95) {
935 u4AFnV3_L |= u4GpioPinAFValue;
936 u4Mask3_L |= u4GpioPinAFMask;
937 fgSet3_L = TRUE;
938 } else if (au4GpioPinArray[i] > 79) {
939 u4AFnV2_U |= u4GpioPinAFValue;
940 u4Mask2_U |= u4GpioPinAFMask;
941 fgSet2_U = TRUE;
942 } else if (au4GpioPinArray[i] > 63) {
943 u4AFnV2_L |= u4GpioPinAFValue;
944 u4Mask2_L |= u4GpioPinAFMask;
945 fgSet2_L = TRUE;
946 } else if (au4GpioPinArray[i] > 47) {
947 u4AFnV1_U |= u4GpioPinAFValue;
948 u4Mask1_U |= u4GpioPinAFMask;
949 fgSet1_U = TRUE;
950 } else if (au4GpioPinArray[i] > 31) {
951 u4AFnV1_L |= u4GpioPinAFValue;
952 u4Mask1_L |= u4GpioPinAFMask;
953 fgSet1_L = TRUE;
954 } else if (au4GpioPinArray[i] > 15) {
955 u4AFnV0_U |= u4GpioPinAFValue;
956 u4Mask0_U |= u4GpioPinAFMask;
957 fgSet0_U = TRUE;
958 } else {
959 u4AFnV0_L |= u4GpioPinAFValue;
960 u4Mask0_L |= u4GpioPinAFMask;
961 fgSet0_L = TRUE;
962 }
963 }
964 if (fgSet3_U) {
965 prGPIO->GAFR3_U =
966 (((prGPIO->GAFR3_U & ~u4Mask3_U) | u4AFnV3_U) & ~GPIO_ALT_RESERVED_BITS);
967 }
968 if (fgSet3_L) {
969 prGPIO->GAFR3_L = ((prGPIO->GAFR3_L & ~u4Mask3_L) | u4AFnV3_L);
970 }
971 if (fgSet2_U) {
972 prGPIO->GAFR2_U = ((prGPIO->GAFR2_U & ~u4Mask2_U) | u4AFnV2_U);
973 }
974 if (fgSet2_L) {
975 prGPIO->GAFR2_L = ((prGPIO->GAFR2_L & ~u4Mask2_L) | u4AFnV2_L);
976 }
977 if (fgSet1_U) {
978 prGPIO->GAFR1_U = ((prGPIO->GAFR1_U & ~u4Mask1_U) | u4AFnV1_U);
979 }
980 if (fgSet1_L) {
981 prGPIO->GAFR1_L = ((prGPIO->GAFR1_L & ~u4Mask1_L) | u4AFnV1_L);
982 }
983 if (fgSet0_U) {
984 prGPIO->GAFR0_U = ((prGPIO->GAFR0_U & ~u4Mask0_U) | u4AFnV0_U);
985 }
986 if (fgSet0_L) {
987 prGPIO->GAFR0_L = ((prGPIO->GAFR0_L & ~u4Mask0_L) | u4AFnV0_L);
988 }
989} /* GpioSetAlternateFn */
990
991
992/*----------------------------------------------------------------------------*/
993/*!
994* \brief Enable Falling Edge Detect,
995* aGpioPinArray[]=array of GPIO pins,
996* aGpioPinArray[0] = size of array
997* \param[in] aGpioPinArray[] - array of GPIO pins
998*
999* \return none
1000*/
1001/*----------------------------------------------------------------------------*/
1002static VOID GpioSetFallingEdgeDetectEnable(P_GPIO_REG prGPIO, UINT_32 au4GpioPinArray[]
1003 )
1004{
1005 UINT_32 u4GpioPinMask;
1006 UINT_32 u4SizeArray;
1007 UINT_32 u4Mask0, u4Mask1, u4Mask2, u4Mask3;
1008 BOOL fgSet0, fgSet1, fgSet2, fgSet3;
1009 UINT_32 i;
1010
1011 ASSERT(prGPIO);
1012 ASSERT(au4GpioPinArray);
1013
1014 /* determine size of array */
1015 u4SizeArray = au4GpioPinArray[0];
1016 u4Mask0 = u4Mask1 = u4Mask2 = u4Mask3 = 0;
1017 fgSet0 = fgSet1 = fgSet2 = fgSet3 = FALSE;
1018
1019 for (i = 1; i <= u4SizeArray; i++) {
1020 u4GpioPinMask = 0x1u << (au4GpioPinArray[i] & 0x1F);
1021 if (au4GpioPinArray[i] > 95) {
1022 u4Mask3 |= u4GpioPinMask;
1023 fgSet3 = TRUE;
1024 } else if (au4GpioPinArray[i] > 63) {
1025 u4Mask2 |= u4GpioPinMask;
1026 fgSet2 = TRUE;
1027 } else if (au4GpioPinArray[i] > 31) {
1028 u4Mask1 |= u4GpioPinMask;
1029 fgSet1 = TRUE;
1030 } else {
1031 u4Mask0 |= u4GpioPinMask;
1032 fgSet0 = TRUE;
1033 }
1034 }
1035 if (fgSet3) {
1036 prGPIO->GFER3 = ((prGPIO->GFER3 | u4Mask3) & ~GPIO_PIN_RESERVED_BITS);
1037 }
1038 if (fgSet2) {
1039 prGPIO->GFER2 = ((prGPIO->GFER2) | u4Mask2);
1040 }
1041 if (fgSet1) {
1042 prGPIO->GFER1 = ((prGPIO->GFER1) | u4Mask1);
1043 }
1044 if (fgSet0) {
1045 prGPIO->GFER0 = ((prGPIO->GFER0) | u4Mask0);
1046 }
1047} /* GpioSetFallingEdgeDetectEnable */
1048
1049
1050/*----------------------------------------------------------------------------*/
1051/*!
1052* \brief Enable Initiate SPI interface for Intel PXA270
1053*
1054* \param[in] none
1055*
1056* \return none
1057*/
1058/*----------------------------------------------------------------------------*/
1059void platformBusInit(IN P_GLUE_INFO_T prGlueInfo)
1060{
1061 P_GL_HIF_INFO_T prHifInfo;
1062 UINT_32 u4Gpio, u4Irq = 0;
1063
1064 /* Memory Map */
1065 NDIS_PHYSICAL_ADDRESS CLKMGR_Base = { CLKMGR_BASE_ADD }; /* PA Clock Manager */
1066 NDIS_PHYSICAL_ADDRESS SSP_Base = { SSP_BASE_ADD }; /* SSP */
1067 NDIS_PHYSICAL_ADDRESS GPIO_Base = { GPIO_BASE_ADD }; /* GPIO */
1068
1069 /* Set GPIO mode */
1070 UINT_32 GpioDirOutList[] = { 3, GPIO23_SCLK, GPIO24_SFRM, GPIO25_STXD };
1071 UINT_32 GpioDirInList[] = { 2, GPIO26_SRXD, GPIO_INTR };
1072 UINT_32 GpioAltFnPinList[] =
1073 { 5, GPIO23_SCLK, GPIO24_SFRM, GPIO25_STXD, GPIO26_SRXD, GPIO_INTR };
1074 UINT_32 GpioAltFnValList[] = { 5, 2, 2, 2, 1, 1 };
1075 UINT_32 GpioAltFnIntPinList[] = { 1, GPIO_INTR }; /* interrupt */
1076
1077 DEBUGFUNC("windowsFindAdapter");
1078
1079 ASSERT(prGlueInfo);
1080
1081 prHifInfo = &prGlueInfo->rHifInfo;
1082
1083 /* Memory Map */
1084 pVClkMgr = (CLK_MGR *) MmMapIoSpace(CLKMGR_Base, sizeof(CLK_MGR), FALSE);
1085
1086 pVSsp = (SSP_REG *) MmMapIoSpace(SSP_Base, sizeof(SSP_REG), FALSE);
1087
1088 pVMem = (GPIO_REG *) MmMapIoSpace(GPIO_Base, sizeof(GPIO_REG), FALSE);
1089
1090 /* Backup GPIO config for restore when unload driver */
1091 GPIOConfigBackup();
1092
1093 /* The InterruptVector is the interrupt line that the card asserts to
1094 interrupt the system, and the InterruptLevel is ignored on Windows CE */
1095 u4Gpio = GPIO_INTR;
1096 KernelIoControl(IOCTL_HAL_GPIO2IRQ, (LPVOID) & u4Gpio, 1, (LPVOID) & u4Irq, 1, NULL);
1097 prHifInfo->u4InterruptVector = u4Irq; /* IRQ : 27:0x7a */
1098 prHifInfo->u4InterruptLevel = u4Irq; /* ignore : 27:0x7a */
1099 DbgPrint("GPIO INTR %d %d %x\n", GPIO_INTR, u4Gpio, u4Irq);
1100
1101 if (pVMem) {
1102 /* set GPIO mode */
1103 GpioSetDirectionIn((P_GPIO_REG) pVMem, GpioDirInList);
1104 GpioSetDirectionOut((P_GPIO_REG) pVMem, GpioDirOutList);
1105 GpioSetAlternateFn((P_GPIO_REG) pVMem, GpioAltFnPinList, GpioAltFnValList);
1106 GpioSetFallingEdgeDetectEnable((P_GPIO_REG) pVMem, GpioAltFnIntPinList); /* interrupt */
1107 }
1108
1109 if (pVSsp) {
1110 /* Configure SSP */
1111 pVClkMgr->cken |= CLKEN_SSP;
1112 pVSsp->sssr = 0;
1113
1114 pVSsp->sscr1 = 0;
1115 pVSsp->sscr1 = SSCR1_SPH | SSCR1_SPO | SSCR1_TTE; /* fifi TTE */
1116 pVSsp->sscr1 |= (3 << 6) | (0 << 10); /* TFT, RFT */
1117
1118 pVSsp->sscr0 = 0;
1119#if CONFIG_SPI_8_BIT_MODE
1120 pVSsp->sscr0 = SSCR0_DSS_8BIT | SSCR0_RIM;
1121#else
1122 pVSsp->sscr0 = SSCR0_EDSS | SSCR0_DSS_32BIT | SSCR0_RIM;
1123#endif
1124 pVSsp->sscr0 |= SSCR0_SSE; /* operation enable at least */
1125 }
1126
1127 /* Set operation mode */
1128 /* Intel PXA27x supports 4~32-bits mode */
1129 SpiSetOpMode();
1130
1131} /* platformBusInit */
1132
1133
1134/*----------------------------------------------------------------------------*/
1135/*!
1136* \brief The PROC function for backup GPIO configuration.
1137*
1138* This service save the preveous config of GPIO we will use.
1139* This procedure only present when initialization.
1140*
1141* \return (none)
1142*/
1143/*----------------------------------------------------------------------------*/
1144VOID GPIOConfigBackup(VOID)
1145{
1146 IO_GPDR0 = pVMem->GPDR0 & (BITS(23, 26) | IO_MASK_INTR); /* 23,24,25,26,intr */
1147 Fun_GAFR0_U = pVMem->GAFR0_U & (BITS(14, 21) | FUN_MASK_INTR); /* 23,24,25,26,intr */
1148} /* BackupGPIOConfig */
1149
1150
1151/*----------------------------------------------------------------------------*/
1152/*!
1153* \brief The PROC function for restore GPIO configuration.
1154*
1155* This service restore the preveous config of GPIO.
1156* This procedure only present when unload driver.
1157*
1158* \return (none)
1159*/
1160/*----------------------------------------------------------------------------*/
1161VOID GPIOConfigRestore(VOID)
1162{
1163 UINT_32 tempA = 0, tempB = 0;
1164
1165 tempA = IO_GPDR0 & (BITS(23, 26) | IO_MASK_INTR); /* 23,24,25,26,intr */
1166 tempB = pVMem->GPDR0 & ~(BITS(23, 26) | IO_MASK_INTR);
1167 pVMem->GPDR0 = tempA | tempB;
1168
1169 tempA = Fun_GAFR0_U & (BITS(14, 21) | FUN_MASK_INTR); /* 23,24,25,26,intr */
1170 tempB = pVMem->GAFR0_U & ~(BITS(14, 21) | FUN_MASK_INTR);
1171 pVMem->GAFR0_U = tempA | tempB;
1172} /* RestoreGPIOConfig */
kernel source for telekom puls (alcatel/mediatek)