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mfd: omap-usb-host: Use devm_gpio_request_one()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / omap-usb-host.c
CommitLineData
17cdd29d
KM		 1/**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/kernel.h>
417e206b 20#include <linux/module.h>
17cdd29d
KM		 21#include <linux/types.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
17cdd29d
KM		 24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
c05995c3 26#include <linux/gpio.h>
e8c4a7ac
FB		 27#include <linux/platform_device.h>
28#include <linux/platform_data/usb-omap.h>
1e7fe1a9 29#include <linux/pm_runtime.h>
17cdd29d 30
e8c4a7ac
FB		 31#include "omap-usb.h"
32
a6d3a662 33#define USBHS_DRIVER_NAME "usbhs_omap"
17cdd29d
KM		 34#define OMAP_EHCI_DEVICE "ehci-omap"
35#define OMAP_OHCI_DEVICE "ohci-omap3"
36
37/* OMAP USBHOST Register addresses */
38
17cdd29d
KM		 39/* UHH Register Set */
40#define OMAP_UHH_REVISION (0x00)
41#define OMAP_UHH_SYSCONFIG (0x10)
42#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
43#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
44#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
45#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
46#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
47#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
48
49#define OMAP_UHH_SYSSTATUS (0x14)
50#define OMAP_UHH_HOSTCONFIG (0x40)
51#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
52#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
53#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
54#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
55#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
56#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
57#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
58#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
59#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
60#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
61#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
62#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
63
64/* OMAP4-specific defines */
65#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
66#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
67#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
68#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
69#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
70
71#define OMAP4_P1_MODE_CLEAR (3 << 16)
72#define OMAP4_P1_MODE_TLL (1 << 16)
73#define OMAP4_P1_MODE_HSIC (3 << 16)
74#define OMAP4_P2_MODE_CLEAR (3 << 18)
75#define OMAP4_P2_MODE_TLL (1 << 18)
76#define OMAP4_P2_MODE_HSIC (3 << 18)
77
17cdd29d
KM		 78#define OMAP_UHH_DEBUG_CSR (0x44)
79
80/* Values of UHH_REVISION - Note: these are not given in the TRM */
81#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
82#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
83
84#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
85#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
86
87#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
88#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
89#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
90
91
92struct usbhs_hcd_omap {
d7eaf866 93 int nports;
06ba7dc7 94 struct clk **utmi_clk;
340c64ea
RQ		 95 struct clk **hsic60m_clk;
96 struct clk **hsic480m_clk;
d7eaf866 97
17cdd29d
KM		 98 struct clk *xclk60mhsp1_ck;
99 struct clk *xclk60mhsp2_ck;
06ba7dc7
RQ		 100 struct clk *utmi_p1_gfclk;
101 struct clk *utmi_p2_gfclk;
17cdd29d 102 struct clk *init_60m_fclk;
1e7fe1a9 103 struct clk *ehci_logic_fck;
17cdd29d
KM		 104
105 void __iomem *uhh_base;
17cdd29d 106
9d9c6ae7 107 struct usbhs_omap_platform_data *pdata;
17cdd29d
KM		 108
109 u32 usbhs_rev;
17cdd29d
KM		 110};
111/*-------------------------------------------------------------------------*/
112
113const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
cbb8c220 114static u64 usbhs_dmamask = DMA_BIT_MASK(32);
17cdd29d
KM		 115
116/*-------------------------------------------------------------------------*/
117
118static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
119{
120 __raw_writel(val, base + reg);
121}
122
123static inline u32 usbhs_read(void __iomem *base, u32 reg)
124{
125 return __raw_readl(base + reg);
126}
127
128static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
129{
130 __raw_writeb(val, base + reg);
131}
132
133static inline u8 usbhs_readb(void __iomem *base, u8 reg)
134{
135 return __raw_readb(base + reg);
136}
137
138/*-------------------------------------------------------------------------*/
139
140static struct platform_device *omap_usbhs_alloc_child(const char *name,
141 struct resource *res, int num_resources, void *pdata,
142 size_t pdata_size, struct device *dev)
143{
144 struct platform_device *child;
145 int ret;
146
147 child = platform_device_alloc(name, 0);
148
149 if (!child) {
150 dev_err(dev, "platform_device_alloc %s failed\n", name);
151 goto err_end;
152 }
153
154 ret = platform_device_add_resources(child, res, num_resources);
155 if (ret) {
156 dev_err(dev, "platform_device_add_resources failed\n");
157 goto err_alloc;
158 }
159
160 ret = platform_device_add_data(child, pdata, pdata_size);
161 if (ret) {
162 dev_err(dev, "platform_device_add_data failed\n");
163 goto err_alloc;
164 }
165
166 child->dev.dma_mask = &usbhs_dmamask;
cbb8c220 167 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
17cdd29d
KM		 168 child->dev.parent = dev;
169
170 ret = platform_device_add(child);
171 if (ret) {
172 dev_err(dev, "platform_device_add failed\n");
173 goto err_alloc;
174 }
175
176 return child;
177
178err_alloc:
179 platform_device_put(child);
180
181err_end:
182 return NULL;
183}
184
185static int omap_usbhs_alloc_children(struct platform_device *pdev)
186{
187 struct device *dev = &pdev->dev;
9d9c6ae7 188 struct usbhs_omap_platform_data *pdata = dev->platform_data;
17cdd29d
KM		 189 struct platform_device *ehci;
190 struct platform_device *ohci;
191 struct resource *res;
192 struct resource resources[2];
193 int ret;
194
17cdd29d
KM		 195 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
196 if (!res) {
197 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
198 ret = -ENODEV;
199 goto err_end;
200 }
201 resources[0] = *res;
202
203 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
204 if (!res) {
205 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
206 ret = -ENODEV;
207 goto err_end;
208 }
209 resources[1] = *res;
210
9d9c6ae7
RQ		 211 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
212 sizeof(*pdata), dev);
17cdd29d
KM		 213
214 if (!ehci) {
215 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 216 ret = -ENOMEM;
17cdd29d
KM		 217 goto err_end;
218 }
219
220 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
221 if (!res) {
222 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
223 ret = -ENODEV;
224 goto err_ehci;
225 }
226 resources[0] = *res;
227
228 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
229 if (!res) {
230 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
231 ret = -ENODEV;
232 goto err_ehci;
233 }
234 resources[1] = *res;
235
9d9c6ae7
RQ		 236 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
237 sizeof(*pdata), dev);
17cdd29d
KM		 238 if (!ohci) {
239 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 240 ret = -ENOMEM;
17cdd29d
KM		 241 goto err_ehci;
242 }
243
244 return 0;
245
246err_ehci:
d910774f 247 platform_device_unregister(ehci);
17cdd29d
KM		 248
249err_end:
250 return ret;
251}
252
17cdd29d
KM		 253static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
254{
255 switch (pmode) {
256 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
258 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
259 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
261 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
262 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
263 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
264 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
265 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
266 return true;
267
268 default:
269 return false;
270 }
271}
272
1e7fe1a9 273static int usbhs_runtime_resume(struct device *dev)
17cdd29d
KM		 274{
275 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 276 struct usbhs_omap_platform_data *pdata = omap->pdata;
06ba7dc7 277 int i, r;
1e7fe1a9
KM		 278
279 dev_dbg(dev, "usbhs_runtime_resume\n");
17cdd29d 280
4dc2cceb 281 omap_tll_enable();
17cdd29d 282
06ba7dc7 283 if (!IS_ERR(omap->ehci_logic_fck))
1e7fe1a9
KM		 284 clk_enable(omap->ehci_logic_fck);
285
06ba7dc7 286 for (i = 0; i < omap->nports; i++) {
340c64ea
RQ		 287 switch (pdata->port_mode[i]) {
288 case OMAP_EHCI_PORT_MODE_HSIC:
289 if (!IS_ERR(omap->hsic60m_clk[i])) {
290 r = clk_enable(omap->hsic60m_clk[i]);
291 if (r) {
292 dev_err(dev,
293 "Can't enable port %d hsic60m clk:%d\n",
294 i, r);
295 }
296 }
297
298 if (!IS_ERR(omap->hsic480m_clk[i])) {
299 r = clk_enable(omap->hsic480m_clk[i]);
300 if (r) {
301 dev_err(dev,
302 "Can't enable port %d hsic480m clk:%d\n",
303 i, r);
304 }
305 }
306 /* Fall through as HSIC mode needs utmi_clk */
307
308 case OMAP_EHCI_PORT_MODE_TLL:
309 if (!IS_ERR(omap->utmi_clk[i])) {
310 r = clk_enable(omap->utmi_clk[i]);
311 if (r) {
312 dev_err(dev,
313 "Can't enable port %d clk : %d\n",
314 i, r);
315 }
316 }
317 break;
318 default:
319 break;
320 }
06ba7dc7 321 }
1e7fe1a9 322
1e7fe1a9
KM		 323 return 0;
324}
325
326static int usbhs_runtime_suspend(struct device *dev)
327{
328 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 329 struct usbhs_omap_platform_data *pdata = omap->pdata;
06ba7dc7 330 int i;
1e7fe1a9
KM		 331
332 dev_dbg(dev, "usbhs_runtime_suspend\n");
333
06ba7dc7 334 for (i = 0; i < omap->nports; i++) {
340c64ea
RQ		 335 switch (pdata->port_mode[i]) {
336 case OMAP_EHCI_PORT_MODE_HSIC:
337 if (!IS_ERR(omap->hsic60m_clk[i]))
338 clk_disable(omap->hsic60m_clk[i]);
339
340 if (!IS_ERR(omap->hsic480m_clk[i]))
341 clk_disable(omap->hsic480m_clk[i]);
342 /* Fall through as utmi_clks were used in HSIC mode */
343
344 case OMAP_EHCI_PORT_MODE_TLL:
345 if (!IS_ERR(omap->utmi_clk[i]))
346 clk_disable(omap->utmi_clk[i]);
347 break;
348 default:
349 break;
350 }
06ba7dc7 351 }
1e7fe1a9 352
06ba7dc7 353 if (!IS_ERR(omap->ehci_logic_fck))
1e7fe1a9
KM		 354 clk_disable(omap->ehci_logic_fck);
355
4dc2cceb 356 omap_tll_disable();
1e7fe1a9
KM		 357
358 return 0;
359}
360
c4df00ae
RQ		 361static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
362 unsigned reg)
363{
364 struct usbhs_omap_platform_data *pdata = omap->pdata;
365 int i;
366
367 for (i = 0; i < omap->nports; i++) {
368 switch (pdata->port_mode[i]) {
369 case OMAP_USBHS_PORT_MODE_UNUSED:
370 reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
371 break;
372 case OMAP_EHCI_PORT_MODE_PHY:
373 if (pdata->single_ulpi_bypass)
374 break;
375
376 if (i == 0)
377 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
378 else
379 reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
380 << (i-1));
381 break;
382 default:
383 if (pdata->single_ulpi_bypass)
384 break;
385
386 if (i == 0)
387 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
388 else
389 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
390 << (i-1);
391 break;
392 }
393 }
394
395 if (pdata->single_ulpi_bypass) {
396 /* bypass ULPI only if none of the ports use PHY mode */
397 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
398
399 for (i = 0; i < omap->nports; i++) {
400 if (is_ehci_phy_mode(pdata->port_mode[i])) {
401 reg &= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
402 break;
403 }
404 }
405 }
406
407 return reg;
408}
409
410static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
411 unsigned reg)
412{
413 struct usbhs_omap_platform_data *pdata = omap->pdata;
414 int i;
415
416 for (i = 0; i < omap->nports; i++) {
417 /* Clear port mode fields for PHY mode */
418 reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
419
420 if (is_ehci_tll_mode(pdata->port_mode[i]) ||
421 (is_ohci_port(pdata->port_mode[i])))
422 reg |= OMAP4_P1_MODE_TLL << 2 * i;
423 else if (is_ehci_hsic_mode(pdata->port_mode[i]))
424 reg |= OMAP4_P1_MODE_HSIC << 2 * i;
425 }
426
427 return reg;
428}
429
1e7fe1a9
KM		 430static void omap_usbhs_init(struct device *dev)
431{
432 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 433 struct usbhs_omap_platform_data *pdata = omap->pdata;
1e7fe1a9
KM		 434 unsigned reg;
435
436 dev_dbg(dev, "starting TI HSUSB Controller\n");
437
9d9c6ae7
RQ		 438 if (pdata->phy_reset) {
439 if (gpio_is_valid(pdata->reset_gpio_port[0]))
71f4b9cd 440 devm_gpio_request_one(dev, pdata->reset_gpio_port[0],
c05995c3
RD		 441 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
442
9d9c6ae7 443 if (gpio_is_valid(pdata->reset_gpio_port[1]))
71f4b9cd 444 devm_gpio_request_one(dev, pdata->reset_gpio_port[1],
c05995c3
RD		 445 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
446
447 /* Hold the PHY in RESET for enough time till DIR is high */
448 udelay(10);
449 }
450
760189b3 451 pm_runtime_get_sync(dev);
17cdd29d 452
17cdd29d
KM		 453 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
454 /* setup ULPI bypass and burst configurations */
455 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
456 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
457 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
458 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
459 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
460
c4df00ae
RQ		 461 switch (omap->usbhs_rev) {
462 case OMAP_USBHS_REV1:
26bacba1 463 reg = omap_usbhs_rev1_hostconfig(omap, reg);
c4df00ae
RQ		 464 break;
465
466 case OMAP_USBHS_REV2:
26bacba1 467 reg = omap_usbhs_rev2_hostconfig(omap, reg);
c4df00ae
RQ		 468 break;
469
470 default: /* newer revisions */
26bacba1 471 reg = omap_usbhs_rev2_hostconfig(omap, reg);
c4df00ae 472 break;
17cdd29d
KM		 473 }
474
475 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
476 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
477
760189b3 478 pm_runtime_put_sync(dev);
9d9c6ae7 479 if (pdata->phy_reset) {
c05995c3
RD		 480 /* Hold the PHY in RESET for enough time till
481 * PHY is settled and ready
482 */
483 udelay(10);
484
9d9c6ae7 485 if (gpio_is_valid(pdata->reset_gpio_port[0]))
c05995c3 486 gpio_set_value_cansleep
9d9c6ae7 487 (pdata->reset_gpio_port[0], 1);
c05995c3 488
9d9c6ae7 489 if (gpio_is_valid(pdata->reset_gpio_port[1]))
c05995c3 490 gpio_set_value_cansleep
9d9c6ae7 491 (pdata->reset_gpio_port[1], 1);
c05995c3 492 }
1e7fe1a9
KM		 493}
494
1e7fe1a9
KM		 495/**
496 * usbhs_omap_probe - initialize TI-based HCDs
497 *
498 * Allocates basic resources for this USB host controller.
499 */
f791be49 500static int usbhs_omap_probe(struct platform_device *pdev)
17cdd29d 501{
1e7fe1a9
KM		 502 struct device *dev = &pdev->dev;
503 struct usbhs_omap_platform_data *pdata = dev->platform_data;
504 struct usbhs_hcd_omap *omap;
505 struct resource *res;
506 int ret = 0;
507 int i;
06ba7dc7 508 bool need_logic_fck;
17cdd29d 509
1e7fe1a9
KM		 510 if (!pdata) {
511 dev_err(dev, "Missing platform data\n");
27d4f2c6 512 return -ENODEV;
1e7fe1a9 513 }
17cdd29d 514
27d4f2c6 515 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
1e7fe1a9
KM		 516 if (!omap) {
517 dev_err(dev, "Memory allocation failed\n");
27d4f2c6
RQ		 518 return -ENOMEM;
519 }
520
521 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
522 omap->uhh_base = devm_request_and_ioremap(dev, res);
523 if (!omap->uhh_base) {
524 dev_err(dev, "Resource request/ioremap failed\n");
525 return -EADDRNOTAVAIL;
1e7fe1a9 526 }
17cdd29d 527
9d9c6ae7 528 omap->pdata = pdata;
17cdd29d 529
1e7fe1a9 530 pm_runtime_enable(dev);
17cdd29d 531
d7eaf866
RQ		 532 platform_set_drvdata(pdev, omap);
533 pm_runtime_get_sync(dev);
534
535 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
536
537 /* we need to call runtime suspend before we update omap->nports
538 * to prevent unbalanced clk_disable()
539 */
540 pm_runtime_put_sync(dev);
541
ccac71a7
RQ		 542 /*
543 * If platform data contains nports then use that
544 * else make out number of ports from USBHS revision
545 */
546 if (pdata->nports) {
547 omap->nports = pdata->nports;
548 } else {
549 switch (omap->usbhs_rev) {
550 case OMAP_USBHS_REV1:
551 omap->nports = 3;
552 break;
553 case OMAP_USBHS_REV2:
554 omap->nports = 2;
555 break;
556 default:
557 omap->nports = OMAP3_HS_USB_PORTS;
558 dev_dbg(dev,
559 "USB HOST Rev:0x%d not recognized, assuming %d ports\n",
560 omap->usbhs_rev, omap->nports);
561 break;
562 }
d7eaf866
RQ		 563 }
564
06ba7dc7
RQ		 565 i = sizeof(struct clk *) * omap->nports;
566 omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
340c64ea
RQ		 567 omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
568 omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
569
570 if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
06ba7dc7
RQ		 571 dev_err(dev, "Memory allocation failed\n");
572 ret = -ENOMEM;
573 goto err_mem;
574 }
575
576 need_logic_fck = false;
577 for (i = 0; i < omap->nports; i++) {
1e7fe1a9 578 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
06ba7dc7
RQ		 579 is_ehci_hsic_mode(i))
580 need_logic_fck |= true;
581 }
582
583 omap->ehci_logic_fck = ERR_PTR(-EINVAL);
584 if (need_logic_fck) {
585 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
586 if (IS_ERR(omap->ehci_logic_fck)) {
587 ret = PTR_ERR(omap->ehci_logic_fck);
588 dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
1e7fe1a9 589 }
06ba7dc7 590 }
17cdd29d 591
06ba7dc7
RQ		 592 omap->utmi_p1_gfclk = clk_get(dev, "utmi_p1_gfclk");
593 if (IS_ERR(omap->utmi_p1_gfclk)) {
594 ret = PTR_ERR(omap->utmi_p1_gfclk);
595 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
596 goto err_p1_gfclk;
597 }
598
599 omap->utmi_p2_gfclk = clk_get(dev, "utmi_p2_gfclk");
600 if (IS_ERR(omap->utmi_p2_gfclk)) {
601 ret = PTR_ERR(omap->utmi_p2_gfclk);
602 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
603 goto err_p2_gfclk;
17cdd29d
KM		 604 }
605
1e7fe1a9
KM		 606 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
607 if (IS_ERR(omap->xclk60mhsp1_ck)) {
608 ret = PTR_ERR(omap->xclk60mhsp1_ck);
609 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
06ba7dc7 610 goto err_xclk60mhsp1;
17cdd29d
KM		 611 }
612
1e7fe1a9
KM		 613 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
614 if (IS_ERR(omap->xclk60mhsp2_ck)) {
615 ret = PTR_ERR(omap->xclk60mhsp2_ck);
616 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
06ba7dc7 617 goto err_xclk60mhsp2;
17cdd29d
KM		 618 }
619
1e7fe1a9
KM		 620 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
621 if (IS_ERR(omap->init_60m_fclk)) {
622 ret = PTR_ERR(omap->init_60m_fclk);
623 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
06ba7dc7
RQ		 624 goto err_init60m;
625 }
626
627 for (i = 0; i < omap->nports; i++) {
340c64ea 628 char clkname[30];
06ba7dc7
RQ		 629
630 /* clock names are indexed from 1*/
631 snprintf(clkname, sizeof(clkname),
632 "usb_host_hs_utmi_p%d_clk", i + 1);
633
634 /* If a clock is not found we won't bail out as not all
635 * platforms have all clocks and we can function without
636 * them
637 */
638 omap->utmi_clk[i] = clk_get(dev, clkname);
639 if (IS_ERR(omap->utmi_clk[i]))
640 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
641 clkname, PTR_ERR(omap->utmi_clk[i]));
340c64ea
RQ		 642
643 snprintf(clkname, sizeof(clkname),
644 "usb_host_hs_hsic480m_p%d_clk", i + 1);
645 omap->hsic480m_clk[i] = clk_get(dev, clkname);
646 if (IS_ERR(omap->hsic480m_clk[i]))
647 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
648 clkname, PTR_ERR(omap->hsic480m_clk[i]));
649
650 snprintf(clkname, sizeof(clkname),
651 "usb_host_hs_hsic60m_p%d_clk", i + 1);
652 omap->hsic60m_clk[i] = clk_get(dev, clkname);
653 if (IS_ERR(omap->hsic60m_clk[i]))
654 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
655 clkname, PTR_ERR(omap->hsic60m_clk[i]));
17cdd29d
KM		 656 }
657
1e7fe1a9 658 if (is_ehci_phy_mode(pdata->port_mode[0])) {
a8c4e9e1 659 /* for OMAP3, clk_set_parent fails */
06ba7dc7 660 ret = clk_set_parent(omap->utmi_p1_gfclk,
1e7fe1a9
KM		 661 omap->xclk60mhsp1_ck);
662 if (ret != 0)
a8c4e9e1
RQ		 663 dev_dbg(dev, "xclk60mhsp1_ck set parent failed: %d\n",
664 ret);
1e7fe1a9 665 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
06ba7dc7 666 ret = clk_set_parent(omap->utmi_p1_gfclk,
1e7fe1a9
KM		 667 omap->init_60m_fclk);
668 if (ret != 0)
a8c4e9e1
RQ		 669 dev_dbg(dev, "P0 init_60m_fclk set parent failed: %d\n",
670 ret);
1e7fe1a9 671 }
17cdd29d 672
1e7fe1a9 673 if (is_ehci_phy_mode(pdata->port_mode[1])) {
06ba7dc7 674 ret = clk_set_parent(omap->utmi_p2_gfclk,
1e7fe1a9
KM		 675 omap->xclk60mhsp2_ck);
676 if (ret != 0)
a8c4e9e1
RQ		 677 dev_dbg(dev, "xclk60mhsp2_ck set parent failed: %d\n",
678 ret);
1e7fe1a9 679 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
06ba7dc7 680 ret = clk_set_parent(omap->utmi_p2_gfclk,
1e7fe1a9
KM		 681 omap->init_60m_fclk);
682 if (ret != 0)
a8c4e9e1
RQ		 683 dev_dbg(dev, "P1 init_60m_fclk set parent failed: %d\n",
684 ret);
1e7fe1a9 685 }
6eb6fbbf 686
f0447a69 687 omap_usbhs_init(dev);
1e7fe1a9
KM		 688 ret = omap_usbhs_alloc_children(pdev);
689 if (ret) {
690 dev_err(dev, "omap_usbhs_alloc_children failed\n");
691 goto err_alloc;
692 }
693
27d4f2c6 694 return 0;
1e7fe1a9
KM		 695
696err_alloc:
340c64ea 697 for (i = 0; i < omap->nports; i++) {
06ba7dc7
RQ		 698 if (!IS_ERR(omap->utmi_clk[i]))
699 clk_put(omap->utmi_clk[i]);
340c64ea
RQ		 700 if (!IS_ERR(omap->hsic60m_clk[i]))
701 clk_put(omap->hsic60m_clk[i]);
702 if (!IS_ERR(omap->hsic480m_clk[i]))
703 clk_put(omap->hsic480m_clk[i]);
704 }
1e7fe1a9 705
06ba7dc7 706 clk_put(omap->init_60m_fclk);
1e7fe1a9 707
06ba7dc7 708err_init60m:
1e7fe1a9
KM		 709 clk_put(omap->xclk60mhsp2_ck);
710
06ba7dc7 711err_xclk60mhsp2:
1e7fe1a9
KM		 712 clk_put(omap->xclk60mhsp1_ck);
713
06ba7dc7
RQ		 714err_xclk60mhsp1:
715 clk_put(omap->utmi_p2_gfclk);
1e7fe1a9 716
06ba7dc7
RQ		 717err_p2_gfclk:
718 clk_put(omap->utmi_p1_gfclk);
719
720err_p1_gfclk:
721 if (!IS_ERR(omap->ehci_logic_fck))
722 clk_put(omap->ehci_logic_fck);
723
724err_mem:
1e7fe1a9 725 pm_runtime_disable(dev);
1e7fe1a9 726
1e7fe1a9 727 return ret;
17cdd29d 728}
17cdd29d 729
1e7fe1a9
KM		 730/**
731 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
732 * @pdev: USB Host Controller being removed
733 *
734 * Reverses the effect of usbhs_omap_probe().
735 */
4740f73f 736static int usbhs_omap_remove(struct platform_device *pdev)
17cdd29d 737{
1e7fe1a9 738 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
06ba7dc7 739 int i;
1e7fe1a9 740
340c64ea 741 for (i = 0; i < omap->nports; i++) {
06ba7dc7
RQ		 742 if (!IS_ERR(omap->utmi_clk[i]))
743 clk_put(omap->utmi_clk[i]);
340c64ea
RQ		 744 if (!IS_ERR(omap->hsic60m_clk[i]))
745 clk_put(omap->hsic60m_clk[i]);
746 if (!IS_ERR(omap->hsic480m_clk[i]))
747 clk_put(omap->hsic480m_clk[i]);
748 }
06ba7dc7 749
1e7fe1a9 750 clk_put(omap->init_60m_fclk);
06ba7dc7
RQ		 751 clk_put(omap->utmi_p1_gfclk);
752 clk_put(omap->utmi_p2_gfclk);
1e7fe1a9 753 clk_put(omap->xclk60mhsp2_ck);
1e7fe1a9 754 clk_put(omap->xclk60mhsp1_ck);
06ba7dc7
RQ		 755
756 if (!IS_ERR(omap->ehci_logic_fck))
757 clk_put(omap->ehci_logic_fck);
758
1e7fe1a9 759 pm_runtime_disable(&pdev->dev);
1e7fe1a9
KM		 760
761 return 0;
17cdd29d 762}
1e7fe1a9
KM		 763
764static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
765 .runtime_suspend = usbhs_runtime_suspend,
766 .runtime_resume = usbhs_runtime_resume,
767};
17cdd29d
KM		 768
769static struct platform_driver usbhs_omap_driver = {
770 .driver = {
771 .name = (char *)usbhs_driver_name,
772 .owner = THIS_MODULE,
1e7fe1a9 773 .pm = &usbhsomap_dev_pm_ops,
17cdd29d 774 },
ab3f2a86 775 .remove = usbhs_omap_remove,
17cdd29d
KM		 776};
777
778MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
779MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
780MODULE_LICENSE("GPL v2");
781MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
782
783static int __init omap_usbhs_drvinit(void)
784{
785 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
786}
787
788/*
789 * init before ehci and ohci drivers;
790 * The usbhs core driver should be initialized much before
791 * the omap ehci and ohci probe functions are called.
4dc2cceb
KM		 792 * This usbhs core driver should be initialized after
793 * usb tll driver
17cdd29d 794 */
4dc2cceb 795fs_initcall_sync(omap_usbhs_drvinit);
17cdd29d
KM		 796
797static void __exit omap_usbhs_drvexit(void)
798{
799 platform_driver_unregister(&usbhs_omap_driver);
800}
801module_exit(omap_usbhs_drvexit);
kernel source for telekom puls (alcatel/mediatek)