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mfd: omap-usb-host: Use devm_kzalloc() and devm_request_and_ioremap()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / omap-usb-host.c
CommitLineData
17cdd29d
KM		 1/**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/kernel.h>
417e206b 20#include <linux/module.h>
17cdd29d
KM		 21#include <linux/types.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
17cdd29d
KM		 24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
26#include <linux/spinlock.h>
c05995c3 27#include <linux/gpio.h>
e8c4a7ac
FB		 28#include <linux/platform_device.h>
29#include <linux/platform_data/usb-omap.h>
1e7fe1a9 30#include <linux/pm_runtime.h>
17cdd29d 31
e8c4a7ac
FB		 32#include "omap-usb.h"
33
a6d3a662 34#define USBHS_DRIVER_NAME "usbhs_omap"
17cdd29d
KM		 35#define OMAP_EHCI_DEVICE "ehci-omap"
36#define OMAP_OHCI_DEVICE "ohci-omap3"
37
38/* OMAP USBHOST Register addresses */
39
17cdd29d
KM		 40/* UHH Register Set */
41#define OMAP_UHH_REVISION (0x00)
42#define OMAP_UHH_SYSCONFIG (0x10)
43#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
44#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
45#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
46#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
47#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
48#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
49
50#define OMAP_UHH_SYSSTATUS (0x14)
51#define OMAP_UHH_HOSTCONFIG (0x40)
52#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
53#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
54#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
55#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
56#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
57#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
58#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
59#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
60#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
61#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
62#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
63#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
64
65/* OMAP4-specific defines */
66#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
67#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
68#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
69#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
70#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
71
72#define OMAP4_P1_MODE_CLEAR (3 << 16)
73#define OMAP4_P1_MODE_TLL (1 << 16)
74#define OMAP4_P1_MODE_HSIC (3 << 16)
75#define OMAP4_P2_MODE_CLEAR (3 << 18)
76#define OMAP4_P2_MODE_TLL (1 << 18)
77#define OMAP4_P2_MODE_HSIC (3 << 18)
78
17cdd29d
KM		 79#define OMAP_UHH_DEBUG_CSR (0x44)
80
81/* Values of UHH_REVISION - Note: these are not given in the TRM */
82#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
83#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
84
85#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
86#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
87
88#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
89#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
90#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
91
92
93struct usbhs_hcd_omap {
17cdd29d
KM		 94 struct clk *xclk60mhsp1_ck;
95 struct clk *xclk60mhsp2_ck;
96 struct clk *utmi_p1_fck;
97 struct clk *usbhost_p1_fck;
17cdd29d
KM		 98 struct clk *utmi_p2_fck;
99 struct clk *usbhost_p2_fck;
17cdd29d 100 struct clk *init_60m_fclk;
1e7fe1a9 101 struct clk *ehci_logic_fck;
17cdd29d
KM		 102
103 void __iomem *uhh_base;
17cdd29d 104
9d9c6ae7 105 struct usbhs_omap_platform_data *pdata;
17cdd29d
KM		 106
107 u32 usbhs_rev;
108 spinlock_t lock;
17cdd29d
KM		 109};
110/*-------------------------------------------------------------------------*/
111
112const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
cbb8c220 113static u64 usbhs_dmamask = DMA_BIT_MASK(32);
17cdd29d
KM		 114
115/*-------------------------------------------------------------------------*/
116
117static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
118{
119 __raw_writel(val, base + reg);
120}
121
122static inline u32 usbhs_read(void __iomem *base, u32 reg)
123{
124 return __raw_readl(base + reg);
125}
126
127static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
128{
129 __raw_writeb(val, base + reg);
130}
131
132static inline u8 usbhs_readb(void __iomem *base, u8 reg)
133{
134 return __raw_readb(base + reg);
135}
136
137/*-------------------------------------------------------------------------*/
138
139static struct platform_device *omap_usbhs_alloc_child(const char *name,
140 struct resource *res, int num_resources, void *pdata,
141 size_t pdata_size, struct device *dev)
142{
143 struct platform_device *child;
144 int ret;
145
146 child = platform_device_alloc(name, 0);
147
148 if (!child) {
149 dev_err(dev, "platform_device_alloc %s failed\n", name);
150 goto err_end;
151 }
152
153 ret = platform_device_add_resources(child, res, num_resources);
154 if (ret) {
155 dev_err(dev, "platform_device_add_resources failed\n");
156 goto err_alloc;
157 }
158
159 ret = platform_device_add_data(child, pdata, pdata_size);
160 if (ret) {
161 dev_err(dev, "platform_device_add_data failed\n");
162 goto err_alloc;
163 }
164
165 child->dev.dma_mask = &usbhs_dmamask;
cbb8c220 166 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
17cdd29d
KM		 167 child->dev.parent = dev;
168
169 ret = platform_device_add(child);
170 if (ret) {
171 dev_err(dev, "platform_device_add failed\n");
172 goto err_alloc;
173 }
174
175 return child;
176
177err_alloc:
178 platform_device_put(child);
179
180err_end:
181 return NULL;
182}
183
184static int omap_usbhs_alloc_children(struct platform_device *pdev)
185{
186 struct device *dev = &pdev->dev;
9d9c6ae7 187 struct usbhs_omap_platform_data *pdata = dev->platform_data;
17cdd29d
KM		 188 struct platform_device *ehci;
189 struct platform_device *ohci;
190 struct resource *res;
191 struct resource resources[2];
192 int ret;
193
17cdd29d
KM		 194 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
195 if (!res) {
196 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
197 ret = -ENODEV;
198 goto err_end;
199 }
200 resources[0] = *res;
201
202 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
203 if (!res) {
204 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
205 ret = -ENODEV;
206 goto err_end;
207 }
208 resources[1] = *res;
209
9d9c6ae7
RQ		 210 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
211 sizeof(*pdata), dev);
17cdd29d
KM		 212
213 if (!ehci) {
214 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 215 ret = -ENOMEM;
17cdd29d
KM		 216 goto err_end;
217 }
218
219 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
220 if (!res) {
221 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
222 ret = -ENODEV;
223 goto err_ehci;
224 }
225 resources[0] = *res;
226
227 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
228 if (!res) {
229 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
230 ret = -ENODEV;
231 goto err_ehci;
232 }
233 resources[1] = *res;
234
9d9c6ae7
RQ		 235 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
236 sizeof(*pdata), dev);
17cdd29d
KM		 237 if (!ohci) {
238 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 239 ret = -ENOMEM;
17cdd29d
KM		 240 goto err_ehci;
241 }
242
243 return 0;
244
245err_ehci:
d910774f 246 platform_device_unregister(ehci);
17cdd29d
KM		 247
248err_end:
249 return ret;
250}
251
17cdd29d
KM		 252static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
253{
254 switch (pmode) {
255 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
256 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
257 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
258 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
259 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
261 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
262 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
263 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
264 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
265 return true;
266
267 default:
268 return false;
269 }
270}
271
1e7fe1a9 272static int usbhs_runtime_resume(struct device *dev)
17cdd29d
KM		 273{
274 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 275 struct usbhs_omap_platform_data *pdata = omap->pdata;
1e7fe1a9
KM		 276 unsigned long flags;
277
278 dev_dbg(dev, "usbhs_runtime_resume\n");
17cdd29d 279
4dc2cceb 280 omap_tll_enable();
17cdd29d 281 spin_lock_irqsave(&omap->lock, flags);
17cdd29d 282
1e7fe1a9
KM		 283 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
284 clk_enable(omap->ehci_logic_fck);
285
760189b3 286 if (is_ehci_tll_mode(pdata->port_mode[0]))
1e7fe1a9 287 clk_enable(omap->usbhost_p1_fck);
760189b3 288 if (is_ehci_tll_mode(pdata->port_mode[1]))
1e7fe1a9 289 clk_enable(omap->usbhost_p2_fck);
760189b3 290
1e7fe1a9
KM		 291 clk_enable(omap->utmi_p1_fck);
292 clk_enable(omap->utmi_p2_fck);
293
294 spin_unlock_irqrestore(&omap->lock, flags);
295
296 return 0;
297}
298
299static int usbhs_runtime_suspend(struct device *dev)
300{
301 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 302 struct usbhs_omap_platform_data *pdata = omap->pdata;
1e7fe1a9
KM		 303 unsigned long flags;
304
305 dev_dbg(dev, "usbhs_runtime_suspend\n");
306
1e7fe1a9
KM		 307 spin_lock_irqsave(&omap->lock, flags);
308
760189b3 309 if (is_ehci_tll_mode(pdata->port_mode[0]))
1e7fe1a9 310 clk_disable(omap->usbhost_p1_fck);
760189b3 311 if (is_ehci_tll_mode(pdata->port_mode[1]))
1e7fe1a9 312 clk_disable(omap->usbhost_p2_fck);
760189b3 313
1e7fe1a9
KM		 314 clk_disable(omap->utmi_p2_fck);
315 clk_disable(omap->utmi_p1_fck);
316
317 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
318 clk_disable(omap->ehci_logic_fck);
319
320 spin_unlock_irqrestore(&omap->lock, flags);
4dc2cceb 321 omap_tll_disable();
1e7fe1a9
KM		 322
323 return 0;
324}
325
326static void omap_usbhs_init(struct device *dev)
327{
328 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 329 struct usbhs_omap_platform_data *pdata = omap->pdata;
1e7fe1a9
KM		 330 unsigned long flags;
331 unsigned reg;
332
333 dev_dbg(dev, "starting TI HSUSB Controller\n");
334
9d9c6ae7
RQ		 335 if (pdata->phy_reset) {
336 if (gpio_is_valid(pdata->reset_gpio_port[0]))
337 gpio_request_one(pdata->reset_gpio_port[0],
c05995c3
RD		 338 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
339
9d9c6ae7
RQ		 340 if (gpio_is_valid(pdata->reset_gpio_port[1]))
341 gpio_request_one(pdata->reset_gpio_port[1],
c05995c3
RD		 342 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
343
344 /* Hold the PHY in RESET for enough time till DIR is high */
345 udelay(10);
346 }
347
760189b3 348 pm_runtime_get_sync(dev);
c05995c3 349 spin_lock_irqsave(&omap->lock, flags);
17cdd29d
KM		 350 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
351 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
352
17cdd29d
KM		 353 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
354 /* setup ULPI bypass and burst configurations */
355 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
356 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
357 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
358 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
359 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
360
361 if (is_omap_usbhs_rev1(omap)) {
362 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
363 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
364 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
365 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
366 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
367 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
368
369 /* Bypass the TLL module for PHY mode operation */
63b68901 370 if (pdata->single_ulpi_bypass) {
17cdd29d
KM		 371 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
372 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
373 is_ehci_phy_mode(pdata->port_mode[1]) ||
374 is_ehci_phy_mode(pdata->port_mode[2]))
375 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
376 else
377 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
378 } else {
379 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
380 if (is_ehci_phy_mode(pdata->port_mode[0]))
381 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
382 else
383 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
384 if (is_ehci_phy_mode(pdata->port_mode[1]))
385 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
386 else
387 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
388 if (is_ehci_phy_mode(pdata->port_mode[2]))
389 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
390 else
391 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
392 }
393 } else if (is_omap_usbhs_rev2(omap)) {
394 /* Clear port mode fields for PHY mode*/
395 reg &= ~OMAP4_P1_MODE_CLEAR;
396 reg &= ~OMAP4_P2_MODE_CLEAR;
397
17cdd29d
KM		 398 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
399 (is_ohci_port(pdata->port_mode[0])))
400 reg |= OMAP4_P1_MODE_TLL;
401 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
402 reg |= OMAP4_P1_MODE_HSIC;
403
404 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
405 (is_ohci_port(pdata->port_mode[1])))
406 reg |= OMAP4_P2_MODE_TLL;
407 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
408 reg |= OMAP4_P2_MODE_HSIC;
409 }
410
411 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
412 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
413
d11536e4 414 spin_unlock_irqrestore(&omap->lock, flags);
c05995c3 415
760189b3 416 pm_runtime_put_sync(dev);
9d9c6ae7 417 if (pdata->phy_reset) {
c05995c3
RD		 418 /* Hold the PHY in RESET for enough time till
419 * PHY is settled and ready
420 */
421 udelay(10);
422
9d9c6ae7 423 if (gpio_is_valid(pdata->reset_gpio_port[0]))
c05995c3 424 gpio_set_value_cansleep
9d9c6ae7 425 (pdata->reset_gpio_port[0], 1);
c05995c3 426
9d9c6ae7 427 if (gpio_is_valid(pdata->reset_gpio_port[1]))
c05995c3 428 gpio_set_value_cansleep
9d9c6ae7 429 (pdata->reset_gpio_port[1], 1);
c05995c3 430 }
1e7fe1a9
KM		 431}
432
c05995c3
RD		 433static void omap_usbhs_deinit(struct device *dev)
434{
435 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 436 struct usbhs_omap_platform_data *pdata = omap->pdata;
c05995c3 437
9d9c6ae7
RQ		 438 if (pdata->phy_reset) {
439 if (gpio_is_valid(pdata->reset_gpio_port[0]))
440 gpio_free(pdata->reset_gpio_port[0]);
c05995c3 441
9d9c6ae7
RQ		 442 if (gpio_is_valid(pdata->reset_gpio_port[1]))
443 gpio_free(pdata->reset_gpio_port[1]);
c05995c3
RD		 444 }
445}
446
1e7fe1a9
KM		 447
448/**
449 * usbhs_omap_probe - initialize TI-based HCDs
450 *
451 * Allocates basic resources for this USB host controller.
452 */
f791be49 453static int usbhs_omap_probe(struct platform_device *pdev)
17cdd29d 454{
1e7fe1a9
KM		 455 struct device *dev = &pdev->dev;
456 struct usbhs_omap_platform_data *pdata = dev->platform_data;
457 struct usbhs_hcd_omap *omap;
458 struct resource *res;
459 int ret = 0;
460 int i;
17cdd29d 461
1e7fe1a9
KM		 462 if (!pdata) {
463 dev_err(dev, "Missing platform data\n");
27d4f2c6 464 return -ENODEV;
1e7fe1a9 465 }
17cdd29d 466
27d4f2c6 467 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
1e7fe1a9
KM		 468 if (!omap) {
469 dev_err(dev, "Memory allocation failed\n");
27d4f2c6
RQ		 470 return -ENOMEM;
471 }
472
473 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
474 omap->uhh_base = devm_request_and_ioremap(dev, res);
475 if (!omap->uhh_base) {
476 dev_err(dev, "Resource request/ioremap failed\n");
477 return -EADDRNOTAVAIL;
1e7fe1a9 478 }
17cdd29d 479
1e7fe1a9 480 spin_lock_init(&omap->lock);
17cdd29d 481
9d9c6ae7 482 omap->pdata = pdata;
17cdd29d 483
1e7fe1a9 484 pm_runtime_enable(dev);
17cdd29d 485
1e7fe1a9
KM		 486 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
487 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
488 is_ehci_hsic_mode(i)) {
489 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
490 if (IS_ERR(omap->ehci_logic_fck)) {
491 ret = PTR_ERR(omap->ehci_logic_fck);
492 dev_warn(dev, "ehci_logic_fck failed:%d\n",
493 ret);
494 }
495 break;
496 }
17cdd29d 497
1e7fe1a9
KM		 498 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
499 if (IS_ERR(omap->utmi_p1_fck)) {
500 ret = PTR_ERR(omap->utmi_p1_fck);
501 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
502 goto err_end;
17cdd29d
KM		 503 }
504
1e7fe1a9
KM		 505 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
506 if (IS_ERR(omap->xclk60mhsp1_ck)) {
507 ret = PTR_ERR(omap->xclk60mhsp1_ck);
508 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
509 goto err_utmi_p1_fck;
510 }
17cdd29d 511
1e7fe1a9
KM		 512 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
513 if (IS_ERR(omap->utmi_p2_fck)) {
514 ret = PTR_ERR(omap->utmi_p2_fck);
515 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
516 goto err_xclk60mhsp1_ck;
17cdd29d
KM		 517 }
518
1e7fe1a9
KM		 519 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
520 if (IS_ERR(omap->xclk60mhsp2_ck)) {
521 ret = PTR_ERR(omap->xclk60mhsp2_ck);
522 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
523 goto err_utmi_p2_fck;
524 }
17cdd29d 525
1e7fe1a9
KM		 526 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
527 if (IS_ERR(omap->usbhost_p1_fck)) {
528 ret = PTR_ERR(omap->usbhost_p1_fck);
529 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
530 goto err_xclk60mhsp2_ck;
17cdd29d
KM		 531 }
532
1e7fe1a9
KM		 533 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
534 if (IS_ERR(omap->usbhost_p2_fck)) {
535 ret = PTR_ERR(omap->usbhost_p2_fck);
536 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
760189b3 537 goto err_usbhost_p1_fck;
17cdd29d
KM		 538 }
539
1e7fe1a9
KM		 540 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
541 if (IS_ERR(omap->init_60m_fclk)) {
542 ret = PTR_ERR(omap->init_60m_fclk);
543 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
760189b3 544 goto err_usbhost_p2_fck;
17cdd29d
KM		 545 }
546
1e7fe1a9
KM		 547 if (is_ehci_phy_mode(pdata->port_mode[0])) {
548 /* for OMAP3 , the clk set paretn fails */
549 ret = clk_set_parent(omap->utmi_p1_fck,
550 omap->xclk60mhsp1_ck);
551 if (ret != 0)
552 dev_err(dev, "xclk60mhsp1_ck set parent"
553 "failed error:%d\n", ret);
554 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
555 ret = clk_set_parent(omap->utmi_p1_fck,
556 omap->init_60m_fclk);
557 if (ret != 0)
558 dev_err(dev, "init_60m_fclk set parent"
559 "failed error:%d\n", ret);
560 }
17cdd29d 561
1e7fe1a9
KM		 562 if (is_ehci_phy_mode(pdata->port_mode[1])) {
563 ret = clk_set_parent(omap->utmi_p2_fck,
564 omap->xclk60mhsp2_ck);
565 if (ret != 0)
566 dev_err(dev, "xclk60mhsp2_ck set parent"
567 "failed error:%d\n", ret);
568 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
569 ret = clk_set_parent(omap->utmi_p2_fck,
570 omap->init_60m_fclk);
571 if (ret != 0)
572 dev_err(dev, "init_60m_fclk set parent"
573 "failed error:%d\n", ret);
574 }
6eb6fbbf 575
1e7fe1a9
KM		 576 platform_set_drvdata(pdev, omap);
577
f0447a69 578 omap_usbhs_init(dev);
1e7fe1a9
KM		 579 ret = omap_usbhs_alloc_children(pdev);
580 if (ret) {
581 dev_err(dev, "omap_usbhs_alloc_children failed\n");
582 goto err_alloc;
583 }
584
27d4f2c6 585 return 0;
1e7fe1a9
KM		 586
587err_alloc:
c05995c3 588 omap_usbhs_deinit(&pdev->dev);
1e7fe1a9
KM		 589 clk_put(omap->init_60m_fclk);
590
1e7fe1a9
KM		 591err_usbhost_p2_fck:
592 clk_put(omap->usbhost_p2_fck);
593
1e7fe1a9
KM		 594err_usbhost_p1_fck:
595 clk_put(omap->usbhost_p1_fck);
596
597err_xclk60mhsp2_ck:
598 clk_put(omap->xclk60mhsp2_ck);
599
600err_utmi_p2_fck:
601 clk_put(omap->utmi_p2_fck);
602
603err_xclk60mhsp1_ck:
604 clk_put(omap->xclk60mhsp1_ck);
605
606err_utmi_p1_fck:
607 clk_put(omap->utmi_p1_fck);
608
609err_end:
610 clk_put(omap->ehci_logic_fck);
611 pm_runtime_disable(dev);
1e7fe1a9 612
1e7fe1a9 613 return ret;
17cdd29d 614}
17cdd29d 615
1e7fe1a9
KM		 616/**
617 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
618 * @pdev: USB Host Controller being removed
619 *
620 * Reverses the effect of usbhs_omap_probe().
621 */
4740f73f 622static int usbhs_omap_remove(struct platform_device *pdev)
17cdd29d 623{
1e7fe1a9
KM		 624 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
625
c05995c3 626 omap_usbhs_deinit(&pdev->dev);
1e7fe1a9 627 clk_put(omap->init_60m_fclk);
1e7fe1a9 628 clk_put(omap->usbhost_p2_fck);
1e7fe1a9
KM		 629 clk_put(omap->usbhost_p1_fck);
630 clk_put(omap->xclk60mhsp2_ck);
631 clk_put(omap->utmi_p2_fck);
632 clk_put(omap->xclk60mhsp1_ck);
633 clk_put(omap->utmi_p1_fck);
634 clk_put(omap->ehci_logic_fck);
635 pm_runtime_disable(&pdev->dev);
1e7fe1a9
KM		 636
637 return 0;
17cdd29d 638}
1e7fe1a9
KM		 639
640static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
641 .runtime_suspend = usbhs_runtime_suspend,
642 .runtime_resume = usbhs_runtime_resume,
643};
17cdd29d
KM		 644
645static struct platform_driver usbhs_omap_driver = {
646 .driver = {
647 .name = (char *)usbhs_driver_name,
648 .owner = THIS_MODULE,
1e7fe1a9 649 .pm = &usbhsomap_dev_pm_ops,
17cdd29d
KM		 650 },
651 .remove = __exit_p(usbhs_omap_remove),
652};
653
654MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
655MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
656MODULE_LICENSE("GPL v2");
657MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
658
659static int __init omap_usbhs_drvinit(void)
660{
661 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
662}
663
664/*
665 * init before ehci and ohci drivers;
666 * The usbhs core driver should be initialized much before
667 * the omap ehci and ohci probe functions are called.
4dc2cceb
KM		 668 * This usbhs core driver should be initialized after
669 * usb tll driver
17cdd29d 670 */
4dc2cceb 671fs_initcall_sync(omap_usbhs_drvinit);
17cdd29d
KM		 672
673static void __exit omap_usbhs_drvexit(void)
674{
675 platform_driver_unregister(&usbhs_omap_driver);
676}
677module_exit(omap_usbhs_drvexit);
kernel source for telekom puls (alcatel/mediatek)