Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
4eb3c30b JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
7e044e05 | 15 | #include <linux/types.h> |
1da177e4 LT |
16 | #include <linux/delay.h> |
17 | #include <linux/module.h> | |
1da177e4 LT |
18 | #include <linux/interrupt.h> |
19 | #include <linux/ioport.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/serio.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/rcupdate.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
553a05b8 | 25 | #include <linux/i8042.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
1da177e4 LT |
27 | |
28 | #include <asm/io.h> | |
29 | ||
30 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
31 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
32 | MODULE_LICENSE("GPL"); | |
33 | ||
386b3849 | 34 | static bool i8042_nokbd; |
945ef0d4 DT |
35 | module_param_named(nokbd, i8042_nokbd, bool, 0); |
36 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
37 | ||
386b3849 | 38 | static bool i8042_noaux; |
1da177e4 LT |
39 | module_param_named(noaux, i8042_noaux, bool, 0); |
40 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
41 | ||
386b3849 | 42 | static bool i8042_nomux; |
1da177e4 | 43 | module_param_named(nomux, i8042_nomux, bool, 0); |
2c860a11 | 44 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); |
1da177e4 | 45 | |
386b3849 | 46 | static bool i8042_unlock; |
1da177e4 LT |
47 | module_param_named(unlock, i8042_unlock, bool, 0); |
48 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
49 | ||
386b3849 | 50 | static bool i8042_reset; |
1da177e4 LT |
51 | module_param_named(reset, i8042_reset, bool, 0); |
52 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
53 | ||
386b3849 | 54 | static bool i8042_direct; |
1da177e4 LT |
55 | module_param_named(direct, i8042_direct, bool, 0); |
56 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
57 | ||
386b3849 | 58 | static bool i8042_dumbkbd; |
1da177e4 LT |
59 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); |
60 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
61 | ||
386b3849 | 62 | static bool i8042_noloop; |
1da177e4 LT |
63 | module_param_named(noloop, i8042_noloop, bool, 0); |
64 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
65 | ||
f8313ef1 JK |
66 | static bool i8042_notimeout; |
67 | module_param_named(notimeout, i8042_notimeout, bool, 0); | |
68 | MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); | |
69 | ||
bdf5d033 SV |
70 | static bool i8042_kbdreset; |
71 | module_param_named(kbdreset, i8042_kbdreset, bool, 0); | |
72 | MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); | |
73 | ||
8987fec0 | 74 | #ifdef CONFIG_X86 |
386b3849 | 75 | static bool i8042_dritek; |
8987fec0 CC |
76 | module_param_named(dritek, i8042_dritek, bool, 0); |
77 | MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); | |
78 | #endif | |
79 | ||
1da177e4 | 80 | #ifdef CONFIG_PNP |
386b3849 | 81 | static bool i8042_nopnp; |
1da177e4 LT |
82 | module_param_named(nopnp, i8042_nopnp, bool, 0); |
83 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
84 | #endif | |
85 | ||
86 | #define DEBUG | |
87 | #ifdef DEBUG | |
386b3849 | 88 | static bool i8042_debug; |
1da177e4 LT |
89 | module_param_named(debug, i8042_debug, bool, 0600); |
90 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
91 | #endif | |
92 | ||
1c7827ae DT |
93 | static bool i8042_bypass_aux_irq_test; |
94 | ||
1da177e4 LT |
95 | #include "i8042.h" |
96 | ||
181d683d DT |
97 | /* |
98 | * i8042_lock protects serialization between i8042_command and | |
99 | * the interrupt handler. | |
100 | */ | |
1da177e4 LT |
101 | static DEFINE_SPINLOCK(i8042_lock); |
102 | ||
181d683d DT |
103 | /* |
104 | * Writers to AUX and KBD ports as well as users issuing i8042_command | |
105 | * directly should acquire i8042_mutex (by means of calling | |
106 | * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that | |
107 | * they do not disturb each other (unfortunately in many i8042 | |
108 | * implementations write to one of the ports will immediately abort | |
109 | * command that is being processed by another port). | |
110 | */ | |
111 | static DEFINE_MUTEX(i8042_mutex); | |
112 | ||
1da177e4 LT |
113 | struct i8042_port { |
114 | struct serio *serio; | |
115 | int irq; | |
386b3849 | 116 | bool exists; |
1da177e4 | 117 | signed char mux; |
1da177e4 LT |
118 | }; |
119 | ||
120 | #define I8042_KBD_PORT_NO 0 | |
121 | #define I8042_AUX_PORT_NO 1 | |
122 | #define I8042_MUX_PORT_NO 2 | |
123 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
124 | |
125 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
126 | |
127 | static unsigned char i8042_initial_ctr; | |
128 | static unsigned char i8042_ctr; | |
386b3849 DT |
129 | static bool i8042_mux_present; |
130 | static bool i8042_kbd_irq_registered; | |
131 | static bool i8042_aux_irq_registered; | |
817e6ba3 | 132 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 LT |
133 | static struct platform_device *i8042_platform_device; |
134 | ||
7d12e780 | 135 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
967c9ef9 MG |
136 | static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, |
137 | struct serio *serio); | |
1da177e4 | 138 | |
181d683d DT |
139 | void i8042_lock_chip(void) |
140 | { | |
141 | mutex_lock(&i8042_mutex); | |
142 | } | |
143 | EXPORT_SYMBOL(i8042_lock_chip); | |
144 | ||
145 | void i8042_unlock_chip(void) | |
146 | { | |
147 | mutex_unlock(&i8042_mutex); | |
148 | } | |
149 | EXPORT_SYMBOL(i8042_unlock_chip); | |
150 | ||
967c9ef9 MG |
151 | int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, |
152 | struct serio *serio)) | |
153 | { | |
154 | unsigned long flags; | |
155 | int ret = 0; | |
156 | ||
157 | spin_lock_irqsave(&i8042_lock, flags); | |
158 | ||
159 | if (i8042_platform_filter) { | |
160 | ret = -EBUSY; | |
161 | goto out; | |
162 | } | |
163 | ||
164 | i8042_platform_filter = filter; | |
165 | ||
166 | out: | |
167 | spin_unlock_irqrestore(&i8042_lock, flags); | |
168 | return ret; | |
169 | } | |
170 | EXPORT_SYMBOL(i8042_install_filter); | |
171 | ||
172 | int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, | |
173 | struct serio *port)) | |
174 | { | |
175 | unsigned long flags; | |
176 | int ret = 0; | |
177 | ||
178 | spin_lock_irqsave(&i8042_lock, flags); | |
179 | ||
180 | if (i8042_platform_filter != filter) { | |
181 | ret = -EINVAL; | |
182 | goto out; | |
183 | } | |
184 | ||
185 | i8042_platform_filter = NULL; | |
186 | ||
187 | out: | |
188 | spin_unlock_irqrestore(&i8042_lock, flags); | |
189 | return ret; | |
190 | } | |
191 | EXPORT_SYMBOL(i8042_remove_filter); | |
192 | ||
1da177e4 LT |
193 | /* |
194 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
195 | * be ready for reading values from it / writing values to it. | |
196 | * Called always with i8042_lock held. | |
197 | */ | |
198 | ||
199 | static int i8042_wait_read(void) | |
200 | { | |
201 | int i = 0; | |
de9ce703 | 202 | |
1da177e4 LT |
203 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
204 | udelay(50); | |
205 | i++; | |
206 | } | |
207 | return -(i == I8042_CTL_TIMEOUT); | |
208 | } | |
209 | ||
210 | static int i8042_wait_write(void) | |
211 | { | |
212 | int i = 0; | |
de9ce703 | 213 | |
1da177e4 LT |
214 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
215 | udelay(50); | |
216 | i++; | |
217 | } | |
218 | return -(i == I8042_CTL_TIMEOUT); | |
219 | } | |
220 | ||
221 | /* | |
222 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
223 | * of the i8042 down the toilet. | |
224 | */ | |
225 | ||
226 | static int i8042_flush(void) | |
227 | { | |
228 | unsigned long flags; | |
229 | unsigned char data, str; | |
230 | int i = 0; | |
231 | ||
232 | spin_lock_irqsave(&i8042_lock, flags); | |
233 | ||
234 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
235 | udelay(50); | |
236 | data = i8042_read_data(); | |
237 | i++; | |
4eb3c30b JP |
238 | dbg("%02x <- i8042 (flush, %s)\n", |
239 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
1da177e4 LT |
240 | } |
241 | ||
242 | spin_unlock_irqrestore(&i8042_lock, flags); | |
243 | ||
244 | return i; | |
245 | } | |
246 | ||
247 | /* | |
248 | * i8042_command() executes a command on the i8042. It also sends the input | |
249 | * parameter(s) of the commands to it, and receives the output value(s). The | |
250 | * parameters are to be stored in the param array, and the output is placed | |
251 | * into the same array. The number of the parameters and output values is | |
252 | * encoded in bits 8-11 of the command number. | |
253 | */ | |
254 | ||
de9ce703 | 255 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 256 | { |
de9ce703 | 257 | int i, error; |
1da177e4 LT |
258 | |
259 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
260 | return -1; | |
261 | ||
de9ce703 DT |
262 | error = i8042_wait_write(); |
263 | if (error) | |
264 | return error; | |
463a4f76 | 265 | |
4eb3c30b | 266 | dbg("%02x -> i8042 (command)\n", command & 0xff); |
463a4f76 DT |
267 | i8042_write_command(command & 0xff); |
268 | ||
269 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 DT |
270 | error = i8042_wait_write(); |
271 | if (error) | |
272 | return error; | |
4eb3c30b | 273 | dbg("%02x -> i8042 (parameter)\n", param[i]); |
463a4f76 | 274 | i8042_write_data(param[i]); |
1da177e4 LT |
275 | } |
276 | ||
463a4f76 | 277 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
278 | error = i8042_wait_read(); |
279 | if (error) { | |
4eb3c30b | 280 | dbg(" -- i8042 (timeout)\n"); |
de9ce703 DT |
281 | return error; |
282 | } | |
1da177e4 | 283 | |
463a4f76 DT |
284 | if (command == I8042_CMD_AUX_LOOP && |
285 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
4eb3c30b | 286 | dbg(" -- i8042 (auxerr)\n"); |
de9ce703 | 287 | return -1; |
1da177e4 LT |
288 | } |
289 | ||
463a4f76 | 290 | param[i] = i8042_read_data(); |
4eb3c30b | 291 | dbg("%02x <- i8042 (return)\n", param[i]); |
463a4f76 | 292 | } |
1da177e4 | 293 | |
de9ce703 DT |
294 | return 0; |
295 | } | |
1da177e4 | 296 | |
553a05b8 | 297 | int i8042_command(unsigned char *param, int command) |
de9ce703 DT |
298 | { |
299 | unsigned long flags; | |
300 | int retval; | |
301 | ||
302 | spin_lock_irqsave(&i8042_lock, flags); | |
303 | retval = __i8042_command(param, command); | |
463a4f76 | 304 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 305 | |
1da177e4 LT |
306 | return retval; |
307 | } | |
553a05b8 | 308 | EXPORT_SYMBOL(i8042_command); |
1da177e4 LT |
309 | |
310 | /* | |
311 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
312 | */ | |
313 | ||
314 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
315 | { | |
316 | unsigned long flags; | |
317 | int retval = 0; | |
318 | ||
319 | spin_lock_irqsave(&i8042_lock, flags); | |
320 | ||
de9ce703 | 321 | if (!(retval = i8042_wait_write())) { |
4eb3c30b | 322 | dbg("%02x -> i8042 (kbd-data)\n", c); |
1da177e4 LT |
323 | i8042_write_data(c); |
324 | } | |
325 | ||
326 | spin_unlock_irqrestore(&i8042_lock, flags); | |
327 | ||
328 | return retval; | |
329 | } | |
330 | ||
331 | /* | |
332 | * i8042_aux_write() sends a byte out through the aux interface. | |
333 | */ | |
334 | ||
335 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
336 | { | |
337 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 338 | |
f4e3c711 DT |
339 | return i8042_command(&c, port->mux == -1 ? |
340 | I8042_CMD_AUX_SEND : | |
341 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
342 | } |
343 | ||
5ddbc77c DT |
344 | |
345 | /* | |
346 | * i8042_aux_close attempts to clear AUX or KBD port state by disabling | |
347 | * and then re-enabling it. | |
348 | */ | |
349 | ||
350 | static void i8042_port_close(struct serio *serio) | |
351 | { | |
352 | int irq_bit; | |
353 | int disable_bit; | |
354 | const char *port_name; | |
355 | ||
356 | if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { | |
357 | irq_bit = I8042_CTR_AUXINT; | |
358 | disable_bit = I8042_CTR_AUXDIS; | |
359 | port_name = "AUX"; | |
360 | } else { | |
361 | irq_bit = I8042_CTR_KBDINT; | |
362 | disable_bit = I8042_CTR_KBDDIS; | |
363 | port_name = "KBD"; | |
364 | } | |
365 | ||
366 | i8042_ctr &= ~irq_bit; | |
367 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 368 | pr_warn("Can't write CTR while closing %s port\n", port_name); |
5ddbc77c DT |
369 | |
370 | udelay(50); | |
371 | ||
372 | i8042_ctr &= ~disable_bit; | |
373 | i8042_ctr |= irq_bit; | |
374 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 375 | pr_err("Can't reactivate %s port\n", port_name); |
5ddbc77c DT |
376 | |
377 | /* | |
378 | * See if there is any data appeared while we were messing with | |
379 | * port state. | |
380 | */ | |
381 | i8042_interrupt(0, NULL); | |
382 | } | |
383 | ||
1da177e4 LT |
384 | /* |
385 | * i8042_start() is called by serio core when port is about to finish | |
386 | * registering. It will mark port as existing so i8042_interrupt can | |
387 | * start sending data through it. | |
388 | */ | |
389 | static int i8042_start(struct serio *serio) | |
390 | { | |
391 | struct i8042_port *port = serio->port_data; | |
392 | ||
386b3849 | 393 | port->exists = true; |
1da177e4 LT |
394 | mb(); |
395 | return 0; | |
396 | } | |
397 | ||
398 | /* | |
399 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
400 | * will not try to send data to the port that is about to go away. | |
401 | * The function is called by serio core as part of unregister procedure. | |
402 | */ | |
403 | static void i8042_stop(struct serio *serio) | |
404 | { | |
405 | struct i8042_port *port = serio->port_data; | |
406 | ||
386b3849 | 407 | port->exists = false; |
a8399c51 DT |
408 | |
409 | /* | |
410 | * We synchronize with both AUX and KBD IRQs because there is | |
411 | * a (very unlikely) chance that AUX IRQ is raised for KBD port | |
412 | * and vice versa. | |
413 | */ | |
414 | synchronize_irq(I8042_AUX_IRQ); | |
415 | synchronize_irq(I8042_KBD_IRQ); | |
1da177e4 LT |
416 | port->serio = NULL; |
417 | } | |
418 | ||
4e8d340d DT |
419 | /* |
420 | * i8042_filter() filters out unwanted bytes from the input data stream. | |
421 | * It is called from i8042_interrupt and thus is running with interrupts | |
422 | * off and i8042_lock held. | |
423 | */ | |
967c9ef9 MG |
424 | static bool i8042_filter(unsigned char data, unsigned char str, |
425 | struct serio *serio) | |
4e8d340d DT |
426 | { |
427 | if (unlikely(i8042_suppress_kbd_ack)) { | |
428 | if ((~str & I8042_STR_AUXDATA) && | |
429 | (data == 0xfa || data == 0xfe)) { | |
430 | i8042_suppress_kbd_ack--; | |
431 | dbg("Extra keyboard ACK - filtered out\n"); | |
432 | return true; | |
433 | } | |
434 | } | |
435 | ||
967c9ef9 | 436 | if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { |
0747e3bc | 437 | dbg("Filtered out by platform filter\n"); |
967c9ef9 MG |
438 | return true; |
439 | } | |
440 | ||
4e8d340d DT |
441 | return false; |
442 | } | |
443 | ||
1da177e4 LT |
444 | /* |
445 | * i8042_interrupt() is the most important function in this driver - | |
446 | * it handles the interrupts from the i8042, and sends incoming bytes | |
447 | * to the upper layers. | |
448 | */ | |
449 | ||
7d12e780 | 450 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
451 | { |
452 | struct i8042_port *port; | |
967c9ef9 | 453 | struct serio *serio; |
1da177e4 LT |
454 | unsigned long flags; |
455 | unsigned char str, data; | |
456 | unsigned int dfl; | |
457 | unsigned int port_no; | |
4e8d340d | 458 | bool filtered; |
817e6ba3 | 459 | int ret = 1; |
1da177e4 | 460 | |
1da177e4 | 461 | spin_lock_irqsave(&i8042_lock, flags); |
4e8d340d | 462 | |
1da177e4 LT |
463 | str = i8042_read_status(); |
464 | if (unlikely(~str & I8042_STR_OBF)) { | |
465 | spin_unlock_irqrestore(&i8042_lock, flags); | |
4eb3c30b JP |
466 | if (irq) |
467 | dbg("Interrupt %d, without any data\n", irq); | |
1da177e4 LT |
468 | ret = 0; |
469 | goto out; | |
470 | } | |
4e8d340d | 471 | |
1da177e4 | 472 | data = i8042_read_data(); |
1da177e4 LT |
473 | |
474 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
475 | static unsigned long last_transmit; | |
476 | static unsigned char last_str; | |
477 | ||
478 | dfl = 0; | |
479 | if (str & I8042_STR_MUXERR) { | |
4eb3c30b JP |
480 | dbg("MUX error, status is %02x, data is %02x\n", |
481 | str, data); | |
1da177e4 LT |
482 | /* |
483 | * When MUXERR condition is signalled the data register can only contain | |
484 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
485 | * it is not always the case. Some KBCs also report 0xfc when there is |
486 | * nothing connected to the port while others sometimes get confused which | |
487 | * port the data came from and signal error leaving the data intact. They | |
488 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
489 | * to legacy mode yet, when we see one we'll add proper handling). | |
490 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
491 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
492 | * was transmitted (if transmission happened not too long ago). |
493 | */ | |
a216a4b6 DT |
494 | |
495 | switch (data) { | |
496 | default: | |
1da177e4 LT |
497 | if (time_before(jiffies, last_transmit + HZ/10)) { |
498 | str = last_str; | |
499 | break; | |
500 | } | |
501 | /* fall through - report timeout */ | |
a216a4b6 | 502 | case 0xfc: |
1da177e4 LT |
503 | case 0xfd: |
504 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
505 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
506 | } | |
507 | } | |
508 | ||
509 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
510 | last_str = str; | |
511 | last_transmit = jiffies; | |
512 | } else { | |
513 | ||
514 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
f8313ef1 | 515 | ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); |
1da177e4 LT |
516 | |
517 | port_no = (str & I8042_STR_AUXDATA) ? | |
518 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
519 | } | |
520 | ||
521 | port = &i8042_ports[port_no]; | |
967c9ef9 | 522 | serio = port->exists ? port->serio : NULL; |
1da177e4 | 523 | |
4eb3c30b | 524 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n", |
de9ce703 | 525 | data, port_no, irq, |
1da177e4 LT |
526 | dfl & SERIO_PARITY ? ", bad parity" : "", |
527 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
528 | ||
967c9ef9 | 529 | filtered = i8042_filter(data, str, serio); |
4e8d340d DT |
530 | |
531 | spin_unlock_irqrestore(&i8042_lock, flags); | |
817e6ba3 | 532 | |
4e8d340d | 533 | if (likely(port->exists && !filtered)) |
967c9ef9 | 534 | serio_interrupt(serio, data, dfl); |
1da177e4 | 535 | |
0854e52d | 536 | out: |
1da177e4 LT |
537 | return IRQ_RETVAL(ret); |
538 | } | |
539 | ||
de9ce703 | 540 | /* |
5ddbc77c | 541 | * i8042_enable_kbd_port enables keyboard port on chip |
de9ce703 DT |
542 | */ |
543 | ||
544 | static int i8042_enable_kbd_port(void) | |
545 | { | |
546 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
547 | i8042_ctr |= I8042_CTR_KBDINT; | |
548 | ||
549 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
550 | i8042_ctr &= ~I8042_CTR_KBDINT; |
551 | i8042_ctr |= I8042_CTR_KBDDIS; | |
4eb3c30b | 552 | pr_err("Failed to enable KBD port\n"); |
de9ce703 DT |
553 | return -EIO; |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | /* | |
560 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
561 | */ | |
562 | ||
563 | static int i8042_enable_aux_port(void) | |
564 | { | |
565 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
566 | i8042_ctr |= I8042_CTR_AUXINT; | |
567 | ||
568 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
569 | i8042_ctr &= ~I8042_CTR_AUXINT; |
570 | i8042_ctr |= I8042_CTR_AUXDIS; | |
4eb3c30b | 571 | pr_err("Failed to enable AUX port\n"); |
de9ce703 DT |
572 | return -EIO; |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | /* | |
579 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
580 | * the controller has been switched into Multiplexed mode | |
581 | */ | |
582 | ||
583 | static int i8042_enable_mux_ports(void) | |
584 | { | |
585 | unsigned char param; | |
586 | int i; | |
587 | ||
588 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
589 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
590 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
591 | } | |
592 | ||
593 | return i8042_enable_aux_port(); | |
594 | } | |
595 | ||
1da177e4 | 596 | /* |
386b3849 DT |
597 | * i8042_set_mux_mode checks whether the controller has an |
598 | * active multiplexor and puts the chip into Multiplexed (true) | |
599 | * or Legacy (false) mode. | |
1da177e4 LT |
600 | */ |
601 | ||
386b3849 | 602 | static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) |
1da177e4 LT |
603 | { |
604 | ||
386b3849 | 605 | unsigned char param, val; |
1da177e4 LT |
606 | /* |
607 | * Get rid of bytes in the queue. | |
608 | */ | |
609 | ||
610 | i8042_flush(); | |
611 | ||
612 | /* | |
613 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 614 | * mouse interface, the last should be version. |
1da177e4 LT |
615 | */ |
616 | ||
386b3849 DT |
617 | param = val = 0xf0; |
618 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
619 | return -1; | |
620 | param = val = multiplex ? 0x56 : 0xf6; | |
621 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
1da177e4 | 622 | return -1; |
386b3849 DT |
623 | param = val = multiplex ? 0xa4 : 0xa5; |
624 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) | |
1da177e4 | 625 | return -1; |
386b3849 DT |
626 | |
627 | /* | |
628 | * Workaround for interference with USB Legacy emulation | |
629 | * that causes a v10.12 MUX to be found. | |
630 | */ | |
631 | if (param == 0xac) | |
1da177e4 LT |
632 | return -1; |
633 | ||
634 | if (mux_version) | |
463a4f76 | 635 | *mux_version = param; |
1da177e4 LT |
636 | |
637 | return 0; | |
638 | } | |
639 | ||
1da177e4 | 640 | /* |
de9ce703 DT |
641 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
642 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
643 | * LCS/Telegraphics. | |
1da177e4 LT |
644 | */ |
645 | ||
f8113416 | 646 | static int __init i8042_check_mux(void) |
1da177e4 | 647 | { |
de9ce703 DT |
648 | unsigned char mux_version; |
649 | ||
386b3849 | 650 | if (i8042_set_mux_mode(true, &mux_version)) |
de9ce703 DT |
651 | return -1; |
652 | ||
4eb3c30b | 653 | pr_info("Detected active multiplexing controller, rev %d.%d\n", |
de9ce703 | 654 | (mux_version >> 4) & 0xf, mux_version & 0xf); |
1da177e4 | 655 | |
de9ce703 DT |
656 | /* |
657 | * Disable all muxed ports by disabling AUX. | |
658 | */ | |
1da177e4 LT |
659 | i8042_ctr |= I8042_CTR_AUXDIS; |
660 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
661 | ||
662 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 663 | pr_err("Failed to disable AUX port, can't use MUX\n"); |
de9ce703 | 664 | return -EIO; |
1da177e4 LT |
665 | } |
666 | ||
386b3849 | 667 | i8042_mux_present = true; |
1da177e4 LT |
668 | |
669 | return 0; | |
670 | } | |
671 | ||
1da177e4 | 672 | /* |
de9ce703 | 673 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 674 | */ |
f8113416 DT |
675 | static struct completion i8042_aux_irq_delivered __initdata; |
676 | static bool i8042_irq_being_tested __initdata; | |
1da177e4 | 677 | |
f8113416 | 678 | static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 679 | { |
de9ce703 DT |
680 | unsigned long flags; |
681 | unsigned char str, data; | |
e3758b2a | 682 | int ret = 0; |
1da177e4 | 683 | |
de9ce703 DT |
684 | spin_lock_irqsave(&i8042_lock, flags); |
685 | str = i8042_read_status(); | |
686 | if (str & I8042_STR_OBF) { | |
687 | data = i8042_read_data(); | |
4eb3c30b JP |
688 | dbg("%02x <- i8042 (aux_test_irq, %s)\n", |
689 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
de9ce703 DT |
690 | if (i8042_irq_being_tested && |
691 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
692 | complete(&i8042_aux_irq_delivered); | |
e3758b2a | 693 | ret = 1; |
de9ce703 DT |
694 | } |
695 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 696 | |
e3758b2a | 697 | return IRQ_RETVAL(ret); |
1da177e4 LT |
698 | } |
699 | ||
d2ada559 RS |
700 | /* |
701 | * i8042_toggle_aux - enables or disables AUX port on i8042 via command and | |
702 | * verifies success by readinng CTR. Used when testing for presence of AUX | |
703 | * port. | |
704 | */ | |
f8113416 | 705 | static int __init i8042_toggle_aux(bool on) |
d2ada559 RS |
706 | { |
707 | unsigned char param; | |
708 | int i; | |
709 | ||
710 | if (i8042_command(¶m, | |
711 | on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) | |
712 | return -1; | |
713 | ||
714 | /* some chips need some time to set the I8042_CTR_AUXDIS bit */ | |
715 | for (i = 0; i < 100; i++) { | |
716 | udelay(50); | |
717 | ||
718 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) | |
719 | return -1; | |
720 | ||
721 | if (!(param & I8042_CTR_AUXDIS) == on) | |
722 | return 0; | |
723 | } | |
724 | ||
725 | return -1; | |
726 | } | |
1da177e4 LT |
727 | |
728 | /* | |
729 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
730 | * the presence of an AUX interface. | |
731 | */ | |
732 | ||
f8113416 | 733 | static int __init i8042_check_aux(void) |
1da177e4 | 734 | { |
de9ce703 | 735 | int retval = -1; |
386b3849 DT |
736 | bool irq_registered = false; |
737 | bool aux_loop_broken = false; | |
de9ce703 | 738 | unsigned long flags; |
1da177e4 | 739 | unsigned char param; |
1da177e4 LT |
740 | |
741 | /* | |
742 | * Get rid of bytes in the queue. | |
743 | */ | |
744 | ||
745 | i8042_flush(); | |
746 | ||
747 | /* | |
748 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
749 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
750 | * though it has an AUX port. | |
751 | */ | |
752 | ||
753 | param = 0x5a; | |
3ca5de6d DT |
754 | retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); |
755 | if (retval || param != 0x5a) { | |
1da177e4 LT |
756 | |
757 | /* | |
758 | * External connection test - filters out AT-soldered PS/2 i8042's | |
759 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
760 | * 0xfa - no error on some notebooks which ignore the spec | |
761 | * Because it's common for chipsets to return error on perfectly functioning | |
762 | * AUX ports, we test for this only when the LOOP command failed. | |
763 | */ | |
764 | ||
de9ce703 DT |
765 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
766 | (param && param != 0xfa && param != 0xff)) | |
767 | return -1; | |
1e4865f8 | 768 | |
3ca5de6d DT |
769 | /* |
770 | * If AUX_LOOP completed without error but returned unexpected data | |
771 | * mark it as broken | |
772 | */ | |
773 | if (!retval) | |
386b3849 | 774 | aux_loop_broken = true; |
1da177e4 LT |
775 | } |
776 | ||
777 | /* | |
778 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
779 | */ | |
780 | ||
386b3849 | 781 | if (i8042_toggle_aux(false)) { |
4eb3c30b JP |
782 | pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
783 | pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); | |
1da177e4 LT |
784 | } |
785 | ||
386b3849 | 786 | if (i8042_toggle_aux(true)) |
1da177e4 LT |
787 | return -1; |
788 | ||
bdf5d033 SV |
789 | /* |
790 | * Reset keyboard (needed on some laptops to successfully detect | |
791 | * touchpad, e.g., some Gigabyte laptop models with Elantech | |
792 | * touchpads). | |
793 | */ | |
794 | if (i8042_kbdreset) { | |
795 | pr_warn("Attempting to reset device connected to KBD port\n"); | |
796 | i8042_kbd_write(NULL, (unsigned char) 0xff); | |
797 | } | |
798 | ||
1da177e4 | 799 | /* |
de9ce703 DT |
800 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
801 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
802 | */ |
803 | ||
1c7827ae | 804 | if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { |
de9ce703 DT |
805 | /* |
806 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
807 | * is working and hope we are right. | |
808 | */ | |
809 | retval = 0; | |
810 | goto out; | |
811 | } | |
1da177e4 | 812 | |
de9ce703 DT |
813 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
814 | "i8042", i8042_platform_device)) | |
815 | goto out; | |
1da177e4 | 816 | |
386b3849 | 817 | irq_registered = true; |
de9ce703 DT |
818 | |
819 | if (i8042_enable_aux_port()) | |
820 | goto out; | |
821 | ||
822 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 823 | |
de9ce703 | 824 | init_completion(&i8042_aux_irq_delivered); |
386b3849 | 825 | i8042_irq_being_tested = true; |
de9ce703 DT |
826 | |
827 | param = 0xa5; | |
828 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
829 | ||
830 | spin_unlock_irqrestore(&i8042_lock, flags); | |
831 | ||
832 | if (retval) | |
833 | goto out; | |
1da177e4 | 834 | |
de9ce703 DT |
835 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
836 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 837 | /* |
de9ce703 DT |
838 | * AUX IRQ was never delivered so we need to flush the controller to |
839 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 840 | */ |
4eb3c30b | 841 | dbg(" -- i8042 (aux irq test timeout)\n"); |
de9ce703 DT |
842 | i8042_flush(); |
843 | retval = -1; | |
844 | } | |
1da177e4 | 845 | |
de9ce703 | 846 | out: |
1da177e4 | 847 | |
de9ce703 DT |
848 | /* |
849 | * Disable the interface. | |
850 | */ | |
1da177e4 | 851 | |
de9ce703 DT |
852 | i8042_ctr |= I8042_CTR_AUXDIS; |
853 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 854 | |
de9ce703 DT |
855 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
856 | retval = -1; | |
1da177e4 | 857 | |
de9ce703 DT |
858 | if (irq_registered) |
859 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 860 | |
de9ce703 DT |
861 | return retval; |
862 | } | |
1da177e4 | 863 | |
de9ce703 | 864 | static int i8042_controller_check(void) |
1da177e4 | 865 | { |
de9ce703 | 866 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
4eb3c30b | 867 | pr_err("No controller found\n"); |
de9ce703 DT |
868 | return -ENODEV; |
869 | } | |
870 | ||
871 | return 0; | |
1da177e4 LT |
872 | } |
873 | ||
de9ce703 | 874 | static int i8042_controller_selftest(void) |
2673c836 VP |
875 | { |
876 | unsigned char param; | |
5ea2fc64 | 877 | int i = 0; |
2673c836 | 878 | |
5ea2fc64 AV |
879 | /* |
880 | * We try this 5 times; on some really fragile systems this does not | |
881 | * take the first time... | |
882 | */ | |
883 | do { | |
884 | ||
885 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
a2a94e73 | 886 | pr_err("i8042 controller selftest timeout\n"); |
5ea2fc64 AV |
887 | return -ENODEV; |
888 | } | |
889 | ||
890 | if (param == I8042_RET_CTL_TEST) | |
891 | return 0; | |
2673c836 | 892 | |
a2a94e73 PB |
893 | dbg("i8042 controller selftest: %#x != %#x\n", |
894 | param, I8042_RET_CTL_TEST); | |
5ea2fc64 AV |
895 | msleep(50); |
896 | } while (i++ < 5); | |
2673c836 | 897 | |
5ea2fc64 AV |
898 | #ifdef CONFIG_X86 |
899 | /* | |
900 | * On x86, we don't fail entire i8042 initialization if controller | |
901 | * reset fails in hopes that keyboard port will still be functional | |
902 | * and user will still get a working keyboard. This is especially | |
903 | * important on netbooks. On other arches we trust hardware more. | |
904 | */ | |
4eb3c30b | 905 | pr_info("giving up on controller selftest, continuing anyway...\n"); |
2673c836 | 906 | return 0; |
5ea2fc64 | 907 | #else |
a2a94e73 | 908 | pr_err("i8042 controller selftest failed\n"); |
5ea2fc64 AV |
909 | return -EIO; |
910 | #endif | |
2673c836 | 911 | } |
1da177e4 LT |
912 | |
913 | /* | |
914 | * i8042_controller init initializes the i8042 controller, and, | |
915 | * most importantly, sets it into non-xlated mode if that's | |
916 | * desired. | |
917 | */ | |
918 | ||
919 | static int i8042_controller_init(void) | |
920 | { | |
921 | unsigned long flags; | |
ee1e82ce DT |
922 | int n = 0; |
923 | unsigned char ctr[2]; | |
1da177e4 | 924 | |
1da177e4 | 925 | /* |
ee1e82ce | 926 | * Save the CTR for restore on unload / reboot. |
1da177e4 LT |
927 | */ |
928 | ||
ee1e82ce DT |
929 | do { |
930 | if (n >= 10) { | |
4eb3c30b | 931 | pr_err("Unable to get stable CTR read\n"); |
ee1e82ce DT |
932 | return -EIO; |
933 | } | |
934 | ||
935 | if (n != 0) | |
936 | udelay(50); | |
937 | ||
938 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { | |
4eb3c30b | 939 | pr_err("Can't read CTR while initializing i8042\n"); |
ee1e82ce DT |
940 | return -EIO; |
941 | } | |
942 | ||
943 | } while (n < 2 || ctr[0] != ctr[1]); | |
1da177e4 | 944 | |
ee1e82ce | 945 | i8042_initial_ctr = i8042_ctr = ctr[0]; |
1da177e4 LT |
946 | |
947 | /* | |
948 | * Disable the keyboard interface and interrupt. | |
949 | */ | |
950 | ||
951 | i8042_ctr |= I8042_CTR_KBDDIS; | |
952 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
953 | ||
954 | /* | |
955 | * Handle keylock. | |
956 | */ | |
957 | ||
958 | spin_lock_irqsave(&i8042_lock, flags); | |
959 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
960 | if (i8042_unlock) | |
961 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
82dd9eff | 962 | else |
4eb3c30b | 963 | pr_warn("Warning: Keylock active\n"); |
1da177e4 LT |
964 | } |
965 | spin_unlock_irqrestore(&i8042_lock, flags); | |
966 | ||
967 | /* | |
968 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
969 | * bother enabling translating and be happy. | |
970 | */ | |
971 | ||
972 | if (~i8042_ctr & I8042_CTR_XLATE) | |
386b3849 | 973 | i8042_direct = true; |
1da177e4 LT |
974 | |
975 | /* | |
976 | * Set nontranslated mode for the kbd interface if requested by an option. | |
977 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
978 | * interface is. We don't do this by default, since it can confuse notebook | |
979 | * BIOSes. | |
980 | */ | |
981 | ||
982 | if (i8042_direct) | |
983 | i8042_ctr &= ~I8042_CTR_XLATE; | |
984 | ||
985 | /* | |
986 | * Write CTR back. | |
987 | */ | |
988 | ||
989 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 990 | pr_err("Can't write CTR while initializing i8042\n"); |
de9ce703 | 991 | return -EIO; |
1da177e4 LT |
992 | } |
993 | ||
ee1e82ce DT |
994 | /* |
995 | * Flush whatever accumulated while we were disabling keyboard port. | |
996 | */ | |
997 | ||
998 | i8042_flush(); | |
999 | ||
1da177e4 LT |
1000 | return 0; |
1001 | } | |
1002 | ||
1003 | ||
1004 | /* | |
de9ce703 | 1005 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 1006 | */ |
de9ce703 | 1007 | |
1729ad1f | 1008 | static void i8042_controller_reset(bool force_reset) |
1da177e4 | 1009 | { |
de9ce703 | 1010 | i8042_flush(); |
1da177e4 | 1011 | |
8d04ddb6 DT |
1012 | /* |
1013 | * Disable both KBD and AUX interfaces so they don't get in the way | |
1014 | */ | |
1015 | ||
1016 | i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; | |
1017 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | |
1018 | ||
ee1e82ce | 1019 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
4eb3c30b | 1020 | pr_warn("Can't write CTR while resetting\n"); |
5ddbc77c | 1021 | |
1da177e4 LT |
1022 | /* |
1023 | * Disable MUX mode if present. | |
1024 | */ | |
1025 | ||
1026 | if (i8042_mux_present) | |
386b3849 | 1027 | i8042_set_mux_mode(false, NULL); |
1da177e4 LT |
1028 | |
1029 | /* | |
de9ce703 | 1030 | * Reset the controller if requested. |
1da177e4 LT |
1031 | */ |
1032 | ||
1729ad1f | 1033 | if (i8042_reset || force_reset) |
1ca56e51 | 1034 | i8042_controller_selftest(); |
1da177e4 | 1035 | |
de9ce703 DT |
1036 | /* |
1037 | * Restore the original control register setting. | |
1038 | */ | |
1039 | ||
1040 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 1041 | pr_warn("Can't restore CTR\n"); |
1da177e4 LT |
1042 | } |
1043 | ||
1044 | ||
1da177e4 | 1045 | /* |
c7ff0d9c TS |
1046 | * i8042_panic_blink() will turn the keyboard LEDs on or off and is called |
1047 | * when kernel panics. Flashing LEDs is useful for users running X who may | |
1da177e4 LT |
1048 | * not see the console and will help distingushing panics from "real" |
1049 | * lockups. | |
1050 | * | |
1051 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
1052 | * waiting for KBC to free up even if KBD interrupt is off | |
1053 | */ | |
1054 | ||
1055 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
1056 | ||
c7ff0d9c | 1057 | static long i8042_panic_blink(int state) |
1da177e4 LT |
1058 | { |
1059 | long delay = 0; | |
c7ff0d9c | 1060 | char led; |
1da177e4 | 1061 | |
c7ff0d9c | 1062 | led = (state) ? 0x01 | 0x04 : 0; |
1da177e4 LT |
1063 | while (i8042_read_status() & I8042_STR_IBF) |
1064 | DELAY; | |
4eb3c30b | 1065 | dbg("%02x -> i8042 (panic blink)\n", 0xed); |
19f3c3e3 | 1066 | i8042_suppress_kbd_ack = 2; |
1da177e4 LT |
1067 | i8042_write_data(0xed); /* set leds */ |
1068 | DELAY; | |
1069 | while (i8042_read_status() & I8042_STR_IBF) | |
1070 | DELAY; | |
1071 | DELAY; | |
4eb3c30b | 1072 | dbg("%02x -> i8042 (panic blink)\n", led); |
1da177e4 LT |
1073 | i8042_write_data(led); |
1074 | DELAY; | |
1da177e4 LT |
1075 | return delay; |
1076 | } | |
1077 | ||
1078 | #undef DELAY | |
1079 | ||
d35895db BP |
1080 | #ifdef CONFIG_X86 |
1081 | static void i8042_dritek_enable(void) | |
1082 | { | |
594d6363 | 1083 | unsigned char param = 0x90; |
d35895db BP |
1084 | int error; |
1085 | ||
1086 | error = i8042_command(¶m, 0x1059); | |
1087 | if (error) | |
4eb3c30b | 1088 | pr_warn("Failed to enable DRITEK extension: %d\n", error); |
d35895db BP |
1089 | } |
1090 | #endif | |
1091 | ||
82dd9eff | 1092 | #ifdef CONFIG_PM |
7e044e05 | 1093 | |
1da177e4 | 1094 | /* |
ebd7768d DT |
1095 | * Here we try to reset everything back to a state we had |
1096 | * before suspending. | |
1da177e4 LT |
1097 | */ |
1098 | ||
1ca56e51 | 1099 | static int i8042_controller_resume(bool force_reset) |
1da177e4 | 1100 | { |
de9ce703 | 1101 | int error; |
1da177e4 | 1102 | |
de9ce703 DT |
1103 | error = i8042_controller_check(); |
1104 | if (error) | |
1105 | return error; | |
2673c836 | 1106 | |
1ca56e51 DT |
1107 | if (i8042_reset || force_reset) { |
1108 | error = i8042_controller_selftest(); | |
1109 | if (error) | |
1110 | return error; | |
1111 | } | |
1da177e4 LT |
1112 | |
1113 | /* | |
82dd9eff | 1114 | * Restore original CTR value and disable all ports |
1da177e4 LT |
1115 | */ |
1116 | ||
82dd9eff DT |
1117 | i8042_ctr = i8042_initial_ctr; |
1118 | if (i8042_direct) | |
1119 | i8042_ctr &= ~I8042_CTR_XLATE; | |
de9ce703 DT |
1120 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
1121 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
1122 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1123 | pr_warn("Can't write CTR to resume, retrying...\n"); |
2f6a77d5 JK |
1124 | msleep(50); |
1125 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1126 | pr_err("CTR write retry failed\n"); |
2f6a77d5 JK |
1127 | return -EIO; |
1128 | } | |
de9ce703 | 1129 | } |
1da177e4 | 1130 | |
d35895db BP |
1131 | |
1132 | #ifdef CONFIG_X86 | |
1133 | if (i8042_dritek) | |
1134 | i8042_dritek_enable(); | |
1135 | #endif | |
1136 | ||
de9ce703 | 1137 | if (i8042_mux_present) { |
386b3849 | 1138 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
4eb3c30b | 1139 | pr_warn("failed to resume active multiplexor, mouse won't work\n"); |
de9ce703 DT |
1140 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) |
1141 | i8042_enable_aux_port(); | |
1da177e4 | 1142 | |
de9ce703 DT |
1143 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
1144 | i8042_enable_kbd_port(); | |
1145 | ||
7d12e780 | 1146 | i8042_interrupt(0, NULL); |
1da177e4 LT |
1147 | |
1148 | return 0; | |
1da177e4 | 1149 | } |
ebd7768d | 1150 | |
1ca56e51 DT |
1151 | /* |
1152 | * Here we try to restore the original BIOS settings to avoid | |
1153 | * upsetting it. | |
1154 | */ | |
1155 | ||
1729ad1f | 1156 | static int i8042_pm_suspend(struct device *dev) |
1ca56e51 | 1157 | { |
1729ad1f | 1158 | i8042_controller_reset(true); |
1ca56e51 DT |
1159 | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | static int i8042_pm_resume(struct device *dev) | |
1164 | { | |
1165 | /* | |
1166 | * On resume from S2R we always try to reset the controller | |
1167 | * to bring it in a sane state. (In case of S2D we expect | |
1168 | * BIOS to reset the controller for us.) | |
1169 | */ | |
1170 | return i8042_controller_resume(true); | |
1171 | } | |
1172 | ||
c2d1a2a1 AJ |
1173 | static int i8042_pm_thaw(struct device *dev) |
1174 | { | |
1175 | i8042_interrupt(0, NULL); | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
1729ad1f DT |
1180 | static int i8042_pm_reset(struct device *dev) |
1181 | { | |
1182 | i8042_controller_reset(false); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
1ca56e51 DT |
1187 | static int i8042_pm_restore(struct device *dev) |
1188 | { | |
1189 | return i8042_controller_resume(false); | |
1190 | } | |
1191 | ||
ebd7768d | 1192 | static const struct dev_pm_ops i8042_pm_ops = { |
1729ad1f | 1193 | .suspend = i8042_pm_suspend, |
1ca56e51 | 1194 | .resume = i8042_pm_resume, |
c2d1a2a1 | 1195 | .thaw = i8042_pm_thaw, |
ebd7768d DT |
1196 | .poweroff = i8042_pm_reset, |
1197 | .restore = i8042_pm_restore, | |
1198 | }; | |
1199 | ||
82dd9eff | 1200 | #endif /* CONFIG_PM */ |
1da177e4 LT |
1201 | |
1202 | /* | |
1203 | * We need to reset the 8042 back to original mode on system shutdown, | |
1204 | * because otherwise BIOSes will be confused. | |
1205 | */ | |
1206 | ||
3ae5eaec | 1207 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 | 1208 | { |
1729ad1f | 1209 | i8042_controller_reset(false); |
1da177e4 LT |
1210 | } |
1211 | ||
f8113416 | 1212 | static int __init i8042_create_kbd_port(void) |
1da177e4 LT |
1213 | { |
1214 | struct serio *serio; | |
1215 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
1216 | ||
d39969de | 1217 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1218 | if (!serio) |
1219 | return -ENOMEM; | |
1220 | ||
1221 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
1222 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
1223 | serio->start = i8042_start; |
1224 | serio->stop = i8042_stop; | |
5ddbc77c | 1225 | serio->close = i8042_port_close; |
6a0f3597 | 1226 | serio->ps2_cmd_mutex = &i8042_mutex; |
0854e52d DT |
1227 | serio->port_data = port; |
1228 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 1229 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d DT |
1230 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
1231 | ||
1232 | port->serio = serio; | |
de9ce703 | 1233 | port->irq = I8042_KBD_IRQ; |
0854e52d | 1234 | |
de9ce703 | 1235 | return 0; |
1da177e4 LT |
1236 | } |
1237 | ||
f8113416 | 1238 | static int __init i8042_create_aux_port(int idx) |
1da177e4 LT |
1239 | { |
1240 | struct serio *serio; | |
de9ce703 DT |
1241 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
1242 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 1243 | |
d39969de | 1244 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1245 | if (!serio) |
1246 | return -ENOMEM; | |
1247 | ||
1248 | serio->id.type = SERIO_8042; | |
1249 | serio->write = i8042_aux_write; | |
0854e52d DT |
1250 | serio->start = i8042_start; |
1251 | serio->stop = i8042_stop; | |
76494f74 | 1252 | serio->ps2_cmd_mutex = &i8042_mutex; |
0854e52d DT |
1253 | serio->port_data = port; |
1254 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
1255 | if (idx < 0) { |
1256 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
1257 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
5ddbc77c | 1258 | serio->close = i8042_port_close; |
de9ce703 DT |
1259 | } else { |
1260 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
1261 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
1262 | } | |
0854e52d DT |
1263 | |
1264 | port->serio = serio; | |
de9ce703 DT |
1265 | port->mux = idx; |
1266 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 1267 | |
de9ce703 | 1268 | return 0; |
1da177e4 LT |
1269 | } |
1270 | ||
f8113416 | 1271 | static void __init i8042_free_kbd_port(void) |
1da177e4 | 1272 | { |
de9ce703 DT |
1273 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
1274 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
1275 | } | |
1da177e4 | 1276 | |
f8113416 | 1277 | static void __init i8042_free_aux_ports(void) |
de9ce703 DT |
1278 | { |
1279 | int i; | |
0854e52d | 1280 | |
de9ce703 DT |
1281 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
1282 | kfree(i8042_ports[i].serio); | |
1283 | i8042_ports[i].serio = NULL; | |
1284 | } | |
1285 | } | |
0854e52d | 1286 | |
f8113416 | 1287 | static void __init i8042_register_ports(void) |
de9ce703 DT |
1288 | { |
1289 | int i; | |
0854e52d | 1290 | |
de9ce703 DT |
1291 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1292 | if (i8042_ports[i].serio) { | |
1293 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", | |
1294 | i8042_ports[i].serio->name, | |
1295 | (unsigned long) I8042_DATA_REG, | |
1296 | (unsigned long) I8042_COMMAND_REG, | |
1297 | i8042_ports[i].irq); | |
1298 | serio_register_port(i8042_ports[i].serio); | |
1299 | } | |
1300 | } | |
1da177e4 LT |
1301 | } |
1302 | ||
e2619cf7 | 1303 | static void i8042_unregister_ports(void) |
1da177e4 | 1304 | { |
de9ce703 | 1305 | int i; |
1da177e4 | 1306 | |
de9ce703 DT |
1307 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1308 | if (i8042_ports[i].serio) { | |
1309 | serio_unregister_port(i8042_ports[i].serio); | |
1310 | i8042_ports[i].serio = NULL; | |
1311 | } | |
1312 | } | |
1313 | } | |
1314 | ||
1315 | static void i8042_free_irqs(void) | |
1316 | { | |
1317 | if (i8042_aux_irq_registered) | |
1318 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1319 | if (i8042_kbd_irq_registered) | |
1320 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1321 | ||
386b3849 | 1322 | i8042_aux_irq_registered = i8042_kbd_irq_registered = false; |
de9ce703 DT |
1323 | } |
1324 | ||
f8113416 | 1325 | static int __init i8042_setup_aux(void) |
de9ce703 DT |
1326 | { |
1327 | int (*aux_enable)(void); | |
1328 | int error; | |
1329 | int i; | |
1da177e4 | 1330 | |
de9ce703 | 1331 | if (i8042_check_aux()) |
87fd6318 | 1332 | return -ENODEV; |
1da177e4 | 1333 | |
de9ce703 DT |
1334 | if (i8042_nomux || i8042_check_mux()) { |
1335 | error = i8042_create_aux_port(-1); | |
1336 | if (error) | |
1337 | goto err_free_ports; | |
1338 | aux_enable = i8042_enable_aux_port; | |
1339 | } else { | |
1340 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1341 | error = i8042_create_aux_port(i); | |
1342 | if (error) | |
1343 | goto err_free_ports; | |
0854e52d | 1344 | } |
de9ce703 | 1345 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1346 | } |
1347 | ||
de9ce703 DT |
1348 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1349 | "i8042", i8042_platform_device); | |
1350 | if (error) | |
1351 | goto err_free_ports; | |
945ef0d4 | 1352 | |
de9ce703 DT |
1353 | if (aux_enable()) |
1354 | goto err_free_irq; | |
1da177e4 | 1355 | |
386b3849 | 1356 | i8042_aux_irq_registered = true; |
1da177e4 | 1357 | return 0; |
0854e52d | 1358 | |
de9ce703 DT |
1359 | err_free_irq: |
1360 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1361 | err_free_ports: | |
1362 | i8042_free_aux_ports(); | |
1363 | return error; | |
1364 | } | |
0854e52d | 1365 | |
f8113416 | 1366 | static int __init i8042_setup_kbd(void) |
de9ce703 DT |
1367 | { |
1368 | int error; | |
1369 | ||
1370 | error = i8042_create_kbd_port(); | |
1371 | if (error) | |
1372 | return error; | |
1373 | ||
1374 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1375 | "i8042", i8042_platform_device); | |
1376 | if (error) | |
1377 | goto err_free_port; | |
1378 | ||
1379 | error = i8042_enable_kbd_port(); | |
1380 | if (error) | |
1381 | goto err_free_irq; | |
1382 | ||
386b3849 | 1383 | i8042_kbd_irq_registered = true; |
de9ce703 DT |
1384 | return 0; |
1385 | ||
1386 | err_free_irq: | |
1387 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1388 | err_free_port: | |
1389 | i8042_free_kbd_port(); | |
1390 | return error; | |
1da177e4 LT |
1391 | } |
1392 | ||
f8113416 | 1393 | static int __init i8042_probe(struct platform_device *dev) |
1da177e4 | 1394 | { |
de9ce703 | 1395 | int error; |
1da177e4 | 1396 | |
ec62e1c8 DT |
1397 | i8042_platform_device = dev; |
1398 | ||
1ca56e51 DT |
1399 | if (i8042_reset) { |
1400 | error = i8042_controller_selftest(); | |
1401 | if (error) | |
1402 | return error; | |
1403 | } | |
1da177e4 | 1404 | |
de9ce703 DT |
1405 | error = i8042_controller_init(); |
1406 | if (error) | |
1407 | return error; | |
1408 | ||
d35895db BP |
1409 | #ifdef CONFIG_X86 |
1410 | if (i8042_dritek) | |
1411 | i8042_dritek_enable(); | |
1412 | #endif | |
1413 | ||
de9ce703 DT |
1414 | if (!i8042_noaux) { |
1415 | error = i8042_setup_aux(); | |
1416 | if (error && error != -ENODEV && error != -EBUSY) | |
1417 | goto out_fail; | |
1418 | } | |
1419 | ||
1420 | if (!i8042_nokbd) { | |
1421 | error = i8042_setup_kbd(); | |
1422 | if (error) | |
1423 | goto out_fail; | |
1424 | } | |
de9ce703 DT |
1425 | /* |
1426 | * Ok, everything is ready, let's register all serio ports | |
1427 | */ | |
1428 | i8042_register_ports(); | |
1429 | ||
1430 | return 0; | |
1431 | ||
1432 | out_fail: | |
1433 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1434 | i8042_free_irqs(); | |
1729ad1f | 1435 | i8042_controller_reset(false); |
ec62e1c8 | 1436 | i8042_platform_device = NULL; |
de9ce703 DT |
1437 | |
1438 | return error; | |
1439 | } | |
1440 | ||
e2619cf7 | 1441 | static int i8042_remove(struct platform_device *dev) |
de9ce703 DT |
1442 | { |
1443 | i8042_unregister_ports(); | |
1444 | i8042_free_irqs(); | |
1729ad1f | 1445 | i8042_controller_reset(false); |
ec62e1c8 | 1446 | i8042_platform_device = NULL; |
1da177e4 | 1447 | |
87fd6318 DT |
1448 | return 0; |
1449 | } | |
1450 | ||
1451 | static struct platform_driver i8042_driver = { | |
1452 | .driver = { | |
1453 | .name = "i8042", | |
1454 | .owner = THIS_MODULE, | |
ebd7768d DT |
1455 | #ifdef CONFIG_PM |
1456 | .pm = &i8042_pm_ops, | |
1457 | #endif | |
87fd6318 | 1458 | }, |
1cb0aa88 | 1459 | .remove = i8042_remove, |
82dd9eff | 1460 | .shutdown = i8042_shutdown, |
87fd6318 DT |
1461 | }; |
1462 | ||
1463 | static int __init i8042_init(void) | |
1464 | { | |
ec62e1c8 | 1465 | struct platform_device *pdev; |
87fd6318 DT |
1466 | int err; |
1467 | ||
1468 | dbg_init(); | |
1469 | ||
1470 | err = i8042_platform_init(); | |
1471 | if (err) | |
1472 | return err; | |
1473 | ||
de9ce703 DT |
1474 | err = i8042_controller_check(); |
1475 | if (err) | |
1476 | goto err_platform_exit; | |
87fd6318 | 1477 | |
ec62e1c8 DT |
1478 | pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); |
1479 | if (IS_ERR(pdev)) { | |
1480 | err = PTR_ERR(pdev); | |
f8113416 | 1481 | goto err_platform_exit; |
87fd6318 DT |
1482 | } |
1483 | ||
de9ce703 DT |
1484 | panic_blink = i8042_panic_blink; |
1485 | ||
87fd6318 DT |
1486 | return 0; |
1487 | ||
87fd6318 DT |
1488 | err_platform_exit: |
1489 | i8042_platform_exit(); | |
87fd6318 DT |
1490 | return err; |
1491 | } | |
1492 | ||
1493 | static void __exit i8042_exit(void) | |
1494 | { | |
f8113416 | 1495 | platform_device_unregister(i8042_platform_device); |
af045b86 | 1496 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1497 | i8042_platform_exit(); |
1498 | ||
1499 | panic_blink = NULL; | |
1500 | } | |
1501 | ||
1502 | module_init(i8042_init); | |
1503 | module_exit(i8042_exit); |