[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / vmwgfx / vmwgfx_fifo.c

/**************************************************************************
 *
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/

#include "vmwgfx_drv.h"
#include <drm/drmP.h>
#include <drm/ttm/ttm_placement.h>

bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t fifo_min, hwversion;
	const struct vmw_fifo_state *fifo = &dev_priv->fifo;

	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;

	fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
		return false;

	hwversion = ioread32(fifo_mem +
			     ((fifo->capabilities &
			       SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
			      SVGA_FIFO_3D_HWVERSION_REVISED :
			      SVGA_FIFO_3D_HWVERSION));

	if (hwversion == 0)
		return false;

	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
		return false;

	/* Non-Screen Object path does not support surfaces */
	if (!dev_priv->sou_priv)
		return false;

	return true;
}

bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t caps;

	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;

	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
		return true;

	return false;
}

int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t dummy;

	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
	fifo->static_buffer = vmalloc(fifo->static_buffer_size);
	if (unlikely(fifo->static_buffer == NULL))
		return -ENOMEM;

	fifo->dynamic_buffer = NULL;
	fifo->reserved_size = 0;
	fifo->using_bounce_buffer = false;

	mutex_init(&fifo->fifo_mutex);
	init_rwsem(&fifo->rwsem);

	/*
	 * Allow mapping the first page read-only to user-space.
	 */

	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));

	mutex_lock(&dev_priv->hw_mutex);
	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);

	min = 4;
	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
		min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	min <<= 2;

	if (min < PAGE_SIZE)
		min = PAGE_SIZE;

	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	wmb();
	iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
	iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
	mb();

	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	mutex_unlock(&dev_priv->hw_mutex);

	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);

	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
		 (unsigned int) max,
		 (unsigned int) min,
		 (unsigned int) fifo->capabilities);

	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
	vmw_marker_queue_init(&fifo->marker_queue);
	return vmw_fifo_send_fence(dev_priv, &dummy);
}

void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

	mutex_lock(&dev_priv->hw_mutex);

	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
		iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
		vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	}

	mutex_unlock(&dev_priv->hw_mutex);
}

void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

	mutex_lock(&dev_priv->hw_mutex);

	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
		;

	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);

	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
		  dev_priv->config_done_state);
	vmw_write(dev_priv, SVGA_REG_ENABLE,
		  dev_priv->enable_state);
	vmw_write(dev_priv, SVGA_REG_TRACES,
		  dev_priv->traces_state);

	mutex_unlock(&dev_priv->hw_mutex);
	vmw_marker_queue_takedown(&fifo->marker_queue);

	if (likely(fifo->static_buffer != NULL)) {
		vfree(fifo->static_buffer);
		fifo->static_buffer = NULL;
	}

	if (likely(fifo->dynamic_buffer != NULL)) {
		vfree(fifo->dynamic_buffer);
		fifo->dynamic_buffer = NULL;
	}
}

static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);

	return ((max - next_cmd) + (stop - min) <= bytes);
}

static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
			       uint32_t bytes, bool interruptible,
			       unsigned long timeout)
{
	int ret = 0;
	unsigned long end_jiffies = jiffies + timeout;
	DEFINE_WAIT(__wait);

	DRM_INFO("Fifo wait noirq.\n");

	for (;;) {
		prepare_to_wait(&dev_priv->fifo_queue, &__wait,
				(interruptible) ?
				TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
		if (!vmw_fifo_is_full(dev_priv, bytes))
			break;
		if (time_after_eq(jiffies, end_jiffies)) {
			ret = -EBUSY;
			DRM_ERROR("SVGA device lockup.\n");
			break;
		}
		schedule_timeout(1);
		if (interruptible && signal_pending(current)) {
			ret = -ERESTARTSYS;
			break;
		}
	}
	finish_wait(&dev_priv->fifo_queue, &__wait);
	wake_up_all(&dev_priv->fifo_queue);
	DRM_INFO("Fifo noirq exit.\n");
	return ret;
}

static int vmw_fifo_wait(struct vmw_private *dev_priv,
			 uint32_t bytes, bool interruptible,
			 unsigned long timeout)
{
	long ret = 1L;
	unsigned long irq_flags;

	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
		return 0;

	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
		return vmw_fifo_wait_noirq(dev_priv, bytes,
					   interruptible, timeout);

	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		outl(SVGA_IRQFLAG_FIFO_PROGRESS,
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
		dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);

	if (interruptible)
		ret = wait_event_interruptible_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);
	else
		ret = wait_event_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);

	if (unlikely(ret == 0))
		ret = -EBUSY;
	else if (likely(ret > 0))
		ret = 0;

	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);

	return ret;
}

/**
 * Reserve @bytes number of bytes in the fifo.
 *
 * This function will return NULL (error) on two conditions:
 *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 *   available fifo space.
 *
 * Returns:
 *   Pointer to the fifo, or null on error (possible hardware hang).
 */
void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t next_cmd;
	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	int ret;

	mutex_lock(&fifo_state->fifo_mutex);
	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);

	if (unlikely(bytes >= (max - min)))
		goto out_err;

	BUG_ON(fifo_state->reserved_size != 0);
	BUG_ON(fifo_state->dynamic_buffer != NULL);

	fifo_state->reserved_size = bytes;

	while (1) {
		uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
		bool need_bounce = false;
		bool reserve_in_place = false;

		if (next_cmd >= stop) {
			if (likely((next_cmd + bytes < max ||
				    (next_cmd + bytes == max && stop > min))))
				reserve_in_place = true;

			else if (vmw_fifo_is_full(dev_priv, bytes)) {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			} else
				need_bounce = true;

		} else {

			if (likely((next_cmd + bytes < stop)))
				reserve_in_place = true;
			else {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			}
		}

		if (reserve_in_place) {
			if (reserveable || bytes <= sizeof(uint32_t)) {
				fifo_state->using_bounce_buffer = false;

				if (reserveable)
					iowrite32(bytes, fifo_mem +
						  SVGA_FIFO_RESERVED);
				return fifo_mem + (next_cmd >> 2);
			} else {
				need_bounce = true;
			}
		}

		if (need_bounce) {
			fifo_state->using_bounce_buffer = true;
			if (bytes < fifo_state->static_buffer_size)
				return fifo_state->static_buffer;
			else {
				fifo_state->dynamic_buffer = vmalloc(bytes);
				if (!fifo_state->dynamic_buffer)
					goto out_err;
				return fifo_state->dynamic_buffer;
			}
		}
	}
out_err:
	fifo_state->reserved_size = 0;
	mutex_unlock(&fifo_state->fifo_mutex);
	return NULL;
}

static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
			      __le32 __iomem *fifo_mem,
			      uint32_t next_cmd,
			      uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t chunk_size = max - next_cmd;
	uint32_t rest;
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;

	if (bytes < chunk_size)
		chunk_size = bytes;

	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	mb();
	memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	rest = bytes - chunk_size;
	if (rest)
		memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
			    rest);
}

static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
			       __le32 __iomem *fifo_mem,
			       uint32_t next_cmd,
			       uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;

	while (bytes > 0) {
		iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
		next_cmd += sizeof(uint32_t);
		if (unlikely(next_cmd == max))
			next_cmd = min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
		mb();
		bytes -= sizeof(uint32_t);
	}
}

void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;

	BUG_ON((bytes & 3) != 0);
	BUG_ON(bytes > fifo_state->reserved_size);

	fifo_state->reserved_size = 0;

	if (fifo_state->using_bounce_buffer) {
		if (reserveable)
			vmw_fifo_res_copy(fifo_state, fifo_mem,
					  next_cmd, max, min, bytes);
		else
			vmw_fifo_slow_copy(fifo_state, fifo_mem,
					   next_cmd, max, min, bytes);

		if (fifo_state->dynamic_buffer) {
			vfree(fifo_state->dynamic_buffer);
			fifo_state->dynamic_buffer = NULL;
		}

	}

	down_write(&fifo_state->rwsem);
	if (fifo_state->using_bounce_buffer || reserveable) {
		next_cmd += bytes;
		if (next_cmd >= max)
			next_cmd -= max - min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	}

	if (reserveable)
		iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
	mb();
	up_write(&fifo_state->rwsem);
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
	mutex_unlock(&fifo_state->fifo_mutex);
}

int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	struct svga_fifo_cmd_fence *cmd_fence;
	void *fm;
	int ret = 0;
	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);

	fm = vmw_fifo_reserve(dev_priv, bytes);
	if (unlikely(fm == NULL)) {
		*seqno = atomic_read(&dev_priv->marker_seq);
		ret = -ENOMEM;
		(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
					false, 3*HZ);
		goto out_err;
	}

	do {
		*seqno = atomic_add_return(1, &dev_priv->marker_seq);
	} while (*seqno == 0);

	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {

		/*
		 * Don't request hardware to send a fence. The
		 * waiting code in vmwgfx_irq.c will emulate this.
		 */

		vmw_fifo_commit(dev_priv, 0);
		return 0;
	}

	*(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
	cmd_fence = (struct svga_fifo_cmd_fence *)
	    ((unsigned long)fm + sizeof(__le32));

	iowrite32(*seqno, &cmd_fence->fence);
	vmw_fifo_commit(dev_priv, bytes);
	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
	vmw_update_seqno(dev_priv, fifo_state);

out_err:
	return ret;
}

/**
 * vmw_fifo_emit_dummy_query - emits a dummy query to the fifo.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * This function is used to emit a dummy occlusion query with
 * no primitives rendered between query begin and query end.
 * It's used to provide a query barrier, in order to know that when
 * this query is finished, all preceding queries are also finished.
 *
 * A Query results structure should have been initialized at the start
 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 * must also be either reserved or pinned when this function is called.
 *
 * Returns -ENOMEM on failure to reserve fifo space.
 */
int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
			      uint32_t cid)
{
	/*
	 * A query wait without a preceding query end will
	 * actually finish all queries for this cid
	 * without writing to the query result structure.
	 */

	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	struct {
		SVGA3dCmdHeader header;
		SVGA3dCmdWaitForQuery body;
	} *cmd;

	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));

	if (unlikely(cmd == NULL)) {
		DRM_ERROR("Out of fifo space for dummy query.\n");
		return -ENOMEM;
	}

	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	cmd->header.size = sizeof(cmd->body);
	cmd->body.cid = cid;
	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;

	if (bo->mem.mem_type == TTM_PL_VRAM) {
		cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
		cmd->body.guestResult.offset = bo->offset;
	} else {
		cmd->body.guestResult.gmrId = bo->mem.start;
		cmd->body.guestResult.offset = 0;
	}

	vmw_fifo_commit(dev_priv, sizeof(*cmd));

	return 0;
}
Commit	Line	Data
fb1d9738 JB	1	/**************************************************************************
	2	*
	3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	**************************************************************************/
	27
	28	#include "vmwgfx_drv.h"
760285e7 DH	29	#include <drm/drmP.h>
760285e7 DH	30	#include <drm/ttm/ttm_placement.h>
fb1d9738	31
8e19a951 JB	32	bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
	33	{
	34	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	35	uint32_t fifo_min, hwversion;
ebd4c6f6	36	const struct vmw_fifo_state *fifo = &dev_priv->fifo;
8e19a951	37
d7e1958d JB	38	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
	39	return false;
	40
8e19a951 JB	41	fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	42	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
	43	return false;
	44
ebd4c6f6 TH	45	hwversion = ioread32(fifo_mem +
	46	((fifo->capabilities &
	47	SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
	48	SVGA_FIFO_3D_HWVERSION_REVISED :
	49	SVGA_FIFO_3D_HWVERSION));
	50
8e19a951 JB	51	if (hwversion == 0)
	52	return false;
	53
b7b70024	54	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
8e19a951 JB	55	return false;
8e19a951 JB	56
01e81419 JB	57	/* Non-Screen Object path does not support surfaces */
	58	if (!dev_priv->sou_priv)
	59	return false;
	60
8e19a951 JB	61	return true;
	62	}
	63
d7e1958d JB	64	bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
	65	{
	66	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	67	uint32_t caps;
	68
	69	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
	70	return false;
	71
	72	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	73	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
	74	return true;
	75
	76	return false;
	77	}
	78
fb1d9738 JB	79	int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
	80	{
	81	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	82	uint32_t max;
	83	uint32_t min;
	84	uint32_t dummy;
fb1d9738 JB	85
	86	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
	87	fifo->static_buffer = vmalloc(fifo->static_buffer_size);
	88	if (unlikely(fifo->static_buffer == NULL))
	89	return -ENOMEM;
	90
fb1d9738 JB	91	fifo->dynamic_buffer = NULL;
	92	fifo->reserved_size = 0;
	93	fifo->using_bounce_buffer = false;
	94
85b9e487	95	mutex_init(&fifo->fifo_mutex);
fb1d9738 JB	96	init_rwsem(&fifo->rwsem);
	97
	98	/*
	99	* Allow mapping the first page read-only to user-space.
	100	*/
	101
	102	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	103	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	104	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
	105
	106	mutex_lock(&dev_priv->hw_mutex);
	107	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	108	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
30c78bb8	109	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
fb1d9738 JB	110	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
	111
	112	min = 4;
	113	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
	114	min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	115	min <<= 2;
	116
	117	if (min < PAGE_SIZE)
	118	min = PAGE_SIZE;
	119
	120	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	121	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	122	wmb();
	123	iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
	124	iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
	125	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
	126	mb();
	127
	128	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	129	mutex_unlock(&dev_priv->hw_mutex);
	130
	131	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	132	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	133	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	134
	135	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
	136	(unsigned int) max,
	137	(unsigned int) min,
	138	(unsigned int) fifo->capabilities);
	139
6bcd8d3c TH	140	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	141	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
	142	vmw_marker_queue_init(&fifo->marker_queue);
fb1d9738	143	return vmw_fifo_send_fence(dev_priv, &dummy);
fb1d9738 JB	144	}
	145
	146	void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
	147	{
	148	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	149
	150	mutex_lock(&dev_priv->hw_mutex);
	151
	152	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
	153	iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
	154	vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	155	}
	156
	157	mutex_unlock(&dev_priv->hw_mutex);
	158	}
	159
	160	void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
	161	{
	162	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	163
	164	mutex_lock(&dev_priv->hw_mutex);
	165
93ba9fc3	166	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
fb1d9738	167	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
93ba9fc3	168	;
fb1d9738	169
6bcd8d3c	170	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
fb1d9738 JB	171
	172	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
	173	dev_priv->config_done_state);
	174	vmw_write(dev_priv, SVGA_REG_ENABLE,
	175	dev_priv->enable_state);
30c78bb8 TH	176	vmw_write(dev_priv, SVGA_REG_TRACES,
30c78bb8 TH	177	dev_priv->traces_state);
fb1d9738 JB	178
fb1d9738 JB	179	mutex_unlock(&dev_priv->hw_mutex);
6bcd8d3c	180	vmw_marker_queue_takedown(&fifo->marker_queue);
fb1d9738	181
fb1d9738 JB	182	if (likely(fifo->static_buffer != NULL)) {
	183	vfree(fifo->static_buffer);
	184	fifo->static_buffer = NULL;
	185	}
	186
	187	if (likely(fifo->dynamic_buffer != NULL)) {
	188	vfree(fifo->dynamic_buffer);
	189	fifo->dynamic_buffer = NULL;
	190	}
	191	}
	192
	193	static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
	194	{
	195	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	196	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	197	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	198	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	199	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
	200
	201	return ((max - next_cmd) + (stop - min) <= bytes);
	202	}
	203
	204	static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
	205	uint32_t bytes, bool interruptible,
	206	unsigned long timeout)
	207	{
	208	int ret = 0;
	209	unsigned long end_jiffies = jiffies + timeout;
	210	DEFINE_WAIT(__wait);
	211
	212	DRM_INFO("Fifo wait noirq.\n");
	213
	214	for (;;) {
	215	prepare_to_wait(&dev_priv->fifo_queue, &__wait,
	216	(interruptible) ?
	217	TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
	218	if (!vmw_fifo_is_full(dev_priv, bytes))
	219	break;
	220	if (time_after_eq(jiffies, end_jiffies)) {
	221	ret = -EBUSY;
	222	DRM_ERROR("SVGA device lockup.\n");
	223	break;
	224	}
	225	schedule_timeout(1);
	226	if (interruptible && signal_pending(current)) {
3d3a5b32	227	ret = -ERESTARTSYS;
fb1d9738 JB	228	break;
	229	}
	230	}
	231	finish_wait(&dev_priv->fifo_queue, &__wait);
	232	wake_up_all(&dev_priv->fifo_queue);
	233	DRM_INFO("Fifo noirq exit.\n");
	234	return ret;
	235	}
	236
	237	static int vmw_fifo_wait(struct vmw_private *dev_priv,
	238	uint32_t bytes, bool interruptible,
	239	unsigned long timeout)
	240	{
	241	long ret = 1L;
	242	unsigned long irq_flags;
	243
	244	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
	245	return 0;
	246
	247	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	248	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
	249	return vmw_fifo_wait_noirq(dev_priv, bytes,
	250	interruptible, timeout);
	251
	252	mutex_lock(&dev_priv->hw_mutex);
	253	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
	254	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
	255	outl(SVGA_IRQFLAG_FIFO_PROGRESS,
	256	dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
57c5ee79 TH	257	dev_priv->irq_mask \|= SVGA_IRQFLAG_FIFO_PROGRESS;
57c5ee79 TH	258	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
fb1d9738 JB	259	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	260	}
	261	mutex_unlock(&dev_priv->hw_mutex);
	262
	263	if (interruptible)
	264	ret = wait_event_interruptible_timeout
	265	(dev_priv->fifo_queue,
	266	!vmw_fifo_is_full(dev_priv, bytes), timeout);
	267	else
	268	ret = wait_event_timeout
	269	(dev_priv->fifo_queue,
	270	!vmw_fifo_is_full(dev_priv, bytes), timeout);
	271
3d3a5b32	272	if (unlikely(ret == 0))
fb1d9738 JB	273	ret = -EBUSY;
	274	else if (likely(ret > 0))
	275	ret = 0;
	276
	277	mutex_lock(&dev_priv->hw_mutex);
	278	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
	279	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
57c5ee79 TH	280	dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
57c5ee79 TH	281	vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
fb1d9738 JB	282	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	283	}
	284	mutex_unlock(&dev_priv->hw_mutex);
	285
	286	return ret;
	287	}
	288
de12d44f JB	289	/**
	290	* Reserve @bytes number of bytes in the fifo.
	291	*
	292	* This function will return NULL (error) on two conditions:
	293	* If it timeouts waiting for fifo space, or if @bytes is larger than the
	294	* available fifo space.
	295	*
	296	* Returns:
	297	* Pointer to the fifo, or null on error (possible hardware hang).
	298	*/
fb1d9738 JB	299	void vmw_fifo_reserve(struct vmw_private dev_priv, uint32_t bytes)
	300	{
	301	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	302	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	303	uint32_t max;
	304	uint32_t min;
	305	uint32_t next_cmd;
	306	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	307	int ret;
	308
85b9e487	309	mutex_lock(&fifo_state->fifo_mutex);
fb1d9738 JB	310	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	311	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	312	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	313
	314	if (unlikely(bytes >= (max - min)))
	315	goto out_err;
	316
	317	BUG_ON(fifo_state->reserved_size != 0);
	318	BUG_ON(fifo_state->dynamic_buffer != NULL);
	319
	320	fifo_state->reserved_size = bytes;
	321
	322	while (1) {
	323	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
	324	bool need_bounce = false;
	325	bool reserve_in_place = false;
	326
	327	if (next_cmd >= stop) {
	328	if (likely((next_cmd + bytes < max \|\|
	329	(next_cmd + bytes == max && stop > min))))
	330	reserve_in_place = true;
	331
	332	else if (vmw_fifo_is_full(dev_priv, bytes)) {
	333	ret = vmw_fifo_wait(dev_priv, bytes,
	334	false, 3 * HZ);
	335	if (unlikely(ret != 0))
	336	goto out_err;
	337	} else
	338	need_bounce = true;
	339
	340	} else {
	341
	342	if (likely((next_cmd + bytes < stop)))
	343	reserve_in_place = true;
	344	else {
	345	ret = vmw_fifo_wait(dev_priv, bytes,
	346	false, 3 * HZ);
	347	if (unlikely(ret != 0))
	348	goto out_err;
	349	}
	350	}
	351
	352	if (reserve_in_place) {
	353	if (reserveable \|\| bytes <= sizeof(uint32_t)) {
	354	fifo_state->using_bounce_buffer = false;
	355
	356	if (reserveable)
	357	iowrite32(bytes, fifo_mem +
	358	SVGA_FIFO_RESERVED);
	359	return fifo_mem + (next_cmd >> 2);
	360	} else {
	361	need_bounce = true;
	362	}
	363	}
	364
	365	if (need_bounce) {
	366	fifo_state->using_bounce_buffer = true;
	367	if (bytes < fifo_state->static_buffer_size)
	368	return fifo_state->static_buffer;
	369	else {
	370	fifo_state->dynamic_buffer = vmalloc(bytes);
7e25c935 DC	371	if (!fifo_state->dynamic_buffer)
7e25c935 DC	372	goto out_err;
fb1d9738 JB	373	return fifo_state->dynamic_buffer;
	374	}
	375	}
	376	}
	377	out_err:
	378	fifo_state->reserved_size = 0;
85b9e487	379	mutex_unlock(&fifo_state->fifo_mutex);
fb1d9738 JB	380	return NULL;
	381	}
	382
	383	static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
	384	__le32 __iomem *fifo_mem,
	385	uint32_t next_cmd,
	386	uint32_t max, uint32_t min, uint32_t bytes)
	387	{
	388	uint32_t chunk_size = max - next_cmd;
	389	uint32_t rest;
	390	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	391	fifo_state->dynamic_buffer : fifo_state->static_buffer;
	392
	393	if (bytes < chunk_size)
	394	chunk_size = bytes;
	395
	396	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	397	mb();
	398	memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	399	rest = bytes - chunk_size;
	400	if (rest)
	401	memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
	402	rest);
	403	}
	404
	405	static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
	406	__le32 __iomem *fifo_mem,
	407	uint32_t next_cmd,
	408	uint32_t max, uint32_t min, uint32_t bytes)
	409	{
	410	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	411	fifo_state->dynamic_buffer : fifo_state->static_buffer;
	412
	413	while (bytes > 0) {
	414	iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
	415	next_cmd += sizeof(uint32_t);
	416	if (unlikely(next_cmd == max))
	417	next_cmd = min;
	418	mb();
	419	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	420	mb();
	421	bytes -= sizeof(uint32_t);
	422	}
	423	}
	424
	425	void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
	426	{
	427	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	428	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	429	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	430	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	431	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	432	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	433
	434	BUG_ON((bytes & 3) != 0);
	435	BUG_ON(bytes > fifo_state->reserved_size);
	436
	437	fifo_state->reserved_size = 0;
	438
	439	if (fifo_state->using_bounce_buffer) {
	440	if (reserveable)
	441	vmw_fifo_res_copy(fifo_state, fifo_mem,
	442	next_cmd, max, min, bytes);
	443	else
444	vmw_fifo_slow_copy(fifo_state, fifo_mem,
445	next_cmd, max, min, bytes);
446
447	if (fifo_state->dynamic_buffer) {
448	vfree(fifo_state->dynamic_buffer);
449	fifo_state->dynamic_buffer = NULL;
450	}
451
452	}
453
85b9e487	454	down_write(&fifo_state->rwsem);
fb1d9738 JB	455	if (fifo_state->using_bounce_buffer \|\| reserveable) {
	456	next_cmd += bytes;
	457	if (next_cmd >= max)
	458	next_cmd -= max - min;
	459	mb();
	460	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	461	}
	462
	463	if (reserveable)
	464	iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
	465	mb();
fb1d9738	466	up_write(&fifo_state->rwsem);
85b9e487 TH	467	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
85b9e487 TH	468	mutex_unlock(&fifo_state->fifo_mutex);
fb1d9738 JB	469	}
fb1d9738 JB	470
6bcd8d3c	471	int vmw_fifo_send_fence(struct vmw_private dev_priv, uint32_t seqno)
fb1d9738 JB	472	{
	473	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	474	struct svga_fifo_cmd_fence *cmd_fence;
	475	void *fm;
	476	int ret = 0;
	477	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
	478
	479	fm = vmw_fifo_reserve(dev_priv, bytes);
	480	if (unlikely(fm == NULL)) {
6bcd8d3c	481	*seqno = atomic_read(&dev_priv->marker_seq);
fb1d9738	482	ret = -ENOMEM;
6bcd8d3c	483	(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
fb1d9738 JB	484	false, 3*HZ);
	485	goto out_err;
	486	}
	487
	488	do {
6bcd8d3c TH	489	*seqno = atomic_add_return(1, &dev_priv->marker_seq);
6bcd8d3c TH	490	} while (*seqno == 0);
fb1d9738 JB	491
	492	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
	493
	494	/*
	495	* Don't request hardware to send a fence. The
	496	* waiting code in vmwgfx_irq.c will emulate this.
	497	*/
	498
	499	vmw_fifo_commit(dev_priv, 0);
	500	return 0;
	501	}
	502
	503	(__le32 ) fm = cpu_to_le32(SVGA_CMD_FENCE);
	504	cmd_fence = (struct svga_fifo_cmd_fence *)
	505	((unsigned long)fm + sizeof(__le32));
	506
6bcd8d3c	507	iowrite32(*seqno, &cmd_fence->fence);
fb1d9738	508	vmw_fifo_commit(dev_priv, bytes);
6bcd8d3c TH	509	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
6bcd8d3c TH	510	vmw_update_seqno(dev_priv, fifo_state);
fb1d9738 JB	511
	512	out_err:
	513	return ret;
	514	}
e2fa3a76 TH	515
	516	/**
	517	* vmw_fifo_emit_dummy_query - emits a dummy query to the fifo.
	518	*
	519	* @dev_priv: The device private structure.
	520	* @cid: The hardware context id used for the query.
	521	*
	522	* This function is used to emit a dummy occlusion query with
	523	* no primitives rendered between query begin and query end.
	524	* It's used to provide a query barrier, in order to know that when
	525	* this query is finished, all preceding queries are also finished.
	526	*
	527	* A Query results structure should have been initialized at the start
	528	* of the dev_priv->dummy_query_bo buffer object. And that buffer object
	529	* must also be either reserved or pinned when this function is called.
	530	*
	531	* Returns -ENOMEM on failure to reserve fifo space.
	532	*/
	533	int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
	534	uint32_t cid)
	535	{
	536	/*
	537	* A query wait without a preceding query end will
	538	* actually finish all queries for this cid
	539	* without writing to the query result structure.
	540	*/
	541
	542	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	543	struct {
	544	SVGA3dCmdHeader header;
	545	SVGA3dCmdWaitForQuery body;
	546	} *cmd;
	547
	548	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
	549
	550	if (unlikely(cmd == NULL)) {
	551	DRM_ERROR("Out of fifo space for dummy query.\n");
	552	return -ENOMEM;
	553	}
	554
	555	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	556	cmd->header.size = sizeof(cmd->body);
	557	cmd->body.cid = cid;
	558	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
	559
	560	if (bo->mem.mem_type == TTM_PL_VRAM) {
	561	cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
	562	cmd->body.guestResult.offset = bo->offset;
	563	} else {
	564	cmd->body.guestResult.gmrId = bo->mem.start;
	565	cmd->body.guestResult.offset = 0;
	566	}
	567
	568	vmw_fifo_commit(dev_priv, sizeof(*cmd));
	569
	570	return 0;
	571	}