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Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965 45#include <crypto/sha.h>
497f2e6b 46#include <crypto/md5.h>
9c4a7965
KP		 47#include <crypto/aead.h>
48#include <crypto/authenc.h>
4de9d0b5 49#include <crypto/skcipher.h>
acbf7c62
LN		 50#include <crypto/hash.h>
51#include <crypto/internal/hash.h>
4de9d0b5 52#include <crypto/scatterwalk.h>
9c4a7965
KP		 53
54#include "talitos.h"
55
81eb024c
KP		 56static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
57{
58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
a752447a 59 talitos_ptr->eptr = upper_32_bits(dma_addr);
81eb024c
KP		 60}
61
9c4a7965
KP		 62/*
63 * map virtual single (contiguous) pointer to h/w descriptor pointer
64 */
65static void map_single_talitos_ptr(struct device *dev,
66 struct talitos_ptr *talitos_ptr,
67 unsigned short len, void *data,
68 unsigned char extent,
69 enum dma_data_direction dir)
70{
81eb024c
KP		 71 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
72
9c4a7965 73 talitos_ptr->len = cpu_to_be16(len);
81eb024c 74 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 75 talitos_ptr->j_extent = extent;
76}
77
78/*
79 * unmap bus single (contiguous) h/w descriptor pointer
80 */
81static void unmap_single_talitos_ptr(struct device *dev,
82 struct talitos_ptr *talitos_ptr,
83 enum dma_data_direction dir)
84{
85 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
86 be16_to_cpu(talitos_ptr->len), dir);
87}
88
89static int reset_channel(struct device *dev, int ch)
90{
91 struct talitos_private *priv = dev_get_drvdata(dev);
92 unsigned int timeout = TALITOS_TIMEOUT;
93
ad42d5fc 94 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
9c4a7965 95
ad42d5fc 96 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
9c4a7965
KP		 97 && --timeout)
98 cpu_relax();
99
100 if (timeout == 0) {
101 dev_err(dev, "failed to reset channel %d\n", ch);
102 return -EIO;
103 }
104
81eb024c 105 /* set 36-bit addressing, done writeback enable and done IRQ enable */
ad42d5fc 106 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
81eb024c 107 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 108
fe5720e2
KP		 109 /* and ICCR writeback, if available */
110 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
ad42d5fc 111 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
fe5720e2
KP		 112 TALITOS_CCCR_LO_IWSE);
113
9c4a7965
KP		 114 return 0;
115}
116
117static int reset_device(struct device *dev)
118{
119 struct talitos_private *priv = dev_get_drvdata(dev);
120 unsigned int timeout = TALITOS_TIMEOUT;
c3e337f8 121 u32 mcr = TALITOS_MCR_SWR;
9c4a7965 122
c3e337f8 123 setbits32(priv->reg + TALITOS_MCR, mcr);
9c4a7965
KP		 124
125 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
126 && --timeout)
127 cpu_relax();
128
2cdba3cf 129 if (priv->irq[1]) {
c3e337f8
KP		 130 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
131 setbits32(priv->reg + TALITOS_MCR, mcr);
132 }
133
9c4a7965
KP		 134 if (timeout == 0) {
135 dev_err(dev, "failed to reset device\n");
136 return -EIO;
137 }
138
139 return 0;
140}
141
142/*
143 * Reset and initialize the device
144 */
145static int init_device(struct device *dev)
146{
147 struct talitos_private *priv = dev_get_drvdata(dev);
148 int ch, err;
149
150 /*
151 * Master reset
152 * errata documentation: warning: certain SEC interrupts
153 * are not fully cleared by writing the MCR:SWR bit,
154 * set bit twice to completely reset
155 */
156 err = reset_device(dev);
157 if (err)
158 return err;
159
160 err = reset_device(dev);
161 if (err)
162 return err;
163
164 /* reset channels */
165 for (ch = 0; ch < priv->num_channels; ch++) {
166 err = reset_channel(dev, ch);
167 if (err)
168 return err;
169 }
170
171 /* enable channel done and error interrupts */
172 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
173 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
174
fe5720e2
KP		 175 /* disable integrity check error interrupts (use writeback instead) */
176 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
177 setbits32(priv->reg + TALITOS_MDEUICR_LO,
178 TALITOS_MDEUICR_LO_ICE);
179
9c4a7965
KP		 180 return 0;
181}
182
183/**
184 * talitos_submit - submits a descriptor to the device for processing
185 * @dev: the SEC device to be used
5228f0f7 186 * @ch: the SEC device channel to be used
9c4a7965
KP		 187 * @desc: the descriptor to be processed by the device
188 * @callback: whom to call when processing is complete
189 * @context: a handle for use by caller (optional)
190 *
191 * desc must contain valid dma-mapped (bus physical) address pointers.
192 * callback must check err and feedback in descriptor header
193 * for device processing status.
194 */
865d5061
HG		 195int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
196 void (*callback)(struct device *dev,
197 struct talitos_desc *desc,
198 void *context, int error),
199 void *context)
9c4a7965
KP		 200{
201 struct talitos_private *priv = dev_get_drvdata(dev);
202 struct talitos_request *request;
5228f0f7 203 unsigned long flags;
9c4a7965
KP		 204 int head;
205
4b992628 206 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 207
4b992628 208 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 209 /* h/w fifo is full */
4b992628 210 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 211 return -EAGAIN;
212 }
213
4b992628
KP		 214 head = priv->chan[ch].head;
215 request = &priv->chan[ch].fifo[head];
ec6644d6 216
9c4a7965
KP		 217 /* map descriptor and save caller data */
218 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
219 DMA_BIDIRECTIONAL);
220 request->callback = callback;
221 request->context = context;
222
223 /* increment fifo head */
4b992628 224 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 225
226 smp_wmb();
227 request->desc = desc;
228
229 /* GO! */
230 wmb();
ad42d5fc
KP		 231 out_be32(priv->chan[ch].reg + TALITOS_FF,
232 upper_32_bits(request->dma_desc));
233 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
a752447a 234 lower_32_bits(request->dma_desc));
9c4a7965 235
4b992628 236 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 237
238 return -EINPROGRESS;
239}
865d5061 240EXPORT_SYMBOL(talitos_submit);
9c4a7965
KP		 241
242/*
243 * process what was done, notify callback of error if not
244 */
245static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
246{
247 struct talitos_private *priv = dev_get_drvdata(dev);
248 struct talitos_request *request, saved_req;
249 unsigned long flags;
250 int tail, status;
251
4b992628 252 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 253
4b992628
KP		 254 tail = priv->chan[ch].tail;
255 while (priv->chan[ch].fifo[tail].desc) {
256 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 257
258 /* descriptors with their done bits set don't get the error */
259 rmb();
ca38a814 260 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 261 status = 0;
ca38a814 262 else
9c4a7965
KP		 263 if (!error)
264 break;
265 else
266 status = error;
267
268 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 269 sizeof(struct talitos_desc),
270 DMA_BIDIRECTIONAL);
9c4a7965
KP		 271
272 /* copy entries so we can call callback outside lock */
273 saved_req.desc = request->desc;
274 saved_req.callback = request->callback;
275 saved_req.context = request->context;
276
277 /* release request entry in fifo */
278 smp_wmb();
279 request->desc = NULL;
280
281 /* increment fifo tail */
4b992628 282 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 283
4b992628 284 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 285
4b992628 286 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 287
9c4a7965
KP		 288 saved_req.callback(dev, saved_req.desc, saved_req.context,
289 status);
290 /* channel may resume processing in single desc error case */
291 if (error && !reset_ch && status == error)
292 return;
4b992628
KP		 293 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
294 tail = priv->chan[ch].tail;
9c4a7965
KP		 295 }
296
4b992628 297 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 298}
299
300/*
301 * process completed requests for channels that have done status
302 */
c3e337f8
KP		 303#define DEF_TALITOS_DONE(name, ch_done_mask) \
304static void talitos_done_##name(unsigned long data) \
305{ \
306 struct device *dev = (struct device *)data; \
307 struct talitos_private *priv = dev_get_drvdata(dev); \
511d63cb 308 unsigned long flags; \
c3e337f8
KP		 309 \
310 if (ch_done_mask & 1) \
311 flush_channel(dev, 0, 0, 0); \
312 if (priv->num_channels == 1) \
313 goto out; \
314 if (ch_done_mask & (1 << 2)) \
315 flush_channel(dev, 1, 0, 0); \
316 if (ch_done_mask & (1 << 4)) \
317 flush_channel(dev, 2, 0, 0); \
318 if (ch_done_mask & (1 << 6)) \
319 flush_channel(dev, 3, 0, 0); \
320 \
321out: \
322 /* At this point, all completed channels have been processed */ \
323 /* Unmask done interrupts for channels completed later on. */ \
511d63cb 324 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 325 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
326 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
511d63cb 327 spin_unlock_irqrestore(&priv->reg_lock, flags); \
9c4a7965 328}
c3e337f8
KP		 329DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
330DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
331DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
9c4a7965
KP		 332
333/*
334 * locate current (offending) descriptor
335 */
3e721aeb 336static u32 current_desc_hdr(struct device *dev, int ch)
9c4a7965
KP		 337{
338 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 339 int tail = priv->chan[ch].tail;
9c4a7965
KP		 340 dma_addr_t cur_desc;
341
ad42d5fc 342 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
9c4a7965 343
4b992628 344 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 345 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 346 if (tail == priv->chan[ch].tail) {
9c4a7965 347 dev_err(dev, "couldn't locate current descriptor\n");
3e721aeb 348 return 0;
9c4a7965
KP		 349 }
350 }
351
3e721aeb 352 return priv->chan[ch].fifo[tail].desc->hdr;
9c4a7965
KP		 353}
354
355/*
356 * user diagnostics; report root cause of error based on execution unit status
357 */
3e721aeb 358static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
9c4a7965
KP		 359{
360 struct talitos_private *priv = dev_get_drvdata(dev);
361 int i;
362
3e721aeb 363 if (!desc_hdr)
ad42d5fc 364 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
3e721aeb
KP		 365
366 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
9c4a7965
KP		 367 case DESC_HDR_SEL0_AFEU:
368 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
369 in_be32(priv->reg + TALITOS_AFEUISR),
370 in_be32(priv->reg + TALITOS_AFEUISR_LO));
371 break;
372 case DESC_HDR_SEL0_DEU:
373 dev_err(dev, "DEUISR 0x%08x_%08x\n",
374 in_be32(priv->reg + TALITOS_DEUISR),
375 in_be32(priv->reg + TALITOS_DEUISR_LO));
376 break;
377 case DESC_HDR_SEL0_MDEUA:
378 case DESC_HDR_SEL0_MDEUB:
379 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
380 in_be32(priv->reg + TALITOS_MDEUISR),
381 in_be32(priv->reg + TALITOS_MDEUISR_LO));
382 break;
383 case DESC_HDR_SEL0_RNG:
384 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
385 in_be32(priv->reg + TALITOS_RNGUISR),
386 in_be32(priv->reg + TALITOS_RNGUISR_LO));
387 break;
388 case DESC_HDR_SEL0_PKEU:
389 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
390 in_be32(priv->reg + TALITOS_PKEUISR),
391 in_be32(priv->reg + TALITOS_PKEUISR_LO));
392 break;
393 case DESC_HDR_SEL0_AESU:
394 dev_err(dev, "AESUISR 0x%08x_%08x\n",
395 in_be32(priv->reg + TALITOS_AESUISR),
396 in_be32(priv->reg + TALITOS_AESUISR_LO));
397 break;
398 case DESC_HDR_SEL0_CRCU:
399 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
400 in_be32(priv->reg + TALITOS_CRCUISR),
401 in_be32(priv->reg + TALITOS_CRCUISR_LO));
402 break;
403 case DESC_HDR_SEL0_KEU:
404 dev_err(dev, "KEUISR 0x%08x_%08x\n",
405 in_be32(priv->reg + TALITOS_KEUISR),
406 in_be32(priv->reg + TALITOS_KEUISR_LO));
407 break;
408 }
409
3e721aeb 410 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
9c4a7965
KP		 411 case DESC_HDR_SEL1_MDEUA:
412 case DESC_HDR_SEL1_MDEUB:
413 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
414 in_be32(priv->reg + TALITOS_MDEUISR),
415 in_be32(priv->reg + TALITOS_MDEUISR_LO));
416 break;
417 case DESC_HDR_SEL1_CRCU:
418 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
419 in_be32(priv->reg + TALITOS_CRCUISR),
420 in_be32(priv->reg + TALITOS_CRCUISR_LO));
421 break;
422 }
423
424 for (i = 0; i < 8; i++)
425 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
ad42d5fc
KP		 426 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
427 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
9c4a7965
KP		 428}
429
430/*
431 * recover from error interrupts
432 */
5e718a09 433static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
9c4a7965 434{
9c4a7965
KP		 435 struct talitos_private *priv = dev_get_drvdata(dev);
436 unsigned int timeout = TALITOS_TIMEOUT;
437 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 438 u32 v, v_lo;
9c4a7965
KP		 439
440 for (ch = 0; ch < priv->num_channels; ch++) {
441 /* skip channels without errors */
442 if (!(isr & (1 << (ch * 2 + 1))))
443 continue;
444
445 error = -EINVAL;
446
ad42d5fc
KP		 447 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
448 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
9c4a7965
KP		 449
450 if (v_lo & TALITOS_CCPSR_LO_DOF) {
451 dev_err(dev, "double fetch fifo overflow error\n");
452 error = -EAGAIN;
453 reset_ch = 1;
454 }
455 if (v_lo & TALITOS_CCPSR_LO_SOF) {
456 /* h/w dropped descriptor */
457 dev_err(dev, "single fetch fifo overflow error\n");
458 error = -EAGAIN;
459 }
460 if (v_lo & TALITOS_CCPSR_LO_MDTE)
461 dev_err(dev, "master data transfer error\n");
462 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
463 dev_err(dev, "s/g data length zero error\n");
464 if (v_lo & TALITOS_CCPSR_LO_FPZ)
465 dev_err(dev, "fetch pointer zero error\n");
466 if (v_lo & TALITOS_CCPSR_LO_IDH)
467 dev_err(dev, "illegal descriptor header error\n");
468 if (v_lo & TALITOS_CCPSR_LO_IEU)
469 dev_err(dev, "invalid execution unit error\n");
470 if (v_lo & TALITOS_CCPSR_LO_EU)
3e721aeb 471 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
9c4a7965
KP		 472 if (v_lo & TALITOS_CCPSR_LO_GB)
473 dev_err(dev, "gather boundary error\n");
474 if (v_lo & TALITOS_CCPSR_LO_GRL)
475 dev_err(dev, "gather return/length error\n");
476 if (v_lo & TALITOS_CCPSR_LO_SB)
477 dev_err(dev, "scatter boundary error\n");
478 if (v_lo & TALITOS_CCPSR_LO_SRL)
479 dev_err(dev, "scatter return/length error\n");
480
481 flush_channel(dev, ch, error, reset_ch);
482
483 if (reset_ch) {
484 reset_channel(dev, ch);
485 } else {
ad42d5fc 486 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
9c4a7965 487 TALITOS_CCCR_CONT);
ad42d5fc
KP		 488 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
489 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
9c4a7965
KP		 490 TALITOS_CCCR_CONT) && --timeout)
491 cpu_relax();
492 if (timeout == 0) {
493 dev_err(dev, "failed to restart channel %d\n",
494 ch);
495 reset_dev = 1;
496 }
497 }
498 }
c3e337f8 499 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
9c4a7965
KP		 500 dev_err(dev, "done overflow, internal time out, or rngu error: "
501 "ISR 0x%08x_%08x\n", isr, isr_lo);
502
503 /* purge request queues */
504 for (ch = 0; ch < priv->num_channels; ch++)
505 flush_channel(dev, ch, -EIO, 1);
506
507 /* reset and reinitialize the device */
508 init_device(dev);
509 }
510}
511
c3e337f8
KP		 512#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
513static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
514{ \
515 struct device *dev = data; \
516 struct talitos_private *priv = dev_get_drvdata(dev); \
517 u32 isr, isr_lo; \
511d63cb 518 unsigned long flags; \
c3e337f8 519 \
511d63cb 520 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 521 isr = in_be32(priv->reg + TALITOS_ISR); \
522 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
523 /* Acknowledge interrupt */ \
524 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
525 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
526 \
511d63cb
HG		 527 if (unlikely(isr & ch_err_mask || isr_lo)) { \
528 spin_unlock_irqrestore(&priv->reg_lock, flags); \
529 talitos_error(dev, isr & ch_err_mask, isr_lo); \
530 } \
531 else { \
c3e337f8
KP		 532 if (likely(isr & ch_done_mask)) { \
533 /* mask further done interrupts. */ \
534 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
535 /* done_task will unmask done interrupts at exit */ \
536 tasklet_schedule(&priv->done_task[tlet]); \
537 } \
511d63cb
HG		 538 spin_unlock_irqrestore(&priv->reg_lock, flags); \
539 } \
c3e337f8
KP		 540 \
541 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
542 IRQ_NONE; \
9c4a7965 543}
c3e337f8
KP		 544DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
545DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
546DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
9c4a7965
KP		 547
548/*
549 * hwrng
550 */
551static int talitos_rng_data_present(struct hwrng *rng, int wait)
552{
553 struct device *dev = (struct device *)rng->priv;
554 struct talitos_private *priv = dev_get_drvdata(dev);
555 u32 ofl;
556 int i;
557
558 for (i = 0; i < 20; i++) {
559 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
560 TALITOS_RNGUSR_LO_OFL;
561 if (ofl || !wait)
562 break;
563 udelay(10);
564 }
565
566 return !!ofl;
567}
568
569static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
570{
571 struct device *dev = (struct device *)rng->priv;
572 struct talitos_private *priv = dev_get_drvdata(dev);
573
574 /* rng fifo requires 64-bit accesses */
575 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
576 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
577
578 return sizeof(u32);
579}
580
581static int talitos_rng_init(struct hwrng *rng)
582{
583 struct device *dev = (struct device *)rng->priv;
584 struct talitos_private *priv = dev_get_drvdata(dev);
585 unsigned int timeout = TALITOS_TIMEOUT;
586
587 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
588 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
589 && --timeout)
590 cpu_relax();
591 if (timeout == 0) {
592 dev_err(dev, "failed to reset rng hw\n");
593 return -ENODEV;
594 }
595
596 /* start generating */
597 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
598
599 return 0;
600}
601
602static int talitos_register_rng(struct device *dev)
603{
604 struct talitos_private *priv = dev_get_drvdata(dev);
605
606 priv->rng.name = dev_driver_string(dev),
607 priv->rng.init = talitos_rng_init,
608 priv->rng.data_present = talitos_rng_data_present,
609 priv->rng.data_read = talitos_rng_data_read,
610 priv->rng.priv = (unsigned long)dev;
611
612 return hwrng_register(&priv->rng);
613}
614
615static void talitos_unregister_rng(struct device *dev)
616{
617 struct talitos_private *priv = dev_get_drvdata(dev);
618
619 hwrng_unregister(&priv->rng);
620}
621
622/*
623 * crypto alg
624 */
625#define TALITOS_CRA_PRIORITY 3000
f9c9c73b 626#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
3952f17e 627#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 628
497f2e6b 629#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 630
631struct talitos_ctx {
632 struct device *dev;
5228f0f7 633 int ch;
9c4a7965
KP		 634 __be32 desc_hdr_template;
635 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 636 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 637 unsigned int keylen;
638 unsigned int enckeylen;
639 unsigned int authkeylen;
640 unsigned int authsize;
641};
642
497f2e6b
LN		 643#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
644#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
645
646struct talitos_ahash_req_ctx {
60f208d7 647 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b
LN		 648 unsigned int hw_context_size;
649 u8 buf[HASH_MAX_BLOCK_SIZE];
650 u8 bufnext[HASH_MAX_BLOCK_SIZE];
60f208d7 651 unsigned int swinit;
497f2e6b
LN		 652 unsigned int first;
653 unsigned int last;
654 unsigned int to_hash_later;
5e833bc4 655 u64 nbuf;
497f2e6b
LN		 656 struct scatterlist bufsl[2];
657 struct scatterlist *psrc;
658};
659
56af8cd4
LN		 660static int aead_setauthsize(struct crypto_aead *authenc,
661 unsigned int authsize)
9c4a7965
KP		 662{
663 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
664
665 ctx->authsize = authsize;
666
667 return 0;
668}
669
56af8cd4
LN		 670static int aead_setkey(struct crypto_aead *authenc,
671 const u8 *key, unsigned int keylen)
9c4a7965
KP		 672{
673 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
674 struct rtattr *rta = (void *)key;
675 struct crypto_authenc_key_param *param;
676 unsigned int authkeylen;
677 unsigned int enckeylen;
678
679 if (!RTA_OK(rta, keylen))
680 goto badkey;
681
682 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
683 goto badkey;
684
685 if (RTA_PAYLOAD(rta) < sizeof(*param))
686 goto badkey;
687
688 param = RTA_DATA(rta);
689 enckeylen = be32_to_cpu(param->enckeylen);
690
691 key += RTA_ALIGN(rta->rta_len);
692 keylen -= RTA_ALIGN(rta->rta_len);
693
694 if (keylen < enckeylen)
695 goto badkey;
696
697 authkeylen = keylen - enckeylen;
698
699 if (keylen > TALITOS_MAX_KEY_SIZE)
700 goto badkey;
701
702 memcpy(&ctx->key, key, keylen);
703
704 ctx->keylen = keylen;
705 ctx->enckeylen = enckeylen;
706 ctx->authkeylen = authkeylen;
707
708 return 0;
709
710badkey:
711 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
712 return -EINVAL;
713}
714
715/*
56af8cd4 716 * talitos_edesc - s/w-extended descriptor
79fd31d3 717 * @assoc_nents: number of segments in associated data scatterlist
9c4a7965
KP		 718 * @src_nents: number of segments in input scatterlist
719 * @dst_nents: number of segments in output scatterlist
79fd31d3 720 * @assoc_chained: whether assoc is chained or not
2a1cfe46
HG		 721 * @src_chained: whether src is chained or not
722 * @dst_chained: whether dst is chained or not
79fd31d3 723 * @iv_dma: dma address of iv for checking continuity and link table
9c4a7965
KP		 724 * @dma_len: length of dma mapped link_tbl space
725 * @dma_link_tbl: bus physical address of link_tbl
726 * @desc: h/w descriptor
727 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
728 *
729 * if decrypting (with authcheck), or either one of src_nents or dst_nents
730 * is greater than 1, an integrity check value is concatenated to the end
731 * of link_tbl data
732 */
56af8cd4 733struct talitos_edesc {
79fd31d3 734 int assoc_nents;
9c4a7965
KP		 735 int src_nents;
736 int dst_nents;
79fd31d3 737 bool assoc_chained;
2a1cfe46
HG		 738 bool src_chained;
739 bool dst_chained;
79fd31d3 740 dma_addr_t iv_dma;
9c4a7965
KP		 741 int dma_len;
742 dma_addr_t dma_link_tbl;
743 struct talitos_desc desc;
744 struct talitos_ptr link_tbl[0];
745};
746
4de9d0b5
LN		 747static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
748 unsigned int nents, enum dma_data_direction dir,
2a1cfe46 749 bool chained)
4de9d0b5
LN		 750{
751 if (unlikely(chained))
752 while (sg) {
753 dma_map_sg(dev, sg, 1, dir);
754 sg = scatterwalk_sg_next(sg);
755 }
756 else
757 dma_map_sg(dev, sg, nents, dir);
758 return nents;
759}
760
761static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
762 enum dma_data_direction dir)
763{
764 while (sg) {
765 dma_unmap_sg(dev, sg, 1, dir);
766 sg = scatterwalk_sg_next(sg);
767 }
768}
769
770static void talitos_sg_unmap(struct device *dev,
771 struct talitos_edesc *edesc,
772 struct scatterlist *src,
773 struct scatterlist *dst)
774{
775 unsigned int src_nents = edesc->src_nents ? : 1;
776 unsigned int dst_nents = edesc->dst_nents ? : 1;
777
778 if (src != dst) {
2a1cfe46 779 if (edesc->src_chained)
4de9d0b5
LN		 780 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
781 else
782 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
783
497f2e6b 784 if (dst) {
2a1cfe46 785 if (edesc->dst_chained)
497f2e6b
LN		 786 talitos_unmap_sg_chain(dev, dst,
787 DMA_FROM_DEVICE);
788 else
789 dma_unmap_sg(dev, dst, dst_nents,
790 DMA_FROM_DEVICE);
791 }
4de9d0b5 792 } else
2a1cfe46 793 if (edesc->src_chained)
4de9d0b5
LN		 794 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
795 else
796 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
797}
798
9c4a7965 799static void ipsec_esp_unmap(struct device *dev,
56af8cd4 800 struct talitos_edesc *edesc,
9c4a7965
KP		 801 struct aead_request *areq)
802{
803 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
804 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
805 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
806 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
807
79fd31d3
HG		 808 if (edesc->assoc_chained)
809 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
810 else
811 /* assoc_nents counts also for IV in non-contiguous cases */
812 dma_unmap_sg(dev, areq->assoc,
813 edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
814 DMA_TO_DEVICE);
9c4a7965 815
4de9d0b5 816 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 817
818 if (edesc->dma_len)
819 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
820 DMA_BIDIRECTIONAL);
821}
822
823/*
824 * ipsec_esp descriptor callbacks
825 */
826static void ipsec_esp_encrypt_done(struct device *dev,
827 struct talitos_desc *desc, void *context,
828 int err)
829{
830 struct aead_request *areq = context;
9c4a7965
KP		 831 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
832 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 833 struct talitos_edesc *edesc;
9c4a7965
KP		 834 struct scatterlist *sg;
835 void *icvdata;
836
19bbbc63
KP		 837 edesc = container_of(desc, struct talitos_edesc, desc);
838
9c4a7965
KP		 839 ipsec_esp_unmap(dev, edesc, areq);
840
841 /* copy the generated ICV to dst */
60542505 842 if (edesc->dst_nents) {
9c4a7965 843 icvdata = &edesc->link_tbl[edesc->src_nents +
79fd31d3
HG		 844 edesc->dst_nents + 2 +
845 edesc->assoc_nents];
9c4a7965
KP		 846 sg = sg_last(areq->dst, edesc->dst_nents);
847 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
848 icvdata, ctx->authsize);
849 }
850
851 kfree(edesc);
852
853 aead_request_complete(areq, err);
854}
855
fe5720e2 856static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 857 struct talitos_desc *desc,
858 void *context, int err)
9c4a7965
KP		 859{
860 struct aead_request *req = context;
9c4a7965
KP		 861 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
862 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 863 struct talitos_edesc *edesc;
9c4a7965
KP		 864 struct scatterlist *sg;
865 void *icvdata;
866
19bbbc63
KP		 867 edesc = container_of(desc, struct talitos_edesc, desc);
868
9c4a7965
KP		 869 ipsec_esp_unmap(dev, edesc, req);
870
871 if (!err) {
872 /* auth check */
873 if (edesc->dma_len)
874 icvdata = &edesc->link_tbl[edesc->src_nents +
79fd31d3
HG		 875 edesc->dst_nents + 2 +
876 edesc->assoc_nents];
9c4a7965
KP		 877 else
878 icvdata = &edesc->link_tbl[0];
879
880 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
881 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
882 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
883 }
884
885 kfree(edesc);
886
887 aead_request_complete(req, err);
888}
889
fe5720e2 890static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 891 struct talitos_desc *desc,
892 void *context, int err)
fe5720e2
KP		 893{
894 struct aead_request *req = context;
19bbbc63
KP		 895 struct talitos_edesc *edesc;
896
897 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 898
899 ipsec_esp_unmap(dev, edesc, req);
900
901 /* check ICV auth status */
e938e465
KP		 902 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
903 DESC_HDR_LO_ICCR1_PASS))
904 err = -EBADMSG;
fe5720e2
KP		 905
906 kfree(edesc);
907
908 aead_request_complete(req, err);
909}
910
9c4a7965
KP		 911/*
912 * convert scatterlist to SEC h/w link table format
913 * stop at cryptlen bytes
914 */
70bcaca7 915static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 916 int cryptlen, struct talitos_ptr *link_tbl_ptr)
917{
70bcaca7
LN		 918 int n_sg = sg_count;
919
920 while (n_sg--) {
81eb024c 921 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 922 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
923 link_tbl_ptr->j_extent = 0;
924 link_tbl_ptr++;
925 cryptlen -= sg_dma_len(sg);
4de9d0b5 926 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 927 }
928
70bcaca7 929 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 930 link_tbl_ptr--;
c0e741d4 931 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 932 /* Empty this entry, and move to previous one */
933 cryptlen += be16_to_cpu(link_tbl_ptr->len);
934 link_tbl_ptr->len = 0;
935 sg_count--;
936 link_tbl_ptr--;
937 }
fd2db9b7
HG		 938 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
939 + cryptlen);
9c4a7965
KP		 940
941 /* tag end of link table */
942 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 943
944 return sg_count;
9c4a7965
KP		 945}
946
947/*
948 * fill in and submit ipsec_esp descriptor
949 */
56af8cd4 950static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
79fd31d3
HG		 951 u64 seq, void (*callback) (struct device *dev,
952 struct talitos_desc *desc,
953 void *context, int error))
9c4a7965
KP		 954{
955 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
956 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
957 struct device *dev = ctx->dev;
958 struct talitos_desc *desc = &edesc->desc;
959 unsigned int cryptlen = areq->cryptlen;
960 unsigned int authsize = ctx->authsize;
e41256f1 961 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 962 int sg_count, ret;
fe5720e2 963 int sg_link_tbl_len;
9c4a7965
KP		 964
965 /* hmac key */
966 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
967 0, DMA_TO_DEVICE);
79fd31d3 968
9c4a7965 969 /* hmac data */
79fd31d3
HG		 970 desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
971 if (edesc->assoc_nents) {
972 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
973 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
974
975 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
976 sizeof(struct talitos_ptr));
977 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
978
979 /* assoc_nents - 1 entries for assoc, 1 for IV */
980 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
981 areq->assoclen, tbl_ptr);
982
983 /* add IV to link table */
984 tbl_ptr += sg_count - 1;
985 tbl_ptr->j_extent = 0;
986 tbl_ptr++;
987 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
988 tbl_ptr->len = cpu_to_be16(ivsize);
989 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
990
991 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
992 edesc->dma_len, DMA_BIDIRECTIONAL);
993 } else {
994 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc));
995 desc->ptr[1].j_extent = 0;
996 }
997
9c4a7965 998 /* cipher iv */
79fd31d3
HG		 999 to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
1000 desc->ptr[2].len = cpu_to_be16(ivsize);
1001 desc->ptr[2].j_extent = 0;
1002 /* Sync needed for the aead_givencrypt case */
1003 dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
9c4a7965
KP		 1004
1005 /* cipher key */
1006 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1007 (char *)&ctx->key + ctx->authkeylen, 0,
1008 DMA_TO_DEVICE);
1009
1010 /*
1011 * cipher in
1012 * map and adjust cipher len to aead request cryptlen.
1013 * extent is bytes of HMAC postpended to ciphertext,
1014 * typically 12 for ipsec
1015 */
1016 desc->ptr[4].len = cpu_to_be16(cryptlen);
1017 desc->ptr[4].j_extent = authsize;
1018
e938e465
KP		 1019 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1020 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1021 : DMA_TO_DEVICE,
2a1cfe46 1022 edesc->src_chained);
9c4a7965
KP		 1023
1024 if (sg_count == 1) {
81eb024c 1025 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 1026 } else {
fe5720e2
KP		 1027 sg_link_tbl_len = cryptlen;
1028
962a9c99 1029 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 1030 sg_link_tbl_len = cryptlen + authsize;
e938e465 1031
fe5720e2 1032 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 1033 &edesc->link_tbl[0]);
1034 if (sg_count > 1) {
1035 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 1036 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 1037 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1038 edesc->dma_len,
1039 DMA_BIDIRECTIONAL);
70bcaca7
LN		 1040 } else {
1041 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1042 to_talitos_ptr(&desc->ptr[4],
1043 sg_dma_address(areq->src));
70bcaca7 1044 }
9c4a7965
KP		 1045 }
1046
1047 /* cipher out */
1048 desc->ptr[5].len = cpu_to_be16(cryptlen);
1049 desc->ptr[5].j_extent = authsize;
1050
e938e465 1051 if (areq->src != areq->dst)
4de9d0b5
LN		 1052 sg_count = talitos_map_sg(dev, areq->dst,
1053 edesc->dst_nents ? : 1,
2a1cfe46 1054 DMA_FROM_DEVICE, edesc->dst_chained);
9c4a7965
KP		 1055
1056 if (sg_count == 1) {
81eb024c 1057 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965 1058 } else {
79fd31d3
HG		 1059 int tbl_off = edesc->src_nents + 1;
1060 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
9c4a7965 1061
81eb024c 1062 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
79fd31d3 1063 tbl_off * sizeof(struct talitos_ptr));
fe5720e2 1064 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
79fd31d3 1065 tbl_ptr);
fe5720e2 1066
f3c85bc1 1067 /* Add an entry to the link table for ICV data */
79fd31d3
HG		 1068 tbl_ptr += sg_count - 1;
1069 tbl_ptr->j_extent = 0;
1070 tbl_ptr++;
1071 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1072 tbl_ptr->len = cpu_to_be16(authsize);
9c4a7965
KP		 1073
1074 /* icv data follows link tables */
79fd31d3
HG		 1075 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1076 (tbl_off + edesc->dst_nents + 1 +
1077 edesc->assoc_nents) *
81eb024c 1078 sizeof(struct talitos_ptr));
9c4a7965
KP		 1079 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1080 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1081 edesc->dma_len, DMA_BIDIRECTIONAL);
1082 }
1083
1084 /* iv out */
1085 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1086 DMA_FROM_DEVICE);
1087
5228f0f7 1088 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1089 if (ret != -EINPROGRESS) {
1090 ipsec_esp_unmap(dev, edesc, areq);
1091 kfree(edesc);
1092 }
1093 return ret;
9c4a7965
KP		 1094}
1095
9c4a7965
KP		 1096/*
1097 * derive number of elements in scatterlist
1098 */
2a1cfe46 1099static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
9c4a7965
KP		 1100{
1101 struct scatterlist *sg = sg_list;
1102 int sg_nents = 0;
1103
2a1cfe46 1104 *chained = false;
4de9d0b5 1105 while (nbytes > 0) {
9c4a7965
KP		 1106 sg_nents++;
1107 nbytes -= sg->length;
4de9d0b5 1108 if (!sg_is_last(sg) && (sg + 1)->length == 0)
2a1cfe46 1109 *chained = true;
4de9d0b5 1110 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1111 }
1112
1113 return sg_nents;
1114}
1115
497f2e6b
LN		 1116/**
1117 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1118 * @sgl: The SG list
1119 * @nents: Number of SG entries
1120 * @buf: Where to copy to
1121 * @buflen: The number of bytes to copy
1122 * @skip: The number of bytes to skip before copying.
1123 * Note: skip + buflen should equal SG total size.
1124 *
1125 * Returns the number of copied bytes.
1126 *
1127 **/
1128static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1129 void *buf, size_t buflen, unsigned int skip)
1130{
1131 unsigned int offset = 0;
1132 unsigned int boffset = 0;
1133 struct sg_mapping_iter miter;
1134 unsigned long flags;
1135 unsigned int sg_flags = SG_MITER_ATOMIC;
1136 size_t total_buffer = buflen + skip;
1137
1138 sg_flags |= SG_MITER_FROM_SG;
1139
1140 sg_miter_start(&miter, sgl, nents, sg_flags);
1141
1142 local_irq_save(flags);
1143
1144 while (sg_miter_next(&miter) && offset < total_buffer) {
1145 unsigned int len;
1146 unsigned int ignore;
1147
1148 if ((offset + miter.length) > skip) {
1149 if (offset < skip) {
1150 /* Copy part of this segment */
1151 ignore = skip - offset;
1152 len = miter.length - ignore;
7260042b
LN		 1153 if (boffset + len > buflen)
1154 len = buflen - boffset;
497f2e6b
LN		 1155 memcpy(buf + boffset, miter.addr + ignore, len);
1156 } else {
7260042b 1157 /* Copy all of this segment (up to buflen) */
497f2e6b 1158 len = miter.length;
7260042b
LN		 1159 if (boffset + len > buflen)
1160 len = buflen - boffset;
497f2e6b
LN		 1161 memcpy(buf + boffset, miter.addr, len);
1162 }
1163 boffset += len;
1164 }
1165 offset += miter.length;
1166 }
1167
1168 sg_miter_stop(&miter);
1169
1170 local_irq_restore(flags);
1171 return boffset;
1172}
1173
9c4a7965 1174/*
56af8cd4 1175 * allocate and map the extended descriptor
9c4a7965 1176 */
4de9d0b5 1177static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
79fd31d3 1178 struct scatterlist *assoc,
4de9d0b5
LN		 1179 struct scatterlist *src,
1180 struct scatterlist *dst,
79fd31d3
HG		 1181 u8 *iv,
1182 unsigned int assoclen,
4de9d0b5
LN		 1183 unsigned int cryptlen,
1184 unsigned int authsize,
79fd31d3 1185 unsigned int ivsize,
4de9d0b5
LN		 1186 int icv_stashing,
1187 u32 cryptoflags)
9c4a7965 1188{
56af8cd4 1189 struct talitos_edesc *edesc;
79fd31d3
HG		 1190 int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1191 bool assoc_chained = false, src_chained = false, dst_chained = false;
1192 dma_addr_t iv_dma = 0;
4de9d0b5 1193 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1194 GFP_ATOMIC;
9c4a7965 1195
4de9d0b5
LN		 1196 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1197 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1198 return ERR_PTR(-EINVAL);
1199 }
1200
79fd31d3
HG		 1201 if (iv)
1202 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1203
1204 if (assoc) {
1205 /*
1206 * Currently it is assumed that iv is provided whenever assoc
1207 * is.
1208 */
1209 BUG_ON(!iv);
1210
1211 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1212 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1213 assoc_chained);
1214 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1215
1216 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1217 assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1218 }
1219
4de9d0b5 1220 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1221 src_nents = (src_nents == 1) ? 0 : src_nents;
1222
602499a3 1223 if (!dst) {
497f2e6b 1224 dst_nents = 0;
9c4a7965 1225 } else {
497f2e6b
LN		 1226 if (dst == src) {
1227 dst_nents = src_nents;
1228 } else {
1229 dst_nents = sg_count(dst, cryptlen + authsize,
1230 &dst_chained);
1231 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1232 }
9c4a7965
KP		 1233 }
1234
1235 /*
1236 * allocate space for base edesc plus the link tables,
f3c85bc1 1237 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1238 * and the ICV data itself
1239 */
56af8cd4 1240 alloc_len = sizeof(struct talitos_edesc);
79fd31d3
HG		 1241 if (assoc_nents || src_nents || dst_nents) {
1242 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1243 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1244 alloc_len += dma_len;
1245 } else {
1246 dma_len = 0;
4de9d0b5 1247 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1248 }
1249
586725f8 1250 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1251 if (!edesc) {
79fd31d3
HG		 1252 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1253 if (iv_dma)
1254 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
4de9d0b5 1255 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1256 return ERR_PTR(-ENOMEM);
1257 }
1258
79fd31d3 1259 edesc->assoc_nents = assoc_nents;
9c4a7965
KP		 1260 edesc->src_nents = src_nents;
1261 edesc->dst_nents = dst_nents;
79fd31d3 1262 edesc->assoc_chained = assoc_chained;
2a1cfe46
HG		 1263 edesc->src_chained = src_chained;
1264 edesc->dst_chained = dst_chained;
79fd31d3 1265 edesc->iv_dma = iv_dma;
9c4a7965 1266 edesc->dma_len = dma_len;
497f2e6b
LN		 1267 if (dma_len)
1268 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1269 edesc->dma_len,
1270 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1271
1272 return edesc;
1273}
1274
79fd31d3 1275static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
4de9d0b5
LN		 1276 int icv_stashing)
1277{
1278 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1279 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
79fd31d3 1280 unsigned int ivsize = crypto_aead_ivsize(authenc);
4de9d0b5 1281
79fd31d3
HG		 1282 return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1283 iv, areq->assoclen, areq->cryptlen,
1284 ctx->authsize, ivsize, icv_stashing,
4de9d0b5
LN		 1285 areq->base.flags);
1286}
1287
56af8cd4 1288static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1289{
1290 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1291 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1292 struct talitos_edesc *edesc;
9c4a7965
KP		 1293
1294 /* allocate extended descriptor */
79fd31d3 1295 edesc = aead_edesc_alloc(req, req->iv, 0);
9c4a7965
KP		 1296 if (IS_ERR(edesc))
1297 return PTR_ERR(edesc);
1298
1299 /* set encrypt */
70bcaca7 1300 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965 1301
79fd31d3 1302 return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
9c4a7965
KP		 1303}
1304
56af8cd4 1305static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1306{
1307 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1308 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1309 unsigned int authsize = ctx->authsize;
fe5720e2 1310 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1311 struct talitos_edesc *edesc;
9c4a7965
KP		 1312 struct scatterlist *sg;
1313 void *icvdata;
1314
1315 req->cryptlen -= authsize;
1316
1317 /* allocate extended descriptor */
79fd31d3 1318 edesc = aead_edesc_alloc(req, req->iv, 1);
9c4a7965
KP		 1319 if (IS_ERR(edesc))
1320 return PTR_ERR(edesc);
1321
fe5720e2 1322 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1323 ((!edesc->src_nents && !edesc->dst_nents) ||
1324 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1325
fe5720e2 1326 /* decrypt and check the ICV */
e938e465
KP		 1327 edesc->desc.hdr = ctx->desc_hdr_template |
1328 DESC_HDR_DIR_INBOUND |
fe5720e2 1329 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1330
fe5720e2
KP		 1331 /* reset integrity check result bits */
1332 edesc->desc.hdr_lo = 0;
9c4a7965 1333
79fd31d3 1334 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
e938e465 1335 }
fe5720e2 1336
e938e465
KP		 1337 /* Have to check the ICV with software */
1338 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1339
e938e465
KP		 1340 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1341 if (edesc->dma_len)
1342 icvdata = &edesc->link_tbl[edesc->src_nents +
79fd31d3
HG		 1343 edesc->dst_nents + 2 +
1344 edesc->assoc_nents];
e938e465
KP		 1345 else
1346 icvdata = &edesc->link_tbl[0];
fe5720e2 1347
e938e465 1348 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1349
e938e465
KP		 1350 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1351 ctx->authsize);
fe5720e2 1352
79fd31d3 1353 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1354}
1355
56af8cd4 1356static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1357{
1358 struct aead_request *areq = &req->areq;
1359 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1360 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1361 struct talitos_edesc *edesc;
9c4a7965
KP		 1362
1363 /* allocate extended descriptor */
79fd31d3 1364 edesc = aead_edesc_alloc(areq, req->giv, 0);
9c4a7965
KP		 1365 if (IS_ERR(edesc))
1366 return PTR_ERR(edesc);
1367
1368 /* set encrypt */
70bcaca7 1369 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1370
1371 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1372 /* avoid consecutive packets going out with same IV */
1373 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965 1374
79fd31d3 1375 return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
9c4a7965
KP		 1376}
1377
4de9d0b5
LN		 1378static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1379 const u8 *key, unsigned int keylen)
1380{
1381 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
4de9d0b5 1382
f9c9c73b
MH		 1383 if (keylen > TALITOS_MAX_KEY_SIZE) {
1384 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1385 return -EINVAL;
1386 }
1387
4de9d0b5
LN		 1388 memcpy(&ctx->key, key, keylen);
1389 ctx->keylen = keylen;
1390
1391 return 0;
4de9d0b5
LN		 1392}
1393
1394static void common_nonsnoop_unmap(struct device *dev,
1395 struct talitos_edesc *edesc,
1396 struct ablkcipher_request *areq)
1397{
1398 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1399 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1400 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1401
1402 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1403
1404 if (edesc->dma_len)
1405 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1406 DMA_BIDIRECTIONAL);
1407}
1408
1409static void ablkcipher_done(struct device *dev,
1410 struct talitos_desc *desc, void *context,
1411 int err)
1412{
1413 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1414 struct talitos_edesc *edesc;
1415
1416 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1417
1418 common_nonsnoop_unmap(dev, edesc, areq);
1419
1420 kfree(edesc);
1421
1422 areq->base.complete(&areq->base, err);
1423}
1424
1425static int common_nonsnoop(struct talitos_edesc *edesc,
1426 struct ablkcipher_request *areq,
4de9d0b5
LN		 1427 void (*callback) (struct device *dev,
1428 struct talitos_desc *desc,
1429 void *context, int error))
1430{
1431 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1432 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1433 struct device *dev = ctx->dev;
1434 struct talitos_desc *desc = &edesc->desc;
1435 unsigned int cryptlen = areq->nbytes;
79fd31d3 1436 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
4de9d0b5
LN		 1437 int sg_count, ret;
1438
1439 /* first DWORD empty */
1440 desc->ptr[0].len = 0;
81eb024c 1441 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1442 desc->ptr[0].j_extent = 0;
1443
1444 /* cipher iv */
79fd31d3
HG		 1445 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1446 desc->ptr[1].len = cpu_to_be16(ivsize);
1447 desc->ptr[1].j_extent = 0;
4de9d0b5
LN		 1448
1449 /* cipher key */
1450 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1451 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1452
1453 /*
1454 * cipher in
1455 */
1456 desc->ptr[3].len = cpu_to_be16(cryptlen);
1457 desc->ptr[3].j_extent = 0;
1458
1459 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1460 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1461 : DMA_TO_DEVICE,
2a1cfe46 1462 edesc->src_chained);
4de9d0b5
LN		 1463
1464 if (sg_count == 1) {
81eb024c 1465 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1466 } else {
1467 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1468 &edesc->link_tbl[0]);
1469 if (sg_count > 1) {
81eb024c 1470 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1471 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1472 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1473 edesc->dma_len,
1474 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1475 } else {
1476 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1477 to_talitos_ptr(&desc->ptr[3],
1478 sg_dma_address(areq->src));
4de9d0b5
LN		 1479 }
1480 }
1481
1482 /* cipher out */
1483 desc->ptr[4].len = cpu_to_be16(cryptlen);
1484 desc->ptr[4].j_extent = 0;
1485
1486 if (areq->src != areq->dst)
1487 sg_count = talitos_map_sg(dev, areq->dst,
1488 edesc->dst_nents ? : 1,
2a1cfe46 1489 DMA_FROM_DEVICE, edesc->dst_chained);
4de9d0b5
LN		 1490
1491 if (sg_count == 1) {
81eb024c 1492 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1493 } else {
1494 struct talitos_ptr *link_tbl_ptr =
1495 &edesc->link_tbl[edesc->src_nents + 1];
1496
81eb024c
KP		 1497 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1498 (edesc->src_nents + 1) *
1499 sizeof(struct talitos_ptr));
4de9d0b5 1500 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1501 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1502 link_tbl_ptr);
1503 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1504 edesc->dma_len, DMA_BIDIRECTIONAL);
1505 }
1506
1507 /* iv out */
1508 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1509 DMA_FROM_DEVICE);
1510
1511 /* last DWORD empty */
1512 desc->ptr[6].len = 0;
81eb024c 1513 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1514 desc->ptr[6].j_extent = 0;
1515
5228f0f7 1516 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1517 if (ret != -EINPROGRESS) {
1518 common_nonsnoop_unmap(dev, edesc, areq);
1519 kfree(edesc);
1520 }
1521 return ret;
1522}
1523
e938e465
KP		 1524static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1525 areq)
4de9d0b5
LN		 1526{
1527 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1528 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
79fd31d3 1529 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
4de9d0b5 1530
79fd31d3
HG		 1531 return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1532 areq->info, 0, areq->nbytes, 0, ivsize, 0,
1533 areq->base.flags);
4de9d0b5
LN		 1534}
1535
1536static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1537{
1538 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1539 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1540 struct talitos_edesc *edesc;
1541
1542 /* allocate extended descriptor */
1543 edesc = ablkcipher_edesc_alloc(areq);
1544 if (IS_ERR(edesc))
1545 return PTR_ERR(edesc);
1546
1547 /* set encrypt */
1548 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1549
febec542 1550 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1551}
1552
1553static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1554{
1555 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1556 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1557 struct talitos_edesc *edesc;
1558
1559 /* allocate extended descriptor */
1560 edesc = ablkcipher_edesc_alloc(areq);
1561 if (IS_ERR(edesc))
1562 return PTR_ERR(edesc);
1563
1564 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1565
febec542 1566 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1567}
1568
497f2e6b
LN		 1569static void common_nonsnoop_hash_unmap(struct device *dev,
1570 struct talitos_edesc *edesc,
1571 struct ahash_request *areq)
1572{
1573 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1574
1575 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1576
1577 /* When using hashctx-in, must unmap it. */
1578 if (edesc->desc.ptr[1].len)
1579 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1580 DMA_TO_DEVICE);
1581
1582 if (edesc->desc.ptr[2].len)
1583 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1584 DMA_TO_DEVICE);
1585
1586 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1587
1588 if (edesc->dma_len)
1589 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1590 DMA_BIDIRECTIONAL);
1591
1592}
1593
1594static void ahash_done(struct device *dev,
1595 struct talitos_desc *desc, void *context,
1596 int err)
1597{
1598 struct ahash_request *areq = context;
1599 struct talitos_edesc *edesc =
1600 container_of(desc, struct talitos_edesc, desc);
1601 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1602
1603 if (!req_ctx->last && req_ctx->to_hash_later) {
1604 /* Position any partial block for next update/final/finup */
1605 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
5e833bc4 1606 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1607 }
1608 common_nonsnoop_hash_unmap(dev, edesc, areq);
1609
1610 kfree(edesc);
1611
1612 areq->base.complete(&areq->base, err);
1613}
1614
1615static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1616 struct ahash_request *areq, unsigned int length,
1617 void (*callback) (struct device *dev,
1618 struct talitos_desc *desc,
1619 void *context, int error))
1620{
1621 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1622 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1623 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1624 struct device *dev = ctx->dev;
1625 struct talitos_desc *desc = &edesc->desc;
1626 int sg_count, ret;
1627
1628 /* first DWORD empty */
1629 desc->ptr[0] = zero_entry;
1630
60f208d7
KP		 1631 /* hash context in */
1632 if (!req_ctx->first || req_ctx->swinit) {
497f2e6b
LN		 1633 map_single_talitos_ptr(dev, &desc->ptr[1],
1634 req_ctx->hw_context_size,
1635 (char *)req_ctx->hw_context, 0,
1636 DMA_TO_DEVICE);
60f208d7 1637 req_ctx->swinit = 0;
497f2e6b
LN		 1638 } else {
1639 desc->ptr[1] = zero_entry;
1640 /* Indicate next op is not the first. */
1641 req_ctx->first = 0;
1642 }
1643
1644 /* HMAC key */
1645 if (ctx->keylen)
1646 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1647 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1648 else
1649 desc->ptr[2] = zero_entry;
1650
1651 /*
1652 * data in
1653 */
1654 desc->ptr[3].len = cpu_to_be16(length);
1655 desc->ptr[3].j_extent = 0;
1656
1657 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1658 edesc->src_nents ? : 1,
2a1cfe46 1659 DMA_TO_DEVICE, edesc->src_chained);
497f2e6b
LN		 1660
1661 if (sg_count == 1) {
1662 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1663 } else {
1664 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1665 &edesc->link_tbl[0]);
1666 if (sg_count > 1) {
1667 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1668 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1669 dma_sync_single_for_device(ctx->dev,
1670 edesc->dma_link_tbl,
1671 edesc->dma_len,
1672 DMA_BIDIRECTIONAL);
1673 } else {
1674 /* Only one segment now, so no link tbl needed */
1675 to_talitos_ptr(&desc->ptr[3],
1676 sg_dma_address(req_ctx->psrc));
1677 }
1678 }
1679
1680 /* fifth DWORD empty */
1681 desc->ptr[4] = zero_entry;
1682
1683 /* hash/HMAC out -or- hash context out */
1684 if (req_ctx->last)
1685 map_single_talitos_ptr(dev, &desc->ptr[5],
1686 crypto_ahash_digestsize(tfm),
1687 areq->result, 0, DMA_FROM_DEVICE);
1688 else
1689 map_single_talitos_ptr(dev, &desc->ptr[5],
1690 req_ctx->hw_context_size,
1691 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1692
1693 /* last DWORD empty */
1694 desc->ptr[6] = zero_entry;
1695
5228f0f7 1696 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1697 if (ret != -EINPROGRESS) {
1698 common_nonsnoop_hash_unmap(dev, edesc, areq);
1699 kfree(edesc);
1700 }
1701 return ret;
1702}
1703
1704static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1705 unsigned int nbytes)
1706{
1707 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1708 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1709 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1710
79fd31d3
HG		 1711 return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1712 nbytes, 0, 0, 0, areq->base.flags);
497f2e6b
LN		 1713}
1714
1715static int ahash_init(struct ahash_request *areq)
1716{
1717 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1718 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1719
1720 /* Initialize the context */
5e833bc4 1721 req_ctx->nbuf = 0;
60f208d7
KP		 1722 req_ctx->first = 1; /* first indicates h/w must init its context */
1723 req_ctx->swinit = 0; /* assume h/w init of context */
497f2e6b
LN		 1724 req_ctx->hw_context_size =
1725 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1726 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1727 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1728
1729 return 0;
1730}
1731
60f208d7
KP		 1732/*
1733 * on h/w without explicit sha224 support, we initialize h/w context
1734 * manually with sha224 constants, and tell it to run sha256.
1735 */
1736static int ahash_init_sha224_swinit(struct ahash_request *areq)
1737{
1738 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1739
1740 ahash_init(areq);
1741 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1742
a752447a
KP		 1743 req_ctx->hw_context[0] = SHA224_H0;
1744 req_ctx->hw_context[1] = SHA224_H1;
1745 req_ctx->hw_context[2] = SHA224_H2;
1746 req_ctx->hw_context[3] = SHA224_H3;
1747 req_ctx->hw_context[4] = SHA224_H4;
1748 req_ctx->hw_context[5] = SHA224_H5;
1749 req_ctx->hw_context[6] = SHA224_H6;
1750 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1751
1752 /* init 64-bit count */
1753 req_ctx->hw_context[8] = 0;
1754 req_ctx->hw_context[9] = 0;
1755
1756 return 0;
1757}
1758
497f2e6b
LN		 1759static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1760{
1761 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1762 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1763 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1764 struct talitos_edesc *edesc;
1765 unsigned int blocksize =
1766 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1767 unsigned int nbytes_to_hash;
1768 unsigned int to_hash_later;
5e833bc4 1769 unsigned int nsg;
2a1cfe46 1770 bool chained;
497f2e6b 1771
5e833bc4
LN		 1772 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1773 /* Buffer up to one whole block */
497f2e6b
LN		 1774 sg_copy_to_buffer(areq->src,
1775 sg_count(areq->src, nbytes, &chained),
5e833bc4
LN		 1776 req_ctx->buf + req_ctx->nbuf, nbytes);
1777 req_ctx->nbuf += nbytes;
497f2e6b
LN		 1778 return 0;
1779 }
1780
5e833bc4
LN		 1781 /* At least (blocksize + 1) bytes are available to hash */
1782 nbytes_to_hash = nbytes + req_ctx->nbuf;
1783 to_hash_later = nbytes_to_hash & (blocksize - 1);
1784
1785 if (req_ctx->last)
1786 to_hash_later = 0;
1787 else if (to_hash_later)
1788 /* There is a partial block. Hash the full block(s) now */
1789 nbytes_to_hash -= to_hash_later;
1790 else {
1791 /* Keep one block buffered */
1792 nbytes_to_hash -= blocksize;
1793 to_hash_later = blocksize;
1794 }
1795
1796 /* Chain in any previously buffered data */
1797 if (req_ctx->nbuf) {
1798 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1799 sg_init_table(req_ctx->bufsl, nsg);
1800 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1801 if (nsg > 1)
1802 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 1803 req_ctx->psrc = req_ctx->bufsl;
5e833bc4 1804 } else
497f2e6b 1805 req_ctx->psrc = areq->src;
5e833bc4
LN		 1806
1807 if (to_hash_later) {
1808 int nents = sg_count(areq->src, nbytes, &chained);
1809 sg_copy_end_to_buffer(areq->src, nents,
1810 req_ctx->bufnext,
1811 to_hash_later,
1812 nbytes - to_hash_later);
497f2e6b 1813 }
5e833bc4 1814 req_ctx->to_hash_later = to_hash_later;
497f2e6b 1815
5e833bc4 1816 /* Allocate extended descriptor */
497f2e6b
LN		 1817 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1818 if (IS_ERR(edesc))
1819 return PTR_ERR(edesc);
1820
1821 edesc->desc.hdr = ctx->desc_hdr_template;
1822
1823 /* On last one, request SEC to pad; otherwise continue */
1824 if (req_ctx->last)
1825 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1826 else
1827 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1828
60f208d7
KP		 1829 /* request SEC to INIT hash. */
1830 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 1831 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1832
1833 /* When the tfm context has a keylen, it's an HMAC.
1834 * A first or last (ie. not middle) descriptor must request HMAC.
1835 */
1836 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1837 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1838
1839 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1840 ahash_done);
1841}
1842
1843static int ahash_update(struct ahash_request *areq)
1844{
1845 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1846
1847 req_ctx->last = 0;
1848
1849 return ahash_process_req(areq, areq->nbytes);
1850}
1851
1852static int ahash_final(struct ahash_request *areq)
1853{
1854 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1855
1856 req_ctx->last = 1;
1857
1858 return ahash_process_req(areq, 0);
1859}
1860
1861static int ahash_finup(struct ahash_request *areq)
1862{
1863 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1864
1865 req_ctx->last = 1;
1866
1867 return ahash_process_req(areq, areq->nbytes);
1868}
1869
1870static int ahash_digest(struct ahash_request *areq)
1871{
1872 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 1873 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 1874
60f208d7 1875 ahash->init(areq);
497f2e6b
LN		 1876 req_ctx->last = 1;
1877
1878 return ahash_process_req(areq, areq->nbytes);
1879}
1880
79b3a418
LN		 1881struct keyhash_result {
1882 struct completion completion;
1883 int err;
1884};
1885
1886static void keyhash_complete(struct crypto_async_request *req, int err)
1887{
1888 struct keyhash_result *res = req->data;
1889
1890 if (err == -EINPROGRESS)
1891 return;
1892
1893 res->err = err;
1894 complete(&res->completion);
1895}
1896
1897static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1898 u8 *hash)
1899{
1900 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1901
1902 struct scatterlist sg[1];
1903 struct ahash_request *req;
1904 struct keyhash_result hresult;
1905 int ret;
1906
1907 init_completion(&hresult.completion);
1908
1909 req = ahash_request_alloc(tfm, GFP_KERNEL);
1910 if (!req)
1911 return -ENOMEM;
1912
1913 /* Keep tfm keylen == 0 during hash of the long key */
1914 ctx->keylen = 0;
1915 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1916 keyhash_complete, &hresult);
1917
1918 sg_init_one(&sg[0], key, keylen);
1919
1920 ahash_request_set_crypt(req, sg, hash, keylen);
1921 ret = crypto_ahash_digest(req);
1922 switch (ret) {
1923 case 0:
1924 break;
1925 case -EINPROGRESS:
1926 case -EBUSY:
1927 ret = wait_for_completion_interruptible(
1928 &hresult.completion);
1929 if (!ret)
1930 ret = hresult.err;
1931 break;
1932 default:
1933 break;
1934 }
1935 ahash_request_free(req);
1936
1937 return ret;
1938}
1939
1940static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1941 unsigned int keylen)
1942{
1943 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1944 unsigned int blocksize =
1945 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1946 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1947 unsigned int keysize = keylen;
1948 u8 hash[SHA512_DIGEST_SIZE];
1949 int ret;
1950
1951 if (keylen <= blocksize)
1952 memcpy(ctx->key, key, keysize);
1953 else {
1954 /* Must get the hash of the long key */
1955 ret = keyhash(tfm, key, keylen, hash);
1956
1957 if (ret) {
1958 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1959 return -EINVAL;
1960 }
1961
1962 keysize = digestsize;
1963 memcpy(ctx->key, hash, digestsize);
1964 }
1965
1966 ctx->keylen = keysize;
1967
1968 return 0;
1969}
1970
1971
9c4a7965 1972struct talitos_alg_template {
d5e4aaef
LN		 1973 u32 type;
1974 union {
1975 struct crypto_alg crypto;
acbf7c62 1976 struct ahash_alg hash;
d5e4aaef 1977 } alg;
9c4a7965
KP		 1978 __be32 desc_hdr_template;
1979};
1980
1981static struct talitos_alg_template driver_algs[] = {
991155ba 1982 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1983 { .type = CRYPTO_ALG_TYPE_AEAD,
1984 .alg.crypto = {
56af8cd4
LN		 1985 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1986 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1987 .cra_blocksize = AES_BLOCK_SIZE,
1988 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 1989 .cra_aead = {
56af8cd4
LN		 1990 .ivsize = AES_BLOCK_SIZE,
1991 .maxauthsize = SHA1_DIGEST_SIZE,
1992 }
1993 },
9c4a7965
KP		 1994 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1995 DESC_HDR_SEL0_AESU |
1996 DESC_HDR_MODE0_AESU_CBC |
1997 DESC_HDR_SEL1_MDEUA |
1998 DESC_HDR_MODE1_MDEU_INIT |
1999 DESC_HDR_MODE1_MDEU_PAD |
2000 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 2001 },
d5e4aaef
LN		 2002 { .type = CRYPTO_ALG_TYPE_AEAD,
2003 .alg.crypto = {
56af8cd4
LN		 2004 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
2005 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
2006 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2007 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2008 .cra_aead = {
56af8cd4
LN		 2009 .ivsize = DES3_EDE_BLOCK_SIZE,
2010 .maxauthsize = SHA1_DIGEST_SIZE,
2011 }
2012 },
70bcaca7
LN		 2013 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2014 DESC_HDR_SEL0_DEU |
2015 DESC_HDR_MODE0_DEU_CBC |
2016 DESC_HDR_MODE0_DEU_3DES |
2017 DESC_HDR_SEL1_MDEUA |
2018 DESC_HDR_MODE1_MDEU_INIT |
2019 DESC_HDR_MODE1_MDEU_PAD |
2020 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 2021 },
357fb605
HG		 2022 { .type = CRYPTO_ALG_TYPE_AEAD,
2023 .alg.crypto = {
2024 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2025 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
2026 .cra_blocksize = AES_BLOCK_SIZE,
2027 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2028 .cra_aead = {
357fb605
HG		 2029 .ivsize = AES_BLOCK_SIZE,
2030 .maxauthsize = SHA224_DIGEST_SIZE,
2031 }
2032 },
2033 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2034 DESC_HDR_SEL0_AESU |
2035 DESC_HDR_MODE0_AESU_CBC |
2036 DESC_HDR_SEL1_MDEUA |
2037 DESC_HDR_MODE1_MDEU_INIT |
2038 DESC_HDR_MODE1_MDEU_PAD |
2039 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2040 },
2041 { .type = CRYPTO_ALG_TYPE_AEAD,
2042 .alg.crypto = {
2043 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
2044 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
2045 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2046 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2047 .cra_aead = {
357fb605
HG		 2048 .ivsize = DES3_EDE_BLOCK_SIZE,
2049 .maxauthsize = SHA224_DIGEST_SIZE,
2050 }
2051 },
2052 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2053 DESC_HDR_SEL0_DEU |
2054 DESC_HDR_MODE0_DEU_CBC |
2055 DESC_HDR_MODE0_DEU_3DES |
2056 DESC_HDR_SEL1_MDEUA |
2057 DESC_HDR_MODE1_MDEU_INIT |
2058 DESC_HDR_MODE1_MDEU_PAD |
2059 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2060 },
d5e4aaef
LN		 2061 { .type = CRYPTO_ALG_TYPE_AEAD,
2062 .alg.crypto = {
56af8cd4
LN		 2063 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2064 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
2065 .cra_blocksize = AES_BLOCK_SIZE,
2066 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2067 .cra_aead = {
56af8cd4
LN		 2068 .ivsize = AES_BLOCK_SIZE,
2069 .maxauthsize = SHA256_DIGEST_SIZE,
2070 }
2071 },
3952f17e
LN		 2072 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2073 DESC_HDR_SEL0_AESU |
2074 DESC_HDR_MODE0_AESU_CBC |
2075 DESC_HDR_SEL1_MDEUA |
2076 DESC_HDR_MODE1_MDEU_INIT |
2077 DESC_HDR_MODE1_MDEU_PAD |
2078 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2079 },
d5e4aaef
LN		 2080 { .type = CRYPTO_ALG_TYPE_AEAD,
2081 .alg.crypto = {
56af8cd4
LN		 2082 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2083 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2084 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2085 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2086 .cra_aead = {
56af8cd4
LN		 2087 .ivsize = DES3_EDE_BLOCK_SIZE,
2088 .maxauthsize = SHA256_DIGEST_SIZE,
2089 }
2090 },
3952f17e
LN		 2091 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2092 DESC_HDR_SEL0_DEU |
2093 DESC_HDR_MODE0_DEU_CBC |
2094 DESC_HDR_MODE0_DEU_3DES |
2095 DESC_HDR_SEL1_MDEUA |
2096 DESC_HDR_MODE1_MDEU_INIT |
2097 DESC_HDR_MODE1_MDEU_PAD |
2098 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2099 },
d5e4aaef 2100 { .type = CRYPTO_ALG_TYPE_AEAD,
357fb605
HG		 2101 .alg.crypto = {
2102 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2103 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2104 .cra_blocksize = AES_BLOCK_SIZE,
2105 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2106 .cra_aead = {
357fb605
HG		 2107 .ivsize = AES_BLOCK_SIZE,
2108 .maxauthsize = SHA384_DIGEST_SIZE,
2109 }
2110 },
2111 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2112 DESC_HDR_SEL0_AESU |
2113 DESC_HDR_MODE0_AESU_CBC |
2114 DESC_HDR_SEL1_MDEUB |
2115 DESC_HDR_MODE1_MDEU_INIT |
2116 DESC_HDR_MODE1_MDEU_PAD |
2117 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2118 },
2119 { .type = CRYPTO_ALG_TYPE_AEAD,
2120 .alg.crypto = {
2121 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2122 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2123 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2124 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2125 .cra_aead = {
357fb605
HG		 2126 .ivsize = DES3_EDE_BLOCK_SIZE,
2127 .maxauthsize = SHA384_DIGEST_SIZE,
2128 }
2129 },
2130 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2131 DESC_HDR_SEL0_DEU |
2132 DESC_HDR_MODE0_DEU_CBC |
2133 DESC_HDR_MODE0_DEU_3DES |
2134 DESC_HDR_SEL1_MDEUB |
2135 DESC_HDR_MODE1_MDEU_INIT |
2136 DESC_HDR_MODE1_MDEU_PAD |
2137 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2138 },
2139 { .type = CRYPTO_ALG_TYPE_AEAD,
2140 .alg.crypto = {
2141 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2142 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2143 .cra_blocksize = AES_BLOCK_SIZE,
2144 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2145 .cra_aead = {
357fb605
HG		 2146 .ivsize = AES_BLOCK_SIZE,
2147 .maxauthsize = SHA512_DIGEST_SIZE,
2148 }
2149 },
2150 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2151 DESC_HDR_SEL0_AESU |
2152 DESC_HDR_MODE0_AESU_CBC |
2153 DESC_HDR_SEL1_MDEUB |
2154 DESC_HDR_MODE1_MDEU_INIT |
2155 DESC_HDR_MODE1_MDEU_PAD |
2156 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2157 },
2158 { .type = CRYPTO_ALG_TYPE_AEAD,
2159 .alg.crypto = {
2160 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2161 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2162 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2163 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605 2164 .cra_aead = {
357fb605
HG		 2165 .ivsize = DES3_EDE_BLOCK_SIZE,
2166 .maxauthsize = SHA512_DIGEST_SIZE,
2167 }
2168 },
2169 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2170 DESC_HDR_SEL0_DEU |
2171 DESC_HDR_MODE0_DEU_CBC |
2172 DESC_HDR_MODE0_DEU_3DES |
2173 DESC_HDR_SEL1_MDEUB |
2174 DESC_HDR_MODE1_MDEU_INIT |
2175 DESC_HDR_MODE1_MDEU_PAD |
2176 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2177 },
2178 { .type = CRYPTO_ALG_TYPE_AEAD,
d5e4aaef 2179 .alg.crypto = {
56af8cd4
LN		 2180 .cra_name = "authenc(hmac(md5),cbc(aes))",
2181 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2182 .cra_blocksize = AES_BLOCK_SIZE,
2183 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2184 .cra_aead = {
56af8cd4
LN		 2185 .ivsize = AES_BLOCK_SIZE,
2186 .maxauthsize = MD5_DIGEST_SIZE,
2187 }
2188 },
3952f17e
LN		 2189 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2190 DESC_HDR_SEL0_AESU |
2191 DESC_HDR_MODE0_AESU_CBC |
2192 DESC_HDR_SEL1_MDEUA |
2193 DESC_HDR_MODE1_MDEU_INIT |
2194 DESC_HDR_MODE1_MDEU_PAD |
2195 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2196 },
d5e4aaef
LN		 2197 { .type = CRYPTO_ALG_TYPE_AEAD,
2198 .alg.crypto = {
56af8cd4
LN		 2199 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2200 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2201 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2202 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4 2203 .cra_aead = {
56af8cd4
LN		 2204 .ivsize = DES3_EDE_BLOCK_SIZE,
2205 .maxauthsize = MD5_DIGEST_SIZE,
2206 }
2207 },
3952f17e
LN		 2208 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2209 DESC_HDR_SEL0_DEU |
2210 DESC_HDR_MODE0_DEU_CBC |
2211 DESC_HDR_MODE0_DEU_3DES |
2212 DESC_HDR_SEL1_MDEUA |
2213 DESC_HDR_MODE1_MDEU_INIT |
2214 DESC_HDR_MODE1_MDEU_PAD |
2215 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2216 },
2217 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2218 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2219 .alg.crypto = {
4de9d0b5
LN		 2220 .cra_name = "cbc(aes)",
2221 .cra_driver_name = "cbc-aes-talitos",
2222 .cra_blocksize = AES_BLOCK_SIZE,
2223 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2224 CRYPTO_ALG_ASYNC,
4de9d0b5 2225 .cra_ablkcipher = {
4de9d0b5
LN		 2226 .min_keysize = AES_MIN_KEY_SIZE,
2227 .max_keysize = AES_MAX_KEY_SIZE,
2228 .ivsize = AES_BLOCK_SIZE,
2229 }
2230 },
2231 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2232 DESC_HDR_SEL0_AESU |
2233 DESC_HDR_MODE0_AESU_CBC,
2234 },
d5e4aaef
LN		 2235 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2236 .alg.crypto = {
4de9d0b5
LN		 2237 .cra_name = "cbc(des3_ede)",
2238 .cra_driver_name = "cbc-3des-talitos",
2239 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2240 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2241 CRYPTO_ALG_ASYNC,
4de9d0b5 2242 .cra_ablkcipher = {
4de9d0b5
LN		 2243 .min_keysize = DES3_EDE_KEY_SIZE,
2244 .max_keysize = DES3_EDE_KEY_SIZE,
2245 .ivsize = DES3_EDE_BLOCK_SIZE,
2246 }
2247 },
2248 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2249 DESC_HDR_SEL0_DEU |
2250 DESC_HDR_MODE0_DEU_CBC |
2251 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2252 },
2253 /* AHASH algorithms. */
2254 { .type = CRYPTO_ALG_TYPE_AHASH,
2255 .alg.hash = {
497f2e6b
LN		 2256 .halg.digestsize = MD5_DIGEST_SIZE,
2257 .halg.base = {
2258 .cra_name = "md5",
2259 .cra_driver_name = "md5-talitos",
2260 .cra_blocksize = MD5_BLOCK_SIZE,
2261 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2262 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2263 }
2264 },
2265 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2266 DESC_HDR_SEL0_MDEUA |
2267 DESC_HDR_MODE0_MDEU_MD5,
2268 },
2269 { .type = CRYPTO_ALG_TYPE_AHASH,
2270 .alg.hash = {
497f2e6b
LN		 2271 .halg.digestsize = SHA1_DIGEST_SIZE,
2272 .halg.base = {
2273 .cra_name = "sha1",
2274 .cra_driver_name = "sha1-talitos",
2275 .cra_blocksize = SHA1_BLOCK_SIZE,
2276 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2277 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2278 }
2279 },
2280 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2281 DESC_HDR_SEL0_MDEUA |
2282 DESC_HDR_MODE0_MDEU_SHA1,
2283 },
60f208d7
KP		 2284 { .type = CRYPTO_ALG_TYPE_AHASH,
2285 .alg.hash = {
60f208d7
KP		 2286 .halg.digestsize = SHA224_DIGEST_SIZE,
2287 .halg.base = {
2288 .cra_name = "sha224",
2289 .cra_driver_name = "sha224-talitos",
2290 .cra_blocksize = SHA224_BLOCK_SIZE,
2291 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2292 CRYPTO_ALG_ASYNC,
60f208d7
KP		 2293 }
2294 },
2295 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2296 DESC_HDR_SEL0_MDEUA |
2297 DESC_HDR_MODE0_MDEU_SHA224,
2298 },
497f2e6b
LN		 2299 { .type = CRYPTO_ALG_TYPE_AHASH,
2300 .alg.hash = {
497f2e6b
LN		 2301 .halg.digestsize = SHA256_DIGEST_SIZE,
2302 .halg.base = {
2303 .cra_name = "sha256",
2304 .cra_driver_name = "sha256-talitos",
2305 .cra_blocksize = SHA256_BLOCK_SIZE,
2306 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2307 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2308 }
2309 },
2310 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2311 DESC_HDR_SEL0_MDEUA |
2312 DESC_HDR_MODE0_MDEU_SHA256,
2313 },
2314 { .type = CRYPTO_ALG_TYPE_AHASH,
2315 .alg.hash = {
497f2e6b
LN		 2316 .halg.digestsize = SHA384_DIGEST_SIZE,
2317 .halg.base = {
2318 .cra_name = "sha384",
2319 .cra_driver_name = "sha384-talitos",
2320 .cra_blocksize = SHA384_BLOCK_SIZE,
2321 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2322 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2323 }
2324 },
2325 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2326 DESC_HDR_SEL0_MDEUB |
2327 DESC_HDR_MODE0_MDEUB_SHA384,
2328 },
2329 { .type = CRYPTO_ALG_TYPE_AHASH,
2330 .alg.hash = {
497f2e6b
LN		 2331 .halg.digestsize = SHA512_DIGEST_SIZE,
2332 .halg.base = {
2333 .cra_name = "sha512",
2334 .cra_driver_name = "sha512-talitos",
2335 .cra_blocksize = SHA512_BLOCK_SIZE,
2336 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2337 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2338 }
2339 },
2340 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2341 DESC_HDR_SEL0_MDEUB |
2342 DESC_HDR_MODE0_MDEUB_SHA512,
2343 },
79b3a418
LN		 2344 { .type = CRYPTO_ALG_TYPE_AHASH,
2345 .alg.hash = {
79b3a418
LN		 2346 .halg.digestsize = MD5_DIGEST_SIZE,
2347 .halg.base = {
2348 .cra_name = "hmac(md5)",
2349 .cra_driver_name = "hmac-md5-talitos",
2350 .cra_blocksize = MD5_BLOCK_SIZE,
2351 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2352 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2353 }
2354 },
2355 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2356 DESC_HDR_SEL0_MDEUA |
2357 DESC_HDR_MODE0_MDEU_MD5,
2358 },
2359 { .type = CRYPTO_ALG_TYPE_AHASH,
2360 .alg.hash = {
79b3a418
LN		 2361 .halg.digestsize = SHA1_DIGEST_SIZE,
2362 .halg.base = {
2363 .cra_name = "hmac(sha1)",
2364 .cra_driver_name = "hmac-sha1-talitos",
2365 .cra_blocksize = SHA1_BLOCK_SIZE,
2366 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2367 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2368 }
2369 },
2370 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2371 DESC_HDR_SEL0_MDEUA |
2372 DESC_HDR_MODE0_MDEU_SHA1,
2373 },
2374 { .type = CRYPTO_ALG_TYPE_AHASH,
2375 .alg.hash = {
79b3a418
LN		 2376 .halg.digestsize = SHA224_DIGEST_SIZE,
2377 .halg.base = {
2378 .cra_name = "hmac(sha224)",
2379 .cra_driver_name = "hmac-sha224-talitos",
2380 .cra_blocksize = SHA224_BLOCK_SIZE,
2381 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2382 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2383 }
2384 },
2385 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2386 DESC_HDR_SEL0_MDEUA |
2387 DESC_HDR_MODE0_MDEU_SHA224,
2388 },
2389 { .type = CRYPTO_ALG_TYPE_AHASH,
2390 .alg.hash = {
79b3a418
LN		 2391 .halg.digestsize = SHA256_DIGEST_SIZE,
2392 .halg.base = {
2393 .cra_name = "hmac(sha256)",
2394 .cra_driver_name = "hmac-sha256-talitos",
2395 .cra_blocksize = SHA256_BLOCK_SIZE,
2396 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2397 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2398 }
2399 },
2400 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2401 DESC_HDR_SEL0_MDEUA |
2402 DESC_HDR_MODE0_MDEU_SHA256,
2403 },
2404 { .type = CRYPTO_ALG_TYPE_AHASH,
2405 .alg.hash = {
79b3a418
LN		 2406 .halg.digestsize = SHA384_DIGEST_SIZE,
2407 .halg.base = {
2408 .cra_name = "hmac(sha384)",
2409 .cra_driver_name = "hmac-sha384-talitos",
2410 .cra_blocksize = SHA384_BLOCK_SIZE,
2411 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2412 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2413 }
2414 },
2415 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2416 DESC_HDR_SEL0_MDEUB |
2417 DESC_HDR_MODE0_MDEUB_SHA384,
2418 },
2419 { .type = CRYPTO_ALG_TYPE_AHASH,
2420 .alg.hash = {
79b3a418
LN		 2421 .halg.digestsize = SHA512_DIGEST_SIZE,
2422 .halg.base = {
2423 .cra_name = "hmac(sha512)",
2424 .cra_driver_name = "hmac-sha512-talitos",
2425 .cra_blocksize = SHA512_BLOCK_SIZE,
2426 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2427 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2428 }
2429 },
2430 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2431 DESC_HDR_SEL0_MDEUB |
2432 DESC_HDR_MODE0_MDEUB_SHA512,
2433 }
9c4a7965
KP		 2434};
2435
2436struct talitos_crypto_alg {
2437 struct list_head entry;
2438 struct device *dev;
acbf7c62 2439 struct talitos_alg_template algt;
9c4a7965
KP		 2440};
2441
2442static int talitos_cra_init(struct crypto_tfm *tfm)
2443{
2444 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2445 struct talitos_crypto_alg *talitos_alg;
9c4a7965 2446 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
5228f0f7 2447 struct talitos_private *priv;
9c4a7965 2448
497f2e6b
LN		 2449 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2450 talitos_alg = container_of(__crypto_ahash_alg(alg),
2451 struct talitos_crypto_alg,
2452 algt.alg.hash);
2453 else
2454 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2455 algt.alg.crypto);
19bbbc63 2456
9c4a7965
KP		 2457 /* update context with ptr to dev */
2458 ctx->dev = talitos_alg->dev;
19bbbc63 2459
5228f0f7
KP		 2460 /* assign SEC channel to tfm in round-robin fashion */
2461 priv = dev_get_drvdata(ctx->dev);
2462 ctx->ch = atomic_inc_return(&priv->last_chan) &
2463 (priv->num_channels - 1);
2464
9c4a7965 2465 /* copy descriptor header template value */
acbf7c62 2466 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2467
602dba5a
KP		 2468 /* select done notification */
2469 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2470
497f2e6b
LN		 2471 return 0;
2472}
2473
2474static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2475{
2476 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2477
2478 talitos_cra_init(tfm);
9c4a7965
KP		 2479
2480 /* random first IV */
70bcaca7 2481 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2482
2483 return 0;
2484}
2485
497f2e6b
LN		 2486static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2487{
2488 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2489
2490 talitos_cra_init(tfm);
2491
2492 ctx->keylen = 0;
2493 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2494 sizeof(struct talitos_ahash_req_ctx));
2495
2496 return 0;
2497}
2498
9c4a7965
KP		 2499/*
2500 * given the alg's descriptor header template, determine whether descriptor
2501 * type and primary/secondary execution units required match the hw
2502 * capabilities description provided in the device tree node.
2503 */
2504static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2505{
2506 struct talitos_private *priv = dev_get_drvdata(dev);
2507 int ret;
2508
2509 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2510 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2511
2512 if (SECONDARY_EU(desc_hdr_template))
2513 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2514 & priv->exec_units);
2515
2516 return ret;
2517}
2518
2dc11581 2519static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 2520{
2521 struct device *dev = &ofdev->dev;
2522 struct talitos_private *priv = dev_get_drvdata(dev);
2523 struct talitos_crypto_alg *t_alg, *n;
2524 int i;
2525
2526 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2527 switch (t_alg->algt.type) {
2528 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2529 case CRYPTO_ALG_TYPE_AEAD:
2530 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2531 break;
2532 case CRYPTO_ALG_TYPE_AHASH:
2533 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2534 break;
2535 }
9c4a7965
KP		 2536 list_del(&t_alg->entry);
2537 kfree(t_alg);
2538 }
2539
2540 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2541 talitos_unregister_rng(dev);
2542
4b992628 2543 for (i = 0; i < priv->num_channels; i++)
0b798247 2544 kfree(priv->chan[i].fifo);
9c4a7965 2545
4b992628 2546 kfree(priv->chan);
9c4a7965 2547
c3e337f8 2548 for (i = 0; i < 2; i++)
2cdba3cf 2549 if (priv->irq[i]) {
c3e337f8
KP		 2550 free_irq(priv->irq[i], dev);
2551 irq_dispose_mapping(priv->irq[i]);
2552 }
9c4a7965 2553
c3e337f8 2554 tasklet_kill(&priv->done_task[0]);
2cdba3cf 2555 if (priv->irq[1])
c3e337f8 2556 tasklet_kill(&priv->done_task[1]);
9c4a7965
KP		 2557
2558 iounmap(priv->reg);
2559
2560 dev_set_drvdata(dev, NULL);
2561
2562 kfree(priv);
2563
2564 return 0;
2565}
2566
2567static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2568 struct talitos_alg_template
2569 *template)
2570{
60f208d7 2571 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 2572 struct talitos_crypto_alg *t_alg;
2573 struct crypto_alg *alg;
2574
2575 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2576 if (!t_alg)
2577 return ERR_PTR(-ENOMEM);
2578
acbf7c62
LN		 2579 t_alg->algt = *template;
2580
2581 switch (t_alg->algt.type) {
2582 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2583 alg = &t_alg->algt.alg.crypto;
2584 alg->cra_init = talitos_cra_init;
d4cd3283 2585 alg->cra_type = &crypto_ablkcipher_type;
b286e003
KP		 2586 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2587 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2588 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2589 alg->cra_ablkcipher.geniv = "eseqiv";
497f2e6b 2590 break;
acbf7c62
LN		 2591 case CRYPTO_ALG_TYPE_AEAD:
2592 alg = &t_alg->algt.alg.crypto;
497f2e6b 2593 alg->cra_init = talitos_cra_init_aead;
d4cd3283 2594 alg->cra_type = &crypto_aead_type;
b286e003
KP		 2595 alg->cra_aead.setkey = aead_setkey;
2596 alg->cra_aead.setauthsize = aead_setauthsize;
2597 alg->cra_aead.encrypt = aead_encrypt;
2598 alg->cra_aead.decrypt = aead_decrypt;
2599 alg->cra_aead.givencrypt = aead_givencrypt;
2600 alg->cra_aead.geniv = "<built-in>";
acbf7c62
LN		 2601 break;
2602 case CRYPTO_ALG_TYPE_AHASH:
2603 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 2604 alg->cra_init = talitos_cra_init_ahash;
d4cd3283 2605 alg->cra_type = &crypto_ahash_type;
b286e003
KP		 2606 t_alg->algt.alg.hash.init = ahash_init;
2607 t_alg->algt.alg.hash.update = ahash_update;
2608 t_alg->algt.alg.hash.final = ahash_final;
2609 t_alg->algt.alg.hash.finup = ahash_finup;
2610 t_alg->algt.alg.hash.digest = ahash_digest;
2611 t_alg->algt.alg.hash.setkey = ahash_setkey;
2612
79b3a418 2613 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
0b2730d8
KP		 2614 !strncmp(alg->cra_name, "hmac", 4)) {
2615 kfree(t_alg);
79b3a418 2616 return ERR_PTR(-ENOTSUPP);
0b2730d8 2617 }
60f208d7 2618 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
79b3a418
LN		 2619 (!strcmp(alg->cra_name, "sha224") ||
2620 !strcmp(alg->cra_name, "hmac(sha224)"))) {
60f208d7
KP		 2621 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2622 t_alg->algt.desc_hdr_template =
2623 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2624 DESC_HDR_SEL0_MDEUA |
2625 DESC_HDR_MODE0_MDEU_SHA256;
2626 }
497f2e6b 2627 break;
1d11911a
KP		 2628 default:
2629 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
54b91579 2630 kfree(t_alg);
1d11911a 2631 return ERR_PTR(-EINVAL);
acbf7c62 2632 }
9c4a7965 2633
9c4a7965 2634 alg->cra_module = THIS_MODULE;
9c4a7965 2635 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2636 alg->cra_alignmask = 0;
9c4a7965 2637 alg->cra_ctxsize = sizeof(struct talitos_ctx);
d912bb76 2638 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
9c4a7965 2639
9c4a7965
KP		 2640 t_alg->dev = dev;
2641
2642 return t_alg;
2643}
2644
c3e337f8
KP		 2645static int talitos_probe_irq(struct platform_device *ofdev)
2646{
2647 struct device *dev = &ofdev->dev;
2648 struct device_node *np = ofdev->dev.of_node;
2649 struct talitos_private *priv = dev_get_drvdata(dev);
2650 int err;
2651
2652 priv->irq[0] = irq_of_parse_and_map(np, 0);
2cdba3cf 2653 if (!priv->irq[0]) {
c3e337f8
KP		 2654 dev_err(dev, "failed to map irq\n");
2655 return -EINVAL;
2656 }
2657
2658 priv->irq[1] = irq_of_parse_and_map(np, 1);
2659
2660 /* get the primary irq line */
2cdba3cf 2661 if (!priv->irq[1]) {
c3e337f8
KP		 2662 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2663 dev_driver_string(dev), dev);
2664 goto primary_out;
2665 }
2666
2667 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2668 dev_driver_string(dev), dev);
2669 if (err)
2670 goto primary_out;
2671
2672 /* get the secondary irq line */
2673 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2674 dev_driver_string(dev), dev);
2675 if (err) {
2676 dev_err(dev, "failed to request secondary irq\n");
2677 irq_dispose_mapping(priv->irq[1]);
2cdba3cf 2678 priv->irq[1] = 0;
c3e337f8
KP		 2679 }
2680
2681 return err;
2682
2683primary_out:
2684 if (err) {
2685 dev_err(dev, "failed to request primary irq\n");
2686 irq_dispose_mapping(priv->irq[0]);
2cdba3cf 2687 priv->irq[0] = 0;
c3e337f8
KP		 2688 }
2689
2690 return err;
2691}
2692
1c48a5c9 2693static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 2694{
2695 struct device *dev = &ofdev->dev;
61c7a080 2696 struct device_node *np = ofdev->dev.of_node;
9c4a7965
KP		 2697 struct talitos_private *priv;
2698 const unsigned int *prop;
2699 int i, err;
2700
2701 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2702 if (!priv)
2703 return -ENOMEM;
2704
2705 dev_set_drvdata(dev, priv);
2706
2707 priv->ofdev = ofdev;
2708
511d63cb
HG		 2709 spin_lock_init(&priv->reg_lock);
2710
c3e337f8
KP		 2711 err = talitos_probe_irq(ofdev);
2712 if (err)
9c4a7965 2713 goto err_out;
9c4a7965 2714
2cdba3cf 2715 if (!priv->irq[1]) {
c3e337f8
KP		 2716 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2717 (unsigned long)dev);
2718 } else {
2719 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2720 (unsigned long)dev);
2721 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2722 (unsigned long)dev);
9c4a7965
KP		 2723 }
2724
c3e337f8
KP		 2725 INIT_LIST_HEAD(&priv->alg_list);
2726
9c4a7965
KP		 2727 priv->reg = of_iomap(np, 0);
2728 if (!priv->reg) {
2729 dev_err(dev, "failed to of_iomap\n");
2730 err = -ENOMEM;
2731 goto err_out;
2732 }
2733
2734 /* get SEC version capabilities from device tree */
2735 prop = of_get_property(np, "fsl,num-channels", NULL);
2736 if (prop)
2737 priv->num_channels = *prop;
2738
2739 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2740 if (prop)
2741 priv->chfifo_len = *prop;
2742
2743 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2744 if (prop)
2745 priv->exec_units = *prop;
2746
2747 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2748 if (prop)
2749 priv->desc_types = *prop;
2750
2751 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2752 !priv->exec_units || !priv->desc_types) {
2753 dev_err(dev, "invalid property data in device tree node\n");
2754 err = -EINVAL;
2755 goto err_out;
2756 }
2757
f3c85bc1
LN		 2758 if (of_device_is_compatible(np, "fsl,sec3.0"))
2759 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2760
fe5720e2 2761 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7 2762 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
79b3a418
LN		 2763 TALITOS_FTR_SHA224_HWINIT |
2764 TALITOS_FTR_HMAC_OK;
fe5720e2 2765
4b992628
KP		 2766 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2767 priv->num_channels, GFP_KERNEL);
2768 if (!priv->chan) {
2769 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2770 err = -ENOMEM;
2771 goto err_out;
2772 }
2773
c3e337f8
KP		 2774 for (i = 0; i < priv->num_channels; i++) {
2775 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2cdba3cf 2776 if (!priv->irq[1] || !(i & 1))
c3e337f8
KP		 2777 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2778 }
ad42d5fc 2779
9c4a7965 2780 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2781 spin_lock_init(&priv->chan[i].head_lock);
2782 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2783 }
2784
2785 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2786
2787 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2788 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2789 priv->fifo_len, GFP_KERNEL);
2790 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2791 dev_err(dev, "failed to allocate request fifo %d\n", i);
2792 err = -ENOMEM;
2793 goto err_out;
2794 }
2795 }
2796
ec6644d6 2797 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2798 atomic_set(&priv->chan[i].submit_count,
2799 -(priv->chfifo_len - 1));
9c4a7965 2800
81eb024c
KP		 2801 dma_set_mask(dev, DMA_BIT_MASK(36));
2802
9c4a7965
KP		 2803 /* reset and initialize the h/w */
2804 err = init_device(dev);
2805 if (err) {
2806 dev_err(dev, "failed to initialize device\n");
2807 goto err_out;
2808 }
2809
2810 /* register the RNG, if available */
2811 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2812 err = talitos_register_rng(dev);
2813 if (err) {
2814 dev_err(dev, "failed to register hwrng: %d\n", err);
2815 goto err_out;
2816 } else
2817 dev_info(dev, "hwrng\n");
2818 }
2819
2820 /* register crypto algorithms the device supports */
9c4a7965
KP		 2821 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2822 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2823 struct talitos_crypto_alg *t_alg;
acbf7c62 2824 char *name = NULL;
9c4a7965
KP		 2825
2826 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2827 if (IS_ERR(t_alg)) {
2828 err = PTR_ERR(t_alg);
0b2730d8 2829 if (err == -ENOTSUPP)
79b3a418 2830 continue;
9c4a7965
KP		 2831 goto err_out;
2832 }
2833
acbf7c62
LN		 2834 switch (t_alg->algt.type) {
2835 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2836 case CRYPTO_ALG_TYPE_AEAD:
2837 err = crypto_register_alg(
2838 &t_alg->algt.alg.crypto);
2839 name = t_alg->algt.alg.crypto.cra_driver_name;
2840 break;
2841 case CRYPTO_ALG_TYPE_AHASH:
2842 err = crypto_register_ahash(
2843 &t_alg->algt.alg.hash);
2844 name =
2845 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2846 break;
2847 }
9c4a7965
KP		 2848 if (err) {
2849 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2850 name);
9c4a7965 2851 kfree(t_alg);
991155ba 2852 } else
9c4a7965 2853 list_add_tail(&t_alg->entry, &priv->alg_list);
9c4a7965
KP		 2854 }
2855 }
5b859b6e
KP		 2856 if (!list_empty(&priv->alg_list))
2857 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2858 (char *)of_get_property(np, "compatible", NULL));
9c4a7965
KP		 2859
2860 return 0;
2861
2862err_out:
2863 talitos_remove(ofdev);
9c4a7965
KP		 2864
2865 return err;
2866}
2867
6c3f975a 2868static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2869 {
2870 .compatible = "fsl,sec2.0",
2871 },
2872 {},
2873};
2874MODULE_DEVICE_TABLE(of, talitos_match);
2875
1c48a5c9 2876static struct platform_driver talitos_driver = {
4018294b
GL		 2877 .driver = {
2878 .name = "talitos",
2879 .owner = THIS_MODULE,
2880 .of_match_table = talitos_match,
2881 },
9c4a7965 2882 .probe = talitos_probe,
596f1034 2883 .remove = talitos_remove,
9c4a7965
KP		 2884};
2885
741e8c2d 2886module_platform_driver(talitos_driver);
9c4a7965
KP		 2887
2888MODULE_LICENSE("GPL");
2889MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2890MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
kernel source for telekom puls (alcatel/mediatek)