[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / cpufreq / s3c2416-cpufreq.c

/*
 * S3C2416/2450 CPUfreq Support
 *
 * Copyright 2011 Heiko Stuebner <heiko@sntech.de>
 *
 * based on s3c64xx_cpufreq.c
 *
 * Copyright 2009 Wolfson Microelectronics plc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/reboot.h>
#include <linux/module.h>

static DEFINE_MUTEX(cpufreq_lock);

struct s3c2416_data {
	struct clk *armdiv;
	struct clk *armclk;
	struct clk *hclk;

	unsigned long regulator_latency;
#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	struct regulator *vddarm;
#endif

	struct cpufreq_frequency_table *freq_table;

	bool is_dvs;
	bool disable_dvs;
};

static struct s3c2416_data s3c2416_cpufreq;

struct s3c2416_dvfs {
	unsigned int vddarm_min;
	unsigned int vddarm_max;
};

/* pseudo-frequency for dvs mode */
#define FREQ_DVS	132333

/* frequency to sleep and reboot in
 * it's essential to leave dvs, as some boards do not reconfigure the
 * regulator on reboot
 */
#define FREQ_SLEEP	133333

/* Sources for the ARMCLK */
#define SOURCE_HCLK	0
#define SOURCE_ARMDIV	1

#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
/* S3C2416 only supports changing the voltage in the dvs-mode.
 * Voltages down to 1.0V seem to work, so we take what the regulator
 * can get us.
 */
static struct s3c2416_dvfs s3c2416_dvfs_table[] = {
	[SOURCE_HCLK] = {  950000, 1250000 },
	[SOURCE_ARMDIV] = { 1250000, 1350000 },
};
#endif

static struct cpufreq_frequency_table s3c2416_freq_table[] = {
	{ SOURCE_HCLK, FREQ_DVS },
	{ SOURCE_ARMDIV, 133333 },
	{ SOURCE_ARMDIV, 266666 },
	{ SOURCE_ARMDIV, 400000 },
	{ 0, CPUFREQ_TABLE_END },
};

static struct cpufreq_frequency_table s3c2450_freq_table[] = {
	{ SOURCE_HCLK, FREQ_DVS },
	{ SOURCE_ARMDIV, 133500 },
	{ SOURCE_ARMDIV, 267000 },
	{ SOURCE_ARMDIV, 534000 },
	{ 0, CPUFREQ_TABLE_END },
};

static int s3c2416_cpufreq_verify_speed(struct cpufreq_policy *policy)
{
	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;

	if (policy->cpu != 0)
		return -EINVAL;

	return cpufreq_frequency_table_verify(policy, s3c_freq->freq_table);
}

static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu)
{
	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;

	if (cpu != 0)
		return 0;

	/* return our pseudo-frequency when in dvs mode */
	if (s3c_freq->is_dvs)
		return FREQ_DVS;

	return clk_get_rate(s3c_freq->armclk) / 1000;
}

static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq,
				      unsigned int freq)
{
	int ret;

	if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) {
		ret = clk_set_rate(s3c_freq->armdiv, freq * 1000);
		if (ret < 0) {
			pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n",
			       freq, ret);
			return ret;
		}
	}

	return 0;
}

static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx)
{
#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	struct s3c2416_dvfs *dvfs;
#endif
	int ret;

	if (s3c_freq->is_dvs) {
		pr_debug("cpufreq: already in dvs mode, nothing to do\n");
		return 0;
	}

	pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n",
		 clk_get_rate(s3c_freq->hclk) / 1000);
	ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk);
	if (ret < 0) {
		pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret);
		return ret;
	}

#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	/* changing the core voltage is only allowed when in dvs mode */
	if (s3c_freq->vddarm) {
		dvfs = &s3c2416_dvfs_table[idx];

		pr_debug("cpufreq: setting regulator to %d-%d\n",
			 dvfs->vddarm_min, dvfs->vddarm_max);
		ret = regulator_set_voltage(s3c_freq->vddarm,
					    dvfs->vddarm_min,
					    dvfs->vddarm_max);

		/* when lowering the voltage failed, there is nothing to do */
		if (ret != 0)
			pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
	}
#endif

	s3c_freq->is_dvs = 1;

	return 0;
}

static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx)
{
#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	struct s3c2416_dvfs *dvfs;
#endif
	int ret;

	if (!s3c_freq->is_dvs) {
		pr_debug("cpufreq: not in dvs mode, so can't leave\n");
		return 0;
	}

#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	if (s3c_freq->vddarm) {
		dvfs = &s3c2416_dvfs_table[idx];

		pr_debug("cpufreq: setting regulator to %d-%d\n",
			 dvfs->vddarm_min, dvfs->vddarm_max);
		ret = regulator_set_voltage(s3c_freq->vddarm,
					    dvfs->vddarm_min,
					    dvfs->vddarm_max);
		if (ret != 0) {
			pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
			return ret;
		}
	}
#endif

	/* force armdiv to hclk frequency for transition from dvs*/
	if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) {
		pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n",
			 clk_get_rate(s3c_freq->hclk) / 1000);
		ret = s3c2416_cpufreq_set_armdiv(s3c_freq,
					clk_get_rate(s3c_freq->hclk) / 1000);
		if (ret < 0) {
			pr_err("cpufreq: Failed to to set the armdiv to %lukHz: %d\n",
			       clk_get_rate(s3c_freq->hclk) / 1000, ret);
			return ret;
		}
	}

	pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n",
			clk_get_rate(s3c_freq->armdiv) / 1000);

	ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv);
	if (ret < 0) {
		pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n",
		       ret);
		return ret;
	}

	s3c_freq->is_dvs = 0;

	return 0;
}

static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy,
				      unsigned int target_freq,
				      unsigned int relation)
{
	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
	struct cpufreq_freqs freqs;
	int idx, ret, to_dvs = 0;
	unsigned int i;

	mutex_lock(&cpufreq_lock);

	pr_debug("cpufreq: to %dKHz, relation %d\n", target_freq, relation);

	ret = cpufreq_frequency_table_target(policy, s3c_freq->freq_table,
					     target_freq, relation, &i);
	if (ret != 0)
		goto out;

	idx = s3c_freq->freq_table[i].index;

	if (idx == SOURCE_HCLK)
		to_dvs = 1;

	/* switching to dvs when it's not allowed */
	if (to_dvs && s3c_freq->disable_dvs) {
		pr_debug("cpufreq: entering dvs mode not allowed\n");
		ret = -EINVAL;
		goto out;
	}

	freqs.flags = 0;
	freqs.old = s3c_freq->is_dvs ? FREQ_DVS
				     : clk_get_rate(s3c_freq->armclk) / 1000;

	/* When leavin dvs mode, always switch the armdiv to the hclk rate
	 * The S3C2416 has stability issues when switching directly to
	 * higher frequencies.
	 */
	freqs.new = (s3c_freq->is_dvs && !to_dvs)
				? clk_get_rate(s3c_freq->hclk) / 1000
				: s3c_freq->freq_table[i].frequency;

	pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);

	if (!to_dvs && freqs.old == freqs.new)
		goto out;

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	if (to_dvs) {
		pr_debug("cpufreq: enter dvs\n");
		ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx);
	} else if (s3c_freq->is_dvs) {
		pr_debug("cpufreq: leave dvs\n");
		ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx);
	} else {
		pr_debug("cpufreq: change armdiv to %dkHz\n", freqs.new);
		ret = s3c2416_cpufreq_set_armdiv(s3c_freq, freqs.new);
	}

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

out:
	mutex_unlock(&cpufreq_lock);

	return ret;
}

#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
static void __init s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq)
{
	int count, v, i, found;
	struct cpufreq_frequency_table *freq;
	struct s3c2416_dvfs *dvfs;

	count = regulator_count_voltages(s3c_freq->vddarm);
	if (count < 0) {
		pr_err("cpufreq: Unable to check supported voltages\n");
		return;
	}

	freq = s3c_freq->freq_table;
	while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
		if (freq->frequency == CPUFREQ_ENTRY_INVALID)
			continue;

		dvfs = &s3c2416_dvfs_table[freq->index];
		found = 0;

		/* Check only the min-voltage, more is always ok on S3C2416 */
		for (i = 0; i < count; i++) {
			v = regulator_list_voltage(s3c_freq->vddarm, i);
			if (v >= dvfs->vddarm_min)
				found = 1;
		}

		if (!found) {
			pr_debug("cpufreq: %dkHz unsupported by regulator\n",
				 freq->frequency);
			freq->frequency = CPUFREQ_ENTRY_INVALID;
		}

		freq++;
	}

	/* Guessed */
	s3c_freq->regulator_latency = 1 * 1000 * 1000;
}
#endif

static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block *this,
					       unsigned long event, void *ptr)
{
	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
	int ret;

	mutex_lock(&cpufreq_lock);

	/* disable further changes */
	s3c_freq->disable_dvs = 1;

	mutex_unlock(&cpufreq_lock);

	/* some boards don't reconfigure the regulator on reboot, which
	 * could lead to undervolting the cpu when the clock is reset.
	 * Therefore we always leave the DVS mode on reboot.
	 */
	if (s3c_freq->is_dvs) {
		pr_debug("cpufreq: leave dvs on reboot\n");
		ret = cpufreq_driver_target(cpufreq_cpu_get(0), FREQ_SLEEP, 0);
		if (ret < 0)
			return NOTIFY_BAD;
	}

	return NOTIFY_DONE;
}

static struct notifier_block s3c2416_cpufreq_reboot_notifier = {
	.notifier_call = s3c2416_cpufreq_reboot_notifier_evt,
};

static int __init s3c2416_cpufreq_driver_init(struct cpufreq_policy *policy)
{
	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
	struct cpufreq_frequency_table *freq;
	struct clk *msysclk;
	unsigned long rate;
	int ret;

	if (policy->cpu != 0)
		return -EINVAL;

	msysclk = clk_get(NULL, "msysclk");
	if (IS_ERR(msysclk)) {
		ret = PTR_ERR(msysclk);
		pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret);
		return ret;
	}

	/*
	 * S3C2416 and S3C2450 share the same processor-ID and also provide no
	 * other means to distinguish them other than through the rate of
	 * msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz.
	 */
	rate = clk_get_rate(msysclk);
	if (rate == 800 * 1000 * 1000) {
		pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n",
			rate / 1000);
		s3c_freq->freq_table = s3c2416_freq_table;
		policy->cpuinfo.max_freq = 400000;
	} else if (rate / 1000 == 534000) {
		pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n",
			rate / 1000);
		s3c_freq->freq_table = s3c2450_freq_table;
		policy->cpuinfo.max_freq = 534000;
	}

	/* not needed anymore */
	clk_put(msysclk);

	if (s3c_freq->freq_table == NULL) {
		pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n",
		       rate / 1000);
		return -ENODEV;
	}

	s3c_freq->is_dvs = 0;

	s3c_freq->armdiv = clk_get(NULL, "armdiv");
	if (IS_ERR(s3c_freq->armdiv)) {
		ret = PTR_ERR(s3c_freq->armdiv);
		pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret);
		return ret;
	}

	s3c_freq->hclk = clk_get(NULL, "hclk");
	if (IS_ERR(s3c_freq->hclk)) {
		ret = PTR_ERR(s3c_freq->hclk);
		pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret);
		goto err_hclk;
	}

	/* chech hclk rate, we only support the common 133MHz for now
	 * hclk could also run at 66MHz, but this not often used
	 */
	rate = clk_get_rate(s3c_freq->hclk);
	if (rate < 133 * 1000 * 1000) {
		pr_err("cpufreq: HCLK not at 133MHz\n");
		ret = -EINVAL;
		goto err_armclk;
	}

	s3c_freq->armclk = clk_get(NULL, "armclk");
	if (IS_ERR(s3c_freq->armclk)) {
		ret = PTR_ERR(s3c_freq->armclk);
		pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret);
		goto err_armclk;
	}

#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	s3c_freq->vddarm = regulator_get(NULL, "vddarm");
	if (IS_ERR(s3c_freq->vddarm)) {
		ret = PTR_ERR(s3c_freq->vddarm);
		pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
		goto err_vddarm;
	}

	s3c2416_cpufreq_cfg_regulator(s3c_freq);
#else
	s3c_freq->regulator_latency = 0;
#endif

	freq = s3c_freq->freq_table;
	while (freq->frequency != CPUFREQ_TABLE_END) {
		/* special handling for dvs mode */
		if (freq->index == 0) {
			if (!s3c_freq->hclk) {
				pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n",
					 freq->frequency);
				freq->frequency = CPUFREQ_ENTRY_INVALID;
			} else {
				freq++;
				continue;
			}
		}

		/* Check for frequencies we can generate */
		rate = clk_round_rate(s3c_freq->armdiv,
				      freq->frequency * 1000);
		rate /= 1000;
		if (rate != freq->frequency) {
			pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n",
				 freq->frequency, rate);
			freq->frequency = CPUFREQ_ENTRY_INVALID;
		}

		freq++;
	}

	policy->cur = clk_get_rate(s3c_freq->armclk) / 1000;

	/* Datasheet says PLL stabalisation time must be at least 300us,
	 * so but add some fudge. (reference in LOCKCON0 register description)
	 */
	policy->cpuinfo.transition_latency = (500 * 1000) +
					     s3c_freq->regulator_latency;

	ret = cpufreq_frequency_table_cpuinfo(policy, s3c_freq->freq_table);
	if (ret)
		goto err_freq_table;

	cpufreq_frequency_table_get_attr(s3c_freq->freq_table, 0);

	register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier);

	return 0;

err_freq_table:
#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	regulator_put(s3c_freq->vddarm);
err_vddarm:
#endif
	clk_put(s3c_freq->armclk);
err_armclk:
	clk_put(s3c_freq->hclk);
err_hclk:
	clk_put(s3c_freq->armdiv);

	return ret;
}

static struct freq_attr *s3c2416_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver s3c2416_cpufreq_driver = {
	.owner		= THIS_MODULE,
	.flags          = 0,
	.verify		= s3c2416_cpufreq_verify_speed,
	.target		= s3c2416_cpufreq_set_target,
	.get		= s3c2416_cpufreq_get_speed,
	.init		= s3c2416_cpufreq_driver_init,
	.name		= "s3c2416",
	.attr		= s3c2416_cpufreq_attr,
};

static int __init s3c2416_cpufreq_init(void)
{
	return cpufreq_register_driver(&s3c2416_cpufreq_driver);
}
module_init(s3c2416_cpufreq_init);
Commit	Line	Data
34ee5507 HS	1	/*
	2	* S3C2416/2450 CPUfreq Support
	3	*
	4	* Copyright 2011 Heiko Stuebner <heiko@sntech.de>
	5	*
	6	* based on s3c64xx_cpufreq.c
	7	*
	8	* Copyright 2009 Wolfson Microelectronics plc
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/types.h>
	17	#include <linux/init.h>
	18	#include <linux/cpufreq.h>
	19	#include <linux/clk.h>
	20	#include <linux/err.h>
	21	#include <linux/regulator/consumer.h>
	22	#include <linux/reboot.h>
	23	#include <linux/module.h>
	24
	25	static DEFINE_MUTEX(cpufreq_lock);
	26
	27	struct s3c2416_data {
	28	struct clk *armdiv;
	29	struct clk *armclk;
	30	struct clk *hclk;
	31
	32	unsigned long regulator_latency;
	33	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	34	struct regulator *vddarm;
	35	#endif
	36
	37	struct cpufreq_frequency_table *freq_table;
	38
	39	bool is_dvs;
	40	bool disable_dvs;
	41	};
	42
	43	static struct s3c2416_data s3c2416_cpufreq;
	44
	45	struct s3c2416_dvfs {
	46	unsigned int vddarm_min;
	47	unsigned int vddarm_max;
	48	};
	49
	50	/* pseudo-frequency for dvs mode */
	51	#define FREQ_DVS 132333
	52
	53	/* frequency to sleep and reboot in
	54	* it's essential to leave dvs, as some boards do not reconfigure the
	55	* regulator on reboot
	56	*/
	57	#define FREQ_SLEEP 133333
	58
	59	/* Sources for the ARMCLK */
	60	#define SOURCE_HCLK 0
	61	#define SOURCE_ARMDIV 1
	62
	63	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	64	/* S3C2416 only supports changing the voltage in the dvs-mode.
65	* Voltages down to 1.0V seem to work, so we take what the regulator
66	* can get us.
67	*/
68	static struct s3c2416_dvfs s3c2416_dvfs_table[] = {
69	[SOURCE_HCLK] = { 950000, 1250000 },
70	[SOURCE_ARMDIV] = { 1250000, 1350000 },
71	};
72	#endif
73
74	static struct cpufreq_frequency_table s3c2416_freq_table[] = {
75	{ SOURCE_HCLK, FREQ_DVS },
76	{ SOURCE_ARMDIV, 133333 },
77	{ SOURCE_ARMDIV, 266666 },
78	{ SOURCE_ARMDIV, 400000 },
79	{ 0, CPUFREQ_TABLE_END },
80	};
81
82	static struct cpufreq_frequency_table s3c2450_freq_table[] = {
83	{ SOURCE_HCLK, FREQ_DVS },
84	{ SOURCE_ARMDIV, 133500 },
85	{ SOURCE_ARMDIV, 267000 },
86	{ SOURCE_ARMDIV, 534000 },
87	{ 0, CPUFREQ_TABLE_END },
88	};
89
90	static int s3c2416_cpufreq_verify_speed(struct cpufreq_policy *policy)
91	{
92	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
93
94	if (policy->cpu != 0)
95	return -EINVAL;
96
97	return cpufreq_frequency_table_verify(policy, s3c_freq->freq_table);
98	}
99
100	static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu)
101	{
102	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
103
104	if (cpu != 0)
105	return 0;
106
107	/* return our pseudo-frequency when in dvs mode */
108	if (s3c_freq->is_dvs)
109	return FREQ_DVS;
110
111	return clk_get_rate(s3c_freq->armclk) / 1000;
112	}
113
114	static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq,
115	unsigned int freq)
116	{
117	int ret;
118
119	if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) {
120	ret = clk_set_rate(s3c_freq->armdiv, freq * 1000);
121	if (ret < 0) {
122	pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n",
123	freq, ret);
124	return ret;
125	}
126	}
127
128	return 0;
129	}
130
131	static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx)
132	{
133	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
134	struct s3c2416_dvfs *dvfs;
135	#endif
136	int ret;
137
138	if (s3c_freq->is_dvs) {
139	pr_debug("cpufreq: already in dvs mode, nothing to do\n");
140	return 0;
141	}
142
143	pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n",
144	clk_get_rate(s3c_freq->hclk) / 1000);
145	ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk);
146	if (ret < 0) {
147	pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret);
148	return ret;
149	}
150
151	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
152	/* changing the core voltage is only allowed when in dvs mode */
153	if (s3c_freq->vddarm) {
154	dvfs = &s3c2416_dvfs_table[idx];
155
c03c3013	156	pr_debug("cpufreq: setting regulator to %d-%d\n",
34ee5507 HS	157	dvfs->vddarm_min, dvfs->vddarm_max);
	158	ret = regulator_set_voltage(s3c_freq->vddarm,
	159	dvfs->vddarm_min,
	160	dvfs->vddarm_max);
	161
	162	/* when lowering the voltage failed, there is nothing to do */
	163	if (ret != 0)
	164	pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
	165	}
	166	#endif
	167
	168	s3c_freq->is_dvs = 1;
	169
	170	return 0;
	171	}
	172
	173	static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx)
	174	{
	175	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	176	struct s3c2416_dvfs *dvfs;
	177	#endif
	178	int ret;
	179
	180	if (!s3c_freq->is_dvs) {
	181	pr_debug("cpufreq: not in dvs mode, so can't leave\n");
	182	return 0;
	183	}
	184
	185	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	186	if (s3c_freq->vddarm) {
	187	dvfs = &s3c2416_dvfs_table[idx];
	188
c03c3013	189	pr_debug("cpufreq: setting regulator to %d-%d\n",
34ee5507 HS	190	dvfs->vddarm_min, dvfs->vddarm_max);
	191	ret = regulator_set_voltage(s3c_freq->vddarm,
	192	dvfs->vddarm_min,
	193	dvfs->vddarm_max);
	194	if (ret != 0) {
	195	pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
	196	return ret;
	197	}
	198	}
	199	#endif
	200
	201	/* force armdiv to hclk frequency for transition from dvs*/
	202	if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) {
	203	pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n",
	204	clk_get_rate(s3c_freq->hclk) / 1000);
	205	ret = s3c2416_cpufreq_set_armdiv(s3c_freq,
	206	clk_get_rate(s3c_freq->hclk) / 1000);
	207	if (ret < 0) {
	208	pr_err("cpufreq: Failed to to set the armdiv to %lukHz: %d\n",
	209	clk_get_rate(s3c_freq->hclk) / 1000, ret);
	210	return ret;
	211	}
	212	}
	213
	214	pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n",
	215	clk_get_rate(s3c_freq->armdiv) / 1000);
	216
	217	ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv);
	218	if (ret < 0) {
	219	pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n",
	220	ret);
	221	return ret;
	222	}
	223
	224	s3c_freq->is_dvs = 0;
	225
	226	return 0;
	227	}
	228
	229	static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy,
	230	unsigned int target_freq,
	231	unsigned int relation)
	232	{
	233	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
	234	struct cpufreq_freqs freqs;
	235	int idx, ret, to_dvs = 0;
	236	unsigned int i;
	237
	238	mutex_lock(&cpufreq_lock);
	239
	240	pr_debug("cpufreq: to %dKHz, relation %d\n", target_freq, relation);
	241
	242	ret = cpufreq_frequency_table_target(policy, s3c_freq->freq_table,
	243	target_freq, relation, &i);
	244	if (ret != 0)
	245	goto out;
	246
	247	idx = s3c_freq->freq_table[i].index;
	248
	249	if (idx == SOURCE_HCLK)
	250	to_dvs = 1;
	251
	252	/* switching to dvs when it's not allowed */
	253	if (to_dvs && s3c_freq->disable_dvs) {
254	pr_debug("cpufreq: entering dvs mode not allowed\n");
255	ret = -EINVAL;
256	goto out;
257	}
258
34ee5507 HS	259	freqs.flags = 0;
	260	freqs.old = s3c_freq->is_dvs ? FREQ_DVS
	261	: clk_get_rate(s3c_freq->armclk) / 1000;
	262
	263	/* When leavin dvs mode, always switch the armdiv to the hclk rate
	264	* The S3C2416 has stability issues when switching directly to
	265	* higher frequencies.
	266	*/
	267	freqs.new = (s3c_freq->is_dvs && !to_dvs)
	268	? clk_get_rate(s3c_freq->hclk) / 1000
	269	: s3c_freq->freq_table[i].frequency;
	270
	271	pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
	272
	273	if (!to_dvs && freqs.old == freqs.new)
	274	goto out;
	275
b43a7ffb	276	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
34ee5507 HS	277
	278	if (to_dvs) {
	279	pr_debug("cpufreq: enter dvs\n");
	280	ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx);
	281	} else if (s3c_freq->is_dvs) {
	282	pr_debug("cpufreq: leave dvs\n");
	283	ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx);
	284	} else {
	285	pr_debug("cpufreq: change armdiv to %dkHz\n", freqs.new);
	286	ret = s3c2416_cpufreq_set_armdiv(s3c_freq, freqs.new);
	287	}
	288
b43a7ffb	289	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
34ee5507 HS	290
	291	out:
	292	mutex_unlock(&cpufreq_lock);
	293
	294	return ret;
	295	}
	296
	297	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	298	static void __init s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq)
	299	{
	300	int count, v, i, found;
	301	struct cpufreq_frequency_table *freq;
	302	struct s3c2416_dvfs *dvfs;
	303
	304	count = regulator_count_voltages(s3c_freq->vddarm);
	305	if (count < 0) {
	306	pr_err("cpufreq: Unable to check supported voltages\n");
	307	return;
	308	}
	309
	310	freq = s3c_freq->freq_table;
	311	while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
	312	if (freq->frequency == CPUFREQ_ENTRY_INVALID)
	313	continue;
	314
	315	dvfs = &s3c2416_dvfs_table[freq->index];
	316	found = 0;
	317
	318	/* Check only the min-voltage, more is always ok on S3C2416 */
	319	for (i = 0; i < count; i++) {
	320	v = regulator_list_voltage(s3c_freq->vddarm, i);
	321	if (v >= dvfs->vddarm_min)
	322	found = 1;
	323	}
	324
	325	if (!found) {
	326	pr_debug("cpufreq: %dkHz unsupported by regulator\n",
	327	freq->frequency);
	328	freq->frequency = CPUFREQ_ENTRY_INVALID;
	329	}
	330
	331	freq++;
	332	}
	333
	334	/* Guessed */
	335	s3c_freq->regulator_latency = 1 * 1000 * 1000;
	336	}
	337	#endif
	338
	339	static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block *this,
	340	unsigned long event, void *ptr)
	341	{
	342	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
	343	int ret;
	344
	345	mutex_lock(&cpufreq_lock);
	346
	347	/* disable further changes */
	348	s3c_freq->disable_dvs = 1;
	349
	350	mutex_unlock(&cpufreq_lock);
	351
	352	/* some boards don't reconfigure the regulator on reboot, which
	353	* could lead to undervolting the cpu when the clock is reset.
354	* Therefore we always leave the DVS mode on reboot.
355	*/
356	if (s3c_freq->is_dvs) {
357	pr_debug("cpufreq: leave dvs on reboot\n");
358	ret = cpufreq_driver_target(cpufreq_cpu_get(0), FREQ_SLEEP, 0);
359	if (ret < 0)
360	return NOTIFY_BAD;
361	}
362
363	return NOTIFY_DONE;
364	}
365
366	static struct notifier_block s3c2416_cpufreq_reboot_notifier = {
367	.notifier_call = s3c2416_cpufreq_reboot_notifier_evt,
368	};
369
370	static int __init s3c2416_cpufreq_driver_init(struct cpufreq_policy *policy)
371	{
372	struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
373	struct cpufreq_frequency_table *freq;
374	struct clk *msysclk;
375	unsigned long rate;
376	int ret;
377
378	if (policy->cpu != 0)
379	return -EINVAL;
380
381	msysclk = clk_get(NULL, "msysclk");
382	if (IS_ERR(msysclk)) {
383	ret = PTR_ERR(msysclk);
384	pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret);
385	return ret;
386	}
387
388	/*
389	* S3C2416 and S3C2450 share the same processor-ID and also provide no
390	* other means to distinguish them other than through the rate of
391	* msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz.
392	*/
393	rate = clk_get_rate(msysclk);
394	if (rate == 800 * 1000 * 1000) {
395	pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n",
396	rate / 1000);
397	s3c_freq->freq_table = s3c2416_freq_table;
398	policy->cpuinfo.max_freq = 400000;
399	} else if (rate / 1000 == 534000) {
400	pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n",
401	rate / 1000);
402	s3c_freq->freq_table = s3c2450_freq_table;
403	policy->cpuinfo.max_freq = 534000;
404	}
405
406	/* not needed anymore */
407	clk_put(msysclk);
408
409	if (s3c_freq->freq_table == NULL) {
410	pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n",
411	rate / 1000);
412	return -ENODEV;
413	}
414
415	s3c_freq->is_dvs = 0;
416
417	s3c_freq->armdiv = clk_get(NULL, "armdiv");
418	if (IS_ERR(s3c_freq->armdiv)) {
419	ret = PTR_ERR(s3c_freq->armdiv);
420	pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret);
421	return ret;
422	}
423
424	s3c_freq->hclk = clk_get(NULL, "hclk");
425	if (IS_ERR(s3c_freq->hclk)) {
426	ret = PTR_ERR(s3c_freq->hclk);
427	pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret);
428	goto err_hclk;
429	}
430
431	/* chech hclk rate, we only support the common 133MHz for now
432	* hclk could also run at 66MHz, but this not often used
433	*/
434	rate = clk_get_rate(s3c_freq->hclk);
435	if (rate < 133 * 1000 * 1000) {
436	pr_err("cpufreq: HCLK not at 133MHz\n");
34ee5507 HS	437	ret = -EINVAL;
	438	goto err_armclk;
	439	}
	440
	441	s3c_freq->armclk = clk_get(NULL, "armclk");
	442	if (IS_ERR(s3c_freq->armclk)) {
	443	ret = PTR_ERR(s3c_freq->armclk);
	444	pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret);
	445	goto err_armclk;
	446	}
	447
	448	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
	449	s3c_freq->vddarm = regulator_get(NULL, "vddarm");
	450	if (IS_ERR(s3c_freq->vddarm)) {
	451	ret = PTR_ERR(s3c_freq->vddarm);
	452	pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
	453	goto err_vddarm;
	454	}
	455
	456	s3c2416_cpufreq_cfg_regulator(s3c_freq);
	457	#else
	458	s3c_freq->regulator_latency = 0;
	459	#endif
	460
	461	freq = s3c_freq->freq_table;
	462	while (freq->frequency != CPUFREQ_TABLE_END) {
	463	/* special handling for dvs mode */
	464	if (freq->index == 0) {
	465	if (!s3c_freq->hclk) {
	466	pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n",
	467	freq->frequency);
	468	freq->frequency = CPUFREQ_ENTRY_INVALID;
	469	} else {
	470	freq++;
	471	continue;
	472	}
	473	}
	474
	475	/* Check for frequencies we can generate */
	476	rate = clk_round_rate(s3c_freq->armdiv,
	477	freq->frequency * 1000);
	478	rate /= 1000;
	479	if (rate != freq->frequency) {
	480	pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n",
	481	freq->frequency, rate);
	482	freq->frequency = CPUFREQ_ENTRY_INVALID;
	483	}
	484
	485	freq++;
	486	}
	487
	488	policy->cur = clk_get_rate(s3c_freq->armclk) / 1000;
	489
	490	/* Datasheet says PLL stabalisation time must be at least 300us,
	491	* so but add some fudge. (reference in LOCKCON0 register description)
	492	*/
	493	policy->cpuinfo.transition_latency = (500 * 1000) +
	494	s3c_freq->regulator_latency;
	495
	496	ret = cpufreq_frequency_table_cpuinfo(policy, s3c_freq->freq_table);
	497	if (ret)
	498	goto err_freq_table;
	499
	500	cpufreq_frequency_table_get_attr(s3c_freq->freq_table, 0);
501
502	register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier);
503
504	return 0;
505
506	err_freq_table:
507	#ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
508	regulator_put(s3c_freq->vddarm);
509	err_vddarm:
510	#endif
511	clk_put(s3c_freq->armclk);
512	err_armclk:
513	clk_put(s3c_freq->hclk);
514	err_hclk:
515	clk_put(s3c_freq->armdiv);
516
517	return ret;
518	}
519
520	static struct freq_attr *s3c2416_cpufreq_attr[] = {
521	&cpufreq_freq_attr_scaling_available_freqs,
522	NULL,
523	};
524
525	static struct cpufreq_driver s3c2416_cpufreq_driver = {
526	.owner = THIS_MODULE,
527	.flags = 0,
528	.verify = s3c2416_cpufreq_verify_speed,
529	.target = s3c2416_cpufreq_set_target,
530	.get = s3c2416_cpufreq_get_speed,
531	.init = s3c2416_cpufreq_driver_init,
532	.name = "s3c2416",
533	.attr = s3c2416_cpufreq_attr,
534	};
535
536	static int __init s3c2416_cpufreq_init(void)
537	{
538	return cpufreq_register_driver(&s3c2416_cpufreq_driver);
539	}
540	module_init(s3c2416_cpufreq_init);