[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / xtensa / include / asm / pgtable.h

/*
 * include/asm-xtensa/pgtable.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Copyright (C) 2001 - 2007 Tensilica Inc.
 */

#ifndef _XTENSA_PGTABLE_H
#define _XTENSA_PGTABLE_H

#include <asm-generic/pgtable-nopmd.h>
#include <asm/page.h>

/*
 * We only use two ring levels, user and kernel space.
 */

#define USER_RING		1	/* user ring level */
#define KERNEL_RING		0	/* kernel ring level */

/*
 * The Xtensa architecture port of Linux has a two-level page table system,
 * i.e. the logical three-level Linux page table layout is folded.
 * Each task has the following memory page tables:
 *
 *   PGD table (page directory), ie. 3rd-level page table:
 *	One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
 *	(Architectures that don't have the PMD folded point to the PMD tables)
 *
 *	The pointer to the PGD table for a given task can be retrieved from
 *	the task structure (struct task_struct*) t, e.g. current():
 *	  (t->mm ? t->mm : t->active_mm)->pgd
 *
 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
 *	Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
 *
 *   PTE tables (page table entry), ie. 1st-level page tables:
 *	One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
 *	invalid_pte_table for absent mappings.
 *
 * The individual pages are 4 kB big with special pages for the empty_zero_page.
 */

#define PGDIR_SHIFT	22
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level: we use two-level, so
 * we don't really have any PMD directory physically.
 */
#define PTRS_PER_PTE		1024
#define PTRS_PER_PTE_SHIFT	10
#define PTRS_PER_PGD		1024
#define PGD_ORDER		0
#define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0
#define FIRST_USER_PGD_NR	(FIRST_USER_ADDRESS >> PGDIR_SHIFT)

/*
 * Virtual memory area. We keep a distance to other memory regions to be
 * on the safe side. We also use this area for cache aliasing.
 */

#define VMALLOC_START		0xC0000000
#define VMALLOC_END		0xC7FEFFFF
#define TLBTEMP_BASE_1		0xC7FF0000
#define TLBTEMP_BASE_2		(TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
#define TLBTEMP_SIZE		(2 * DCACHE_WAY_SIZE)
#else
#define TLBTEMP_SIZE		ICACHE_WAY_SIZE
#endif

/*
 * Xtensa Linux config PTE layout (when present):
 *	31-12:	PPN
 *	11-6:	Software
 *	5-4:	RING
 *	3-0:	CA
 *
 * Similar to the Alpha and MIPS ports, we need to keep track of the ref
 * and mod bits in software.  We have a software "you can read
 * from this page" bit, and a hardware one which actually lets the
 * process read from the page.  On the same token we have a software
 * writable bit and the real hardware one which actually lets the
 * process write to the page.
 *
 * See further below for PTE layout for swapped-out pages.
 */

#define _PAGE_HW_EXEC		(1<<0)	/* hardware: page is executable */
#define _PAGE_HW_WRITE		(1<<1)	/* hardware: page is writable */

#define _PAGE_FILE		(1<<1)	/* non-linear mapping, if !present */
#define _PAGE_PROTNONE		(3<<0)	/* special case for VM_PROT_NONE */

/* None of these cache modes include MP coherency:  */
#define _PAGE_CA_BYPASS		(0<<2)	/* bypass, non-speculative */
#define _PAGE_CA_WB		(1<<2)	/* write-back */
#define _PAGE_CA_WT		(2<<2)	/* write-through */
#define _PAGE_CA_MASK		(3<<2)
#define _PAGE_INVALID		(3<<2)

#define _PAGE_USER		(1<<4)	/* user access (ring=1) */

/* Software */
#define _PAGE_WRITABLE_BIT	6
#define _PAGE_WRITABLE		(1<<6)	/* software: page writable */
#define _PAGE_DIRTY		(1<<7)	/* software: page dirty */
#define _PAGE_ACCESSED		(1<<8)	/* software: page accessed (read) */

/* On older HW revisions, we always have to set bit 0 */
#if XCHAL_HW_VERSION_MAJOR < 2000
# define _PAGE_VALID		(1<<0)
#else
# define _PAGE_VALID		0
#endif

#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_PRESENT	(_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)

#ifdef CONFIG_MMU

#define PAGE_NONE	   __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE)
#define PAGE_COPY	   __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_COPY_EXEC	   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
#define PAGE_READONLY	   __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
#define PAGE_SHARED	   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
#define PAGE_SHARED_EXEC \
	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
#define PAGE_KERNEL	   __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
#define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)

#if (DCACHE_WAY_SIZE > PAGE_SIZE)
# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
#else
# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
#endif

#else /* no mmu */

# define PAGE_NONE       __pgprot(0)
# define PAGE_SHARED     __pgprot(0)
# define PAGE_COPY       __pgprot(0)
# define PAGE_READONLY   __pgprot(0)
# define PAGE_KERNEL     __pgprot(0)

#endif

/*
 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 * the MMU can't do page protection for execute, and considers that the same as
 * read.  Also, write permissions may imply read permissions.
 * What follows is the closest we can get by reasonable means..
 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 */
#define __P000	PAGE_NONE		/* private --- */
#define __P001	PAGE_READONLY		/* private --r */
#define __P010	PAGE_COPY		/* private -w- */
#define __P011	PAGE_COPY		/* private -wr */
#define __P100	PAGE_READONLY_EXEC	/* private x-- */
#define __P101	PAGE_READONLY_EXEC	/* private x-r */
#define __P110	PAGE_COPY_EXEC		/* private xw- */
#define __P111	PAGE_COPY_EXEC		/* private xwr */

#define __S000	PAGE_NONE		/* shared  --- */
#define __S001	PAGE_READONLY		/* shared  --r */
#define __S010	PAGE_SHARED		/* shared  -w- */
#define __S011	PAGE_SHARED		/* shared  -wr */
#define __S100	PAGE_READONLY_EXEC	/* shared  x-- */
#define __S101	PAGE_READONLY_EXEC	/* shared  x-r */
#define __S110	PAGE_SHARED_EXEC	/* shared  xw- */
#define __S111	PAGE_SHARED_EXEC	/* shared  xwr */

#ifndef __ASSEMBLY__

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern unsigned long empty_zero_page[1024];

#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

#ifdef CONFIG_MMU
extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
extern void paging_init(void);
extern void pgtable_cache_init(void);
#else
# define swapper_pg_dir NULL
static inline void paging_init(void) { }
static inline void pgtable_cache_init(void) { }
#endif

/*
 * The pmd contains the kernel virtual address of the pte page.
 */
#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) virt_to_page(pmd_val(pmd))

/*
 * pte status.
 */
#define pte_none(pte)	 (pte_val(pte) == _PAGE_INVALID)
#define pte_present(pte)						\
	(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID)		\
	 || ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
#define pte_clear(mm,addr,ptep)						\
	do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)

#define pmd_none(pmd)	 (!pmd_val(pmd))
#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
#define pmd_bad(pmd)	 (pmd_val(pmd) & ~PAGE_MASK)
#define pmd_clear(pmdp)	 do { set_pmd(pmdp, __pmd(0)); } while (0)

static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
static inline int pte_file(pte_t pte)  { return pte_val(pte) & _PAGE_FILE; }
static inline int pte_special(pte_t pte) { return 0; }

static inline pte_t pte_wrprotect(pte_t pte)	
	{ pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
static inline pte_t pte_mkclean(pte_t pte)
	{ pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
static inline pte_t pte_mkold(pte_t pte)
	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkdirty(pte_t pte)
	{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte)
	{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkwrite(pte_t pte)
	{ pte_val(pte) |= _PAGE_WRITABLE; return pte; }
static inline pte_t pte_mkspecial(pte_t pte)
	{ return pte; }

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */

#define pte_pfn(pte)		(pte_val(pte) >> PAGE_SHIFT)
#define pte_same(a,b)		(pte_val(a) == pte_val(b))
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define mk_pte(page, prot)	pfn_pte(page_to_pfn(page), prot)

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}

/*
 * Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
static inline void update_pte(pte_t *ptep, pte_t pteval)
{
	*ptep = pteval;
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
#endif

}

struct mm_struct;

static inline void
set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
{
	update_pte(ptep, pteval);
}


static inline void
set_pmd(pmd_t *pmdp, pmd_t pmdval)
{
	*pmdp = pmdval;
}

struct vm_area_struct;

static inline int
ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
			  pte_t *ptep)
{
	pte_t pte = *ptep;
	if (!pte_young(pte))
		return 0;
	update_pte(ptep, pte_mkold(pte));
	return 1;
}

static inline pte_t
ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	pte_clear(mm, addr, ptep);
	return pte;
}

static inline void
ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	update_pte(ptep, pte_wrprotect(pte));
}

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address)	pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm,address)	((mm)->pgd + pgd_index(address))

#define pgd_index(address)	((address) >> PGDIR_SHIFT)

/* Find an entry in the second-level page table.. */
#define pmd_offset(dir,address) ((pmd_t*)(dir))

/* Find an entry in the third-level page table.. */
#define pte_index(address)	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir,addr) 					\
	((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
#define pte_offset_map(dir,addr)	pte_offset_kernel((dir),(addr))
#define pte_unmap(pte)		do { } while (0)


/*
 * Encode and decode a swap entry.
 *
 * Format of swap pte:
 *  bit	   0	   MBZ
 *  bit	   1	   page-file (must be zero)
 *  bits   2 -  3  page hw access mode (must be 11: _PAGE_INVALID)
 *  bits   4 -  5  ring protection (must be 01: _PAGE_USER)
 *  bits   6 - 10  swap type (5 bits -> 32 types)
 *  bits  11 - 31  swap offset / PAGE_SIZE (21 bits -> 8GB)
 
 * Format of file pte:
 *  bit	   0	   MBZ
 *  bit	   1	   page-file (must be one: _PAGE_FILE)
 *  bits   2 -  3  page hw access mode (must be 11: _PAGE_INVALID)
 *  bits   4 -  5  ring protection (must be 01: _PAGE_USER)
 *  bits   6 - 31  file offset / PAGE_SIZE
 */

#define __swp_type(entry)	(((entry).val >> 6) & 0x1f)
#define __swp_offset(entry)	((entry).val >> 11)
#define __swp_entry(type,offs)	\
	((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID})
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

#define PTE_FILE_MAX_BITS	28
#define pte_to_pgoff(pte)	(pte_val(pte) >> 4)
#define pgoff_to_pte(off)	\
	((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE })

#endif /*  !defined (__ASSEMBLY__) */


#ifdef __ASSEMBLY__

/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 *
 * Note: We require an additional temporary register which can be the same as
 *       the register that holds the address.
 *
 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 *
 */
#define _PGD_INDEX(rt,rs)	extui	rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
#define _PTE_INDEX(rt,rs)	extui	rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT

#define _PGD_OFFSET(mm,adr,tmp)		l32i	mm, mm, MM_PGD;		\
					_PGD_INDEX(tmp, adr);		\
					addx4	mm, tmp, mm

#define _PTE_OFFSET(pmd,adr,tmp)	_PTE_INDEX(tmp, adr);		\
					srli	pmd, pmd, PAGE_SHIFT;	\
					slli	pmd, pmd, PAGE_SHIFT;	\
					addx4	pmd, tmp, pmd

#else

#define kern_addr_valid(addr)	(1)

extern  void update_mmu_cache(struct vm_area_struct * vma,
			      unsigned long address, pte_t *ptep);

/*
 * remap a physical page `pfn' of size `size' with page protection `prot'
 * into virtual address `from'
 */

#define io_remap_pfn_range(vma,from,pfn,size,prot) \
	remap_pfn_range(vma, from, pfn, size, prot)

typedef pte_t *pte_addr_t;

#endif /* !defined (__ASSEMBLY__) */

#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
#define __HAVE_ARCH_PTEP_MKDIRTY
#define __HAVE_ARCH_PTE_SAME
/* We provide our own get_unmapped_area to cope with
 * SHM area cache aliasing for userland.
 */
#define HAVE_ARCH_UNMAPPED_AREA

#include <asm-generic/pgtable.h>

#endif /* _XTENSA_PGTABLE_H */
Commit	Line	Data
9a8fd558	1	/*
6656920b	2	* include/asm-xtensa/pgtable.h
9a8fd558 CZ	3	*
9a8fd558 CZ	4	* This program is free software; you can redistribute it and/or modify
01858d1b	5	* it under the terms of the GNU General Public License version 2 as
9a8fd558 CZ	6	* published by the Free Software Foundation.
9a8fd558 CZ	7	*
01858d1b	8	* Copyright (C) 2001 - 2007 Tensilica Inc.
9a8fd558 CZ	9	*/
	10
	11	#ifndef _XTENSA_PGTABLE_H
	12	#define _XTENSA_PGTABLE_H
	13
	14	#include <asm-generic/pgtable-nopmd.h>
	15	#include <asm/page.h>
	16
9a8fd558 CZ	17	/*
	18	* We only use two ring levels, user and kernel space.
	19	*/
	20
	21	#define USER_RING 1 /* user ring level */
	22	#define KERNEL_RING 0 /* kernel ring level */
	23
	24	/*
	25	* The Xtensa architecture port of Linux has a two-level page table system,
01858d1b	26	* i.e. the logical three-level Linux page table layout is folded.
9a8fd558 CZ	27	* Each task has the following memory page tables:
	28	*
	29	* PGD table (page directory), ie. 3rd-level page table:
	30	* One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
	31	* (Architectures that don't have the PMD folded point to the PMD tables)
	32	*
	33	* The pointer to the PGD table for a given task can be retrieved from
	34	* the task structure (struct task_struct*) t, e.g. current():
	35	* (t->mm ? t->mm : t->active_mm)->pgd
	36	*
	37	* PMD tables (page middle-directory), ie. 2nd-level page tables:
	38	* Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
	39	*
	40	* PTE tables (page table entry), ie. 1st-level page tables:
	41	* One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
	42	* invalid_pte_table for absent mappings.
	43	*
	44	* The individual pages are 4 kB big with special pages for the empty_zero_page.
	45	*/
01858d1b	46
9a8fd558 CZ	47	#define PGDIR_SHIFT 22
	48	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	49	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	50
	51	/*
	52	* Entries per page directory level: we use two-level, so
	53	* we don't really have any PMD directory physically.
	54	*/
	55	#define PTRS_PER_PTE 1024
	56	#define PTRS_PER_PTE_SHIFT 10
9a8fd558 CZ	57	#define PTRS_PER_PGD 1024
9a8fd558 CZ	58	#define PGD_ORDER 0
9a8fd558	59	#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
01858d1b	60	#define FIRST_USER_ADDRESS 0
9a8fd558 CZ	61	#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
9a8fd558 CZ	62
6656920b CZ	63	/*
6656920b CZ	64	* Virtual memory area. We keep a distance to other memory regions to be
9a8fd558 CZ	65	* on the safe side. We also use this area for cache aliasing.
	66	*/
	67
9a8fd558	68	#define VMALLOC_START 0xC0000000
3b4a49e2 CZ	69	#define VMALLOC_END 0xC7FEFFFF
3b4a49e2 CZ	70	#define TLBTEMP_BASE_1 0xC7FF0000
af3a54ff MF	71	#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
	72	#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
	73	#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
	74	#else
	75	#define TLBTEMP_SIZE ICACHE_WAY_SIZE
	76	#endif
9a8fd558	77
6656920b CZ	78	/*
6656920b CZ	79	* Xtensa Linux config PTE layout (when present):
9a8fd558 CZ	80	* 31-12: PPN
	81	* 11-6: Software
	82	* 5-4: RING
	83	* 3-0: CA
	84	*
	85	* Similar to the Alpha and MIPS ports, we need to keep track of the ref
	86	* and mod bits in software. We have a software "you can read
	87	* from this page" bit, and a hardware one which actually lets the
	88	* process read from the page. On the same token we have a software
	89	* writable bit and the real hardware one which actually lets the
	90	* process write to the page.
	91	*
	92	* See further below for PTE layout for swapped-out pages.
	93	*/
	94
01858d1b CZ	95	#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
	96	#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
	97
	98	#define _PAGE_FILE (1<<1) /* non-linear mapping, if !present */
	99	#define _PAGE_PROTNONE (3<<0) /* special case for VM_PROT_NONE */
9a8fd558 CZ	100
9a8fd558 CZ	101	/* None of these cache modes include MP coherency: */
01858d1b CZ	102	#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
	103	#define _PAGE_CA_WB (1<<2) /* write-back */
	104	#define _PAGE_CA_WT (2<<2) /* write-through */
	105	#define _PAGE_CA_MASK (3<<2)
	106	#define _PAGE_INVALID (3<<2)
9a8fd558 CZ	107
9a8fd558 CZ	108	#define _PAGE_USER (1<<4) /* user access (ring=1) */
9a8fd558 CZ	109
9a8fd558 CZ	110	/* Software */
01858d1b CZ	111	#define _PAGE_WRITABLE_BIT 6
01858d1b CZ	112	#define _PAGE_WRITABLE (1<<6) /* software: page writable */
9a8fd558 CZ	113	#define _PAGE_DIRTY (1<<7) /* software: page dirty */
9a8fd558 CZ	114	#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
9a8fd558	115
01858d1b CZ	116	/* On older HW revisions, we always have to set bit 0 */
	117	#if XCHAL_HW_VERSION_MAJOR < 2000
	118	# define _PAGE_VALID (1<<0)
	119	#else
	120	# define _PAGE_VALID 0
	121	#endif
	122
	123	#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
	124	#define _PAGE_PRESENT (_PAGE_VALID \| _PAGE_CA_WB \| _PAGE_ACCESSED)
9a8fd558 CZ	125
	126	#ifdef CONFIG_MMU
	127
01858d1b CZ	128	#define PAGE_NONE __pgprot(_PAGE_INVALID \| _PAGE_USER \| _PAGE_PROTNONE)
	129	#define PAGE_COPY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	130	#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_HW_EXEC)
	131	#define PAGE_READONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	132	#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_HW_EXEC)
	133	#define PAGE_SHARED __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITABLE)
	134	#define PAGE_SHARED_EXEC \
	135	__pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITABLE \| _PAGE_HW_EXEC)
6656920b CZ	136	#define PAGE_KERNEL __pgprot(_PAGE_PRESENT \| _PAGE_HW_WRITE)
6656920b CZ	137	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT\|_PAGE_HW_WRITE\|_PAGE_HW_EXEC)
01858d1b CZ	138
01858d1b CZ	139	#if (DCACHE_WAY_SIZE > PAGE_SIZE)
6656920b	140	# define _PAGE_DIRECTORY (_PAGE_VALID \| _PAGE_ACCESSED)
01858d1b	141	#else
6656920b	142	# define _PAGE_DIRECTORY (_PAGE_VALID \| _PAGE_ACCESSED \| _PAGE_CA_WB)
01858d1b	143	#endif
9a8fd558 CZ	144
	145	#else /* no mmu */
	146
	147	# define PAGE_NONE __pgprot(0)
	148	# define PAGE_SHARED __pgprot(0)
	149	# define PAGE_COPY __pgprot(0)
	150	# define PAGE_READONLY __pgprot(0)
	151	# define PAGE_KERNEL __pgprot(0)
	152
	153	#endif
	154
	155	/*
	156	* On certain configurations of Xtensa MMUs (eg. the initial Linux config),
	157	* the MMU can't do page protection for execute, and considers that the same as
	158	* read. Also, write permissions may imply read permissions.
	159	* What follows is the closest we can get by reasonable means..
	160	* See linux/mm/mmap.c for protection_map[] array that uses these definitions.
	161	*/
01858d1b CZ	162	#define __P000 PAGE_NONE /* private --- */
	163	#define __P001 PAGE_READONLY /* private --r */
	164	#define __P010 PAGE_COPY /* private -w- */
	165	#define __P011 PAGE_COPY /* private -wr */
	166	#define __P100 PAGE_READONLY_EXEC /* private x-- */
	167	#define __P101 PAGE_READONLY_EXEC /* private x-r */
	168	#define __P110 PAGE_COPY_EXEC /* private xw- */
	169	#define __P111 PAGE_COPY_EXEC /* private xwr */
	170
	171	#define __S000 PAGE_NONE /* shared --- */
	172	#define __S001 PAGE_READONLY /* shared --r */
	173	#define __S010 PAGE_SHARED /* shared -w- */
	174	#define __S011 PAGE_SHARED /* shared -wr */
	175	#define __S100 PAGE_READONLY_EXEC /* shared x-- */
	176	#define __S101 PAGE_READONLY_EXEC /* shared x-r */
	177	#define __S110 PAGE_SHARED_EXEC /* shared xw- */
	178	#define __S111 PAGE_SHARED_EXEC /* shared xwr */
9a8fd558 CZ	179
	180	#ifndef __ASSEMBLY__
	181
	182	#define pte_ERROR(e) \
	183	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	184	#define pgd_ERROR(e) \
	185	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	186
	187	extern unsigned long empty_zero_page[1024];
	188
	189	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	190
e5083a63	191	#ifdef CONFIG_MMU
9a8fd558	192	extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
e5083a63 JW	193	extern void paging_init(void);
	194	extern void pgtable_cache_init(void);
	195	#else
	196	# define swapper_pg_dir NULL
	197	static inline void paging_init(void) { }
	198	static inline void pgtable_cache_init(void) { }
	199	#endif
9a8fd558 CZ	200
	201	/*
	202	* The pmd contains the kernel virtual address of the pte page.
	203	*/
46a82b2d	204	#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
9a8fd558 CZ	205	#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
	206
	207	/*
01858d1b	208	* pte status.
9a8fd558	209	*/
01858d1b CZ	210	#define pte_none(pte) (pte_val(pte) == _PAGE_INVALID)
	211	#define pte_present(pte) \
	212	(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID) \
	213	\|\| ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
9a8fd558	214	#define pte_clear(mm,addr,ptep) \
01858d1b	215	do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)
9a8fd558 CZ	216
	217	#define pmd_none(pmd) (!pmd_val(pmd))
	218	#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
9a8fd558	219	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
01858d1b	220	#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
9a8fd558	221
01858d1b	222	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
9a8fd558 CZ	223	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
	224	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
	225	static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
7e675137 NP	226	static inline int pte_special(pte_t pte) { return 0; }
7e675137 NP	227
01858d1b CZ	228	static inline pte_t pte_wrprotect(pte_t pte)
	229	{ pte_val(pte) &= ~(_PAGE_WRITABLE \| _PAGE_HW_WRITE); return pte; }
	230	static inline pte_t pte_mkclean(pte_t pte)
	231	{ pte_val(pte) &= ~(_PAGE_DIRTY \| _PAGE_HW_WRITE); return pte; }
	232	static inline pte_t pte_mkold(pte_t pte)
	233	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
	234	static inline pte_t pte_mkdirty(pte_t pte)
	235	{ pte_val(pte) \|= _PAGE_DIRTY; return pte; }
	236	static inline pte_t pte_mkyoung(pte_t pte)
	237	{ pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
	238	static inline pte_t pte_mkwrite(pte_t pte)
	239	{ pte_val(pte) \|= _PAGE_WRITABLE; return pte; }
7e675137 NP	240	static inline pte_t pte_mkspecial(pte_t pte)
7e675137 NP	241	{ return pte; }
9a8fd558 CZ	242
	243	/*
	244	* Conversion functions: convert a page and protection to a page entry,
	245	* and a page entry and page directory to the page they refer to.
	246	*/
01858d1b	247
9a8fd558 CZ	248	#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
	249	#define pte_same(a,b) (pte_val(a) == pte_val(b))
	250	#define pte_page(x) pfn_to_page(pte_pfn(x))
	251	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	252	#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
	253
d99cf715	254	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
9a8fd558 CZ	255	{
	256	return __pte((pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot));
	257	}
	258
	259	/*
	260	* Certain architectures need to do special things when pte's
	261	* within a page table are directly modified. Thus, the following
	262	* hook is made available.
	263	*/
	264	static inline void update_pte(pte_t *ptep, pte_t pteval)
	265	{
	266	*ptep = pteval;
6656920b CZ	267	#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	268	__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
	269	#endif
	270
9a8fd558 CZ	271	}
9a8fd558 CZ	272
8c65b4a6 TS	273	struct mm_struct;
8c65b4a6 TS	274
d99cf715	275	static inline void
9a8fd558 CZ	276	set_pte_at(struct mm_struct mm, unsigned long addr, pte_t ptep, pte_t pteval)
	277	{
	278	update_pte(ptep, pteval);
	279	}
	280
	281
d99cf715	282	static inline void
9a8fd558 CZ	283	set_pmd(pmd_t *pmdp, pmd_t pmdval)
	284	{
	285	*pmdp = pmdval;
9a8fd558 CZ	286	}
9a8fd558 CZ	287
8c65b4a6	288	struct vm_area_struct;
9a8fd558 CZ	289
	290	static inline int
	291	ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
c4c4594b	292	pte_t *ptep)
9a8fd558 CZ	293	{
	294	pte_t pte = *ptep;
	295	if (!pte_young(pte))
	296	return 0;
	297	update_pte(ptep, pte_mkold(pte));
	298	return 1;
	299	}
	300
9a8fd558 CZ	301	static inline pte_t
	302	ptep_get_and_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	303	{
	304	pte_t pte = *ptep;
	305	pte_clear(mm, addr, ptep);
	306	return pte;
	307	}
	308
	309	static inline void
	310	ptep_set_wrprotect(struct mm_struct mm, unsigned long addr, pte_t ptep)
	311	{
c4c4594b CZ	312	pte_t pte = *ptep;
c4c4594b CZ	313	update_pte(ptep, pte_wrprotect(pte));
9a8fd558 CZ	314	}
	315
	316	/* to find an entry in a kernel page-table-directory */
	317	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	318
	319	/* to find an entry in a page-table-directory */
	320	#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
	321
	322	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	323
	324	/* Find an entry in the second-level page table.. */
	325	#define pmd_offset(dir,address) ((pmd_t*)(dir))
	326
	327	/* Find an entry in the third-level page table.. */
	328	#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	329	#define pte_offset_kernel(dir,addr) \
46a82b2d	330	((pte_t) pmd_page_vaddr((dir)) + pte_index(addr))
9a8fd558	331	#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
9a8fd558	332	#define pte_unmap(pte) do { } while (0)
9a8fd558 CZ	333
	334
	335	/*
	336	* Encode and decode a swap entry.
9a8fd558	337	*
01858d1b CZ	338	* Format of swap pte:
	339	* bit 0 MBZ
	340	* bit 1 page-file (must be zero)
	341	* bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
	342	* bits 4 - 5 ring protection (must be 01: _PAGE_USER)
	343	* bits 6 - 10 swap type (5 bits -> 32 types)
	344	* bits 11 - 31 swap offset / PAGE_SIZE (21 bits -> 8GB)
	345
	346	* Format of file pte:
	347	* bit 0 MBZ
	348	* bit 1 page-file (must be one: _PAGE_FILE)
	349	* bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
	350	* bits 4 - 5 ring protection (must be 01: _PAGE_USER)
	351	* bits 6 - 31 file offset / PAGE_SIZE
9a8fd558 CZ	352	*/
9a8fd558 CZ	353
01858d1b CZ	354	#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
	355	#define __swp_offset(entry) ((entry).val >> 11)
	356	#define __swp_entry(type,offs) \
	357	((swp_entry_t) {((type) << 6) \| ((offs) << 11) \| _PAGE_INVALID})
9a8fd558 CZ	358	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	359	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	360
01858d1b CZ	361	#define PTE_FILE_MAX_BITS 28
	362	#define pte_to_pgoff(pte) (pte_val(pte) >> 4)
	363	#define pgoff_to_pte(off) \
	364	((pte_t) { ((off) << 4) \| _PAGE_INVALID \| _PAGE_FILE })
9a8fd558 CZ	365
	366	#endif /* !defined (__ASSEMBLY__) */
	367
	368
	369	#ifdef __ASSEMBLY__
	370
	371	/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
	372	* _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
	373	* _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
	374	* _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
	375	*
	376	* Note: We require an additional temporary register which can be the same as
	377	* the register that holds the address.
	378	*
	379	* ((pte_t) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) + pte_index(addr))
	380	*
	381	*/
	382	#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
	383	#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
	384
	385	#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
	386	_PGD_INDEX(tmp, adr); \
	387	addx4 mm, tmp, mm
	388
	389	#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
	390	srli pmd, pmd, PAGE_SHIFT; \
	391	slli pmd, pmd, PAGE_SHIFT; \
	392	addx4 pmd, tmp, pmd
	393
	394	#else
	395
9a8fd558 CZ	396	#define kern_addr_valid(addr) (1)
	397
	398	extern void update_mmu_cache(struct vm_area_struct * vma,
4b3073e1	399	unsigned long address, pte_t *ptep);
9a8fd558 CZ	400
9a8fd558 CZ	401	/*
33bf5610	402	* remap a physical page `pfn' of size `size' with page protection `prot'
9a8fd558 CZ	403	* into virtual address `from'
9a8fd558 CZ	404	*/
6656920b	405
33bf5610	406	#define io_remap_pfn_range(vma,from,pfn,size,prot) \
c4c4594b	407	remap_pfn_range(vma, from, pfn, size, prot)
9a8fd558	408
9a8fd558 CZ	409	typedef pte_t *pte_addr_t;
	410
	411	#endif /* !defined (__ASSEMBLY__) */
	412
	413	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
9a8fd558 CZ	414	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	415	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	416	#define __HAVE_ARCH_PTEP_MKDIRTY
	417	#define __HAVE_ARCH_PTE_SAME
de73b6b1 MF	418	/* We provide our own get_unmapped_area to cope with
	419	* SHM area cache aliasing for userland.
	420	*/
	421	#define HAVE_ARCH_UNMAPPED_AREA
9a8fd558 CZ	422
	423	#include <asm-generic/pgtable.h>
	424
	425	#endif /* _XTENSA_PGTABLE_H */