projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
512f3430
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
01c22882
IA		 181 unsigned long flags;
182
183 /*
184 * Disabling irqs at this point since the following code could be
185 * interrupted and executed through kvm_arch_hardware_disable()
186 */
187 local_irq_save(flags);
188 if (locals->registered) {
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192 local_irq_restore(flags);
18863bdd 193 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 194 values = &locals->values[slot];
195 if (values->host != values->curr) {
196 wrmsrl(shared_msrs_global.msrs[slot], values->host);
197 values->curr = values->host;
18863bdd
AK		 198 }
199 }
18863bdd
AK		 200}
201
2bf78fa7 202static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 203{
18863bdd 204 u64 value;
013f6a5d
MT		 205 unsigned int cpu = smp_processor_id();
206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 207
2bf78fa7
SY		 208 /* only read, and nobody should modify it at this time,
209 * so don't need lock */
210 if (slot >= shared_msrs_global.nr) {
211 printk(KERN_ERR "kvm: invalid MSR slot!");
212 return;
213 }
214 rdmsrl_safe(msr, &value);
215 smsr->values[slot].host = value;
216 smsr->values[slot].curr = value;
217}
218
219void kvm_define_shared_msr(unsigned slot, u32 msr)
220{
18863bdd
AK		 221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
225 smp_wmb();
18863bdd
AK		 226}
227EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
228
229static void kvm_shared_msr_cpu_online(void)
230{
231 unsigned i;
18863bdd
AK		 232
233 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 234 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 235}
236
1bea37d6 237int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 238{
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
1bea37d6 241 int err;
18863bdd 242
2bf78fa7 243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
1bea37d6 244 return 0;
2bf78fa7 245 smsr->values[slot].curr = value;
1bea37d6
AH		 246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
247 if (err)
248 return 1;
249
18863bdd
AK		 250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
254 }
1bea37d6 255 return 0;
18863bdd
AK		 256}
257EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
258
3548bab5
AK		 259static void drop_user_return_notifiers(void *ignore)
260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 263
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
266}
267
6866b83e
CO		 268u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
269{
8a5a87d9 270 return vcpu->arch.apic_base;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_get_apic_base);
273
274void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
275{
276 /* TODO: reserve bits check */
8a5a87d9 277 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 278}
279EXPORT_SYMBOL_GPL(kvm_set_apic_base);
280
e3ba45b8
GL		 281asmlinkage void kvm_spurious_fault(void)
282{
283 /* Fault while not rebooting. We want the trace. */
284 BUG();
285}
286EXPORT_SYMBOL_GPL(kvm_spurious_fault);
287
3fd28fce
ED		 288#define EXCPT_BENIGN 0
289#define EXCPT_CONTRIBUTORY 1
290#define EXCPT_PF 2
291
292static int exception_class(int vector)
293{
294 switch (vector) {
295 case PF_VECTOR:
296 return EXCPT_PF;
297 case DE_VECTOR:
298 case TS_VECTOR:
299 case NP_VECTOR:
300 case SS_VECTOR:
301 case GP_VECTOR:
302 return EXCPT_CONTRIBUTORY;
303 default:
304 break;
305 }
306 return EXCPT_BENIGN;
307}
308
309static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 310 unsigned nr, bool has_error, u32 error_code,
311 bool reinject)
3fd28fce
ED		 312{
313 u32 prev_nr;
314 int class1, class2;
315
3842d135
AK		 316 kvm_make_request(KVM_REQ_EVENT, vcpu);
317
3fd28fce
ED		 318 if (!vcpu->arch.exception.pending) {
319 queue:
320 vcpu->arch.exception.pending = true;
321 vcpu->arch.exception.has_error_code = has_error;
322 vcpu->arch.exception.nr = nr;
323 vcpu->arch.exception.error_code = error_code;
3f0fd292 324 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 325 return;
326 }
327
328 /* to check exception */
329 prev_nr = vcpu->arch.exception.nr;
330 if (prev_nr == DF_VECTOR) {
331 /* triple fault -> shutdown */
a8eeb04a 332 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 333 return;
334 }
335 class1 = exception_class(prev_nr);
336 class2 = exception_class(nr);
337 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
338 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
339 /* generate double fault per SDM Table 5-5 */
340 vcpu->arch.exception.pending = true;
341 vcpu->arch.exception.has_error_code = true;
342 vcpu->arch.exception.nr = DF_VECTOR;
343 vcpu->arch.exception.error_code = 0;
344 } else
345 /* replace previous exception with a new one in a hope
346 that instruction re-execution will regenerate lost
347 exception */
348 goto queue;
349}
350
298101da
AK		 351void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
352{
ce7ddec4 353 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 354}
355EXPORT_SYMBOL_GPL(kvm_queue_exception);
356
ce7ddec4
JR		 357void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
358{
359 kvm_multiple_exception(vcpu, nr, false, 0, true);
360}
361EXPORT_SYMBOL_GPL(kvm_requeue_exception);
362
db8fcefa 363void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 364{
db8fcefa
AP		 365 if (err)
366 kvm_inject_gp(vcpu, 0);
367 else
368 kvm_x86_ops->skip_emulated_instruction(vcpu);
369}
370EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 371
6389ee94 372void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 373{
374 ++vcpu->stat.pf_guest;
6389ee94
AK		 375 vcpu->arch.cr2 = fault->address;
376 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 377}
27d6c865 378EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 379
6389ee94 380void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 381{
6389ee94
AK		 382 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
383 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 384 else
6389ee94 385 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 386}
387
3419ffc8
SY		 388void kvm_inject_nmi(struct kvm_vcpu *vcpu)
389{
7460fb4a
AK		 390 atomic_inc(&vcpu->arch.nmi_queued);
391 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 392}
393EXPORT_SYMBOL_GPL(kvm_inject_nmi);
394
298101da
AK		 395void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
396{
ce7ddec4 397 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 398}
399EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
400
ce7ddec4
JR		 401void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
402{
403 kvm_multiple_exception(vcpu, nr, true, error_code, true);
404}
405EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
406
0a79b009
AK		 407/*
408 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
409 * a #GP and return false.
410 */
411bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 412{
0a79b009
AK		 413 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
414 return true;
415 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
416 return false;
298101da 417}
0a79b009 418EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 419
ec92fe44
JR		 420/*
421 * This function will be used to read from the physical memory of the currently
422 * running guest. The difference to kvm_read_guest_page is that this function
423 * can read from guest physical or from the guest's guest physical memory.
424 */
425int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
426 gfn_t ngfn, void *data, int offset, int len,
427 u32 access)
428{
429 gfn_t real_gfn;
430 gpa_t ngpa;
431
432 ngpa = gfn_to_gpa(ngfn);
433 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
434 if (real_gfn == UNMAPPED_GVA)
435 return -EFAULT;
436
437 real_gfn = gpa_to_gfn(real_gfn);
438
439 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
440}
441EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
442
3d06b8bf
JR		 443int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
444 void *data, int offset, int len, u32 access)
445{
446 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
447 data, offset, len, access);
448}
449
a03490ed
CO		 450/*
451 * Load the pae pdptrs. Return true is they are all valid.
452 */
ff03a073 453int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 454{
455 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
456 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
457 int i;
458 int ret;
ff03a073 459 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 460
ff03a073
JR		 461 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
462 offset * sizeof(u64), sizeof(pdpte),
463 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 464 if (ret < 0) {
465 ret = 0;
466 goto out;
467 }
468 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 469 if (is_present_gpte(pdpte[i]) &&
20c466b5 470 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 471 ret = 0;
472 goto out;
473 }
474 }
475 ret = 1;
476
ff03a073 477 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 478 __set_bit(VCPU_EXREG_PDPTR,
479 (unsigned long *)&vcpu->arch.regs_avail);
480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 482out:
a03490ed
CO		 483
484 return ret;
485}
cc4b6871 486EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 487
d835dfec
AK		 488static bool pdptrs_changed(struct kvm_vcpu *vcpu)
489{
ff03a073 490 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 491 bool changed = true;
3d06b8bf
JR		 492 int offset;
493 gfn_t gfn;
d835dfec
AK		 494 int r;
495
496 if (is_long_mode(vcpu) || !is_pae(vcpu))
497 return false;
498
6de4f3ad
AK		 499 if (!test_bit(VCPU_EXREG_PDPTR,
500 (unsigned long *)&vcpu->arch.regs_avail))
501 return true;
502
9f8fe504
AK		 503 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
504 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 505 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
506 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 507 if (r < 0)
508 goto out;
ff03a073 509 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 510out:
d835dfec
AK		 511
512 return changed;
513}
514
49a9b07e 515int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 516{
aad82703
SY		 517 unsigned long old_cr0 = kvm_read_cr0(vcpu);
518 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
519 X86_CR0_CD | X86_CR0_NW;
520
f9a48e6a
AK		 521 cr0 |= X86_CR0_ET;
522
ab344828 523#ifdef CONFIG_X86_64
0f12244f
GN		 524 if (cr0 & 0xffffffff00000000UL)
525 return 1;
ab344828
GN		 526#endif
527
528 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 529
0f12244f
GN		 530 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
531 return 1;
a03490ed 532
0f12244f
GN		 533 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
534 return 1;
a03490ed
CO		 535
536 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
537#ifdef CONFIG_X86_64
f6801dff 538 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 539 int cs_db, cs_l;
540
0f12244f
GN		 541 if (!is_pae(vcpu))
542 return 1;
a03490ed 543 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 544 if (cs_l)
545 return 1;
a03490ed
CO		 546 } else
547#endif
ff03a073 548 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 549 kvm_read_cr3(vcpu)))
0f12244f 550 return 1;
a03490ed
CO		 551 }
552
ad756a16
MJ		 553 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
554 return 1;
555
a03490ed 556 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 557
d170c419 558 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 559 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 560 kvm_async_pf_hash_reset(vcpu);
561 }
e5f3f027 562
aad82703
SY		 563 if ((cr0 ^ old_cr0) & update_bits)
564 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 565 return 0;
566}
2d3ad1f4 567EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 568
2d3ad1f4 569void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 570{
49a9b07e 571 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 572}
2d3ad1f4 573EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 574
42bdf991
MT		 575static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
576{
577 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
578 !vcpu->guest_xcr0_loaded) {
579 /* kvm_set_xcr() also depends on this */
580 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
581 vcpu->guest_xcr0_loaded = 1;
582 }
583}
584
585static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
586{
587 if (vcpu->guest_xcr0_loaded) {
588 if (vcpu->arch.xcr0 != host_xcr0)
589 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
590 vcpu->guest_xcr0_loaded = 0;
591 }
592}
593
2acf923e
DC		 594int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
595{
596 u64 xcr0;
597
598 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
599 if (index != XCR_XFEATURE_ENABLED_MASK)
600 return 1;
601 xcr0 = xcr;
2acf923e
DC		 602 if (!(xcr0 & XSTATE_FP))
603 return 1;
604 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
605 return 1;
606 if (xcr0 & ~host_xcr0)
607 return 1;
42bdf991 608 kvm_put_guest_xcr0(vcpu);
2acf923e 609 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 610 return 0;
611}
612
613int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
614{
764bcbc5
Z		 615 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
616 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 617 kvm_inject_gp(vcpu, 0);
618 return 1;
619 }
620 return 0;
621}
622EXPORT_SYMBOL_GPL(kvm_set_xcr);
623
a83b29c6 624int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 625{
fc78f519 626 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 627 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
628 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 629 if (cr4 & CR4_RESERVED_BITS)
630 return 1;
a03490ed 631
2acf923e
DC		 632 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
633 return 1;
634
c68b734f
YW		 635 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
636 return 1;
637
f85cb761 638 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 639 return 1;
640
a03490ed 641 if (is_long_mode(vcpu)) {
0f12244f
GN		 642 if (!(cr4 & X86_CR4_PAE))
643 return 1;
a2edf57f
AK		 644 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
645 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 646 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
647 kvm_read_cr3(vcpu)))
0f12244f
GN		 648 return 1;
649
ad756a16
MJ		 650 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
651 if (!guest_cpuid_has_pcid(vcpu))
652 return 1;
653
654 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
655 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
656 return 1;
657 }
658
5e1746d6 659 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 660 return 1;
a03490ed 661
ad756a16
MJ		 662 if (((cr4 ^ old_cr4) & pdptr_bits) ||
663 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 664 kvm_mmu_reset_context(vcpu);
0f12244f 665
2acf923e 666 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 667 kvm_update_cpuid(vcpu);
2acf923e 668
0f12244f
GN		 669 return 0;
670}
2d3ad1f4 671EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 672
2390218b 673int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 674{
9f8fe504 675 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 676 kvm_mmu_sync_roots(vcpu);
d835dfec 677 kvm_mmu_flush_tlb(vcpu);
0f12244f 678 return 0;
d835dfec
AK		 679 }
680
a03490ed 681 if (is_long_mode(vcpu)) {
471842ec 682 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 683 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
684 return 1;
685 } else
686 if (cr3 & CR3_L_MODE_RESERVED_BITS)
687 return 1;
a03490ed
CO		 688 } else {
689 if (is_pae(vcpu)) {
0f12244f
GN		 690 if (cr3 & CR3_PAE_RESERVED_BITS)
691 return 1;
ff03a073
JR		 692 if (is_paging(vcpu) &&
693 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 694 return 1;
a03490ed
CO		 695 }
696 /*
697 * We don't check reserved bits in nonpae mode, because
698 * this isn't enforced, and VMware depends on this.
699 */
700 }
701
a03490ed
CO		 702 /*
703 * Does the new cr3 value map to physical memory? (Note, we
704 * catch an invalid cr3 even in real-mode, because it would
705 * cause trouble later on when we turn on paging anyway.)
706 *
707 * A real CPU would silently accept an invalid cr3 and would
708 * attempt to use it - with largely undefined (and often hard
709 * to debug) behavior on the guest side.
710 */
711 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 712 return 1;
713 vcpu->arch.cr3 = cr3;
aff48baa 714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 715 vcpu->arch.mmu.new_cr3(vcpu);
716 return 0;
717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 719
eea1cff9 720int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 721{
0f12244f
GN		 722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
a03490ed
CO		 724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
ad312c7c 727 vcpu->arch.cr8 = cr8;
0f12244f
GN		 728 return 0;
729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 731
2d3ad1f4 732unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 733{
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
ad312c7c 737 return vcpu->arch.cr8;
a03490ed 738}
2d3ad1f4 739EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 740
c8639010
JK		 741static void kvm_update_dr7(struct kvm_vcpu *vcpu)
742{
743 unsigned long dr7;
744
745 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
746 dr7 = vcpu->arch.guest_debug_dr7;
747 else
748 dr7 = vcpu->arch.dr7;
749 kvm_x86_ops->set_dr7(vcpu, dr7);
750 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
751}
752
338dbc97 753static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 754{
755 switch (dr) {
756 case 0 ... 3:
757 vcpu->arch.db[dr] = val;
758 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
759 vcpu->arch.eff_db[dr] = val;
760 break;
761 case 4:
338dbc97
GN		 762 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
763 return 1; /* #UD */
020df079
GN		 764 /* fall through */
765 case 6:
338dbc97
GN		 766 if (val & 0xffffffff00000000ULL)
767 return -1; /* #GP */
020df079
GN		 768 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
769 break;
770 case 5:
338dbc97
GN		 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1; /* #UD */
020df079
GN		 773 /* fall through */
774 default: /* 7 */
338dbc97
GN		 775 if (val & 0xffffffff00000000ULL)
776 return -1; /* #GP */
020df079 777 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 778 kvm_update_dr7(vcpu);
020df079
GN		 779 break;
780 }
781
782 return 0;
783}
338dbc97
GN		 784
785int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
786{
787 int res;
788
789 res = __kvm_set_dr(vcpu, dr, val);
790 if (res > 0)
791 kvm_queue_exception(vcpu, UD_VECTOR);
792 else if (res < 0)
793 kvm_inject_gp(vcpu, 0);
794
795 return res;
796}
020df079
GN		 797EXPORT_SYMBOL_GPL(kvm_set_dr);
798
338dbc97 799static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 800{
801 switch (dr) {
802 case 0 ... 3:
803 *val = vcpu->arch.db[dr];
804 break;
805 case 4:
338dbc97 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 807 return 1;
020df079
GN		 808 /* fall through */
809 case 6:
810 *val = vcpu->arch.dr6;
811 break;
812 case 5:
338dbc97 813 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 814 return 1;
020df079
GN		 815 /* fall through */
816 default: /* 7 */
817 *val = vcpu->arch.dr7;
818 break;
819 }
820
821 return 0;
822}
338dbc97
GN		 823
824int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
825{
826 if (_kvm_get_dr(vcpu, dr, val)) {
827 kvm_queue_exception(vcpu, UD_VECTOR);
828 return 1;
829 }
830 return 0;
831}
020df079
GN		 832EXPORT_SYMBOL_GPL(kvm_get_dr);
833
022cd0e8
AK		 834bool kvm_rdpmc(struct kvm_vcpu *vcpu)
835{
836 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
837 u64 data;
838 int err;
839
840 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
841 if (err)
842 return err;
843 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
844 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
845 return err;
846}
847EXPORT_SYMBOL_GPL(kvm_rdpmc);
848
043405e1
CO		 849/*
850 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
851 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
852 *
853 * This list is modified at module load time to reflect the
e3267cbb
GC		 854 * capabilities of the host cpu. This capabilities test skips MSRs that are
855 * kvm-specific. Those are put in the beginning of the list.
043405e1 856 */
e3267cbb 857
439793d4 858#define KVM_SAVE_MSRS_BEGIN 10
043405e1 859static u32 msrs_to_save[] = {
e3267cbb 860 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 861 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 862 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 863 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 864 MSR_KVM_PV_EOI_EN,
043405e1 865 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 866 MSR_STAR,
043405e1
CO		 867#ifdef CONFIG_X86_64
868 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
869#endif
e90aa41e 870 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 871};
872
873static unsigned num_msrs_to_save;
874
f1d24831 875static const u32 emulated_msrs[] = {
ba904635 876 MSR_IA32_TSC_ADJUST,
a3e06bbe 877 MSR_IA32_TSCDEADLINE,
043405e1 878 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 879 MSR_IA32_MCG_STATUS,
880 MSR_IA32_MCG_CTL,
043405e1
CO		 881};
882
384bb783 883bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 884{
b69e8cae 885 if (efer & efer_reserved_bits)
384bb783 886 return false;
15c4a640 887
1b2fd70c
AG		 888 if (efer & EFER_FFXSR) {
889 struct kvm_cpuid_entry2 *feat;
890
891 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 892 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 893 return false;
1b2fd70c
AG		 894 }
895
d8017474
AG		 896 if (efer & EFER_SVME) {
897 struct kvm_cpuid_entry2 *feat;
898
899 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 900 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 901 return false;
d8017474
AG		 902 }
903
384bb783
JK		 904 return true;
905}
906EXPORT_SYMBOL_GPL(kvm_valid_efer);
907
908static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
909{
910 u64 old_efer = vcpu->arch.efer;
911
912 if (!kvm_valid_efer(vcpu, efer))
913 return 1;
914
915 if (is_paging(vcpu)
916 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
917 return 1;
918
15c4a640 919 efer &= ~EFER_LMA;
f6801dff 920 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 921
a3d204e2
SY		 922 kvm_x86_ops->set_efer(vcpu, efer);
923
aad82703
SY		 924 /* Update reserved bits */
925 if ((efer ^ old_efer) & EFER_NX)
926 kvm_mmu_reset_context(vcpu);
927
b69e8cae 928 return 0;
15c4a640
CO		 929}
930
f2b4b7dd
JR		 931void kvm_enable_efer_bits(u64 mask)
932{
933 efer_reserved_bits &= ~mask;
934}
935EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
936
15c4a640
CO		 937/*
938 * Writes msr value into into the appropriate "register".
939 * Returns 0 on success, non-0 otherwise.
940 * Assumes vcpu_load() was already called.
941 */
8fe8ab46 942int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 943{
ea306147
NA		 944 switch (msr->index) {
945 case MSR_FS_BASE:
946 case MSR_GS_BASE:
947 case MSR_KERNEL_GS_BASE:
948 case MSR_CSTAR:
949 case MSR_LSTAR:
950 if (is_noncanonical_address(msr->data))
951 return 1;
952 break;
953 case MSR_IA32_SYSENTER_EIP:
954 case MSR_IA32_SYSENTER_ESP:
955 /*
956 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
957 * non-canonical address is written on Intel but not on
958 * AMD (which ignores the top 32-bits, because it does
959 * not implement 64-bit SYSENTER).
960 *
961 * 64-bit code should hence be able to write a non-canonical
962 * value on AMD. Making the address canonical ensures that
963 * vmentry does not fail on Intel after writing a non-canonical
964 * value, and that something deterministic happens if the guest
965 * invokes 64-bit SYSENTER.
966 */
967 msr->data = get_canonical(msr->data);
968 }
8fe8ab46 969 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 970}
ea306147 971EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 972
313a3dc7
CO		 973/*
974 * Adapt set_msr() to msr_io()'s calling convention
975 */
976static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
977{
8fe8ab46
WA		 978 struct msr_data msr;
979
980 msr.data = *data;
981 msr.index = index;
982 msr.host_initiated = true;
983 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 984}
985
16e8d74d
MT		 986#ifdef CONFIG_X86_64
987struct pvclock_gtod_data {
988 seqcount_t seq;
989
990 struct { /* extract of a clocksource struct */
991 int vclock_mode;
992 cycle_t cycle_last;
993 cycle_t mask;
994 u32 mult;
995 u32 shift;
996 } clock;
997
998 /* open coded 'struct timespec' */
999 u64 monotonic_time_snsec;
1000 time_t monotonic_time_sec;
1001};
1002
1003static struct pvclock_gtod_data pvclock_gtod_data;
1004
1005static void update_pvclock_gtod(struct timekeeper *tk)
1006{
1007 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1008
1009 write_seqcount_begin(&vdata->seq);
1010
1011 /* copy pvclock gtod data */
1012 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1013 vdata->clock.cycle_last = tk->clock->cycle_last;
1014 vdata->clock.mask = tk->clock->mask;
1015 vdata->clock.mult = tk->mult;
1016 vdata->clock.shift = tk->shift;
1017
1018 vdata->monotonic_time_sec = tk->xtime_sec
1019 + tk->wall_to_monotonic.tv_sec;
1020 vdata->monotonic_time_snsec = tk->xtime_nsec
1021 + (tk->wall_to_monotonic.tv_nsec
1022 << tk->shift);
1023 while (vdata->monotonic_time_snsec >=
1024 (((u64)NSEC_PER_SEC) << tk->shift)) {
1025 vdata->monotonic_time_snsec -=
1026 ((u64)NSEC_PER_SEC) << tk->shift;
1027 vdata->monotonic_time_sec++;
1028 }
1029
1030 write_seqcount_end(&vdata->seq);
1031}
1032#endif
1033
1034
18068523
GOC		 1035static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1036{
9ed3c444
AK		 1037 int version;
1038 int r;
50d0a0f9 1039 struct pvclock_wall_clock wc;
923de3cf 1040 struct timespec boot;
18068523
GOC		 1041
1042 if (!wall_clock)
1043 return;
1044
9ed3c444
AK		 1045 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1046 if (r)
1047 return;
1048
1049 if (version & 1)
1050 ++version; /* first time write, random junk */
1051
1052 ++version;
18068523 1053
18068523
GOC		 1054 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1055
50d0a0f9
GH		 1056 /*
1057 * The guest calculates current wall clock time by adding
34c238a1 1058 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1059 * wall clock specified here. guest system time equals host
1060 * system time for us, thus we must fill in host boot time here.
1061 */
923de3cf 1062 getboottime(&boot);
50d0a0f9 1063
4b648665
BR		 1064 if (kvm->arch.kvmclock_offset) {
1065 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1066 boot = timespec_sub(boot, ts);
1067 }
50d0a0f9
GH		 1068 wc.sec = boot.tv_sec;
1069 wc.nsec = boot.tv_nsec;
1070 wc.version = version;
18068523
GOC		 1071
1072 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1073
1074 version++;
1075 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1076}
1077
50d0a0f9
GH		 1078static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1079{
1080 uint32_t quotient, remainder;
1081
1082 /* Don't try to replace with do_div(), this one calculates
1083 * "(dividend << 32) / divisor" */
1084 __asm__ ( "divl %4"
1085 : "=a" (quotient), "=d" (remainder)
1086 : "0" (0), "1" (dividend), "r" (divisor) );
1087 return quotient;
1088}
1089
5f4e3f88
ZA		 1090static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1091 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1092{
5f4e3f88 1093 uint64_t scaled64;
50d0a0f9
GH		 1094 int32_t shift = 0;
1095 uint64_t tps64;
1096 uint32_t tps32;
1097
5f4e3f88
ZA		 1098 tps64 = base_khz * 1000LL;
1099 scaled64 = scaled_khz * 1000LL;
50933623 1100 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1101 tps64 >>= 1;
1102 shift--;
1103 }
1104
1105 tps32 = (uint32_t)tps64;
50933623
JK		 1106 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1107 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1108 scaled64 >>= 1;
1109 else
1110 tps32 <<= 1;
50d0a0f9
GH		 1111 shift++;
1112 }
1113
5f4e3f88
ZA		 1114 *pshift = shift;
1115 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1116
5f4e3f88
ZA		 1117 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1118 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1119}
1120
759379dd
ZA		 1121static inline u64 get_kernel_ns(void)
1122{
1123 struct timespec ts;
1124
1125 WARN_ON(preemptible());
1126 ktime_get_ts(&ts);
1127 monotonic_to_bootbased(&ts);
1128 return timespec_to_ns(&ts);
50d0a0f9
GH		 1129}
1130
d828199e 1131#ifdef CONFIG_X86_64
16e8d74d 1132static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1133#endif
16e8d74d 1134
c8076604 1135static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1136unsigned long max_tsc_khz;
c8076604 1137
cc578287 1138static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1139{
cc578287
ZA		 1140 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1141 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1142}
1143
cc578287 1144static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1145{
cc578287
ZA		 1146 u64 v = (u64)khz * (1000000 + ppm);
1147 do_div(v, 1000000);
1148 return v;
1e993611
JR		 1149}
1150
cc578287 1151static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1152{
cc578287
ZA		 1153 u32 thresh_lo, thresh_hi;
1154 int use_scaling = 0;
217fc9cf 1155
03ba32ca
MT		 1156 /* tsc_khz can be zero if TSC calibration fails */
1157 if (this_tsc_khz == 0)
1158 return;
1159
c285545f
ZA		 1160 /* Compute a scale to convert nanoseconds in TSC cycles */
1161 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1162 &vcpu->arch.virtual_tsc_shift,
1163 &vcpu->arch.virtual_tsc_mult);
1164 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1165
1166 /*
1167 * Compute the variation in TSC rate which is acceptable
1168 * within the range of tolerance and decide if the
1169 * rate being applied is within that bounds of the hardware
1170 * rate. If so, no scaling or compensation need be done.
1171 */
1172 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1173 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1174 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1175 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1176 use_scaling = 1;
1177 }
1178 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1179}
1180
1181static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1182{
e26101b1 1183 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1184 vcpu->arch.virtual_tsc_mult,
1185 vcpu->arch.virtual_tsc_shift);
e26101b1 1186 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1187 return tsc;
1188}
1189
b48aa97e
MT		 1190void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1191{
1192#ifdef CONFIG_X86_64
1193 bool vcpus_matched;
b48aa97e
MT		 1194 struct kvm_arch *ka = &vcpu->kvm->arch;
1195 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1196
1197 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1198 atomic_read(&vcpu->kvm->online_vcpus));
1199
b7e4884e
MT		 1200 /*
1201 * Once the masterclock is enabled, always perform request in
1202 * order to update it.
1203 *
1204 * In order to enable masterclock, the host clocksource must be TSC
1205 * and the vcpus need to have matched TSCs. When that happens,
1206 * perform request to enable masterclock.
1207 */
1208 if (ka->use_master_clock ||
1209 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1210 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1211
1212 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1213 atomic_read(&vcpu->kvm->online_vcpus),
1214 ka->use_master_clock, gtod->clock.vclock_mode);
1215#endif
1216}
1217
ba904635
WA		 1218static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1219{
1220 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1221 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1222}
1223
8fe8ab46 1224void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1225{
1226 struct kvm *kvm = vcpu->kvm;
f38e098f 1227 u64 offset, ns, elapsed;
99e3e30a 1228 unsigned long flags;
02626b6a 1229 s64 usdiff;
b48aa97e 1230 bool matched;
8fe8ab46 1231 u64 data = msr->data;
99e3e30a 1232
038f8c11 1233 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1234 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1235 ns = get_kernel_ns();
f38e098f 1236 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1237
03ba32ca 1238 if (vcpu->arch.virtual_tsc_khz) {
bdbdc407
MT		 1239 int faulted = 0;
1240
03ba32ca
MT		 1241 /* n.b - signed multiplication and division required */
1242 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1243#ifdef CONFIG_X86_64
03ba32ca 1244 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1245#else
03ba32ca 1246 /* do_div() only does unsigned */
bdbdc407
MT		 1247 asm("1: idivl %[divisor]\n"
1248 "2: xor %%edx, %%edx\n"
1249 " movl $0, %[faulted]\n"
1250 "3:\n"
1251 ".section .fixup,\"ax\"\n"
1252 "4: movl $1, %[faulted]\n"
1253 " jmp 3b\n"
1254 ".previous\n"
1255
1256 _ASM_EXTABLE(1b, 4b)
1257
1258 : "=A"(usdiff), [faulted] "=r" (faulted)
1259 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1260
5d3cb0f6 1261#endif
03ba32ca
MT		 1262 do_div(elapsed, 1000);
1263 usdiff -= elapsed;
1264 if (usdiff < 0)
1265 usdiff = -usdiff;
bdbdc407
MT		 1266
1267 /* idivl overflow => difference is larger than USEC_PER_SEC */
1268 if (faulted)
1269 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1270 } else
1271 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1272
1273 /*
5d3cb0f6
ZA		 1274 * Special case: TSC write with a small delta (1 second) of virtual
1275 * cycle time against real time is interpreted as an attempt to
1276 * synchronize the CPU.
1277 *
1278 * For a reliable TSC, we can match TSC offsets, and for an unstable
1279 * TSC, we add elapsed time in this computation. We could let the
1280 * compensation code attempt to catch up if we fall behind, but
1281 * it's better to try to match offsets from the beginning.
1282 */
02626b6a 1283 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1284 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1285 if (!check_tsc_unstable()) {
e26101b1 1286 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1287 pr_debug("kvm: matched tsc offset for %llu\n", data);
1288 } else {
857e4099 1289 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1290 data += delta;
1291 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1292 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1293 }
b48aa97e 1294 matched = true;
e26101b1
ZA		 1295 } else {
1296 /*
1297 * We split periods of matched TSC writes into generations.
1298 * For each generation, we track the original measured
1299 * nanosecond time, offset, and write, so if TSCs are in
1300 * sync, we can match exact offset, and if not, we can match
4a969980 1301 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1302 *
1303 * These values are tracked in kvm->arch.cur_xxx variables.
1304 */
1305 kvm->arch.cur_tsc_generation++;
1306 kvm->arch.cur_tsc_nsec = ns;
1307 kvm->arch.cur_tsc_write = data;
1308 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1309 matched = false;
e26101b1
ZA		 1310 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1311 kvm->arch.cur_tsc_generation, data);
f38e098f 1312 }
e26101b1
ZA		 1313
1314 /*
1315 * We also track th most recent recorded KHZ, write and time to
1316 * allow the matching interval to be extended at each write.
1317 */
f38e098f
ZA		 1318 kvm->arch.last_tsc_nsec = ns;
1319 kvm->arch.last_tsc_write = data;
5d3cb0f6 1320 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1321
1322 /* Reset of TSC must disable overshoot protection below */
1323 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1324 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1325
1326 /* Keep track of which generation this VCPU has synchronized to */
1327 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1328 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1329 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1330
ba904635
WA		 1331 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1332 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1333 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1334 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1335
1336 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1337 if (matched)
1338 kvm->arch.nr_vcpus_matched_tsc++;
1339 else
1340 kvm->arch.nr_vcpus_matched_tsc = 0;
1341
1342 kvm_track_tsc_matching(vcpu);
1343 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1344}
e26101b1 1345
99e3e30a
ZA		 1346EXPORT_SYMBOL_GPL(kvm_write_tsc);
1347
d828199e
MT		 1348#ifdef CONFIG_X86_64
1349
1350static cycle_t read_tsc(void)
1351{
1352 cycle_t ret;
1353 u64 last;
1354
1355 /*
1356 * Empirically, a fence (of type that depends on the CPU)
1357 * before rdtsc is enough to ensure that rdtsc is ordered
1358 * with respect to loads. The various CPU manuals are unclear
1359 * as to whether rdtsc can be reordered with later loads,
1360 * but no one has ever seen it happen.
1361 */
1362 rdtsc_barrier();
1363 ret = (cycle_t)vget_cycles();
1364
1365 last = pvclock_gtod_data.clock.cycle_last;
1366
1367 if (likely(ret >= last))
1368 return ret;
1369
1370 /*
1371 * GCC likes to generate cmov here, but this branch is extremely
1372 * predictable (it's just a funciton of time and the likely is
1373 * very likely) and there's a data dependence, so force GCC
1374 * to generate a branch instead. I don't barrier() because
1375 * we don't actually need a barrier, and if this function
1376 * ever gets inlined it will generate worse code.
1377 */
1378 asm volatile ("");
1379 return last;
1380}
1381
1382static inline u64 vgettsc(cycle_t *cycle_now)
1383{
1384 long v;
1385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1386
1387 *cycle_now = read_tsc();
1388
1389 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1390 return v * gtod->clock.mult;
1391}
1392
1393static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1394{
1395 unsigned long seq;
1396 u64 ns;
1397 int mode;
1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1399
1400 ts->tv_nsec = 0;
1401 do {
1402 seq = read_seqcount_begin(&gtod->seq);
1403 mode = gtod->clock.vclock_mode;
1404 ts->tv_sec = gtod->monotonic_time_sec;
1405 ns = gtod->monotonic_time_snsec;
1406 ns += vgettsc(cycle_now);
1407 ns >>= gtod->clock.shift;
1408 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1409 timespec_add_ns(ts, ns);
1410
1411 return mode;
1412}
1413
1414/* returns true if host is using tsc clocksource */
1415static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1416{
1417 struct timespec ts;
1418
1419 /* checked again under seqlock below */
1420 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1421 return false;
1422
1423 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1424 return false;
1425
1426 monotonic_to_bootbased(&ts);
1427 *kernel_ns = timespec_to_ns(&ts);
1428
1429 return true;
1430}
1431#endif
1432
1433/*
1434 *
b48aa97e
MT		 1435 * Assuming a stable TSC across physical CPUS, and a stable TSC
1436 * across virtual CPUs, the following condition is possible.
1437 * Each numbered line represents an event visible to both
d828199e
MT		 1438 * CPUs at the next numbered event.
1439 *
1440 * "timespecX" represents host monotonic time. "tscX" represents
1441 * RDTSC value.
1442 *
1443 * VCPU0 on CPU0 | VCPU1 on CPU1
1444 *
1445 * 1. read timespec0,tsc0
1446 * 2. | timespec1 = timespec0 + N
1447 * | tsc1 = tsc0 + M
1448 * 3. transition to guest | transition to guest
1449 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1450 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1451 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1452 *
1453 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1454 *
1455 * - ret0 < ret1
1456 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1457 * ...
1458 * - 0 < N - M => M < N
1459 *
1460 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1461 * always the case (the difference between two distinct xtime instances
1462 * might be smaller then the difference between corresponding TSC reads,
1463 * when updating guest vcpus pvclock areas).
1464 *
1465 * To avoid that problem, do not allow visibility of distinct
1466 * system_timestamp/tsc_timestamp values simultaneously: use a master
1467 * copy of host monotonic time values. Update that master copy
1468 * in lockstep.
1469 *
b48aa97e 1470 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1471 *
1472 */
1473
1474static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1475{
1476#ifdef CONFIG_X86_64
1477 struct kvm_arch *ka = &kvm->arch;
1478 int vclock_mode;
b48aa97e
MT		 1479 bool host_tsc_clocksource, vcpus_matched;
1480
1481 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1482 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1483
1484 /*
1485 * If the host uses TSC clock, then passthrough TSC as stable
1486 * to the guest.
1487 */
b48aa97e 1488 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1489 &ka->master_kernel_ns,
1490 &ka->master_cycle_now);
1491
b48aa97e
MT		 1492 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1493
d828199e
MT		 1494 if (ka->use_master_clock)
1495 atomic_set(&kvm_guest_has_master_clock, 1);
1496
1497 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1498 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1499 vcpus_matched);
d828199e
MT		 1500#endif
1501}
1502
34c238a1 1503static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1504{
d828199e 1505 unsigned long flags, this_tsc_khz;
18068523 1506 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1507 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1508 s64 kernel_ns, max_kernel_ns;
d828199e 1509 u64 tsc_timestamp, host_tsc;
0b79459b 1510 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1511 u8 pvclock_flags;
d828199e
MT		 1512 bool use_master_clock;
1513
1514 kernel_ns = 0;
1515 host_tsc = 0;
18068523 1516
d828199e
MT		 1517 /*
1518 * If the host uses TSC clock, then passthrough TSC as stable
1519 * to the guest.
1520 */
1521 spin_lock(&ka->pvclock_gtod_sync_lock);
1522 use_master_clock = ka->use_master_clock;
1523 if (use_master_clock) {
1524 host_tsc = ka->master_cycle_now;
1525 kernel_ns = ka->master_kernel_ns;
1526 }
1527 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1528
1529 /* Keep irq disabled to prevent changes to the clock */
1530 local_irq_save(flags);
1531 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1532 if (unlikely(this_tsc_khz == 0)) {
1533 local_irq_restore(flags);
1534 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1535 return 1;
1536 }
d828199e
MT		 1537 if (!use_master_clock) {
1538 host_tsc = native_read_tsc();
1539 kernel_ns = get_kernel_ns();
1540 }
1541
1542 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1543
c285545f
ZA		 1544 /*
1545 * We may have to catch up the TSC to match elapsed wall clock
1546 * time for two reasons, even if kvmclock is used.
1547 * 1) CPU could have been running below the maximum TSC rate
1548 * 2) Broken TSC compensation resets the base at each VCPU
1549 * entry to avoid unknown leaps of TSC even when running
1550 * again on the same CPU. This may cause apparent elapsed
1551 * time to disappear, and the guest to stand still or run
1552 * very slowly.
1553 */
1554 if (vcpu->tsc_catchup) {
1555 u64 tsc = compute_guest_tsc(v, kernel_ns);
1556 if (tsc > tsc_timestamp) {
f1e2b260 1557 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1558 tsc_timestamp = tsc;
1559 }
50d0a0f9
GH		 1560 }
1561
18068523
GOC		 1562 local_irq_restore(flags);
1563
0b79459b 1564 if (!vcpu->pv_time_enabled)
c285545f 1565 return 0;
18068523 1566
1d5f066e
ZA		 1567 /*
1568 * Time as measured by the TSC may go backwards when resetting the base
1569 * tsc_timestamp. The reason for this is that the TSC resolution is
1570 * higher than the resolution of the other clock scales. Thus, many
1571 * possible measurments of the TSC correspond to one measurement of any
1572 * other clock, and so a spread of values is possible. This is not a
1573 * problem for the computation of the nanosecond clock; with TSC rates
1574 * around 1GHZ, there can only be a few cycles which correspond to one
1575 * nanosecond value, and any path through this code will inevitably
1576 * take longer than that. However, with the kernel_ns value itself,
1577 * the precision may be much lower, down to HZ granularity. If the
1578 * first sampling of TSC against kernel_ns ends in the low part of the
1579 * range, and the second in the high end of the range, we can get:
1580 *
1581 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1582 *
1583 * As the sampling errors potentially range in the thousands of cycles,
1584 * it is possible such a time value has already been observed by the
1585 * guest. To protect against this, we must compute the system time as
1586 * observed by the guest and ensure the new system time is greater.
1587 */
1588 max_kernel_ns = 0;
b183aa58 1589 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1590 max_kernel_ns = vcpu->last_guest_tsc -
1591 vcpu->hv_clock.tsc_timestamp;
1592 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1593 vcpu->hv_clock.tsc_to_system_mul,
1594 vcpu->hv_clock.tsc_shift);
1595 max_kernel_ns += vcpu->last_kernel_ns;
1596 }
afbcf7ab 1597
e48672fa 1598 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1599 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1600 &vcpu->hv_clock.tsc_shift,
1601 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1602 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1603 }
1604
d828199e
MT		 1605 /* with a master <monotonic time, tsc value> tuple,
1606 * pvclock clock reads always increase at the (scaled) rate
1607 * of guest TSC - no need to deal with sampling errors.
1608 */
1609 if (!use_master_clock) {
1610 if (max_kernel_ns > kernel_ns)
1611 kernel_ns = max_kernel_ns;
1612 }
8cfdc000 1613 /* With all the info we got, fill in the values */
1d5f066e 1614 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1615 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1616 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1617 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1618
18068523
GOC		 1619 /*
1620 * The interface expects us to write an even number signaling that the
1621 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1622 * state, we just increase by 2 at the end.
18068523 1623 */
50d0a0f9 1624 vcpu->hv_clock.version += 2;
18068523 1625
0b79459b
AH		 1626 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1627 &guest_hv_clock, sizeof(guest_hv_clock))))
1628 return 0;
78c0337a
MT		 1629
1630 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1631 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1632
1633 if (vcpu->pvclock_set_guest_stopped_request) {
1634 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1635 vcpu->pvclock_set_guest_stopped_request = false;
1636 }
1637
d828199e
MT		 1638 /* If the host uses TSC clocksource, then it is stable */
1639 if (use_master_clock)
1640 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1641
78c0337a
MT		 1642 vcpu->hv_clock.flags = pvclock_flags;
1643
0b79459b
AH		 1644 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1645 &vcpu->hv_clock,
1646 sizeof(vcpu->hv_clock));
8cfdc000 1647 return 0;
c8076604
GH		 1648}
1649
9ba075a6
AK		 1650static bool msr_mtrr_valid(unsigned msr)
1651{
1652 switch (msr) {
1653 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1654 case MSR_MTRRfix64K_00000:
1655 case MSR_MTRRfix16K_80000:
1656 case MSR_MTRRfix16K_A0000:
1657 case MSR_MTRRfix4K_C0000:
1658 case MSR_MTRRfix4K_C8000:
1659 case MSR_MTRRfix4K_D0000:
1660 case MSR_MTRRfix4K_D8000:
1661 case MSR_MTRRfix4K_E0000:
1662 case MSR_MTRRfix4K_E8000:
1663 case MSR_MTRRfix4K_F0000:
1664 case MSR_MTRRfix4K_F8000:
1665 case MSR_MTRRdefType:
1666 case MSR_IA32_CR_PAT:
1667 return true;
1668 case 0x2f8:
1669 return true;
1670 }
1671 return false;
1672}
1673
d6289b93
MT		 1674static bool valid_pat_type(unsigned t)
1675{
1676 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1677}
1678
1679static bool valid_mtrr_type(unsigned t)
1680{
1681 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1682}
1683
1684static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1685{
1686 int i;
1687
1688 if (!msr_mtrr_valid(msr))
1689 return false;
1690
1691 if (msr == MSR_IA32_CR_PAT) {
1692 for (i = 0; i < 8; i++)
1693 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1694 return false;
1695 return true;
1696 } else if (msr == MSR_MTRRdefType) {
1697 if (data & ~0xcff)
1698 return false;
1699 return valid_mtrr_type(data & 0xff);
1700 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1701 for (i = 0; i < 8 ; i++)
1702 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1703 return false;
1704 return true;
1705 }
1706
1707 /* variable MTRRs */
1708 return valid_mtrr_type(data & 0xff);
1709}
1710
9ba075a6
AK		 1711static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1712{
0bed3b56
SY		 1713 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1714
d6289b93 1715 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1716 return 1;
1717
0bed3b56
SY		 1718 if (msr == MSR_MTRRdefType) {
1719 vcpu->arch.mtrr_state.def_type = data;
1720 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1721 } else if (msr == MSR_MTRRfix64K_00000)
1722 p[0] = data;
1723 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1724 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1725 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1726 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1727 else if (msr == MSR_IA32_CR_PAT)
1728 vcpu->arch.pat = data;
1729 else { /* Variable MTRRs */
1730 int idx, is_mtrr_mask;
1731 u64 *pt;
1732
1733 idx = (msr - 0x200) / 2;
1734 is_mtrr_mask = msr - 0x200 - 2 * idx;
1735 if (!is_mtrr_mask)
1736 pt =
1737 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1738 else
1739 pt =
1740 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1741 *pt = data;
1742 }
1743
1744 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1745 return 0;
1746}
15c4a640 1747
890ca9ae 1748static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1749{
890ca9ae
HY		 1750 u64 mcg_cap = vcpu->arch.mcg_cap;
1751 unsigned bank_num = mcg_cap & 0xff;
1752
15c4a640 1753 switch (msr) {
15c4a640 1754 case MSR_IA32_MCG_STATUS:
890ca9ae 1755 vcpu->arch.mcg_status = data;
15c4a640 1756 break;
c7ac679c 1757 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1758 if (!(mcg_cap & MCG_CTL_P))
1759 return 1;
1760 if (data != 0 && data != ~(u64)0)
1761 return -1;
1762 vcpu->arch.mcg_ctl = data;
1763 break;
1764 default:
1765 if (msr >= MSR_IA32_MC0_CTL &&
1766 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1767 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1768 /* only 0 or all 1s can be written to IA32_MCi_CTL
1769 * some Linux kernels though clear bit 10 in bank 4 to
1770 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1771 * this to avoid an uncatched #GP in the guest
1772 */
890ca9ae 1773 if ((offset & 0x3) == 0 &&
114be429 1774 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1775 return -1;
1776 vcpu->arch.mce_banks[offset] = data;
1777 break;
1778 }
1779 return 1;
1780 }
1781 return 0;
1782}
1783
ffde22ac
ES		 1784static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1785{
1786 struct kvm *kvm = vcpu->kvm;
1787 int lm = is_long_mode(vcpu);
1788 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1789 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1790 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1791 : kvm->arch.xen_hvm_config.blob_size_32;
1792 u32 page_num = data & ~PAGE_MASK;
1793 u64 page_addr = data & PAGE_MASK;
1794 u8 *page;
1795 int r;
1796
1797 r = -E2BIG;
1798 if (page_num >= blob_size)
1799 goto out;
1800 r = -ENOMEM;
ff5c2c03
SL		 1801 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1802 if (IS_ERR(page)) {
1803 r = PTR_ERR(page);
ffde22ac 1804 goto out;
ff5c2c03 1805 }
ffde22ac
ES		 1806 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1807 goto out_free;
1808 r = 0;
1809out_free:
1810 kfree(page);
1811out:
1812 return r;
1813}
1814
55cd8e5a
GN		 1815static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1816{
1817 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1818}
1819
1820static bool kvm_hv_msr_partition_wide(u32 msr)
1821{
1822 bool r = false;
1823 switch (msr) {
1824 case HV_X64_MSR_GUEST_OS_ID:
1825 case HV_X64_MSR_HYPERCALL:
1826 r = true;
1827 break;
1828 }
1829
1830 return r;
1831}
1832
1833static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1834{
1835 struct kvm *kvm = vcpu->kvm;
1836
1837 switch (msr) {
1838 case HV_X64_MSR_GUEST_OS_ID:
1839 kvm->arch.hv_guest_os_id = data;
1840 /* setting guest os id to zero disables hypercall page */
1841 if (!kvm->arch.hv_guest_os_id)
1842 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1843 break;
1844 case HV_X64_MSR_HYPERCALL: {
1845 u64 gfn;
1846 unsigned long addr;
1847 u8 instructions[4];
1848
1849 /* if guest os id is not set hypercall should remain disabled */
1850 if (!kvm->arch.hv_guest_os_id)
1851 break;
1852 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1853 kvm->arch.hv_hypercall = data;
1854 break;
1855 }
1856 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1857 addr = gfn_to_hva(kvm, gfn);
1858 if (kvm_is_error_hva(addr))
1859 return 1;
1860 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1861 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1862 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1863 return 1;
1864 kvm->arch.hv_hypercall = data;
1865 break;
1866 }
1867 default:
a737f256
CD		 1868 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1869 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1870 return 1;
1871 }
1872 return 0;
1873}
1874
1875static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1876{
10388a07
GN		 1877 switch (msr) {
1878 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1879 unsigned long addr;
55cd8e5a 1880
10388a07
GN		 1881 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1882 vcpu->arch.hv_vapic = data;
1883 break;
1884 }
1885 addr = gfn_to_hva(vcpu->kvm, data >>
1886 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1887 if (kvm_is_error_hva(addr))
1888 return 1;
8b0cedff 1889 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1890 return 1;
1891 vcpu->arch.hv_vapic = data;
1892 break;
1893 }
1894 case HV_X64_MSR_EOI:
1895 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1896 case HV_X64_MSR_ICR:
1897 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1898 case HV_X64_MSR_TPR:
1899 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1900 default:
a737f256
CD		 1901 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1902 "data 0x%llx\n", msr, data);
10388a07
GN		 1903 return 1;
1904 }
1905
1906 return 0;
55cd8e5a
GN		 1907}
1908
344d9588
GN		 1909static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1910{
1911 gpa_t gpa = data & ~0x3f;
1912
4a969980 1913 /* Bits 2:5 are reserved, Should be zero */
6adba527 1914 if (data & 0x3c)
344d9588
GN		 1915 return 1;
1916
1917 vcpu->arch.apf.msr_val = data;
1918
1919 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1920 kvm_clear_async_pf_completion_queue(vcpu);
1921 kvm_async_pf_hash_reset(vcpu);
1922 return 0;
1923 }
1924
8f964525
AH		 1925 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1926 sizeof(u32)))
344d9588
GN		 1927 return 1;
1928
6adba527 1929 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1930 kvm_async_pf_wakeup_all(vcpu);
1931 return 0;
1932}
1933
12f9a48f
GC		 1934static void kvmclock_reset(struct kvm_vcpu *vcpu)
1935{
0b79459b 1936 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1937}
1938
c9aaa895
GC		 1939static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1940{
1941 u64 delta;
1942
1943 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1944 return;
1945
1946 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1947 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1948 vcpu->arch.st.accum_steal = delta;
1949}
1950
1951static void record_steal_time(struct kvm_vcpu *vcpu)
1952{
73c1d981
MT		 1953 accumulate_steal_time(vcpu);
1954
c9aaa895
GC		 1955 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1956 return;
1957
1958 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1959 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1960 return;
1961
1962 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1963 vcpu->arch.st.steal.version += 2;
1964 vcpu->arch.st.accum_steal = 0;
1965
1966 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1967 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1968}
1969
8fe8ab46 1970int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1971{
5753785f 1972 bool pr = false;
8fe8ab46
WA		 1973 u32 msr = msr_info->index;
1974 u64 data = msr_info->data;
5753785f 1975
15c4a640 1976 switch (msr) {
2e32b719
BP		 1977 case MSR_AMD64_NB_CFG:
1978 case MSR_IA32_UCODE_REV:
1979 case MSR_IA32_UCODE_WRITE:
1980 case MSR_VM_HSAVE_PA:
1981 case MSR_AMD64_PATCH_LOADER:
1982 case MSR_AMD64_BU_CFG2:
1983 break;
1984
15c4a640 1985 case MSR_EFER:
b69e8cae 1986 return set_efer(vcpu, data);
8f1589d9
AP		 1987 case MSR_K7_HWCR:
1988 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1989 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1990 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1991 if (data != 0) {
a737f256
CD		 1992 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1993 data);
8f1589d9
AP		 1994 return 1;
1995 }
15c4a640 1996 break;
f7c6d140
AP		 1997 case MSR_FAM10H_MMIO_CONF_BASE:
1998 if (data != 0) {
a737f256
CD		 1999 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2000 "0x%llx\n", data);
f7c6d140
AP		 2001 return 1;
2002 }
15c4a640 2003 break;
b5e2fec0
AG		 2004 case MSR_IA32_DEBUGCTLMSR:
2005 if (!data) {
2006 /* We support the non-activated case already */
2007 break;
2008 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2009 /* Values other than LBR and BTF are vendor-specific,
2010 thus reserved and should throw a #GP */
2011 return 1;
2012 }
a737f256
CD		 2013 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2014 __func__, data);
b5e2fec0 2015 break;
9ba075a6
AK		 2016 case 0x200 ... 0x2ff:
2017 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 2018 case MSR_IA32_APICBASE:
2019 kvm_set_apic_base(vcpu, data);
2020 break;
0105d1a5
GN		 2021 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2022 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2023 case MSR_IA32_TSCDEADLINE:
2024 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2025 break;
ba904635
WA		 2026 case MSR_IA32_TSC_ADJUST:
2027 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2028 if (!msr_info->host_initiated) {
2029 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2030 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2031 }
2032 vcpu->arch.ia32_tsc_adjust_msr = data;
2033 }
2034 break;
15c4a640 2035 case MSR_IA32_MISC_ENABLE:
ad312c7c 2036 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2037 break;
11c6bffa 2038 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2039 case MSR_KVM_WALL_CLOCK:
2040 vcpu->kvm->arch.wall_clock = data;
2041 kvm_write_wall_clock(vcpu->kvm, data);
2042 break;
11c6bffa 2043 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2044 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2045 u64 gpa_offset;
12f9a48f 2046 kvmclock_reset(vcpu);
18068523
GOC		 2047
2048 vcpu->arch.time = data;
c285545f 2049 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 2050
2051 /* we verify if the enable bit is set... */
2052 if (!(data & 1))
2053 break;
2054
0b79459b 2055 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2056
0b79459b 2057 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2058 &vcpu->arch.pv_time, data & ~1ULL,
2059 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2060 vcpu->arch.pv_time_enabled = false;
2061 else
2062 vcpu->arch.pv_time_enabled = true;
32cad84f 2063
18068523
GOC		 2064 break;
2065 }
344d9588
GN		 2066 case MSR_KVM_ASYNC_PF_EN:
2067 if (kvm_pv_enable_async_pf(vcpu, data))
2068 return 1;
2069 break;
c9aaa895
GC		 2070 case MSR_KVM_STEAL_TIME:
2071
2072 if (unlikely(!sched_info_on()))
2073 return 1;
2074
2075 if (data & KVM_STEAL_RESERVED_MASK)
2076 return 1;
2077
2078 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2079 data & KVM_STEAL_VALID_BITS,
2080 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2081 return 1;
2082
2083 vcpu->arch.st.msr_val = data;
2084
2085 if (!(data & KVM_MSR_ENABLED))
2086 break;
2087
c9aaa895
GC		 2088 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2089
2090 break;
ae7a2a3f
MT		 2091 case MSR_KVM_PV_EOI_EN:
2092 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2093 return 1;
2094 break;
c9aaa895 2095
890ca9ae
HY		 2096 case MSR_IA32_MCG_CTL:
2097 case MSR_IA32_MCG_STATUS:
2098 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2099 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2100
2101 /* Performance counters are not protected by a CPUID bit,
2102 * so we should check all of them in the generic path for the sake of
2103 * cross vendor migration.
2104 * Writing a zero into the event select MSRs disables them,
2105 * which we perfectly emulate ;-). Any other value should be at least
2106 * reported, some guests depend on them.
2107 */
71db6023
AP		 2108 case MSR_K7_EVNTSEL0:
2109 case MSR_K7_EVNTSEL1:
2110 case MSR_K7_EVNTSEL2:
2111 case MSR_K7_EVNTSEL3:
2112 if (data != 0)
a737f256
CD		 2113 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2114 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2115 break;
2116 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2117 * so we ignore writes to make it happy.
2118 */
71db6023
AP		 2119 case MSR_K7_PERFCTR0:
2120 case MSR_K7_PERFCTR1:
2121 case MSR_K7_PERFCTR2:
2122 case MSR_K7_PERFCTR3:
a737f256
CD		 2123 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2124 "0x%x data 0x%llx\n", msr, data);
71db6023 2125 break;
5753785f
GN		 2126 case MSR_P6_PERFCTR0:
2127 case MSR_P6_PERFCTR1:
2128 pr = true;
2129 case MSR_P6_EVNTSEL0:
2130 case MSR_P6_EVNTSEL1:
2131 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2132 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2133
2134 if (pr || data != 0)
a737f256
CD		 2135 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2136 "0x%x data 0x%llx\n", msr, data);
5753785f 2137 break;
84e0cefa
JS		 2138 case MSR_K7_CLK_CTL:
2139 /*
2140 * Ignore all writes to this no longer documented MSR.
2141 * Writes are only relevant for old K7 processors,
2142 * all pre-dating SVM, but a recommended workaround from
4a969980 2143 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2144 * affected processor models on the command line, hence
2145 * the need to ignore the workaround.
2146 */
2147 break;
55cd8e5a
GN		 2148 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2149 if (kvm_hv_msr_partition_wide(msr)) {
2150 int r;
2151 mutex_lock(&vcpu->kvm->lock);
2152 r = set_msr_hyperv_pw(vcpu, msr, data);
2153 mutex_unlock(&vcpu->kvm->lock);
2154 return r;
2155 } else
2156 return set_msr_hyperv(vcpu, msr, data);
2157 break;
91c9c3ed 2158 case MSR_IA32_BBL_CR_CTL3:
2159 /* Drop writes to this legacy MSR -- see rdmsr
2160 * counterpart for further detail.
2161 */
a737f256 2162 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2163 break;
2b036c6b
BO		 2164 case MSR_AMD64_OSVW_ID_LENGTH:
2165 if (!guest_cpuid_has_osvw(vcpu))
2166 return 1;
2167 vcpu->arch.osvw.length = data;
2168 break;
2169 case MSR_AMD64_OSVW_STATUS:
2170 if (!guest_cpuid_has_osvw(vcpu))
2171 return 1;
2172 vcpu->arch.osvw.status = data;
2173 break;
15c4a640 2174 default:
ffde22ac
ES		 2175 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2176 return xen_hvm_config(vcpu, data);
f5132b01 2177 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2178 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2179 if (!ignore_msrs) {
a737f256
CD		 2180 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2181 msr, data);
ed85c068
AP		 2182 return 1;
2183 } else {
a737f256
CD		 2184 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2185 msr, data);
ed85c068
AP		 2186 break;
2187 }
15c4a640
CO		 2188 }
2189 return 0;
2190}
2191EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2192
2193
2194/*
2195 * Reads an msr value (of 'msr_index') into 'pdata'.
2196 * Returns 0 on success, non-0 otherwise.
2197 * Assumes vcpu_load() was already called.
2198 */
2199int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2200{
2201 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2202}
2203
9ba075a6
AK		 2204static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2205{
0bed3b56
SY		 2206 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2207
9ba075a6
AK		 2208 if (!msr_mtrr_valid(msr))
2209 return 1;
2210
0bed3b56
SY		 2211 if (msr == MSR_MTRRdefType)
2212 *pdata = vcpu->arch.mtrr_state.def_type +
2213 (vcpu->arch.mtrr_state.enabled << 10);
2214 else if (msr == MSR_MTRRfix64K_00000)
2215 *pdata = p[0];
2216 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2217 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2218 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2219 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2220 else if (msr == MSR_IA32_CR_PAT)
2221 *pdata = vcpu->arch.pat;
2222 else { /* Variable MTRRs */
2223 int idx, is_mtrr_mask;
2224 u64 *pt;
2225
2226 idx = (msr - 0x200) / 2;
2227 is_mtrr_mask = msr - 0x200 - 2 * idx;
2228 if (!is_mtrr_mask)
2229 pt =
2230 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2231 else
2232 pt =
2233 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2234 *pdata = *pt;
2235 }
2236
9ba075a6
AK		 2237 return 0;
2238}
2239
890ca9ae 2240static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2241{
2242 u64 data;
890ca9ae
HY		 2243 u64 mcg_cap = vcpu->arch.mcg_cap;
2244 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2245
2246 switch (msr) {
15c4a640
CO		 2247 case MSR_IA32_P5_MC_ADDR:
2248 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2249 data = 0;
2250 break;
15c4a640 2251 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2252 data = vcpu->arch.mcg_cap;
2253 break;
c7ac679c 2254 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2255 if (!(mcg_cap & MCG_CTL_P))
2256 return 1;
2257 data = vcpu->arch.mcg_ctl;
2258 break;
2259 case MSR_IA32_MCG_STATUS:
2260 data = vcpu->arch.mcg_status;
2261 break;
2262 default:
2263 if (msr >= MSR_IA32_MC0_CTL &&
2264 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2265 u32 offset = msr - MSR_IA32_MC0_CTL;
2266 data = vcpu->arch.mce_banks[offset];
2267 break;
2268 }
2269 return 1;
2270 }
2271 *pdata = data;
2272 return 0;
2273}
2274
55cd8e5a
GN		 2275static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2276{
2277 u64 data = 0;
2278 struct kvm *kvm = vcpu->kvm;
2279
2280 switch (msr) {
2281 case HV_X64_MSR_GUEST_OS_ID:
2282 data = kvm->arch.hv_guest_os_id;
2283 break;
2284 case HV_X64_MSR_HYPERCALL:
2285 data = kvm->arch.hv_hypercall;
2286 break;
2287 default:
a737f256 2288 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2289 return 1;
2290 }
2291
2292 *pdata = data;
2293 return 0;
2294}
2295
2296static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2297{
2298 u64 data = 0;
2299
2300 switch (msr) {
2301 case HV_X64_MSR_VP_INDEX: {
2302 int r;
2303 struct kvm_vcpu *v;
2304 kvm_for_each_vcpu(r, v, vcpu->kvm)
2305 if (v == vcpu)
2306 data = r;
2307 break;
2308 }
10388a07
GN		 2309 case HV_X64_MSR_EOI:
2310 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2311 case HV_X64_MSR_ICR:
2312 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2313 case HV_X64_MSR_TPR:
2314 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2315 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2316 data = vcpu->arch.hv_vapic;
2317 break;
55cd8e5a 2318 default:
a737f256 2319 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2320 return 1;
2321 }
2322 *pdata = data;
2323 return 0;
2324}
2325
890ca9ae
HY		 2326int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2327{
2328 u64 data;
2329
2330 switch (msr) {
890ca9ae 2331 case MSR_IA32_PLATFORM_ID:
15c4a640 2332 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2333 case MSR_IA32_DEBUGCTLMSR:
2334 case MSR_IA32_LASTBRANCHFROMIP:
2335 case MSR_IA32_LASTBRANCHTOIP:
2336 case MSR_IA32_LASTINTFROMIP:
2337 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2338 case MSR_K8_SYSCFG:
2339 case MSR_K7_HWCR:
61a6bd67 2340 case MSR_VM_HSAVE_PA:
9e699624 2341 case MSR_K7_EVNTSEL0:
1f3ee616 2342 case MSR_K7_PERFCTR0:
1fdbd48c 2343 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2344 case MSR_AMD64_NB_CFG:
f7c6d140 2345 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2346 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2347 data = 0;
2348 break;
5753785f
GN		 2349 case MSR_P6_PERFCTR0:
2350 case MSR_P6_PERFCTR1:
2351 case MSR_P6_EVNTSEL0:
2352 case MSR_P6_EVNTSEL1:
2353 if (kvm_pmu_msr(vcpu, msr))
2354 return kvm_pmu_get_msr(vcpu, msr, pdata);
2355 data = 0;
2356 break;
742bc670
MT		 2357 case MSR_IA32_UCODE_REV:
2358 data = 0x100000000ULL;
2359 break;
9ba075a6
AK		 2360 case MSR_MTRRcap:
2361 data = 0x500 | KVM_NR_VAR_MTRR;
2362 break;
2363 case 0x200 ... 0x2ff:
2364 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2365 case 0xcd: /* fsb frequency */
2366 data = 3;
2367 break;
7b914098
JS		 2368 /*
2369 * MSR_EBC_FREQUENCY_ID
2370 * Conservative value valid for even the basic CPU models.
2371 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2372 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2373 * and 266MHz for model 3, or 4. Set Core Clock
2374 * Frequency to System Bus Frequency Ratio to 1 (bits
2375 * 31:24) even though these are only valid for CPU
2376 * models > 2, however guests may end up dividing or
2377 * multiplying by zero otherwise.
2378 */
2379 case MSR_EBC_FREQUENCY_ID:
2380 data = 1 << 24;
2381 break;
15c4a640
CO		 2382 case MSR_IA32_APICBASE:
2383 data = kvm_get_apic_base(vcpu);
2384 break;
0105d1a5
GN		 2385 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2386 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2387 break;
a3e06bbe
LJ		 2388 case MSR_IA32_TSCDEADLINE:
2389 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2390 break;
ba904635
WA		 2391 case MSR_IA32_TSC_ADJUST:
2392 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2393 break;
15c4a640 2394 case MSR_IA32_MISC_ENABLE:
ad312c7c 2395 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2396 break;
847f0ad8
AG		 2397 case MSR_IA32_PERF_STATUS:
2398 /* TSC increment by tick */
2399 data = 1000ULL;
2400 /* CPU multiplier */
2401 data |= (((uint64_t)4ULL) << 40);
2402 break;
15c4a640 2403 case MSR_EFER:
f6801dff 2404 data = vcpu->arch.efer;
15c4a640 2405 break;
18068523 2406 case MSR_KVM_WALL_CLOCK:
11c6bffa 2407 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2408 data = vcpu->kvm->arch.wall_clock;
2409 break;
2410 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2411 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2412 data = vcpu->arch.time;
2413 break;
344d9588
GN		 2414 case MSR_KVM_ASYNC_PF_EN:
2415 data = vcpu->arch.apf.msr_val;
2416 break;
c9aaa895
GC		 2417 case MSR_KVM_STEAL_TIME:
2418 data = vcpu->arch.st.msr_val;
2419 break;
1d92128f
MT		 2420 case MSR_KVM_PV_EOI_EN:
2421 data = vcpu->arch.pv_eoi.msr_val;
2422 break;
890ca9ae
HY		 2423 case MSR_IA32_P5_MC_ADDR:
2424 case MSR_IA32_P5_MC_TYPE:
2425 case MSR_IA32_MCG_CAP:
2426 case MSR_IA32_MCG_CTL:
2427 case MSR_IA32_MCG_STATUS:
2428 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2429 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2430 case MSR_K7_CLK_CTL:
2431 /*
2432 * Provide expected ramp-up count for K7. All other
2433 * are set to zero, indicating minimum divisors for
2434 * every field.
2435 *
2436 * This prevents guest kernels on AMD host with CPU
2437 * type 6, model 8 and higher from exploding due to
2438 * the rdmsr failing.
2439 */
2440 data = 0x20000000;
2441 break;
55cd8e5a
GN		 2442 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2443 if (kvm_hv_msr_partition_wide(msr)) {
2444 int r;
2445 mutex_lock(&vcpu->kvm->lock);
2446 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2447 mutex_unlock(&vcpu->kvm->lock);
2448 return r;
2449 } else
2450 return get_msr_hyperv(vcpu, msr, pdata);
2451 break;
91c9c3ed 2452 case MSR_IA32_BBL_CR_CTL3:
2453 /* This legacy MSR exists but isn't fully documented in current
2454 * silicon. It is however accessed by winxp in very narrow
2455 * scenarios where it sets bit #19, itself documented as
2456 * a "reserved" bit. Best effort attempt to source coherent
2457 * read data here should the balance of the register be
2458 * interpreted by the guest:
2459 *
2460 * L2 cache control register 3: 64GB range, 256KB size,
2461 * enabled, latency 0x1, configured
2462 */
2463 data = 0xbe702111;
2464 break;
2b036c6b
BO		 2465 case MSR_AMD64_OSVW_ID_LENGTH:
2466 if (!guest_cpuid_has_osvw(vcpu))
2467 return 1;
2468 data = vcpu->arch.osvw.length;
2469 break;
2470 case MSR_AMD64_OSVW_STATUS:
2471 if (!guest_cpuid_has_osvw(vcpu))
2472 return 1;
2473 data = vcpu->arch.osvw.status;
2474 break;
15c4a640 2475 default:
f5132b01
GN		 2476 if (kvm_pmu_msr(vcpu, msr))
2477 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2478 if (!ignore_msrs) {
a737f256 2479 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2480 return 1;
2481 } else {
a737f256 2482 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2483 data = 0;
2484 }
2485 break;
15c4a640
CO		 2486 }
2487 *pdata = data;
2488 return 0;
2489}
2490EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2491
313a3dc7
CO		 2492/*
2493 * Read or write a bunch of msrs. All parameters are kernel addresses.
2494 *
2495 * @return number of msrs set successfully.
2496 */
2497static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2498 struct kvm_msr_entry *entries,
2499 int (*do_msr)(struct kvm_vcpu *vcpu,
2500 unsigned index, u64 *data))
2501{
f656ce01 2502 int i, idx;
313a3dc7 2503
f656ce01 2504 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2505 for (i = 0; i < msrs->nmsrs; ++i)
2506 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2507 break;
f656ce01 2508 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2509
313a3dc7
CO		 2510 return i;
2511}
2512
2513/*
2514 * Read or write a bunch of msrs. Parameters are user addresses.
2515 *
2516 * @return number of msrs set successfully.
2517 */
2518static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2519 int (*do_msr)(struct kvm_vcpu *vcpu,
2520 unsigned index, u64 *data),
2521 int writeback)
2522{
2523 struct kvm_msrs msrs;
2524 struct kvm_msr_entry *entries;
2525 int r, n;
2526 unsigned size;
2527
2528 r = -EFAULT;
2529 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2530 goto out;
2531
2532 r = -E2BIG;
2533 if (msrs.nmsrs >= MAX_IO_MSRS)
2534 goto out;
2535
313a3dc7 2536 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2537 entries = memdup_user(user_msrs->entries, size);
2538 if (IS_ERR(entries)) {
2539 r = PTR_ERR(entries);
313a3dc7 2540 goto out;
ff5c2c03 2541 }
313a3dc7
CO		 2542
2543 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2544 if (r < 0)
2545 goto out_free;
2546
2547 r = -EFAULT;
2548 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2549 goto out_free;
2550
2551 r = n;
2552
2553out_free:
7a73c028 2554 kfree(entries);
313a3dc7
CO		 2555out:
2556 return r;
2557}
2558
018d00d2
ZX		 2559int kvm_dev_ioctl_check_extension(long ext)
2560{
2561 int r;
2562
2563 switch (ext) {
2564 case KVM_CAP_IRQCHIP:
2565 case KVM_CAP_HLT:
2566 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2567 case KVM_CAP_SET_TSS_ADDR:
07716717 2568 case KVM_CAP_EXT_CPUID:
c8076604 2569 case KVM_CAP_CLOCKSOURCE:
7837699f 2570 case KVM_CAP_PIT:
a28e4f5a 2571 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2572 case KVM_CAP_MP_STATE:
ed848624 2573 case KVM_CAP_SYNC_MMU:
a355c85c 2574 case KVM_CAP_USER_NMI:
52d939a0 2575 case KVM_CAP_REINJECT_CONTROL:
4925663a 2576 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2577 case KVM_CAP_IRQFD:
d34e6b17 2578 case KVM_CAP_IOEVENTFD:
c5ff41ce 2579 case KVM_CAP_PIT2:
e9f42757 2580 case KVM_CAP_PIT_STATE2:
b927a3ce 2581 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2582 case KVM_CAP_XEN_HVM:
afbcf7ab 2583 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2584 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2585 case KVM_CAP_HYPERV:
10388a07 2586 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2587 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2588 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2589 case KVM_CAP_DEBUGREGS:
d2be1651 2590 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2591 case KVM_CAP_XSAVE:
344d9588 2592 case KVM_CAP_ASYNC_PF:
92a1f12d 2593 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2594 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2595 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2596#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2597 case KVM_CAP_ASSIGN_DEV_IRQ:
2598 case KVM_CAP_PCI_2_3:
2599#endif
018d00d2
ZX		 2600 r = 1;
2601 break;
542472b5
LV		 2602 case KVM_CAP_COALESCED_MMIO:
2603 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2604 break;
774ead3a
AK		 2605 case KVM_CAP_VAPIC:
2606 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2607 break;
f725230a 2608 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2609 r = KVM_SOFT_MAX_VCPUS;
2610 break;
2611 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2612 r = KVM_MAX_VCPUS;
2613 break;
a988b910 2614 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2615 r = KVM_USER_MEM_SLOTS;
a988b910 2616 break;
a68a6a72
MT		 2617 case KVM_CAP_PV_MMU: /* obsolete */
2618 r = 0;
2f333bcb 2619 break;
4cee4b72 2620#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2621 case KVM_CAP_IOMMU:
a1b60c1c 2622 r = iommu_present(&pci_bus_type);
62c476c7 2623 break;
4cee4b72 2624#endif
890ca9ae
HY		 2625 case KVM_CAP_MCE:
2626 r = KVM_MAX_MCE_BANKS;
2627 break;
2d5b5a66
SY		 2628 case KVM_CAP_XCRS:
2629 r = cpu_has_xsave;
2630 break;
92a1f12d
JR		 2631 case KVM_CAP_TSC_CONTROL:
2632 r = kvm_has_tsc_control;
2633 break;
4d25a066
JK		 2634 case KVM_CAP_TSC_DEADLINE_TIMER:
2635 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2636 break;
018d00d2
ZX		 2637 default:
2638 r = 0;
2639 break;
2640 }
2641 return r;
2642
2643}
2644
043405e1
CO		 2645long kvm_arch_dev_ioctl(struct file *filp,
2646 unsigned int ioctl, unsigned long arg)
2647{
2648 void __user *argp = (void __user *)arg;
2649 long r;
2650
2651 switch (ioctl) {
2652 case KVM_GET_MSR_INDEX_LIST: {
2653 struct kvm_msr_list __user *user_msr_list = argp;
2654 struct kvm_msr_list msr_list;
2655 unsigned n;
2656
2657 r = -EFAULT;
2658 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2659 goto out;
2660 n = msr_list.nmsrs;
2661 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2662 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2663 goto out;
2664 r = -E2BIG;
e125e7b6 2665 if (n < msr_list.nmsrs)
043405e1
CO		 2666 goto out;
2667 r = -EFAULT;
2668 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2669 num_msrs_to_save * sizeof(u32)))
2670 goto out;
e125e7b6 2671 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2672 &emulated_msrs,
2673 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2674 goto out;
2675 r = 0;
2676 break;
2677 }
674eea0f
AK		 2678 case KVM_GET_SUPPORTED_CPUID: {
2679 struct kvm_cpuid2 __user *cpuid_arg = argp;
2680 struct kvm_cpuid2 cpuid;
2681
2682 r = -EFAULT;
2683 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2684 goto out;
2685 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2686 cpuid_arg->entries);
674eea0f
AK		 2687 if (r)
2688 goto out;
2689
2690 r = -EFAULT;
2691 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2692 goto out;
2693 r = 0;
2694 break;
2695 }
890ca9ae
HY		 2696 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2697 u64 mce_cap;
2698
2699 mce_cap = KVM_MCE_CAP_SUPPORTED;
2700 r = -EFAULT;
2701 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2702 goto out;
2703 r = 0;
2704 break;
2705 }
043405e1
CO		 2706 default:
2707 r = -EINVAL;
2708 }
2709out:
2710 return r;
2711}
2712
f5f48ee1
SY		 2713static void wbinvd_ipi(void *garbage)
2714{
2715 wbinvd();
2716}
2717
2718static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2719{
2720 return vcpu->kvm->arch.iommu_domain &&
2721 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2722}
2723
313a3dc7
CO		 2724void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2725{
f5f48ee1
SY		 2726 /* Address WBINVD may be executed by guest */
2727 if (need_emulate_wbinvd(vcpu)) {
2728 if (kvm_x86_ops->has_wbinvd_exit())
2729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2730 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2731 smp_call_function_single(vcpu->cpu,
2732 wbinvd_ipi, NULL, 1);
2733 }
2734
313a3dc7 2735 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2736
0dd6a6ed
ZA		 2737 /* Apply any externally detected TSC adjustments (due to suspend) */
2738 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2739 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2740 vcpu->arch.tsc_offset_adjustment = 0;
2741 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2742 }
8f6055cb 2743
48434c20 2744 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2745 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2746 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2747 if (tsc_delta < 0)
2748 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2749 if (check_tsc_unstable()) {
b183aa58
ZA		 2750 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2751 vcpu->arch.last_guest_tsc);
2752 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2753 vcpu->arch.tsc_catchup = 1;
c285545f 2754 }
d98d07ca
MT		 2755 /*
2756 * On a host with synchronized TSC, there is no need to update
2757 * kvmclock on vcpu->cpu migration
2758 */
2759 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2760 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2761 if (vcpu->cpu != cpu)
2762 kvm_migrate_timers(vcpu);
e48672fa 2763 vcpu->cpu = cpu;
6b7d7e76 2764 }
c9aaa895 2765
c9aaa895 2766 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2767}
2768
2769void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2770{
02daab21 2771 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2772 kvm_put_guest_fpu(vcpu);
6f526ec5 2773 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2774}
2775
313a3dc7
CO		 2776static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778{
5a71785d 2779 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2780 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2781
2782 return 0;
2783}
2784
2785static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2786 struct kvm_lapic_state *s)
2787{
64eb0620 2788 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2789 update_cr8_intercept(vcpu);
313a3dc7
CO		 2790
2791 return 0;
2792}
2793
f77bc6a4
ZX		 2794static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2795 struct kvm_interrupt *irq)
2796{
02cdb50f 2797 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2798 return -EINVAL;
2799 if (irqchip_in_kernel(vcpu->kvm))
2800 return -ENXIO;
f77bc6a4 2801
66fd3f7f 2802 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2803 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2804
f77bc6a4
ZX		 2805 return 0;
2806}
2807
c4abb7c9
JK		 2808static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2809{
c4abb7c9 2810 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2811
2812 return 0;
2813}
2814
b209749f
AK		 2815static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2816 struct kvm_tpr_access_ctl *tac)
2817{
2818 if (tac->flags)
2819 return -EINVAL;
2820 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2821 return 0;
2822}
2823
890ca9ae
HY		 2824static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2825 u64 mcg_cap)
2826{
2827 int r;
2828 unsigned bank_num = mcg_cap & 0xff, bank;
2829
2830 r = -EINVAL;
a9e38c3e 2831 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2832 goto out;
2833 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2834 goto out;
2835 r = 0;
2836 vcpu->arch.mcg_cap = mcg_cap;
2837 /* Init IA32_MCG_CTL to all 1s */
2838 if (mcg_cap & MCG_CTL_P)
2839 vcpu->arch.mcg_ctl = ~(u64)0;
2840 /* Init IA32_MCi_CTL to all 1s */
2841 for (bank = 0; bank < bank_num; bank++)
2842 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2843out:
2844 return r;
2845}
2846
2847static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2848 struct kvm_x86_mce *mce)
2849{
2850 u64 mcg_cap = vcpu->arch.mcg_cap;
2851 unsigned bank_num = mcg_cap & 0xff;
2852 u64 *banks = vcpu->arch.mce_banks;
2853
2854 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2855 return -EINVAL;
2856 /*
2857 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2858 * reporting is disabled
2859 */
2860 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2861 vcpu->arch.mcg_ctl != ~(u64)0)
2862 return 0;
2863 banks += 4 * mce->bank;
2864 /*
2865 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2866 * reporting is disabled for the bank
2867 */
2868 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2869 return 0;
2870 if (mce->status & MCI_STATUS_UC) {
2871 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2872 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2873 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2874 return 0;
2875 }
2876 if (banks[1] & MCI_STATUS_VAL)
2877 mce->status |= MCI_STATUS_OVER;
2878 banks[2] = mce->addr;
2879 banks[3] = mce->misc;
2880 vcpu->arch.mcg_status = mce->mcg_status;
2881 banks[1] = mce->status;
2882 kvm_queue_exception(vcpu, MC_VECTOR);
2883 } else if (!(banks[1] & MCI_STATUS_VAL)
2884 || !(banks[1] & MCI_STATUS_UC)) {
2885 if (banks[1] & MCI_STATUS_VAL)
2886 mce->status |= MCI_STATUS_OVER;
2887 banks[2] = mce->addr;
2888 banks[3] = mce->misc;
2889 banks[1] = mce->status;
2890 } else
2891 banks[1] |= MCI_STATUS_OVER;
2892 return 0;
2893}
2894
3cfc3092
JK		 2895static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2896 struct kvm_vcpu_events *events)
2897{
7460fb4a 2898 process_nmi(vcpu);
03b82a30
JK		 2899 events->exception.injected =
2900 vcpu->arch.exception.pending &&
2901 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2902 events->exception.nr = vcpu->arch.exception.nr;
2903 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2904 events->exception.pad = 0;
3cfc3092
JK		 2905 events->exception.error_code = vcpu->arch.exception.error_code;
2906
03b82a30
JK		 2907 events->interrupt.injected =
2908 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2909 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2910 events->interrupt.soft = 0;
48005f64
JK		 2911 events->interrupt.shadow =
2912 kvm_x86_ops->get_interrupt_shadow(vcpu,
2913 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2914
2915 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2916 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2917 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2918 events->nmi.pad = 0;
3cfc3092 2919
66450a21 2920 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2921
dab4b911 2922 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2923 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2924 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2925}
2926
2927static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2928 struct kvm_vcpu_events *events)
2929{
dab4b911 2930 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2931 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2932 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2933 return -EINVAL;
2934
7460fb4a 2935 process_nmi(vcpu);
3cfc3092
JK		 2936 vcpu->arch.exception.pending = events->exception.injected;
2937 vcpu->arch.exception.nr = events->exception.nr;
2938 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2939 vcpu->arch.exception.error_code = events->exception.error_code;
2940
2941 vcpu->arch.interrupt.pending = events->interrupt.injected;
2942 vcpu->arch.interrupt.nr = events->interrupt.nr;
2943 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2944 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2945 kvm_x86_ops->set_interrupt_shadow(vcpu,
2946 events->interrupt.shadow);
3cfc3092
JK		 2947
2948 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2949 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2950 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2951 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2952
66450a21
JK		 2953 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2954 kvm_vcpu_has_lapic(vcpu))
2955 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2956
3842d135
AK		 2957 kvm_make_request(KVM_REQ_EVENT, vcpu);
2958
3cfc3092
JK		 2959 return 0;
2960}
2961
a1efbe77
JK		 2962static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2963 struct kvm_debugregs *dbgregs)
2964{
a1efbe77
JK		 2965 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2966 dbgregs->dr6 = vcpu->arch.dr6;
2967 dbgregs->dr7 = vcpu->arch.dr7;
2968 dbgregs->flags = 0;
97e69aa6 2969 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2970}
2971
2972static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2973 struct kvm_debugregs *dbgregs)
2974{
2975 if (dbgregs->flags)
2976 return -EINVAL;
2977
42bc57b6
PB		 2978 if (dbgregs->dr6 & ~0xffffffffull)
2979 return -EINVAL;
2980 if (dbgregs->dr7 & ~0xffffffffull)
2981 return -EINVAL;
2982
a1efbe77
JK		 2983 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2984 vcpu->arch.dr6 = dbgregs->dr6;
2985 vcpu->arch.dr7 = dbgregs->dr7;
2986
a1efbe77
JK		 2987 return 0;
2988}
2989
2d5b5a66
SY		 2990static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2991 struct kvm_xsave *guest_xsave)
2992{
2993 if (cpu_has_xsave)
2994 memcpy(guest_xsave->region,
2995 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2996 xstate_size);
2d5b5a66
SY		 2997 else {
2998 memcpy(guest_xsave->region,
2999 &vcpu->arch.guest_fpu.state->fxsave,
3000 sizeof(struct i387_fxsave_struct));
3001 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3002 XSTATE_FPSSE;
3003 }
3004}
3005
3006static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3007 struct kvm_xsave *guest_xsave)
3008{
3009 u64 xstate_bv =
3010 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3011
3012 if (cpu_has_xsave)
3013 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 3014 guest_xsave->region, xstate_size);
2d5b5a66
SY		 3015 else {
3016 if (xstate_bv & ~XSTATE_FPSSE)
3017 return -EINVAL;
3018 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3019 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3020 }
3021 return 0;
3022}
3023
3024static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3025 struct kvm_xcrs *guest_xcrs)
3026{
3027 if (!cpu_has_xsave) {
3028 guest_xcrs->nr_xcrs = 0;
3029 return;
3030 }
3031
3032 guest_xcrs->nr_xcrs = 1;
3033 guest_xcrs->flags = 0;
3034 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3035 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3036}
3037
3038static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3039 struct kvm_xcrs *guest_xcrs)
3040{
3041 int i, r = 0;
3042
3043 if (!cpu_has_xsave)
3044 return -EINVAL;
3045
3046 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3047 return -EINVAL;
3048
3049 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3050 /* Only support XCR0 currently */
3051 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3052 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3053 guest_xcrs->xcrs[0].value);
3054 break;
3055 }
3056 if (r)
3057 r = -EINVAL;
3058 return r;
3059}
3060
1c0b28c2
EM		 3061/*
3062 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3063 * stopped by the hypervisor. This function will be called from the host only.
3064 * EINVAL is returned when the host attempts to set the flag for a guest that
3065 * does not support pv clocks.
3066 */
3067static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3068{
0b79459b 3069 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3070 return -EINVAL;
51d59c6b 3071 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3072 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3073 return 0;
3074}
3075
313a3dc7
CO		 3076long kvm_arch_vcpu_ioctl(struct file *filp,
3077 unsigned int ioctl, unsigned long arg)
3078{
3079 struct kvm_vcpu *vcpu = filp->private_data;
3080 void __user *argp = (void __user *)arg;
3081 int r;
d1ac91d8
AK		 3082 union {
3083 struct kvm_lapic_state *lapic;
3084 struct kvm_xsave *xsave;
3085 struct kvm_xcrs *xcrs;
3086 void *buffer;
3087 } u;
3088
3089 u.buffer = NULL;
313a3dc7
CO		 3090 switch (ioctl) {
3091 case KVM_GET_LAPIC: {
2204ae3c
MT		 3092 r = -EINVAL;
3093 if (!vcpu->arch.apic)
3094 goto out;
d1ac91d8 3095 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3096
b772ff36 3097 r = -ENOMEM;
d1ac91d8 3098 if (!u.lapic)
b772ff36 3099 goto out;
d1ac91d8 3100 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3101 if (r)
3102 goto out;
3103 r = -EFAULT;
d1ac91d8 3104 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3105 goto out;
3106 r = 0;
3107 break;
3108 }
3109 case KVM_SET_LAPIC: {
2204ae3c
MT		 3110 r = -EINVAL;
3111 if (!vcpu->arch.apic)
3112 goto out;
ff5c2c03 3113 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3114 if (IS_ERR(u.lapic))
3115 return PTR_ERR(u.lapic);
ff5c2c03 3116
d1ac91d8 3117 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3118 break;
3119 }
f77bc6a4
ZX		 3120 case KVM_INTERRUPT: {
3121 struct kvm_interrupt irq;
3122
3123 r = -EFAULT;
3124 if (copy_from_user(&irq, argp, sizeof irq))
3125 goto out;
3126 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3127 break;
3128 }
c4abb7c9
JK		 3129 case KVM_NMI: {
3130 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3131 break;
3132 }
313a3dc7
CO		 3133 case KVM_SET_CPUID: {
3134 struct kvm_cpuid __user *cpuid_arg = argp;
3135 struct kvm_cpuid cpuid;
3136
3137 r = -EFAULT;
3138 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3139 goto out;
3140 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3141 break;
3142 }
07716717
DK		 3143 case KVM_SET_CPUID2: {
3144 struct kvm_cpuid2 __user *cpuid_arg = argp;
3145 struct kvm_cpuid2 cpuid;
3146
3147 r = -EFAULT;
3148 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3149 goto out;
3150 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3151 cpuid_arg->entries);
07716717
DK		 3152 break;
3153 }
3154 case KVM_GET_CPUID2: {
3155 struct kvm_cpuid2 __user *cpuid_arg = argp;
3156 struct kvm_cpuid2 cpuid;
3157
3158 r = -EFAULT;
3159 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3160 goto out;
3161 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3162 cpuid_arg->entries);
07716717
DK		 3163 if (r)
3164 goto out;
3165 r = -EFAULT;
3166 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3167 goto out;
3168 r = 0;
3169 break;
3170 }
313a3dc7
CO		 3171 case KVM_GET_MSRS:
3172 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3173 break;
3174 case KVM_SET_MSRS:
3175 r = msr_io(vcpu, argp, do_set_msr, 0);
3176 break;
b209749f
AK		 3177 case KVM_TPR_ACCESS_REPORTING: {
3178 struct kvm_tpr_access_ctl tac;
3179
3180 r = -EFAULT;
3181 if (copy_from_user(&tac, argp, sizeof tac))
3182 goto out;
3183 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3184 if (r)
3185 goto out;
3186 r = -EFAULT;
3187 if (copy_to_user(argp, &tac, sizeof tac))
3188 goto out;
3189 r = 0;
3190 break;
3191 };
b93463aa
AK		 3192 case KVM_SET_VAPIC_ADDR: {
3193 struct kvm_vapic_addr va;
014db7f6 3194 int idx;
b93463aa
AK		 3195
3196 r = -EINVAL;
3197 if (!irqchip_in_kernel(vcpu->kvm))
3198 goto out;
3199 r = -EFAULT;
3200 if (copy_from_user(&va, argp, sizeof va))
3201 goto out;
014db7f6 3202 idx = srcu_read_lock(&vcpu->kvm->srcu);
0e03b79f 3203 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
014db7f6 3204 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3205 break;
3206 }
890ca9ae
HY		 3207 case KVM_X86_SETUP_MCE: {
3208 u64 mcg_cap;
3209
3210 r = -EFAULT;
3211 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3212 goto out;
3213 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3214 break;
3215 }
3216 case KVM_X86_SET_MCE: {
3217 struct kvm_x86_mce mce;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&mce, argp, sizeof mce))
3221 goto out;
3222 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3223 break;
3224 }
3cfc3092
JK		 3225 case KVM_GET_VCPU_EVENTS: {
3226 struct kvm_vcpu_events events;
3227
3228 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3229
3230 r = -EFAULT;
3231 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3232 break;
3233 r = 0;
3234 break;
3235 }
3236 case KVM_SET_VCPU_EVENTS: {
3237 struct kvm_vcpu_events events;
3238
3239 r = -EFAULT;
3240 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3241 break;
3242
3243 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3244 break;
3245 }
a1efbe77
JK		 3246 case KVM_GET_DEBUGREGS: {
3247 struct kvm_debugregs dbgregs;
3248
3249 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3250
3251 r = -EFAULT;
3252 if (copy_to_user(argp, &dbgregs,
3253 sizeof(struct kvm_debugregs)))
3254 break;
3255 r = 0;
3256 break;
3257 }
3258 case KVM_SET_DEBUGREGS: {
3259 struct kvm_debugregs dbgregs;
3260
3261 r = -EFAULT;
3262 if (copy_from_user(&dbgregs, argp,
3263 sizeof(struct kvm_debugregs)))
3264 break;
3265
3266 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3267 break;
3268 }
2d5b5a66 3269 case KVM_GET_XSAVE: {
d1ac91d8 3270 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3271 r = -ENOMEM;
d1ac91d8 3272 if (!u.xsave)
2d5b5a66
SY		 3273 break;
3274
d1ac91d8 3275 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3276
3277 r = -EFAULT;
d1ac91d8 3278 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3279 break;
3280 r = 0;
3281 break;
3282 }
3283 case KVM_SET_XSAVE: {
ff5c2c03 3284 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3285 if (IS_ERR(u.xsave))
3286 return PTR_ERR(u.xsave);
2d5b5a66 3287
d1ac91d8 3288 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3289 break;
3290 }
3291 case KVM_GET_XCRS: {
d1ac91d8 3292 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3293 r = -ENOMEM;
d1ac91d8 3294 if (!u.xcrs)
2d5b5a66
SY		 3295 break;
3296
d1ac91d8 3297 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3298
3299 r = -EFAULT;
d1ac91d8 3300 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3301 sizeof(struct kvm_xcrs)))
3302 break;
3303 r = 0;
3304 break;
3305 }
3306 case KVM_SET_XCRS: {
ff5c2c03 3307 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3308 if (IS_ERR(u.xcrs))
3309 return PTR_ERR(u.xcrs);
2d5b5a66 3310
d1ac91d8 3311 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3312 break;
3313 }
92a1f12d
JR		 3314 case KVM_SET_TSC_KHZ: {
3315 u32 user_tsc_khz;
3316
3317 r = -EINVAL;
92a1f12d
JR		 3318 user_tsc_khz = (u32)arg;
3319
3320 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3321 goto out;
3322
cc578287
ZA		 3323 if (user_tsc_khz == 0)
3324 user_tsc_khz = tsc_khz;
3325
3326 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3327
3328 r = 0;
3329 goto out;
3330 }
3331 case KVM_GET_TSC_KHZ: {
cc578287 3332 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3333 goto out;
3334 }
1c0b28c2
EM		 3335 case KVM_KVMCLOCK_CTRL: {
3336 r = kvm_set_guest_paused(vcpu);
3337 goto out;
3338 }
313a3dc7
CO		 3339 default:
3340 r = -EINVAL;
3341 }
3342out:
d1ac91d8 3343 kfree(u.buffer);
313a3dc7
CO		 3344 return r;
3345}
3346
5b1c1493
CO		 3347int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3348{
3349 return VM_FAULT_SIGBUS;
3350}
3351
1fe779f8
CO		 3352static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3353{
3354 int ret;
3355
3356 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3357 return -EINVAL;
1fe779f8
CO		 3358 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3359 return ret;
3360}
3361
b927a3ce
SY		 3362static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3363 u64 ident_addr)
3364{
3365 kvm->arch.ept_identity_map_addr = ident_addr;
3366 return 0;
3367}
3368
1fe779f8
CO		 3369static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3370 u32 kvm_nr_mmu_pages)
3371{
3372 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3373 return -EINVAL;
3374
79fac95e 3375 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3376
3377 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3378 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3379
79fac95e 3380 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3381 return 0;
3382}
3383
3384static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3385{
39de71ec 3386 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3387}
3388
1fe779f8
CO		 3389static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3390{
3391 int r;
3392
3393 r = 0;
3394 switch (chip->chip_id) {
3395 case KVM_IRQCHIP_PIC_MASTER:
3396 memcpy(&chip->chip.pic,
3397 &pic_irqchip(kvm)->pics[0],
3398 sizeof(struct kvm_pic_state));
3399 break;
3400 case KVM_IRQCHIP_PIC_SLAVE:
3401 memcpy(&chip->chip.pic,
3402 &pic_irqchip(kvm)->pics[1],
3403 sizeof(struct kvm_pic_state));
3404 break;
3405 case KVM_IRQCHIP_IOAPIC:
eba0226b 3406 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3407 break;
3408 default:
3409 r = -EINVAL;
3410 break;
3411 }
3412 return r;
3413}
3414
3415static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3416{
3417 int r;
3418
3419 r = 0;
3420 switch (chip->chip_id) {
3421 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3422 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3423 memcpy(&pic_irqchip(kvm)->pics[0],
3424 &chip->chip.pic,
3425 sizeof(struct kvm_pic_state));
f4f51050 3426 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3427 break;
3428 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3429 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3430 memcpy(&pic_irqchip(kvm)->pics[1],
3431 &chip->chip.pic,
3432 sizeof(struct kvm_pic_state));
f4f51050 3433 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3434 break;
3435 case KVM_IRQCHIP_IOAPIC:
eba0226b 3436 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3437 break;
3438 default:
3439 r = -EINVAL;
3440 break;
3441 }
3442 kvm_pic_update_irq(pic_irqchip(kvm));
3443 return r;
3444}
3445
e0f63cb9
SY		 3446static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3447{
3448 int r = 0;
3449
894a9c55 3450 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3451 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3452 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3453 return r;
3454}
3455
3456static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3457{
3458 int r = 0;
3459
894a9c55 3460 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3461 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3462 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3463 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3464 return r;
3465}
3466
3467static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3468{
3469 int r = 0;
3470
3471 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3472 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3473 sizeof(ps->channels));
3474 ps->flags = kvm->arch.vpit->pit_state.flags;
3475 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3476 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3477 return r;
3478}
3479
3480static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3481{
3482 int r = 0, start = 0;
3483 u32 prev_legacy, cur_legacy;
3484 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3485 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3486 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3487 if (!prev_legacy && cur_legacy)
3488 start = 1;
3489 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3490 sizeof(kvm->arch.vpit->pit_state.channels));
3491 kvm->arch.vpit->pit_state.flags = ps->flags;
3492 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3493 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3494 return r;
3495}
3496
52d939a0
MT		 3497static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3498 struct kvm_reinject_control *control)
3499{
3500 if (!kvm->arch.vpit)
3501 return -ENXIO;
894a9c55 3502 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3503 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3504 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3505 return 0;
3506}
3507
95d4c16c 3508/**
60c34612
TY		 3509 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3510 * @kvm: kvm instance
3511 * @log: slot id and address to which we copy the log
95d4c16c 3512 *
60c34612
TY		 3513 * We need to keep it in mind that VCPU threads can write to the bitmap
3514 * concurrently. So, to avoid losing data, we keep the following order for
3515 * each bit:
95d4c16c 3516 *
60c34612
TY		 3517 * 1. Take a snapshot of the bit and clear it if needed.
3518 * 2. Write protect the corresponding page.
3519 * 3. Flush TLB's if needed.
3520 * 4. Copy the snapshot to the userspace.
95d4c16c 3521 *
60c34612
TY		 3522 * Between 2 and 3, the guest may write to the page using the remaining TLB
3523 * entry. This is not a problem because the page will be reported dirty at
3524 * step 4 using the snapshot taken before and step 3 ensures that successive
3525 * writes will be logged for the next call.
5bb064dc 3526 */
60c34612 3527int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3528{
7850ac54 3529 int r;
5bb064dc 3530 struct kvm_memory_slot *memslot;
60c34612
TY		 3531 unsigned long n, i;
3532 unsigned long *dirty_bitmap;
3533 unsigned long *dirty_bitmap_buffer;
3534 bool is_dirty = false;
5bb064dc 3535
79fac95e 3536 mutex_lock(&kvm->slots_lock);
5bb064dc 3537
b050b015 3538 r = -EINVAL;
bbacc0c1 3539 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3540 goto out;
3541
28a37544 3542 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3543
3544 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3545 r = -ENOENT;
60c34612 3546 if (!dirty_bitmap)
b050b015
MT		 3547 goto out;
3548
87bf6e7d 3549 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3550
60c34612
TY		 3551 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3552 memset(dirty_bitmap_buffer, 0, n);
b050b015 3553
60c34612 3554 spin_lock(&kvm->mmu_lock);
b050b015 3555
60c34612
TY		 3556 for (i = 0; i < n / sizeof(long); i++) {
3557 unsigned long mask;
3558 gfn_t offset;
cdfca7b3 3559
60c34612
TY		 3560 if (!dirty_bitmap[i])
3561 continue;
b050b015 3562
60c34612 3563 is_dirty = true;
914ebccd 3564
60c34612
TY		 3565 mask = xchg(&dirty_bitmap[i], 0);
3566 dirty_bitmap_buffer[i] = mask;
edde99ce 3567
60c34612
TY		 3568 offset = i * BITS_PER_LONG;
3569 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3570 }
60c34612
TY		 3571 if (is_dirty)
3572 kvm_flush_remote_tlbs(kvm);
3573
3574 spin_unlock(&kvm->mmu_lock);
3575
3576 r = -EFAULT;
3577 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3578 goto out;
b050b015 3579
5bb064dc
ZX		 3580 r = 0;
3581out:
79fac95e 3582 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3583 return r;
3584}
3585
aa2fbe6d
YZ		 3586int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3587 bool line_status)
23d43cf9
CD		 3588{
3589 if (!irqchip_in_kernel(kvm))
3590 return -ENXIO;
3591
3592 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3593 irq_event->irq, irq_event->level,
3594 line_status);
23d43cf9
CD		 3595 return 0;
3596}
3597
1fe779f8
CO		 3598long kvm_arch_vm_ioctl(struct file *filp,
3599 unsigned int ioctl, unsigned long arg)
3600{
3601 struct kvm *kvm = filp->private_data;
3602 void __user *argp = (void __user *)arg;
367e1319 3603 int r = -ENOTTY;
f0d66275
DH		 3604 /*
3605 * This union makes it completely explicit to gcc-3.x
3606 * that these two variables' stack usage should be
3607 * combined, not added together.
3608 */
3609 union {
3610 struct kvm_pit_state ps;
e9f42757 3611 struct kvm_pit_state2 ps2;
c5ff41ce 3612 struct kvm_pit_config pit_config;
f0d66275 3613 } u;
1fe779f8
CO		 3614
3615 switch (ioctl) {
3616 case KVM_SET_TSS_ADDR:
3617 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3618 break;
b927a3ce
SY		 3619 case KVM_SET_IDENTITY_MAP_ADDR: {
3620 u64 ident_addr;
3621
3622 r = -EFAULT;
3623 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3624 goto out;
3625 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3626 break;
3627 }
1fe779f8
CO		 3628 case KVM_SET_NR_MMU_PAGES:
3629 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3630 break;
3631 case KVM_GET_NR_MMU_PAGES:
3632 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3633 break;
3ddea128
MT		 3634 case KVM_CREATE_IRQCHIP: {
3635 struct kvm_pic *vpic;
3636
3637 mutex_lock(&kvm->lock);
3638 r = -EEXIST;
3639 if (kvm->arch.vpic)
3640 goto create_irqchip_unlock;
3e515705
AK		 3641 r = -EINVAL;
3642 if (atomic_read(&kvm->online_vcpus))
3643 goto create_irqchip_unlock;
1fe779f8 3644 r = -ENOMEM;
3ddea128
MT		 3645 vpic = kvm_create_pic(kvm);
3646 if (vpic) {
1fe779f8
CO		 3647 r = kvm_ioapic_init(kvm);
3648 if (r) {
175504cd 3649 mutex_lock(&kvm->slots_lock);
72bb2fcd 3650 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3651 &vpic->dev_master);
3652 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3653 &vpic->dev_slave);
3654 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3655 &vpic->dev_eclr);
175504cd 3656 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3657 kfree(vpic);
3658 goto create_irqchip_unlock;
1fe779f8
CO		 3659 }
3660 } else
3ddea128
MT		 3661 goto create_irqchip_unlock;
3662 smp_wmb();
3663 kvm->arch.vpic = vpic;
3664 smp_wmb();
399ec807
AK		 3665 r = kvm_setup_default_irq_routing(kvm);
3666 if (r) {
175504cd 3667 mutex_lock(&kvm->slots_lock);
3ddea128 3668 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3669 kvm_ioapic_destroy(kvm);
3670 kvm_destroy_pic(kvm);
3ddea128 3671 mutex_unlock(&kvm->irq_lock);
175504cd 3672 mutex_unlock(&kvm->slots_lock);
399ec807 3673 }
3ddea128
MT		 3674 create_irqchip_unlock:
3675 mutex_unlock(&kvm->lock);
1fe779f8 3676 break;
3ddea128 3677 }
7837699f 3678 case KVM_CREATE_PIT:
c5ff41ce
JK		 3679 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3680 goto create_pit;
3681 case KVM_CREATE_PIT2:
3682 r = -EFAULT;
3683 if (copy_from_user(&u.pit_config, argp,
3684 sizeof(struct kvm_pit_config)))
3685 goto out;
3686 create_pit:
79fac95e 3687 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3688 r = -EEXIST;
3689 if (kvm->arch.vpit)
3690 goto create_pit_unlock;
7837699f 3691 r = -ENOMEM;
c5ff41ce 3692 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3693 if (kvm->arch.vpit)
3694 r = 0;
269e05e4 3695 create_pit_unlock:
79fac95e 3696 mutex_unlock(&kvm->slots_lock);
7837699f 3697 break;
1fe779f8
CO		 3698 case KVM_GET_IRQCHIP: {
3699 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3700 struct kvm_irqchip *chip;
1fe779f8 3701
ff5c2c03
SL		 3702 chip = memdup_user(argp, sizeof(*chip));
3703 if (IS_ERR(chip)) {
3704 r = PTR_ERR(chip);
1fe779f8 3705 goto out;
ff5c2c03
SL		 3706 }
3707
1fe779f8
CO		 3708 r = -ENXIO;
3709 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3710 goto get_irqchip_out;
3711 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3712 if (r)
f0d66275 3713 goto get_irqchip_out;
1fe779f8 3714 r = -EFAULT;
f0d66275
DH		 3715 if (copy_to_user(argp, chip, sizeof *chip))
3716 goto get_irqchip_out;
1fe779f8 3717 r = 0;
f0d66275
DH		 3718 get_irqchip_out:
3719 kfree(chip);
1fe779f8
CO		 3720 break;
3721 }
3722 case KVM_SET_IRQCHIP: {
3723 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3724 struct kvm_irqchip *chip;
1fe779f8 3725
ff5c2c03
SL		 3726 chip = memdup_user(argp, sizeof(*chip));
3727 if (IS_ERR(chip)) {
3728 r = PTR_ERR(chip);
1fe779f8 3729 goto out;
ff5c2c03
SL		 3730 }
3731
1fe779f8
CO		 3732 r = -ENXIO;
3733 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3734 goto set_irqchip_out;
3735 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3736 if (r)
f0d66275 3737 goto set_irqchip_out;
1fe779f8 3738 r = 0;
f0d66275
DH		 3739 set_irqchip_out:
3740 kfree(chip);
1fe779f8
CO		 3741 break;
3742 }
e0f63cb9 3743 case KVM_GET_PIT: {
e0f63cb9 3744 r = -EFAULT;
f0d66275 3745 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3746 goto out;
3747 r = -ENXIO;
3748 if (!kvm->arch.vpit)
3749 goto out;
f0d66275 3750 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3751 if (r)
3752 goto out;
3753 r = -EFAULT;
f0d66275 3754 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3755 goto out;
3756 r = 0;
3757 break;
3758 }
3759 case KVM_SET_PIT: {
e0f63cb9 3760 r = -EFAULT;
f0d66275 3761 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3762 goto out;
3763 r = -ENXIO;
3764 if (!kvm->arch.vpit)
3765 goto out;
f0d66275 3766 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3767 break;
3768 }
e9f42757
BK		 3769 case KVM_GET_PIT2: {
3770 r = -ENXIO;
3771 if (!kvm->arch.vpit)
3772 goto out;
3773 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3774 if (r)
3775 goto out;
3776 r = -EFAULT;
3777 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3778 goto out;
3779 r = 0;
3780 break;
3781 }
3782 case KVM_SET_PIT2: {
3783 r = -EFAULT;
3784 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3785 goto out;
3786 r = -ENXIO;
3787 if (!kvm->arch.vpit)
3788 goto out;
3789 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3790 break;
3791 }
52d939a0
MT		 3792 case KVM_REINJECT_CONTROL: {
3793 struct kvm_reinject_control control;
3794 r = -EFAULT;
3795 if (copy_from_user(&control, argp, sizeof(control)))
3796 goto out;
3797 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3798 break;
3799 }
ffde22ac
ES		 3800 case KVM_XEN_HVM_CONFIG: {
3801 r = -EFAULT;
3802 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3803 sizeof(struct kvm_xen_hvm_config)))
3804 goto out;
3805 r = -EINVAL;
3806 if (kvm->arch.xen_hvm_config.flags)
3807 goto out;
3808 r = 0;
3809 break;
3810 }
afbcf7ab 3811 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3812 struct kvm_clock_data user_ns;
3813 u64 now_ns;
3814 s64 delta;
3815
3816 r = -EFAULT;
3817 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3818 goto out;
3819
3820 r = -EINVAL;
3821 if (user_ns.flags)
3822 goto out;
3823
3824 r = 0;
395c6b0a 3825 local_irq_disable();
759379dd 3826 now_ns = get_kernel_ns();
afbcf7ab 3827 delta = user_ns.clock - now_ns;
395c6b0a 3828 local_irq_enable();
afbcf7ab
GC		 3829 kvm->arch.kvmclock_offset = delta;
3830 break;
3831 }
3832 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3833 struct kvm_clock_data user_ns;
3834 u64 now_ns;
3835
395c6b0a 3836 local_irq_disable();
759379dd 3837 now_ns = get_kernel_ns();
afbcf7ab 3838 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3839 local_irq_enable();
afbcf7ab 3840 user_ns.flags = 0;
97e69aa6 3841 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3842
3843 r = -EFAULT;
3844 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3845 goto out;
3846 r = 0;
3847 break;
3848 }
3849
1fe779f8
CO		 3850 default:
3851 ;
3852 }
3853out:
3854 return r;
3855}
3856
a16b043c 3857static void kvm_init_msr_list(void)
043405e1
CO		 3858{
3859 u32 dummy[2];
3860 unsigned i, j;
3861
e3267cbb
GC		 3862 /* skip the first msrs in the list. KVM-specific */
3863 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3864 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3865 continue;
3866 if (j < i)
3867 msrs_to_save[j] = msrs_to_save[i];
3868 j++;
3869 }
3870 num_msrs_to_save = j;
3871}
3872
bda9020e
MT		 3873static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3874 const void *v)
bbd9b64e 3875{
70252a10
AK		 3876 int handled = 0;
3877 int n;
3878
3879 do {
3880 n = min(len, 8);
3881 if (!(vcpu->arch.apic &&
3882 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3883 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3884 break;
3885 handled += n;
3886 addr += n;
3887 len -= n;
3888 v += n;
3889 } while (len);
bbd9b64e 3890
70252a10 3891 return handled;
bbd9b64e
CO		 3892}
3893
bda9020e 3894static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3895{
70252a10
AK		 3896 int handled = 0;
3897 int n;
3898
3899 do {
3900 n = min(len, 8);
3901 if (!(vcpu->arch.apic &&
3902 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3903 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3904 break;
3905 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3906 handled += n;
3907 addr += n;
3908 len -= n;
3909 v += n;
3910 } while (len);
bbd9b64e 3911
70252a10 3912 return handled;
bbd9b64e
CO		 3913}
3914
2dafc6c2
GN		 3915static void kvm_set_segment(struct kvm_vcpu *vcpu,
3916 struct kvm_segment *var, int seg)
3917{
3918 kvm_x86_ops->set_segment(vcpu, var, seg);
3919}
3920
3921void kvm_get_segment(struct kvm_vcpu *vcpu,
3922 struct kvm_segment *var, int seg)
3923{
3924 kvm_x86_ops->get_segment(vcpu, var, seg);
3925}
3926
e459e322 3927gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3928{
3929 gpa_t t_gpa;
ab9ae313 3930 struct x86_exception exception;
02f59dc9
JR		 3931
3932 BUG_ON(!mmu_is_nested(vcpu));
3933
3934 /* NPT walks are always user-walks */
3935 access |= PFERR_USER_MASK;
ab9ae313 3936 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3937
3938 return t_gpa;
3939}
3940
ab9ae313
AK		 3941gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3942 struct x86_exception *exception)
1871c602
GN		 3943{
3944 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3945 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3946}
3947
ab9ae313
AK		 3948 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3949 struct x86_exception *exception)
1871c602
GN		 3950{
3951 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3952 access |= PFERR_FETCH_MASK;
ab9ae313 3953 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3954}
3955
ab9ae313
AK		 3956gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3957 struct x86_exception *exception)
1871c602
GN		 3958{
3959 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3960 access |= PFERR_WRITE_MASK;
ab9ae313 3961 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3962}
3963
3964/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3965gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3966 struct x86_exception *exception)
1871c602 3967{
ab9ae313 3968 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3969}
3970
3971static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3972 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3973 struct x86_exception *exception)
bbd9b64e
CO		 3974{
3975 void *data = val;
10589a46 3976 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3977
3978 while (bytes) {
14dfe855 3979 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3980 exception);
bbd9b64e 3981 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3982 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3983 int ret;
3984
bcc55cba 3985 if (gpa == UNMAPPED_GVA)
ab9ae313 3986 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3987 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3988 if (ret < 0) {
c3cd7ffa 3989 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3990 goto out;
3991 }
bbd9b64e 3992
77c2002e
IE		 3993 bytes -= toread;
3994 data += toread;
3995 addr += toread;
bbd9b64e 3996 }
10589a46 3997out:
10589a46 3998 return r;
bbd9b64e 3999}
77c2002e 4000
1871c602 4001/* used for instruction fetching */
0f65dd70
AK		 4002static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4003 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4004 struct x86_exception *exception)
1871c602 4005{
0f65dd70 4006 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4007 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4008
1871c602 4009 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4010 access | PFERR_FETCH_MASK,
4011 exception);
1871c602
GN		 4012}
4013
064aea77 4014int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4015 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4016 struct x86_exception *exception)
1871c602 4017{
0f65dd70 4018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4019 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4020
1871c602 4021 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4022 exception);
1871c602 4023}
064aea77 4024EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4025
0f65dd70
AK		 4026static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4027 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4028 struct x86_exception *exception)
1871c602 4029{
0f65dd70 4030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4031 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4032}
4033
6a4d7550 4034int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4035 gva_t addr, void *val,
2dafc6c2 4036 unsigned int bytes,
bcc55cba 4037 struct x86_exception *exception)
77c2002e 4038{
0f65dd70 4039 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4040 void *data = val;
4041 int r = X86EMUL_CONTINUE;
4042
4043 while (bytes) {
14dfe855
JR		 4044 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4045 PFERR_WRITE_MASK,
ab9ae313 4046 exception);
77c2002e
IE		 4047 unsigned offset = addr & (PAGE_SIZE-1);
4048 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4049 int ret;
4050
bcc55cba 4051 if (gpa == UNMAPPED_GVA)
ab9ae313 4052 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4053 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4054 if (ret < 0) {
c3cd7ffa 4055 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4056 goto out;
4057 }
4058
4059 bytes -= towrite;
4060 data += towrite;
4061 addr += towrite;
4062 }
4063out:
4064 return r;
4065}
6a4d7550 4066EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4067
af7cc7d1
XG		 4068static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4069 gpa_t *gpa, struct x86_exception *exception,
4070 bool write)
4071{
97d64b78
AK		 4072 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4073 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4074
97d64b78
AK		 4075 if (vcpu_match_mmio_gva(vcpu, gva)
4076 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4077 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4078 (gva & (PAGE_SIZE - 1));
4f022648 4079 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4080 return 1;
4081 }
4082
af7cc7d1
XG		 4083 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4084
4085 if (*gpa == UNMAPPED_GVA)
4086 return -1;
4087
4088 /* For APIC access vmexit */
4089 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4090 return 1;
4091
4f022648
XG		 4092 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4093 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4094 return 1;
4f022648 4095 }
bebb106a 4096
af7cc7d1
XG		 4097 return 0;
4098}
4099
3200f405 4100int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4101 const void *val, int bytes)
bbd9b64e
CO		 4102{
4103 int ret;
4104
4105 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4106 if (ret < 0)
bbd9b64e 4107 return 0;
f57f2ef5 4108 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4109 return 1;
4110}
4111
77d197b2
XG		 4112struct read_write_emulator_ops {
4113 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4114 int bytes);
4115 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4116 void *val, int bytes);
4117 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4118 int bytes, void *val);
4119 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4120 void *val, int bytes);
4121 bool write;
4122};
4123
4124static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4125{
4126 if (vcpu->mmio_read_completed) {
77d197b2 4127 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4128 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4129 vcpu->mmio_read_completed = 0;
4130 return 1;
4131 }
4132
4133 return 0;
4134}
4135
4136static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4137 void *val, int bytes)
4138{
4139 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4140}
4141
4142static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4143 void *val, int bytes)
4144{
4145 return emulator_write_phys(vcpu, gpa, val, bytes);
4146}
4147
4148static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4149{
4150 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4151 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4152}
4153
4154static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4155 void *val, int bytes)
4156{
4157 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4158 return X86EMUL_IO_NEEDED;
4159}
4160
4161static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4162 void *val, int bytes)
4163{
f78146b0
AK		 4164 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4165
87da7e66 4166 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4167 return X86EMUL_CONTINUE;
4168}
4169
0fbe9b0b 4170static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4171 .read_write_prepare = read_prepare,
4172 .read_write_emulate = read_emulate,
4173 .read_write_mmio = vcpu_mmio_read,
4174 .read_write_exit_mmio = read_exit_mmio,
4175};
4176
0fbe9b0b 4177static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4178 .read_write_emulate = write_emulate,
4179 .read_write_mmio = write_mmio,
4180 .read_write_exit_mmio = write_exit_mmio,
4181 .write = true,
4182};
4183
22388a3c
XG		 4184static int emulator_read_write_onepage(unsigned long addr, void *val,
4185 unsigned int bytes,
4186 struct x86_exception *exception,
4187 struct kvm_vcpu *vcpu,
0fbe9b0b 4188 const struct read_write_emulator_ops *ops)
bbd9b64e 4189{
af7cc7d1
XG		 4190 gpa_t gpa;
4191 int handled, ret;
22388a3c 4192 bool write = ops->write;
f78146b0 4193 struct kvm_mmio_fragment *frag;
10589a46 4194
22388a3c 4195 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4196
af7cc7d1 4197 if (ret < 0)
bbd9b64e 4198 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4199
4200 /* For APIC access vmexit */
af7cc7d1 4201 if (ret)
bbd9b64e
CO		 4202 goto mmio;
4203
22388a3c 4204 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4205 return X86EMUL_CONTINUE;
4206
4207mmio:
4208 /*
4209 * Is this MMIO handled locally?
4210 */
22388a3c 4211 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4212 if (handled == bytes)
bbd9b64e 4213 return X86EMUL_CONTINUE;
bbd9b64e 4214
70252a10
AK		 4215 gpa += handled;
4216 bytes -= handled;
4217 val += handled;
4218
87da7e66
XG		 4219 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4220 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4221 frag->gpa = gpa;
4222 frag->data = val;
4223 frag->len = bytes;
f78146b0 4224 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4225}
4226
22388a3c
XG		 4227int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4228 void *val, unsigned int bytes,
4229 struct x86_exception *exception,
0fbe9b0b 4230 const struct read_write_emulator_ops *ops)
bbd9b64e 4231{
0f65dd70 4232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4233 gpa_t gpa;
4234 int rc;
4235
4236 if (ops->read_write_prepare &&
4237 ops->read_write_prepare(vcpu, val, bytes))
4238 return X86EMUL_CONTINUE;
4239
4240 vcpu->mmio_nr_fragments = 0;
0f65dd70 4241
bbd9b64e
CO		 4242 /* Crossing a page boundary? */
4243 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4244 int now;
bbd9b64e
CO		 4245
4246 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4247 rc = emulator_read_write_onepage(addr, val, now, exception,
4248 vcpu, ops);
4249
bbd9b64e
CO		 4250 if (rc != X86EMUL_CONTINUE)
4251 return rc;
4252 addr += now;
4253 val += now;
4254 bytes -= now;
4255 }
22388a3c 4256
f78146b0
AK		 4257 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4258 vcpu, ops);
4259 if (rc != X86EMUL_CONTINUE)
4260 return rc;
4261
4262 if (!vcpu->mmio_nr_fragments)
4263 return rc;
4264
4265 gpa = vcpu->mmio_fragments[0].gpa;
4266
4267 vcpu->mmio_needed = 1;
4268 vcpu->mmio_cur_fragment = 0;
4269
87da7e66 4270 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4271 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4272 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4273 vcpu->run->mmio.phys_addr = gpa;
4274
4275 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4276}
4277
4278static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4279 unsigned long addr,
4280 void *val,
4281 unsigned int bytes,
4282 struct x86_exception *exception)
4283{
4284 return emulator_read_write(ctxt, addr, val, bytes,
4285 exception, &read_emultor);
4286}
4287
4288int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4289 unsigned long addr,
4290 const void *val,
4291 unsigned int bytes,
4292 struct x86_exception *exception)
4293{
4294 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4295 exception, &write_emultor);
bbd9b64e 4296}
bbd9b64e 4297
daea3e73
AK		 4298#define CMPXCHG_TYPE(t, ptr, old, new) \
4299 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4300
4301#ifdef CONFIG_X86_64
4302# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4303#else
4304# define CMPXCHG64(ptr, old, new) \
9749a6c0 4305 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4306#endif
4307
0f65dd70
AK		 4308static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4309 unsigned long addr,
bbd9b64e
CO		 4310 const void *old,
4311 const void *new,
4312 unsigned int bytes,
0f65dd70 4313 struct x86_exception *exception)
bbd9b64e 4314{
0f65dd70 4315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4316 gpa_t gpa;
4317 struct page *page;
4318 char *kaddr;
4319 bool exchanged;
2bacc55c 4320
daea3e73
AK		 4321 /* guests cmpxchg8b have to be emulated atomically */
4322 if (bytes > 8 || (bytes & (bytes - 1)))
4323 goto emul_write;
10589a46 4324
daea3e73 4325 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4326
daea3e73
AK		 4327 if (gpa == UNMAPPED_GVA ||
4328 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4329 goto emul_write;
2bacc55c 4330
daea3e73
AK		 4331 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4332 goto emul_write;
72dc67a6 4333
daea3e73 4334 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4335 if (is_error_page(page))
c19b8bd6 4336 goto emul_write;
72dc67a6 4337
8fd75e12 4338 kaddr = kmap_atomic(page);
daea3e73
AK		 4339 kaddr += offset_in_page(gpa);
4340 switch (bytes) {
4341 case 1:
4342 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4343 break;
4344 case 2:
4345 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4346 break;
4347 case 4:
4348 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4349 break;
4350 case 8:
4351 exchanged = CMPXCHG64(kaddr, old, new);
4352 break;
4353 default:
4354 BUG();
2bacc55c 4355 }
8fd75e12 4356 kunmap_atomic(kaddr);
daea3e73
AK		 4357 kvm_release_page_dirty(page);
4358
4359 if (!exchanged)
4360 return X86EMUL_CMPXCHG_FAILED;
4361
f57f2ef5 4362 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4363
4364 return X86EMUL_CONTINUE;
4a5f48f6 4365
3200f405 4366emul_write:
daea3e73 4367 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4368
0f65dd70 4369 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4370}
4371
cf8f70bf
GN		 4372static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4373{
4374 /* TODO: String I/O for in kernel device */
4375 int r;
4376
4377 if (vcpu->arch.pio.in)
4378 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4379 vcpu->arch.pio.size, pd);
4380 else
4381 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4382 vcpu->arch.pio.port, vcpu->arch.pio.size,
4383 pd);
4384 return r;
4385}
4386
6f6fbe98
XG		 4387static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4388 unsigned short port, void *val,
4389 unsigned int count, bool in)
cf8f70bf 4390{
6f6fbe98 4391 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4392
4393 vcpu->arch.pio.port = port;
6f6fbe98 4394 vcpu->arch.pio.in = in;
7972995b 4395 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4396 vcpu->arch.pio.size = size;
4397
4398 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4399 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4400 return 1;
4401 }
4402
4403 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4404 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4405 vcpu->run->io.size = size;
4406 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4407 vcpu->run->io.count = count;
4408 vcpu->run->io.port = port;
4409
4410 return 0;
4411}
4412
6f6fbe98
XG		 4413static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4414 int size, unsigned short port, void *val,
4415 unsigned int count)
cf8f70bf 4416{
ca1d4a9e 4417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4418 int ret;
ca1d4a9e 4419
6f6fbe98
XG		 4420 if (vcpu->arch.pio.count)
4421 goto data_avail;
cf8f70bf 4422
6f6fbe98
XG		 4423 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4424 if (ret) {
4425data_avail:
4426 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4427 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4428 return 1;
4429 }
4430
cf8f70bf
GN		 4431 return 0;
4432}
4433
6f6fbe98
XG		 4434static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4435 int size, unsigned short port,
4436 const void *val, unsigned int count)
4437{
4438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4439
4440 memcpy(vcpu->arch.pio_data, val, size * count);
4441 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4442}
4443
bbd9b64e
CO		 4444static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4445{
4446 return kvm_x86_ops->get_segment_base(vcpu, seg);
4447}
4448
3cb16fe7 4449static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4450{
3cb16fe7 4451 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4452}
4453
f5f48ee1
SY		 4454int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4455{
4456 if (!need_emulate_wbinvd(vcpu))
4457 return X86EMUL_CONTINUE;
4458
4459 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4460 int cpu = get_cpu();
4461
4462 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4463 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4464 wbinvd_ipi, NULL, 1);
2eec7343 4465 put_cpu();
f5f48ee1 4466 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4467 } else
4468 wbinvd();
f5f48ee1
SY		 4469 return X86EMUL_CONTINUE;
4470}
4471EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4472
bcaf5cc5
AK		 4473static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4474{
4475 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4476}
4477
717746e3 4478int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4479{
717746e3 4480 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4481}
4482
717746e3 4483int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4484{
338dbc97 4485
717746e3 4486 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4487}
4488
52a46617 4489static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4490{
52a46617 4491 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4492}
4493
717746e3 4494static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4495{
717746e3 4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4497 unsigned long value;
4498
4499 switch (cr) {
4500 case 0:
4501 value = kvm_read_cr0(vcpu);
4502 break;
4503 case 2:
4504 value = vcpu->arch.cr2;
4505 break;
4506 case 3:
9f8fe504 4507 value = kvm_read_cr3(vcpu);
52a46617
GN		 4508 break;
4509 case 4:
4510 value = kvm_read_cr4(vcpu);
4511 break;
4512 case 8:
4513 value = kvm_get_cr8(vcpu);
4514 break;
4515 default:
a737f256 4516 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4517 return 0;
4518 }
4519
4520 return value;
4521}
4522
717746e3 4523static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4524{
717746e3 4525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4526 int res = 0;
4527
52a46617
GN		 4528 switch (cr) {
4529 case 0:
49a9b07e 4530 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4531 break;
4532 case 2:
4533 vcpu->arch.cr2 = val;
4534 break;
4535 case 3:
2390218b 4536 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4537 break;
4538 case 4:
a83b29c6 4539 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4540 break;
4541 case 8:
eea1cff9 4542 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4543 break;
4544 default:
a737f256 4545 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4546 res = -1;
52a46617 4547 }
0f12244f
GN		 4548
4549 return res;
52a46617
GN		 4550}
4551
4cee4798
KW		 4552static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4553{
4554 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4555}
4556
717746e3 4557static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4558{
717746e3 4559 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4560}
4561
4bff1e86 4562static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4563{
4bff1e86 4564 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4565}
4566
4bff1e86 4567static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4568{
4bff1e86 4569 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4570}
4571
1ac9d0cf
AK		 4572static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4573{
4574 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4575}
4576
4577static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4578{
4579 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4580}
4581
4bff1e86
AK		 4582static unsigned long emulator_get_cached_segment_base(
4583 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4584{
4bff1e86 4585 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4586}
4587
1aa36616
AK		 4588static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4589 struct desc_struct *desc, u32 *base3,
4590 int seg)
2dafc6c2
GN		 4591{
4592 struct kvm_segment var;
4593
4bff1e86 4594 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4595 *selector = var.selector;
2dafc6c2 4596
378a8b09
GN		 4597 if (var.unusable) {
4598 memset(desc, 0, sizeof(*desc));
fe77accb
RK		 4599 if (base3)
4600 *base3 = 0;
2dafc6c2 4601 return false;
378a8b09 4602 }
2dafc6c2
GN		 4603
4604 if (var.g)
4605 var.limit >>= 12;
4606 set_desc_limit(desc, var.limit);
4607 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4608#ifdef CONFIG_X86_64
4609 if (base3)
4610 *base3 = var.base >> 32;
4611#endif
2dafc6c2
GN		 4612 desc->type = var.type;
4613 desc->s = var.s;
4614 desc->dpl = var.dpl;
4615 desc->p = var.present;
4616 desc->avl = var.avl;
4617 desc->l = var.l;
4618 desc->d = var.db;
4619 desc->g = var.g;
4620
4621 return true;
4622}
4623
1aa36616
AK		 4624static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4625 struct desc_struct *desc, u32 base3,
4626 int seg)
2dafc6c2 4627{
4bff1e86 4628 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4629 struct kvm_segment var;
4630
1aa36616 4631 var.selector = selector;
2dafc6c2 4632 var.base = get_desc_base(desc);
5601d05b
GN		 4633#ifdef CONFIG_X86_64
4634 var.base |= ((u64)base3) << 32;
4635#endif
2dafc6c2
GN		 4636 var.limit = get_desc_limit(desc);
4637 if (desc->g)
4638 var.limit = (var.limit << 12) | 0xfff;
4639 var.type = desc->type;
4640 var.present = desc->p;
4641 var.dpl = desc->dpl;
4642 var.db = desc->d;
4643 var.s = desc->s;
4644 var.l = desc->l;
4645 var.g = desc->g;
4646 var.avl = desc->avl;
4647 var.present = desc->p;
4648 var.unusable = !var.present;
4649 var.padding = 0;
4650
4651 kvm_set_segment(vcpu, &var, seg);
4652 return;
4653}
4654
717746e3
AK		 4655static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4656 u32 msr_index, u64 *pdata)
4657{
4658 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4659}
4660
4661static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4662 u32 msr_index, u64 data)
4663{
8fe8ab46
WA		 4664 struct msr_data msr;
4665
4666 msr.data = data;
4667 msr.index = msr_index;
4668 msr.host_initiated = false;
4669 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4670}
4671
222d21aa
AK		 4672static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4673 u32 pmc, u64 *pdata)
4674{
4675 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4676}
4677
6c3287f7
AK		 4678static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4679{
4680 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4681}
4682
5037f6f3
AK		 4683static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4684{
4685 preempt_disable();
5197b808 4686 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4687 /*
4688 * CR0.TS may reference the host fpu state, not the guest fpu state,
4689 * so it may be clear at this point.
4690 */
4691 clts();
4692}
4693
4694static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4695{
4696 preempt_enable();
4697}
4698
2953538e 4699static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4700 struct x86_instruction_info *info,
c4f035c6
AK		 4701 enum x86_intercept_stage stage)
4702{
2953538e 4703 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4704}
4705
0017f93a 4706static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4707 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4708{
0017f93a 4709 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4710}
4711
dd856efa
AK		 4712static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4713{
4714 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4715}
4716
4717static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4718{
4719 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4720}
4721
0225fb50 4722static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4723 .read_gpr = emulator_read_gpr,
4724 .write_gpr = emulator_write_gpr,
1871c602 4725 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4726 .write_std = kvm_write_guest_virt_system,
1871c602 4727 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4728 .read_emulated = emulator_read_emulated,
4729 .write_emulated = emulator_write_emulated,
4730 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4731 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4732 .pio_in_emulated = emulator_pio_in_emulated,
4733 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4734 .get_segment = emulator_get_segment,
4735 .set_segment = emulator_set_segment,
5951c442 4736 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4737 .get_gdt = emulator_get_gdt,
160ce1f1 4738 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4739 .set_gdt = emulator_set_gdt,
4740 .set_idt = emulator_set_idt,
52a46617
GN		 4741 .get_cr = emulator_get_cr,
4742 .set_cr = emulator_set_cr,
4cee4798 4743 .set_rflags = emulator_set_rflags,
9c537244 4744 .cpl = emulator_get_cpl,
35aa5375
GN		 4745 .get_dr = emulator_get_dr,
4746 .set_dr = emulator_set_dr,
717746e3
AK		 4747 .set_msr = emulator_set_msr,
4748 .get_msr = emulator_get_msr,
222d21aa 4749 .read_pmc = emulator_read_pmc,
6c3287f7 4750 .halt = emulator_halt,
bcaf5cc5 4751 .wbinvd = emulator_wbinvd,
d6aa1000 4752 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4753 .get_fpu = emulator_get_fpu,
4754 .put_fpu = emulator_put_fpu,
c4f035c6 4755 .intercept = emulator_intercept,
bdb42f5a 4756 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4757};
4758
95cb2295
GN		 4759static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4760{
4761 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4762 /*
4763 * an sti; sti; sequence only disable interrupts for the first
4764 * instruction. So, if the last instruction, be it emulated or
4765 * not, left the system with the INT_STI flag enabled, it
4766 * means that the last instruction is an sti. We should not
4767 * leave the flag on in this case. The same goes for mov ss
4768 */
4769 if (!(int_shadow & mask))
4770 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4771}
4772
54b8486f
GN		 4773static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4774{
4775 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4776 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4777 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4778 else if (ctxt->exception.error_code_valid)
4779 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4780 ctxt->exception.error_code);
54b8486f 4781 else
da9cb575 4782 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4783}
4784
dd856efa 4785static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4786{
9dac77fa 4787 memset(&ctxt->twobyte, 0,
dd856efa 4788 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4789
9dac77fa
AK		 4790 ctxt->fetch.start = 0;
4791 ctxt->fetch.end = 0;
4792 ctxt->io_read.pos = 0;
4793 ctxt->io_read.end = 0;
4794 ctxt->mem_read.pos = 0;
4795 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4796}
4797
8ec4722d
MG		 4798static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4799{
adf52235 4800 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4801 int cs_db, cs_l;
4802
8ec4722d
MG		 4803 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4804
adf52235
TY		 4805 ctxt->eflags = kvm_get_rflags(vcpu);
4806 ctxt->eip = kvm_rip_read(vcpu);
4807 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4808 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4809 cs_l ? X86EMUL_MODE_PROT64 :
4810 cs_db ? X86EMUL_MODE_PROT32 :
4811 X86EMUL_MODE_PROT16;
4812 ctxt->guest_mode = is_guest_mode(vcpu);
4813
dd856efa 4814 init_decode_cache(ctxt);
7ae441ea 4815 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4816}
4817
71f9833b 4818int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4819{
9d74191a 4820 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4821 int ret;
4822
4823 init_emulate_ctxt(vcpu);
4824
9dac77fa
AK		 4825 ctxt->op_bytes = 2;
4826 ctxt->ad_bytes = 2;
4827 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4828 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4829
4830 if (ret != X86EMUL_CONTINUE)
4831 return EMULATE_FAIL;
4832
9dac77fa 4833 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4834 kvm_rip_write(vcpu, ctxt->eip);
4835 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4836
4837 if (irq == NMI_VECTOR)
7460fb4a 4838 vcpu->arch.nmi_pending = 0;
63995653
MG		 4839 else
4840 vcpu->arch.interrupt.pending = false;
4841
4842 return EMULATE_DONE;
4843}
4844EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4845
6d77dbfc
GN		 4846static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4847{
fc3a9157
JR		 4848 int r = EMULATE_DONE;
4849
6d77dbfc
GN		 4850 ++vcpu->stat.insn_emulation_fail;
4851 trace_kvm_emulate_insn_failed(vcpu);
c75f3949 4852 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4853 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4854 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4855 vcpu->run->internal.ndata = 0;
4856 r = EMULATE_FAIL;
4857 }
6d77dbfc 4858 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4859
4860 return r;
6d77dbfc
GN		 4861}
4862
93c05d3e 4863static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4864 bool write_fault_to_shadow_pgtable,
4865 int emulation_type)
a6f177ef 4866{
95b3cf69 4867 gpa_t gpa = cr2;
8e3d9d06 4868 pfn_t pfn;
a6f177ef 4869
991eebf9
GN		 4870 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4871 return false;
4872
95b3cf69
XG		 4873 if (!vcpu->arch.mmu.direct_map) {
4874 /*
4875 * Write permission should be allowed since only
4876 * write access need to be emulated.
4877 */
4878 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4879
95b3cf69
XG		 4880 /*
4881 * If the mapping is invalid in guest, let cpu retry
4882 * it to generate fault.
4883 */
4884 if (gpa == UNMAPPED_GVA)
4885 return true;
4886 }
a6f177ef 4887
8e3d9d06
XG		 4888 /*
4889 * Do not retry the unhandleable instruction if it faults on the
4890 * readonly host memory, otherwise it will goto a infinite loop:
4891 * retry instruction -> write #PF -> emulation fail -> retry
4892 * instruction -> ...
4893 */
4894 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4895
4896 /*
4897 * If the instruction failed on the error pfn, it can not be fixed,
4898 * report the error to userspace.
4899 */
4900 if (is_error_noslot_pfn(pfn))
4901 return false;
4902
4903 kvm_release_pfn_clean(pfn);
4904
4905 /* The instructions are well-emulated on direct mmu. */
4906 if (vcpu->arch.mmu.direct_map) {
4907 unsigned int indirect_shadow_pages;
4908
4909 spin_lock(&vcpu->kvm->mmu_lock);
4910 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4911 spin_unlock(&vcpu->kvm->mmu_lock);
4912
4913 if (indirect_shadow_pages)
4914 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4915
a6f177ef 4916 return true;
8e3d9d06 4917 }
a6f177ef 4918
95b3cf69
XG		 4919 /*
4920 * if emulation was due to access to shadowed page table
4921 * and it failed try to unshadow page and re-enter the
4922 * guest to let CPU execute the instruction.
4923 */
4924 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4925
4926 /*
4927 * If the access faults on its page table, it can not
4928 * be fixed by unprotecting shadow page and it should
4929 * be reported to userspace.
4930 */
4931 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4932}
4933
1cb3f3ae
XG		 4934static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4935 unsigned long cr2, int emulation_type)
4936{
4937 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4938 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4939
4940 last_retry_eip = vcpu->arch.last_retry_eip;
4941 last_retry_addr = vcpu->arch.last_retry_addr;
4942
4943 /*
4944 * If the emulation is caused by #PF and it is non-page_table
4945 * writing instruction, it means the VM-EXIT is caused by shadow
4946 * page protected, we can zap the shadow page and retry this
4947 * instruction directly.
4948 *
4949 * Note: if the guest uses a non-page-table modifying instruction
4950 * on the PDE that points to the instruction, then we will unmap
4951 * the instruction and go to an infinite loop. So, we cache the
4952 * last retried eip and the last fault address, if we meet the eip
4953 * and the address again, we can break out of the potential infinite
4954 * loop.
4955 */
4956 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4957
4958 if (!(emulation_type & EMULTYPE_RETRY))
4959 return false;
4960
4961 if (x86_page_table_writing_insn(ctxt))
4962 return false;
4963
4964 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4965 return false;
4966
4967 vcpu->arch.last_retry_eip = ctxt->eip;
4968 vcpu->arch.last_retry_addr = cr2;
4969
4970 if (!vcpu->arch.mmu.direct_map)
4971 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4972
22368028 4973 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4974
4975 return true;
4976}
4977
716d51ab
GN		 4978static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4979static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4980
51d8b661
AP		 4981int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4982 unsigned long cr2,
dc25e89e
AP		 4983 int emulation_type,
4984 void *insn,
4985 int insn_len)
bbd9b64e 4986{
95cb2295 4987 int r;
9d74191a 4988 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4989 bool writeback = true;
93c05d3e 4990 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4991
93c05d3e
XG		 4992 /*
4993 * Clear write_fault_to_shadow_pgtable here to ensure it is
4994 * never reused.
4995 */
4996 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4997 kvm_clear_exception_queue(vcpu);
8d7d8102 4998
571008da 4999 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5000 init_emulate_ctxt(vcpu);
9d74191a
TY		 5001 ctxt->interruptibility = 0;
5002 ctxt->have_exception = false;
5003 ctxt->perm_ok = false;
bbd9b64e 5004
9d74191a 5005 ctxt->only_vendor_specific_insn
4005996e
AK		 5006 = emulation_type & EMULTYPE_TRAP_UD;
5007
9d74191a 5008 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5009
e46479f8 5010 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5011 ++vcpu->stat.insn_emulation;
1d2887e2 5012 if (r != EMULATION_OK) {
4005996e
AK		 5013 if (emulation_type & EMULTYPE_TRAP_UD)
5014 return EMULATE_FAIL;
991eebf9
GN		 5015 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5016 emulation_type))
bbd9b64e 5017 return EMULATE_DONE;
6d77dbfc
GN		 5018 if (emulation_type & EMULTYPE_SKIP)
5019 return EMULATE_FAIL;
5020 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5021 }
5022 }
5023
ba8afb6b 5024 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5025 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5026 return EMULATE_DONE;
5027 }
5028
1cb3f3ae
XG		 5029 if (retry_instruction(ctxt, cr2, emulation_type))
5030 return EMULATE_DONE;
5031
7ae441ea 5032 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5033 changes registers values during IO operation */
7ae441ea
GN		 5034 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5035 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5036 emulator_invalidate_register_cache(ctxt);
7ae441ea 5037 }
4d2179e1 5038
5cd21917 5039restart:
9d74191a 5040 r = x86_emulate_insn(ctxt);
bbd9b64e 5041
775fde86
JR		 5042 if (r == EMULATION_INTERCEPTED)
5043 return EMULATE_DONE;
5044
d2ddd1c4 5045 if (r == EMULATION_FAILED) {
991eebf9
GN		 5046 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5047 emulation_type))
c3cd7ffa
GN		 5048 return EMULATE_DONE;
5049
6d77dbfc 5050 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5051 }
5052
9d74191a 5053 if (ctxt->have_exception) {
54b8486f 5054 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5055 r = EMULATE_DONE;
5056 } else if (vcpu->arch.pio.count) {
3457e419
GN		 5057 if (!vcpu->arch.pio.in)
5058 vcpu->arch.pio.count = 0;
716d51ab 5059 else {
7ae441ea 5060 writeback = false;
716d51ab
GN		 5061 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5062 }
e85d28f8 5063 r = EMULATE_DO_MMIO;
7ae441ea
GN		 5064 } else if (vcpu->mmio_needed) {
5065 if (!vcpu->mmio_is_write)
5066 writeback = false;
e85d28f8 5067 r = EMULATE_DO_MMIO;
716d51ab 5068 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5069 } else if (r == EMULATION_RESTART)
5cd21917 5070 goto restart;
d2ddd1c4
GN		 5071 else
5072 r = EMULATE_DONE;
f850e2e6 5073
7ae441ea 5074 if (writeback) {
9d74191a
TY		 5075 toggle_interruptibility(vcpu, ctxt->interruptibility);
5076 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 5077 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5078 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5079 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 5080 } else
5081 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5082
5083 return r;
de7d789a 5084}
51d8b661 5085EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5086
cf8f70bf 5087int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5088{
cf8f70bf 5089 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5090 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5091 size, port, &val, 1);
cf8f70bf 5092 /* do not return to emulator after return from userspace */
7972995b 5093 vcpu->arch.pio.count = 0;
de7d789a
CO		 5094 return ret;
5095}
cf8f70bf 5096EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5097
8cfdc000
ZA		 5098static void tsc_bad(void *info)
5099{
0a3aee0d 5100 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5101}
5102
5103static void tsc_khz_changed(void *data)
c8076604 5104{
8cfdc000
ZA		 5105 struct cpufreq_freqs *freq = data;
5106 unsigned long khz = 0;
5107
5108 if (data)
5109 khz = freq->new;
5110 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5111 khz = cpufreq_quick_get(raw_smp_processor_id());
5112 if (!khz)
5113 khz = tsc_khz;
0a3aee0d 5114 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5115}
5116
c8076604
GH		 5117static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5118 void *data)
5119{
5120 struct cpufreq_freqs *freq = data;
5121 struct kvm *kvm;
5122 struct kvm_vcpu *vcpu;
5123 int i, send_ipi = 0;
5124
8cfdc000
ZA		 5125 /*
5126 * We allow guests to temporarily run on slowing clocks,
5127 * provided we notify them after, or to run on accelerating
5128 * clocks, provided we notify them before. Thus time never
5129 * goes backwards.
5130 *
5131 * However, we have a problem. We can't atomically update
5132 * the frequency of a given CPU from this function; it is
5133 * merely a notifier, which can be called from any CPU.
5134 * Changing the TSC frequency at arbitrary points in time
5135 * requires a recomputation of local variables related to
5136 * the TSC for each VCPU. We must flag these local variables
5137 * to be updated and be sure the update takes place with the
5138 * new frequency before any guests proceed.
5139 *
5140 * Unfortunately, the combination of hotplug CPU and frequency
5141 * change creates an intractable locking scenario; the order
5142 * of when these callouts happen is undefined with respect to
5143 * CPU hotplug, and they can race with each other. As such,
5144 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5145 * undefined; you can actually have a CPU frequency change take
5146 * place in between the computation of X and the setting of the
5147 * variable. To protect against this problem, all updates of
5148 * the per_cpu tsc_khz variable are done in an interrupt
5149 * protected IPI, and all callers wishing to update the value
5150 * must wait for a synchronous IPI to complete (which is trivial
5151 * if the caller is on the CPU already). This establishes the
5152 * necessary total order on variable updates.
5153 *
5154 * Note that because a guest time update may take place
5155 * anytime after the setting of the VCPU's request bit, the
5156 * correct TSC value must be set before the request. However,
5157 * to ensure the update actually makes it to any guest which
5158 * starts running in hardware virtualization between the set
5159 * and the acquisition of the spinlock, we must also ping the
5160 * CPU after setting the request bit.
5161 *
5162 */
5163
c8076604
GH		 5164 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5165 return 0;
5166 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5167 return 0;
8cfdc000
ZA		 5168
5169 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5170
e935b837 5171 raw_spin_lock(&kvm_lock);
c8076604 5172 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5173 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5174 if (vcpu->cpu != freq->cpu)
5175 continue;
c285545f 5176 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5177 if (vcpu->cpu != smp_processor_id())
8cfdc000 5178 send_ipi = 1;
c8076604
GH		 5179 }
5180 }
e935b837 5181 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5182
5183 if (freq->old < freq->new && send_ipi) {
5184 /*
5185 * We upscale the frequency. Must make the guest
5186 * doesn't see old kvmclock values while running with
5187 * the new frequency, otherwise we risk the guest sees
5188 * time go backwards.
5189 *
5190 * In case we update the frequency for another cpu
5191 * (which might be in guest context) send an interrupt
5192 * to kick the cpu out of guest context. Next time
5193 * guest context is entered kvmclock will be updated,
5194 * so the guest will not see stale values.
5195 */
8cfdc000 5196 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5197 }
5198 return 0;
5199}
5200
5201static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5202 .notifier_call = kvmclock_cpufreq_notifier
5203};
5204
5205static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5206 unsigned long action, void *hcpu)
5207{
5208 unsigned int cpu = (unsigned long)hcpu;
5209
5210 switch (action) {
5211 case CPU_ONLINE:
5212 case CPU_DOWN_FAILED:
5213 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5214 break;
5215 case CPU_DOWN_PREPARE:
5216 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5217 break;
5218 }
5219 return NOTIFY_OK;
5220}
5221
5222static struct notifier_block kvmclock_cpu_notifier_block = {
5223 .notifier_call = kvmclock_cpu_notifier,
5224 .priority = -INT_MAX
c8076604
GH		 5225};
5226
b820cc0c
ZA		 5227static void kvm_timer_init(void)
5228{
5229 int cpu;
5230
c285545f 5231 max_tsc_khz = tsc_khz;
8cfdc000 5232 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5233 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5234#ifdef CONFIG_CPU_FREQ
5235 struct cpufreq_policy policy;
5236 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5237 cpu = get_cpu();
5238 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5239 if (policy.cpuinfo.max_freq)
5240 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5241 put_cpu();
c285545f 5242#endif
b820cc0c
ZA		 5243 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5244 CPUFREQ_TRANSITION_NOTIFIER);
5245 }
c285545f 5246 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5247 for_each_online_cpu(cpu)
5248 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5249}
5250
ff9d07a0
ZY		 5251static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5252
f5132b01 5253int kvm_is_in_guest(void)
ff9d07a0 5254{
086c9855 5255 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5256}
5257
5258static int kvm_is_user_mode(void)
5259{
5260 int user_mode = 3;
dcf46b94 5261
086c9855
AS		 5262 if (__this_cpu_read(current_vcpu))
5263 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5264
ff9d07a0
ZY		 5265 return user_mode != 0;
5266}
5267
5268static unsigned long kvm_get_guest_ip(void)
5269{
5270 unsigned long ip = 0;
dcf46b94 5271
086c9855
AS		 5272 if (__this_cpu_read(current_vcpu))
5273 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5274
ff9d07a0
ZY		 5275 return ip;
5276}
5277
5278static struct perf_guest_info_callbacks kvm_guest_cbs = {
5279 .is_in_guest = kvm_is_in_guest,
5280 .is_user_mode = kvm_is_user_mode,
5281 .get_guest_ip = kvm_get_guest_ip,
5282};
5283
5284void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5285{
086c9855 5286 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5287}
5288EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5289
5290void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5291{
086c9855 5292 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5293}
5294EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5295
ce88decf
XG		 5296static void kvm_set_mmio_spte_mask(void)
5297{
5298 u64 mask;
5299 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5300
5301 /*
5302 * Set the reserved bits and the present bit of an paging-structure
5303 * entry to generate page fault with PFER.RSV = 1.
5304 */
5305 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5306 mask |= 1ull;
5307
5308#ifdef CONFIG_X86_64
5309 /*
5310 * If reserved bit is not supported, clear the present bit to disable
5311 * mmio page fault.
5312 */
5313 if (maxphyaddr == 52)
5314 mask &= ~1ull;
5315#endif
5316
5317 kvm_mmu_set_mmio_spte_mask(mask);
5318}
5319
16e8d74d
MT		 5320#ifdef CONFIG_X86_64
5321static void pvclock_gtod_update_fn(struct work_struct *work)
5322{
d828199e
MT		 5323 struct kvm *kvm;
5324
5325 struct kvm_vcpu *vcpu;
5326 int i;
5327
5328 raw_spin_lock(&kvm_lock);
5329 list_for_each_entry(kvm, &vm_list, vm_list)
5330 kvm_for_each_vcpu(i, vcpu, kvm)
5331 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5332 atomic_set(&kvm_guest_has_master_clock, 0);
5333 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5334}
5335
5336static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5337
5338/*
5339 * Notification about pvclock gtod data update.
5340 */
5341static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5342 void *priv)
5343{
5344 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5345 struct timekeeper *tk = priv;
5346
5347 update_pvclock_gtod(tk);
5348
5349 /* disable master clock if host does not trust, or does not
5350 * use, TSC clocksource
5351 */
5352 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5353 atomic_read(&kvm_guest_has_master_clock) != 0)
5354 queue_work(system_long_wq, &pvclock_gtod_work);
5355
5356 return 0;
5357}
5358
5359static struct notifier_block pvclock_gtod_notifier = {
5360 .notifier_call = pvclock_gtod_notify,
5361};
5362#endif
5363
f8c16bba 5364int kvm_arch_init(void *opaque)
043405e1 5365{
b820cc0c 5366 int r;
f8c16bba
ZX		 5367 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5368
f8c16bba
ZX		 5369 if (kvm_x86_ops) {
5370 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5371 r = -EEXIST;
5372 goto out;
f8c16bba
ZX		 5373 }
5374
5375 if (!ops->cpu_has_kvm_support()) {
5376 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5377 r = -EOPNOTSUPP;
5378 goto out;
f8c16bba
ZX		 5379 }
5380 if (ops->disabled_by_bios()) {
5381 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5382 r = -EOPNOTSUPP;
5383 goto out;
f8c16bba
ZX		 5384 }
5385
013f6a5d
MT		 5386 r = -ENOMEM;
5387 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5388 if (!shared_msrs) {
5389 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5390 goto out;
5391 }
5392
97db56ce
AK		 5393 r = kvm_mmu_module_init();
5394 if (r)
013f6a5d 5395 goto out_free_percpu;
97db56ce 5396
ce88decf 5397 kvm_set_mmio_spte_mask();
97db56ce
AK		 5398 kvm_init_msr_list();
5399
f8c16bba 5400 kvm_x86_ops = ops;
7b52345e 5401 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5402 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5403
b820cc0c 5404 kvm_timer_init();
c8076604 5405
ff9d07a0
ZY		 5406 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5407
2acf923e
DC		 5408 if (cpu_has_xsave)
5409 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5410
c5cc421b 5411 kvm_lapic_init();
16e8d74d
MT		 5412#ifdef CONFIG_X86_64
5413 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5414#endif
5415
f8c16bba 5416 return 0;
56c6d28a 5417
013f6a5d
MT		 5418out_free_percpu:
5419 free_percpu(shared_msrs);
56c6d28a 5420out:
56c6d28a 5421 return r;
043405e1 5422}
8776e519 5423
f8c16bba
ZX		 5424void kvm_arch_exit(void)
5425{
ff9d07a0
ZY		 5426 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5427
888d256e
JK		 5428 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5429 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5430 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5431 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5432#ifdef CONFIG_X86_64
5433 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5434#endif
f8c16bba 5435 kvm_x86_ops = NULL;
56c6d28a 5436 kvm_mmu_module_exit();
013f6a5d 5437 free_percpu(shared_msrs);
56c6d28a 5438}
f8c16bba 5439
8776e519
HB		 5440int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5441{
5442 ++vcpu->stat.halt_exits;
5443 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5444 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5445 return 1;
5446 } else {
5447 vcpu->run->exit_reason = KVM_EXIT_HLT;
5448 return 0;
5449 }
5450}
5451EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5452
55cd8e5a
GN		 5453int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5454{
5455 u64 param, ingpa, outgpa, ret;
5456 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5457 bool fast, longmode;
5458 int cs_db, cs_l;
5459
5460 /*
5461 * hypercall generates UD from non zero cpl and real mode
5462 * per HYPER-V spec
5463 */
3eeb3288 5464 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5465 kvm_queue_exception(vcpu, UD_VECTOR);
5466 return 0;
5467 }
5468
5469 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5470 longmode = is_long_mode(vcpu) && cs_l == 1;
5471
5472 if (!longmode) {
ccd46936
GN		 5473 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5474 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5475 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5476 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5477 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5478 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5479 }
5480#ifdef CONFIG_X86_64
5481 else {
5482 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5483 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5484 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5485 }
5486#endif
5487
5488 code = param & 0xffff;
5489 fast = (param >> 16) & 0x1;
5490 rep_cnt = (param >> 32) & 0xfff;
5491 rep_idx = (param >> 48) & 0xfff;
5492
5493 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5494
c25bc163
GN		 5495 switch (code) {
5496 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5497 kvm_vcpu_on_spin(vcpu);
5498 break;
5499 default:
5500 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5501 break;
5502 }
55cd8e5a
GN		 5503
5504 ret = res | (((u64)rep_done & 0xfff) << 32);
5505 if (longmode) {
5506 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5507 } else {
5508 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5509 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5510 }
5511
5512 return 1;
5513}
5514
8776e519
HB		 5515int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5516{
5517 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5518 int r = 1;
8776e519 5519
55cd8e5a
GN		 5520 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5521 return kvm_hv_hypercall(vcpu);
5522
5fdbf976
MT		 5523 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5524 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5525 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5526 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5527 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5528
229456fc 5529 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5530
8776e519
HB		 5531 if (!is_long_mode(vcpu)) {
5532 nr &= 0xFFFFFFFF;
5533 a0 &= 0xFFFFFFFF;
5534 a1 &= 0xFFFFFFFF;
5535 a2 &= 0xFFFFFFFF;
5536 a3 &= 0xFFFFFFFF;
5537 }
5538
07708c4a
JK		 5539 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5540 ret = -KVM_EPERM;
5541 goto out;
5542 }
5543
8776e519 5544 switch (nr) {
b93463aa
AK		 5545 case KVM_HC_VAPIC_POLL_IRQ:
5546 ret = 0;
5547 break;
8776e519
HB		 5548 default:
5549 ret = -KVM_ENOSYS;
5550 break;
5551 }
07708c4a 5552out:
5fdbf976 5553 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5554 ++vcpu->stat.hypercalls;
2f333bcb 5555 return r;
8776e519
HB		 5556}
5557EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5558
b6785def 5559static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5560{
d6aa1000 5561 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5562 char instruction[3];
5fdbf976 5563 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5564
8776e519
HB		 5565 /*
5566 * Blow out the MMU to ensure that no other VCPU has an active mapping
5567 * to ensure that the updated hypercall appears atomically across all
5568 * VCPUs.
5569 */
5570 kvm_mmu_zap_all(vcpu->kvm);
5571
8776e519 5572 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5573
9d74191a 5574 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5575}
5576
b6c7a5dc
HB		 5577/*
5578 * Check if userspace requested an interrupt window, and that the
5579 * interrupt window is open.
5580 *
5581 * No need to exit to userspace if we already have an interrupt queued.
5582 */
851ba692 5583static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5584{
8061823a 5585 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5586 vcpu->run->request_interrupt_window &&
5df56646 5587 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5588}
5589
851ba692 5590static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5591{
851ba692
AK		 5592 struct kvm_run *kvm_run = vcpu->run;
5593
91586a3b 5594 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5595 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5596 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5597 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5598 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5599 else
b6c7a5dc 5600 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5601 kvm_arch_interrupt_allowed(vcpu) &&
5602 !kvm_cpu_has_interrupt(vcpu) &&
5603 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5604}
5605
95ba8273
GN		 5606static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5607{
5608 int max_irr, tpr;
5609
5610 if (!kvm_x86_ops->update_cr8_intercept)
5611 return;
5612
88c808fd
AK		 5613 if (!vcpu->arch.apic)
5614 return;
5615
8db3baa2
GN		 5616 if (!vcpu->arch.apic->vapic_addr)
5617 max_irr = kvm_lapic_find_highest_irr(vcpu);
5618 else
5619 max_irr = -1;
95ba8273
GN		 5620
5621 if (max_irr != -1)
5622 max_irr >>= 4;
5623
5624 tpr = kvm_lapic_get_cr8(vcpu);
5625
5626 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5627}
5628
851ba692 5629static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5630{
5631 /* try to reinject previous events if any */
b59bb7bd 5632 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5633 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5634 vcpu->arch.exception.has_error_code,
5635 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5636 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5637 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5638 vcpu->arch.exception.error_code,
5639 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5640 return;
5641 }
5642
95ba8273
GN		 5643 if (vcpu->arch.nmi_injected) {
5644 kvm_x86_ops->set_nmi(vcpu);
5645 return;
5646 }
5647
5648 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5649 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5650 return;
5651 }
5652
5653 /* try to inject new event if pending */
5654 if (vcpu->arch.nmi_pending) {
5655 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5656 --vcpu->arch.nmi_pending;
95ba8273
GN		 5657 vcpu->arch.nmi_injected = true;
5658 kvm_x86_ops->set_nmi(vcpu);
5659 }
c7c9c56c 5660 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5661 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5662 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5663 false);
5664 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5665 }
5666 }
5667}
5668
7460fb4a
AK		 5669static void process_nmi(struct kvm_vcpu *vcpu)
5670{
5671 unsigned limit = 2;
5672
5673 /*
5674 * x86 is limited to one NMI running, and one NMI pending after it.
5675 * If an NMI is already in progress, limit further NMIs to just one.
5676 * Otherwise, allow two (and we'll inject the first one immediately).
5677 */
5678 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5679 limit = 1;
5680
5681 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5682 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5683 kvm_make_request(KVM_REQ_EVENT, vcpu);
5684}
5685
d828199e
MT		 5686static void kvm_gen_update_masterclock(struct kvm *kvm)
5687{
5688#ifdef CONFIG_X86_64
5689 int i;
5690 struct kvm_vcpu *vcpu;
5691 struct kvm_arch *ka = &kvm->arch;
5692
5693 spin_lock(&ka->pvclock_gtod_sync_lock);
5694 kvm_make_mclock_inprogress_request(kvm);
5695 /* no guest entries from this point */
5696 pvclock_update_vm_gtod_copy(kvm);
5697
5698 kvm_for_each_vcpu(i, vcpu, kvm)
5699 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5700
5701 /* guest entries allowed */
5702 kvm_for_each_vcpu(i, vcpu, kvm)
5703 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5704
5705 spin_unlock(&ka->pvclock_gtod_sync_lock);
5706#endif
5707}
5708
3d81bc7e 5709static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5710{
5711 u64 eoi_exit_bitmap[4];
cf9e65b7 5712 u32 tmr[8];
c7c9c56c 5713
3d81bc7e
YZ		 5714 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5715 return;
c7c9c56c
YZ		 5716
5717 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5718 memset(tmr, 0, 32);
c7c9c56c 5719
cf9e65b7 5720 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5721 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5722 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5723}
5724
851ba692 5725static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5726{
5727 int r;
6a8b1d13 5728 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5729 vcpu->run->request_interrupt_window;
730dca42 5730 bool req_immediate_exit = false;
b6c7a5dc 5731
3e007509 5732 if (vcpu->requests) {
a8eeb04a 5733 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5734 kvm_mmu_unload(vcpu);
a8eeb04a 5735 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5736 __kvm_migrate_timers(vcpu);
d828199e
MT		 5737 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5738 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5739 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5740 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5741 if (unlikely(r))
5742 goto out;
5743 }
a8eeb04a 5744 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5745 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5746 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5747 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5748 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5749 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5750 r = 0;
5751 goto out;
5752 }
a8eeb04a 5753 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5754 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5755 r = 0;
5756 goto out;
5757 }
a8eeb04a 5758 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5759 vcpu->fpu_active = 0;
5760 kvm_x86_ops->fpu_deactivate(vcpu);
5761 }
af585b92
GN		 5762 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5763 /* Page is swapped out. Do synthetic halt */
5764 vcpu->arch.apf.halted = true;
5765 r = 1;
5766 goto out;
5767 }
c9aaa895
GC		 5768 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5769 record_steal_time(vcpu);
7460fb4a
AK		 5770 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5771 process_nmi(vcpu);
f5132b01
GN		 5772 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5773 kvm_handle_pmu_event(vcpu);
5774 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5775 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5776 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5777 vcpu_scan_ioapic(vcpu);
2f52d58c 5778 }
b93463aa 5779
b463a6f7 5780 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5781 kvm_apic_accept_events(vcpu);
5782 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5783 r = 1;
5784 goto out;
5785 }
5786
b463a6f7
AK		 5787 inject_pending_event(vcpu);
5788
5789 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5790 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5791 req_immediate_exit =
5792 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5793 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5794 req_immediate_exit =
5795 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5796
5797 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5798 /*
5799 * Update architecture specific hints for APIC
5800 * virtual interrupt delivery.
5801 */
5802 if (kvm_x86_ops->hwapic_irr_update)
5803 kvm_x86_ops->hwapic_irr_update(vcpu,
5804 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5805 update_cr8_intercept(vcpu);
5806 kvm_lapic_sync_to_vapic(vcpu);
5807 }
5808 }
5809
d8368af8
AK		 5810 r = kvm_mmu_reload(vcpu);
5811 if (unlikely(r)) {
d905c069 5812 goto cancel_injection;
d8368af8
AK		 5813 }
5814
b6c7a5dc
HB		 5815 preempt_disable();
5816
5817 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5818 if (vcpu->fpu_active)
5819 kvm_load_guest_fpu(vcpu);
2acf923e 5820 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5821
6b7e2d09
XG		 5822 vcpu->mode = IN_GUEST_MODE;
5823
5824 /* We should set ->mode before check ->requests,
5825 * see the comment in make_all_cpus_request.
5826 */
5827 smp_mb();
b6c7a5dc 5828
d94e1dc9 5829 local_irq_disable();
32f88400 5830
6b7e2d09 5831 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5832 || need_resched() || signal_pending(current)) {
6b7e2d09 5833 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5834 smp_wmb();
6c142801
AK		 5835 local_irq_enable();
5836 preempt_enable();
5837 r = 1;
d905c069 5838 goto cancel_injection;
6c142801
AK		 5839 }
5840
f656ce01 5841 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5842
d6185f20
NHE		 5843 if (req_immediate_exit)
5844 smp_send_reschedule(vcpu->cpu);
5845
b6c7a5dc
HB		 5846 kvm_guest_enter();
5847
42dbaa5a 5848 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5849 set_debugreg(0, 7);
5850 set_debugreg(vcpu->arch.eff_db[0], 0);
5851 set_debugreg(vcpu->arch.eff_db[1], 1);
5852 set_debugreg(vcpu->arch.eff_db[2], 2);
5853 set_debugreg(vcpu->arch.eff_db[3], 3);
5854 }
b6c7a5dc 5855
229456fc 5856 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5857 kvm_x86_ops->run(vcpu);
b6c7a5dc 5858
24f1e32c
FW		 5859 /*
5860 * If the guest has used debug registers, at least dr7
5861 * will be disabled while returning to the host.
5862 * If we don't have active breakpoints in the host, we don't
5863 * care about the messed up debug address registers. But if
5864 * we have some of them active, restore the old state.
5865 */
59d8eb53 5866 if (hw_breakpoint_active())
24f1e32c 5867 hw_breakpoint_restore();
42dbaa5a 5868
886b470c
MT		 5869 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5870 native_read_tsc());
1d5f066e 5871
6b7e2d09 5872 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5873 smp_wmb();
a547c6db
YZ		 5874
5875 /* Interrupt is enabled by handle_external_intr() */
5876 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5877
5878 ++vcpu->stat.exits;
5879
5880 /*
5881 * We must have an instruction between local_irq_enable() and
5882 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5883 * the interrupt shadow. The stat.exits increment will do nicely.
5884 * But we need to prevent reordering, hence this barrier():
5885 */
5886 barrier();
5887
5888 kvm_guest_exit();
5889
5890 preempt_enable();
5891
f656ce01 5892 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5893
b6c7a5dc
HB		 5894 /*
5895 * Profile KVM exit RIPs:
5896 */
5897 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5898 unsigned long rip = kvm_rip_read(vcpu);
5899 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5900 }
5901
cc578287
ZA		 5902 if (unlikely(vcpu->arch.tsc_always_catchup))
5903 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5904
5cfb1d5a
MT		 5905 if (vcpu->arch.apic_attention)
5906 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5907
851ba692 5908 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5909 return r;
5910
5911cancel_injection:
5912 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5913 if (unlikely(vcpu->arch.apic_attention))
5914 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5915out:
5916 return r;
5917}
b6c7a5dc 5918
09cec754 5919
851ba692 5920static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5921{
5922 int r;
f656ce01 5923 struct kvm *kvm = vcpu->kvm;
d7690175 5924
f656ce01 5925 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5926
5927 r = 1;
5928 while (r > 0) {
af585b92
GN		 5929 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5930 !vcpu->arch.apf.halted)
851ba692 5931 r = vcpu_enter_guest(vcpu);
d7690175 5932 else {
f656ce01 5933 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5934 kvm_vcpu_block(vcpu);
f656ce01 5935 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 5936 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5937 kvm_apic_accept_events(vcpu);
09cec754
GN		 5938 switch(vcpu->arch.mp_state) {
5939 case KVM_MP_STATE_HALTED:
d7690175 5940 vcpu->arch.mp_state =
09cec754
GN		 5941 KVM_MP_STATE_RUNNABLE;
5942 case KVM_MP_STATE_RUNNABLE:
af585b92 5943 vcpu->arch.apf.halted = false;
09cec754 5944 break;
66450a21
JK		 5945 case KVM_MP_STATE_INIT_RECEIVED:
5946 break;
09cec754
GN		 5947 default:
5948 r = -EINTR;
5949 break;
5950 }
5951 }
d7690175
MT		 5952 }
5953
09cec754
GN		 5954 if (r <= 0)
5955 break;
5956
5957 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5958 if (kvm_cpu_has_pending_timer(vcpu))
5959 kvm_inject_pending_timer_irqs(vcpu);
5960
851ba692 5961 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5962 r = -EINTR;
851ba692 5963 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5964 ++vcpu->stat.request_irq_exits;
5965 }
af585b92
GN		 5966
5967 kvm_check_async_pf_completion(vcpu);
5968
09cec754
GN		 5969 if (signal_pending(current)) {
5970 r = -EINTR;
851ba692 5971 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5972 ++vcpu->stat.signal_exits;
5973 }
5974 if (need_resched()) {
f656ce01 5975 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5976 kvm_resched(vcpu);
f656ce01 5977 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5978 }
b6c7a5dc
HB		 5979 }
5980
f656ce01 5981 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 5982
5983 return r;
5984}
5985
716d51ab
GN		 5986static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5987{
5988 int r;
5989 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5990 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5991 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5992 if (r != EMULATE_DONE)
5993 return 0;
5994 return 1;
5995}
5996
5997static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5998{
5999 BUG_ON(!vcpu->arch.pio.count);
6000
6001 return complete_emulated_io(vcpu);
6002}
6003
f78146b0
AK		 6004/*
6005 * Implements the following, as a state machine:
6006 *
6007 * read:
6008 * for each fragment
87da7e66
XG		 6009 * for each mmio piece in the fragment
6010 * write gpa, len
6011 * exit
6012 * copy data
f78146b0
AK		 6013 * execute insn
6014 *
6015 * write:
6016 * for each fragment
87da7e66
XG		 6017 * for each mmio piece in the fragment
6018 * write gpa, len
6019 * copy data
6020 * exit
f78146b0 6021 */
716d51ab 6022static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6023{
6024 struct kvm_run *run = vcpu->run;
f78146b0 6025 struct kvm_mmio_fragment *frag;
87da7e66 6026 unsigned len;
5287f194 6027
716d51ab 6028 BUG_ON(!vcpu->mmio_needed);
5287f194 6029
716d51ab 6030 /* Complete previous fragment */
87da7e66
XG		 6031 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6032 len = min(8u, frag->len);
716d51ab 6033 if (!vcpu->mmio_is_write)
87da7e66
XG		 6034 memcpy(frag->data, run->mmio.data, len);
6035
6036 if (frag->len <= 8) {
6037 /* Switch to the next fragment. */
6038 frag++;
6039 vcpu->mmio_cur_fragment++;
6040 } else {
6041 /* Go forward to the next mmio piece. */
6042 frag->data += len;
6043 frag->gpa += len;
6044 frag->len -= len;
6045 }
6046
5a03bc08 6047 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6048 vcpu->mmio_needed = 0;
cef4dea0 6049 if (vcpu->mmio_is_write)
716d51ab
GN		 6050 return 1;
6051 vcpu->mmio_read_completed = 1;
6052 return complete_emulated_io(vcpu);
6053 }
87da7e66 6054
716d51ab
GN		 6055 run->exit_reason = KVM_EXIT_MMIO;
6056 run->mmio.phys_addr = frag->gpa;
6057 if (vcpu->mmio_is_write)
87da7e66
XG		 6058 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6059 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6060 run->mmio.is_write = vcpu->mmio_is_write;
6061 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6062 return 0;
5287f194
AK		 6063}
6064
716d51ab 6065
b6c7a5dc
HB		 6066int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6067{
6068 int r;
6069 sigset_t sigsaved;
6070
e5c30142
AK		 6071 if (!tsk_used_math(current) && init_fpu(current))
6072 return -ENOMEM;
6073
ac9f6dc0
AK		 6074 if (vcpu->sigset_active)
6075 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6076
a4535290 6077 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6078 kvm_vcpu_block(vcpu);
66450a21 6079 kvm_apic_accept_events(vcpu);
d7690175 6080 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6081 r = -EAGAIN;
6082 goto out;
b6c7a5dc
HB		 6083 }
6084
b6c7a5dc 6085 /* re-sync apic's tpr */
eea1cff9
AP		 6086 if (!irqchip_in_kernel(vcpu->kvm)) {
6087 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6088 r = -EINVAL;
6089 goto out;
6090 }
6091 }
b6c7a5dc 6092
716d51ab
GN		 6093 if (unlikely(vcpu->arch.complete_userspace_io)) {
6094 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6095 vcpu->arch.complete_userspace_io = NULL;
6096 r = cui(vcpu);
6097 if (r <= 0)
6098 goto out;
6099 } else
6100 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6101
851ba692 6102 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6103
6104out:
f1d86e46 6105 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6106 if (vcpu->sigset_active)
6107 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6108
b6c7a5dc
HB		 6109 return r;
6110}
6111
6112int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6113{
7ae441ea
GN		 6114 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6115 /*
6116 * We are here if userspace calls get_regs() in the middle of
6117 * instruction emulation. Registers state needs to be copied
4a969980 6118 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6119 * that usually, but some bad designed PV devices (vmware
6120 * backdoor interface) need this to work
6121 */
dd856efa 6122 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6123 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6124 }
5fdbf976
MT		 6125 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6126 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6127 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6128 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6129 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6130 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6131 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6132 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6133#ifdef CONFIG_X86_64
5fdbf976
MT		 6134 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6135 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6136 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6137 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6138 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6139 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6140 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6141 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6142#endif
6143
5fdbf976 6144 regs->rip = kvm_rip_read(vcpu);
91586a3b 6145 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6146
b6c7a5dc
HB		 6147 return 0;
6148}
6149
6150int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6151{
7ae441ea
GN		 6152 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6153 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6154
5fdbf976
MT		 6155 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6156 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6157 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6158 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6159 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6160 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6161 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6162 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6163#ifdef CONFIG_X86_64
5fdbf976
MT		 6164 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6165 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6166 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6167 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6168 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6169 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6170 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6171 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6172#endif
6173
5fdbf976 6174 kvm_rip_write(vcpu, regs->rip);
91586a3b 6175 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6176
b4f14abd
JK		 6177 vcpu->arch.exception.pending = false;
6178
3842d135
AK		 6179 kvm_make_request(KVM_REQ_EVENT, vcpu);
6180
b6c7a5dc
HB		 6181 return 0;
6182}
6183
b6c7a5dc
HB		 6184void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6185{
6186 struct kvm_segment cs;
6187
3e6e0aab 6188 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6189 *db = cs.db;
6190 *l = cs.l;
6191}
6192EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6193
6194int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6195 struct kvm_sregs *sregs)
6196{
89a27f4d 6197 struct desc_ptr dt;
b6c7a5dc 6198
3e6e0aab
GT		 6199 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6200 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6201 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6202 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6203 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6204 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6205
3e6e0aab
GT		 6206 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6207 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6208
6209 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6210 sregs->idt.limit = dt.size;
6211 sregs->idt.base = dt.address;
b6c7a5dc 6212 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6213 sregs->gdt.limit = dt.size;
6214 sregs->gdt.base = dt.address;
b6c7a5dc 6215
4d4ec087 6216 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6217 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6218 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6219 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6220 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6221 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6222 sregs->apic_base = kvm_get_apic_base(vcpu);
6223
923c61bb 6224 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6225
36752c9b 6226 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6227 set_bit(vcpu->arch.interrupt.nr,
6228 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6229
b6c7a5dc
HB		 6230 return 0;
6231}
6232
62d9f0db
MT		 6233int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6234 struct kvm_mp_state *mp_state)
6235{
66450a21 6236 kvm_apic_accept_events(vcpu);
62d9f0db 6237 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6238 return 0;
6239}
6240
6241int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6242 struct kvm_mp_state *mp_state)
6243{
66450a21
JK		 6244 if (!kvm_vcpu_has_lapic(vcpu) &&
6245 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6246 return -EINVAL;
6247
6248 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6249 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6250 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6251 } else
6252 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6253 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6254 return 0;
6255}
6256
7f3d35fd
KW		 6257int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6258 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6259{
9d74191a 6260 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6261 int ret;
e01c2426 6262
8ec4722d 6263 init_emulate_ctxt(vcpu);
c697518a 6264
7f3d35fd 6265 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6266 has_error_code, error_code);
c697518a 6267
c697518a 6268 if (ret)
19d04437 6269 return EMULATE_FAIL;
37817f29 6270
9d74191a
TY		 6271 kvm_rip_write(vcpu, ctxt->eip);
6272 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6273 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6274 return EMULATE_DONE;
37817f29
IE		 6275}
6276EXPORT_SYMBOL_GPL(kvm_task_switch);
6277
b6c7a5dc
HB		 6278int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6279 struct kvm_sregs *sregs)
6280{
6281 int mmu_reset_needed = 0;
63f42e02 6282 int pending_vec, max_bits, idx;
89a27f4d 6283 struct desc_ptr dt;
b6c7a5dc 6284
6d1068b3
PM		 6285 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6286 return -EINVAL;
6287
89a27f4d
GN		 6288 dt.size = sregs->idt.limit;
6289 dt.address = sregs->idt.base;
b6c7a5dc 6290 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6291 dt.size = sregs->gdt.limit;
6292 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6293 kvm_x86_ops->set_gdt(vcpu, &dt);
6294
ad312c7c 6295 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6296 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6297 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6298 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6299
2d3ad1f4 6300 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6301
f6801dff 6302 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6303 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6304 kvm_set_apic_base(vcpu, sregs->apic_base);
6305
4d4ec087 6306 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6307 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6308 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6309
fc78f519 6310 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6311 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6312 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6313 kvm_update_cpuid(vcpu);
63f42e02
XG		 6314
6315 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6316 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6317 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6318 mmu_reset_needed = 1;
6319 }
63f42e02 6320 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6321
6322 if (mmu_reset_needed)
6323 kvm_mmu_reset_context(vcpu);
6324
a50abc3b 6325 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6326 pending_vec = find_first_bit(
6327 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6328 if (pending_vec < max_bits) {
66fd3f7f 6329 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6330 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6331 }
6332
3e6e0aab
GT		 6333 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6334 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6335 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6336 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6337 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6338 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6339
3e6e0aab
GT		 6340 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6341 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6342
5f0269f5
ME		 6343 update_cr8_intercept(vcpu);
6344
9c3e4aab 6345 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6346 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6347 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6348 !is_protmode(vcpu))
9c3e4aab
MT		 6349 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6350
3842d135
AK		 6351 kvm_make_request(KVM_REQ_EVENT, vcpu);
6352
b6c7a5dc
HB		 6353 return 0;
6354}
6355
d0bfb940
JK		 6356int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6357 struct kvm_guest_debug *dbg)
b6c7a5dc 6358{
355be0b9 6359 unsigned long rflags;
ae675ef0 6360 int i, r;
b6c7a5dc 6361
4f926bf2
JK		 6362 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6363 r = -EBUSY;
6364 if (vcpu->arch.exception.pending)
2122ff5e 6365 goto out;
4f926bf2
JK		 6366 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6367 kvm_queue_exception(vcpu, DB_VECTOR);
6368 else
6369 kvm_queue_exception(vcpu, BP_VECTOR);
6370 }
6371
91586a3b
JK		 6372 /*
6373 * Read rflags as long as potentially injected trace flags are still
6374 * filtered out.
6375 */
6376 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6377
6378 vcpu->guest_debug = dbg->control;
6379 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6380 vcpu->guest_debug = 0;
6381
6382 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6383 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6384 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6385 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6386 } else {
6387 for (i = 0; i < KVM_NR_DB_REGS; i++)
6388 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6389 }
c8639010 6390 kvm_update_dr7(vcpu);
ae675ef0 6391
f92653ee
JK		 6392 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6393 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6394 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6395
91586a3b
JK		 6396 /*
6397 * Trigger an rflags update that will inject or remove the trace
6398 * flags.
6399 */
6400 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6401
c8639010 6402 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6403
4f926bf2 6404 r = 0;
d0bfb940 6405
2122ff5e 6406out:
b6c7a5dc
HB		 6407
6408 return r;
6409}
6410
8b006791
ZX		 6411/*
6412 * Translate a guest virtual address to a guest physical address.
6413 */
6414int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6415 struct kvm_translation *tr)
6416{
6417 unsigned long vaddr = tr->linear_address;
6418 gpa_t gpa;
f656ce01 6419 int idx;
8b006791 6420
f656ce01 6421 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6422 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6423 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6424 tr->physical_address = gpa;
6425 tr->valid = gpa != UNMAPPED_GVA;
6426 tr->writeable = 1;
6427 tr->usermode = 0;
8b006791
ZX		 6428
6429 return 0;
6430}
6431
d0752060
HB		 6432int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6433{
98918833
SY		 6434 struct i387_fxsave_struct *fxsave =
6435 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6436
d0752060
HB		 6437 memcpy(fpu->fpr, fxsave->st_space, 128);
6438 fpu->fcw = fxsave->cwd;
6439 fpu->fsw = fxsave->swd;
6440 fpu->ftwx = fxsave->twd;
6441 fpu->last_opcode = fxsave->fop;
6442 fpu->last_ip = fxsave->rip;
6443 fpu->last_dp = fxsave->rdp;
6444 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6445
d0752060
HB		 6446 return 0;
6447}
6448
6449int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6450{
98918833
SY		 6451 struct i387_fxsave_struct *fxsave =
6452 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6453
d0752060
HB		 6454 memcpy(fxsave->st_space, fpu->fpr, 128);
6455 fxsave->cwd = fpu->fcw;
6456 fxsave->swd = fpu->fsw;
6457 fxsave->twd = fpu->ftwx;
6458 fxsave->fop = fpu->last_opcode;
6459 fxsave->rip = fpu->last_ip;
6460 fxsave->rdp = fpu->last_dp;
6461 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6462
d0752060
HB		 6463 return 0;
6464}
6465
10ab25cd 6466int fx_init(struct kvm_vcpu *vcpu)
d0752060 6467{
10ab25cd
JK		 6468 int err;
6469
6470 err = fpu_alloc(&vcpu->arch.guest_fpu);
6471 if (err)
6472 return err;
6473
98918833 6474 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6475
2acf923e
DC		 6476 /*
6477 * Ensure guest xcr0 is valid for loading
6478 */
6479 vcpu->arch.xcr0 = XSTATE_FP;
6480
ad312c7c 6481 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6482
6483 return 0;
d0752060
HB		 6484}
6485EXPORT_SYMBOL_GPL(fx_init);
6486
98918833
SY		 6487static void fx_free(struct kvm_vcpu *vcpu)
6488{
6489 fpu_free(&vcpu->arch.guest_fpu);
6490}
6491
d0752060
HB		 6492void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6493{
2608d7a1 6494 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6495 return;
6496
2acf923e
DC		 6497 /*
6498 * Restore all possible states in the guest,
6499 * and assume host would use all available bits.
6500 * Guest xcr0 would be loaded later.
6501 */
6502 kvm_put_guest_xcr0(vcpu);
d0752060 6503 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6504 __kernel_fpu_begin();
98918833 6505 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6506 trace_kvm_fpu(1);
d0752060 6507}
d0752060
HB		 6508
6509void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6510{
2acf923e
DC		 6511 kvm_put_guest_xcr0(vcpu);
6512
d0752060
HB		 6513 if (!vcpu->guest_fpu_loaded)
6514 return;
6515
6516 vcpu->guest_fpu_loaded = 0;
98918833 6517 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6518 __kernel_fpu_end();
f096ed85 6519 ++vcpu->stat.fpu_reload;
a8eeb04a 6520 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6521 trace_kvm_fpu(0);
d0752060 6522}
e9b11c17
ZX		 6523
6524void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6525{
a3e49e60
IY		 6526 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
6527
12f9a48f 6528 kvmclock_reset(vcpu);
7f1ea208 6529
98918833 6530 fx_free(vcpu);
e9b11c17 6531 kvm_x86_ops->vcpu_free(vcpu);
a3e49e60 6532 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 6533}
6534
6535struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6536 unsigned int id)
6537{
6755bae8
ZA		 6538 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6539 printk_once(KERN_WARNING
6540 "kvm: SMP vm created on host with unstable TSC; "
6541 "guest TSC will not be reliable\n");
26e5215f
AK		 6542 return kvm_x86_ops->vcpu_create(kvm, id);
6543}
e9b11c17 6544
26e5215f
AK		 6545int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6546{
6547 int r;
e9b11c17 6548
0bed3b56 6549 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6550 r = vcpu_load(vcpu);
6551 if (r)
6552 return r;
57f252f2
JK		 6553 kvm_vcpu_reset(vcpu);
6554 r = kvm_mmu_setup(vcpu);
e9b11c17 6555 vcpu_put(vcpu);
e9b11c17 6556
26e5215f 6557 return r;
e9b11c17
ZX		 6558}
6559
42897d86
MT		 6560int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6561{
6562 int r;
8fe8ab46 6563 struct msr_data msr;
42897d86
MT		 6564
6565 r = vcpu_load(vcpu);
6566 if (r)
6567 return r;
8fe8ab46
WA		 6568 msr.data = 0x0;
6569 msr.index = MSR_IA32_TSC;
6570 msr.host_initiated = true;
6571 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6572 vcpu_put(vcpu);
6573
6574 return r;
6575}
6576
d40ccc62 6577void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6578{
9fc77441 6579 int r;
344d9588
GN		 6580 vcpu->arch.apf.msr_val = 0;
6581
9fc77441
MT		 6582 r = vcpu_load(vcpu);
6583 BUG_ON(r);
e9b11c17
ZX		 6584 kvm_mmu_unload(vcpu);
6585 vcpu_put(vcpu);
6586
98918833 6587 fx_free(vcpu);
e9b11c17
ZX		 6588 kvm_x86_ops->vcpu_free(vcpu);
6589}
6590
66450a21 6591void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6592{
7460fb4a
AK		 6593 atomic_set(&vcpu->arch.nmi_queued, 0);
6594 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6595 vcpu->arch.nmi_injected = false;
6596
42dbaa5a
JK		 6597 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6598 vcpu->arch.dr6 = DR6_FIXED_1;
6599 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6600 kvm_update_dr7(vcpu);
42dbaa5a 6601
3842d135 6602 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6603 vcpu->arch.apf.msr_val = 0;
c9aaa895 6604 vcpu->arch.st.msr_val = 0;
3842d135 6605
12f9a48f
GC		 6606 kvmclock_reset(vcpu);
6607
af585b92
GN		 6608 kvm_clear_async_pf_completion_queue(vcpu);
6609 kvm_async_pf_hash_reset(vcpu);
6610 vcpu->arch.apf.halted = false;
3842d135 6611
f5132b01
GN		 6612 kvm_pmu_reset(vcpu);
6613
66f7b72e
JS		 6614 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6615 vcpu->arch.regs_avail = ~0;
6616 vcpu->arch.regs_dirty = ~0;
6617
57f252f2 6618 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6619}
6620
66450a21
JK		 6621void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6622{
6623 struct kvm_segment cs;
6624
6625 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6626 cs.selector = vector << 8;
6627 cs.base = vector << 12;
6628 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6629 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6630}
6631
10474ae8 6632int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6633{
ca84d1a2
ZA		 6634 struct kvm *kvm;
6635 struct kvm_vcpu *vcpu;
6636 int i;
0dd6a6ed
ZA		 6637 int ret;
6638 u64 local_tsc;
6639 u64 max_tsc = 0;
6640 bool stable, backwards_tsc = false;
18863bdd
AK		 6641
6642 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6643 ret = kvm_x86_ops->hardware_enable(garbage);
6644 if (ret != 0)
6645 return ret;
6646
6647 local_tsc = native_read_tsc();
6648 stable = !check_tsc_unstable();
6649 list_for_each_entry(kvm, &vm_list, vm_list) {
6650 kvm_for_each_vcpu(i, vcpu, kvm) {
6651 if (!stable && vcpu->cpu == smp_processor_id())
6652 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6653 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6654 backwards_tsc = true;
6655 if (vcpu->arch.last_host_tsc > max_tsc)
6656 max_tsc = vcpu->arch.last_host_tsc;
6657 }
6658 }
6659 }
6660
6661 /*
6662 * Sometimes, even reliable TSCs go backwards. This happens on
6663 * platforms that reset TSC during suspend or hibernate actions, but
6664 * maintain synchronization. We must compensate. Fortunately, we can
6665 * detect that condition here, which happens early in CPU bringup,
6666 * before any KVM threads can be running. Unfortunately, we can't
6667 * bring the TSCs fully up to date with real time, as we aren't yet far
6668 * enough into CPU bringup that we know how much real time has actually
6669 * elapsed; our helper function, get_kernel_ns() will be using boot
6670 * variables that haven't been updated yet.
6671 *
6672 * So we simply find the maximum observed TSC above, then record the
6673 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6674 * the adjustment will be applied. Note that we accumulate
6675 * adjustments, in case multiple suspend cycles happen before some VCPU
6676 * gets a chance to run again. In the event that no KVM threads get a
6677 * chance to run, we will miss the entire elapsed period, as we'll have
6678 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6679 * loose cycle time. This isn't too big a deal, since the loss will be
6680 * uniform across all VCPUs (not to mention the scenario is extremely
6681 * unlikely). It is possible that a second hibernate recovery happens
6682 * much faster than a first, causing the observed TSC here to be
6683 * smaller; this would require additional padding adjustment, which is
6684 * why we set last_host_tsc to the local tsc observed here.
6685 *
6686 * N.B. - this code below runs only on platforms with reliable TSC,
6687 * as that is the only way backwards_tsc is set above. Also note
6688 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6689 * have the same delta_cyc adjustment applied if backwards_tsc
6690 * is detected. Note further, this adjustment is only done once,
6691 * as we reset last_host_tsc on all VCPUs to stop this from being
6692 * called multiple times (one for each physical CPU bringup).
6693 *
4a969980 6694 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6695 * will be compensated by the logic in vcpu_load, which sets the TSC to
6696 * catchup mode. This will catchup all VCPUs to real time, but cannot
6697 * guarantee that they stay in perfect synchronization.
6698 */
6699 if (backwards_tsc) {
6700 u64 delta_cyc = max_tsc - local_tsc;
6701 list_for_each_entry(kvm, &vm_list, vm_list) {
6702 kvm_for_each_vcpu(i, vcpu, kvm) {
6703 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6704 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6705 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6706 &vcpu->requests);
0dd6a6ed
ZA		 6707 }
6708
6709 /*
6710 * We have to disable TSC offset matching.. if you were
6711 * booting a VM while issuing an S4 host suspend....
6712 * you may have some problem. Solving this issue is
6713 * left as an exercise to the reader.
6714 */
6715 kvm->arch.last_tsc_nsec = 0;
6716 kvm->arch.last_tsc_write = 0;
6717 }
6718
6719 }
6720 return 0;
e9b11c17
ZX		 6721}
6722
6723void kvm_arch_hardware_disable(void *garbage)
6724{
6725 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6726 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6727}
6728
6729int kvm_arch_hardware_setup(void)
6730{
6731 return kvm_x86_ops->hardware_setup();
6732}
6733
6734void kvm_arch_hardware_unsetup(void)
6735{
6736 kvm_x86_ops->hardware_unsetup();
6737}
6738
6739void kvm_arch_check_processor_compat(void *rtn)
6740{
6741 kvm_x86_ops->check_processor_compatibility(rtn);
6742}
6743
3e515705
AK		 6744bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6745{
6746 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6747}
6748
54e9818f
GN		 6749struct static_key kvm_no_apic_vcpu __read_mostly;
6750
e9b11c17
ZX		 6751int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6752{
6753 struct page *page;
6754 struct kvm *kvm;
6755 int r;
6756
6757 BUG_ON(vcpu->kvm == NULL);
6758 kvm = vcpu->kvm;
6759
9aabc88f 6760 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6761 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6762 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6763 else
a4535290 6764 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6765
6766 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6767 if (!page) {
6768 r = -ENOMEM;
6769 goto fail;
6770 }
ad312c7c 6771 vcpu->arch.pio_data = page_address(page);
e9b11c17 6772
cc578287 6773 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6774
e9b11c17
ZX		 6775 r = kvm_mmu_create(vcpu);
6776 if (r < 0)
6777 goto fail_free_pio_data;
6778
6779 if (irqchip_in_kernel(kvm)) {
6780 r = kvm_create_lapic(vcpu);
6781 if (r < 0)
6782 goto fail_mmu_destroy;
54e9818f
GN		 6783 } else
6784 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6785
890ca9ae
HY		 6786 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6787 GFP_KERNEL);
6788 if (!vcpu->arch.mce_banks) {
6789 r = -ENOMEM;
443c39bc 6790 goto fail_free_lapic;
890ca9ae
HY		 6791 }
6792 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6793
f1797359
WY		 6794 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6795 r = -ENOMEM;
f5f48ee1 6796 goto fail_free_mce_banks;
f1797359 6797 }
f5f48ee1 6798
66f7b72e
JS		 6799 r = fx_init(vcpu);
6800 if (r)
6801 goto fail_free_wbinvd_dirty_mask;
6802
ba904635 6803 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6804 vcpu->arch.pv_time_enabled = false;
af585b92 6805 kvm_async_pf_hash_reset(vcpu);
f5132b01 6806 kvm_pmu_init(vcpu);
af585b92 6807
e9b11c17 6808 return 0;
66f7b72e
JS		 6809fail_free_wbinvd_dirty_mask:
6810 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6811fail_free_mce_banks:
6812 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6813fail_free_lapic:
6814 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6815fail_mmu_destroy:
6816 kvm_mmu_destroy(vcpu);
6817fail_free_pio_data:
ad312c7c 6818 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6819fail:
6820 return r;
6821}
6822
6823void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6824{
f656ce01
MT		 6825 int idx;
6826
f5132b01 6827 kvm_pmu_destroy(vcpu);
36cb93fd 6828 kfree(vcpu->arch.mce_banks);
e9b11c17 6829 kvm_free_lapic(vcpu);
f656ce01 6830 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6831 kvm_mmu_destroy(vcpu);
f656ce01 6832 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6833 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6834 if (!irqchip_in_kernel(vcpu->kvm))
6835 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6836}
d19a9cd2 6837
e08b9637 6838int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6839{
e08b9637
CO		 6840 if (type)
6841 return -EINVAL;
6842
f05e70ac 6843 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6844 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6845
5550af4d
SY		 6846 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6847 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6848 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6849 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6850 &kvm->arch.irq_sources_bitmap);
5550af4d 6851
038f8c11 6852 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6853 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6854 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6855
6856 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6857
d89f5eff 6858 return 0;
d19a9cd2
ZX		 6859}
6860
6861static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6862{
9fc77441
MT		 6863 int r;
6864 r = vcpu_load(vcpu);
6865 BUG_ON(r);
d19a9cd2
ZX		 6866 kvm_mmu_unload(vcpu);
6867 vcpu_put(vcpu);
6868}
6869
6870static void kvm_free_vcpus(struct kvm *kvm)
6871{
6872 unsigned int i;
988a2cae 6873 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6874
6875 /*
6876 * Unpin any mmu pages first.
6877 */
af585b92
GN		 6878 kvm_for_each_vcpu(i, vcpu, kvm) {
6879 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6880 kvm_unload_vcpu_mmu(vcpu);
af585b92 6881 }
988a2cae
GN		 6882 kvm_for_each_vcpu(i, vcpu, kvm)
6883 kvm_arch_vcpu_free(vcpu);
6884
6885 mutex_lock(&kvm->lock);
6886 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6887 kvm->vcpus[i] = NULL;
d19a9cd2 6888
988a2cae
GN		 6889 atomic_set(&kvm->online_vcpus, 0);
6890 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6891}
6892
ad8ba2cd
SY		 6893void kvm_arch_sync_events(struct kvm *kvm)
6894{
ba4cef31 6895 kvm_free_all_assigned_devices(kvm);
aea924f6 6896 kvm_free_pit(kvm);
ad8ba2cd
SY		 6897}
6898
d19a9cd2
ZX		 6899void kvm_arch_destroy_vm(struct kvm *kvm)
6900{
27469d29
AH		 6901 if (current->mm == kvm->mm) {
6902 /*
6903 * Free memory regions allocated on behalf of userspace,
6904 * unless the the memory map has changed due to process exit
6905 * or fd copying.
6906 */
6907 struct kvm_userspace_memory_region mem;
6908 memset(&mem, 0, sizeof(mem));
6909 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6910 kvm_set_memory_region(kvm, &mem);
6911
6912 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6913 kvm_set_memory_region(kvm, &mem);
6914
6915 mem.slot = TSS_PRIVATE_MEMSLOT;
6916 kvm_set_memory_region(kvm, &mem);
6917 }
6eb55818 6918 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6919 kfree(kvm->arch.vpic);
6920 kfree(kvm->arch.vioapic);
d19a9cd2 6921 kvm_free_vcpus(kvm);
3d45830c
AK		 6922 if (kvm->arch.apic_access_page)
6923 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6924 if (kvm->arch.ept_identity_pagetable)
6925 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6926 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6927}
0de10343 6928
db3fe4eb
TY		 6929void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6930 struct kvm_memory_slot *dont)
6931{
6932 int i;
6933
d89cc617
TY		 6934 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6935 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6936 kvm_kvfree(free->arch.rmap[i]);
6937 free->arch.rmap[i] = NULL;
77d11309 6938 }
d89cc617
TY		 6939 if (i == 0)
6940 continue;
6941
6942 if (!dont || free->arch.lpage_info[i - 1] !=
6943 dont->arch.lpage_info[i - 1]) {
6944 kvm_kvfree(free->arch.lpage_info[i - 1]);
6945 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6946 }
6947 }
6948}
6949
6950int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6951{
6952 int i;
6953
d89cc617 6954 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6955 unsigned long ugfn;
6956 int lpages;
d89cc617 6957 int level = i + 1;
db3fe4eb
TY		 6958
6959 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6960 slot->base_gfn, level) + 1;
6961
d89cc617
TY		 6962 slot->arch.rmap[i] =
6963 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6964 if (!slot->arch.rmap[i])
77d11309 6965 goto out_free;
d89cc617
TY		 6966 if (i == 0)
6967 continue;
77d11309 6968
d89cc617
TY		 6969 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6970 sizeof(*slot->arch.lpage_info[i - 1]));
6971 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6972 goto out_free;
6973
6974 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6975 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6976 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6977 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6978 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6979 /*
6980 * If the gfn and userspace address are not aligned wrt each
6981 * other, or if explicitly asked to, disable large page
6982 * support for this slot
6983 */
6984 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6985 !kvm_largepages_enabled()) {
6986 unsigned long j;
6987
6988 for (j = 0; j < lpages; ++j)
d89cc617 6989 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6990 }
6991 }
6992
6993 return 0;
6994
6995out_free:
d89cc617
TY		 6996 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6997 kvm_kvfree(slot->arch.rmap[i]);
6998 slot->arch.rmap[i] = NULL;
6999 if (i == 0)
7000 continue;
7001
7002 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7003 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7004 }
7005 return -ENOMEM;
7006}
7007
f7784b8e
MT		 7008int kvm_arch_prepare_memory_region(struct kvm *kvm,
7009 struct kvm_memory_slot *memslot,
f7784b8e 7010 struct kvm_userspace_memory_region *mem,
7b6195a9 7011 enum kvm_mr_change change)
0de10343 7012{
7a905b14
TY		 7013 /*
7014 * Only private memory slots need to be mapped here since
7015 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7016 */
7b6195a9 7017 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7018 unsigned long userspace_addr;
604b38ac 7019
7a905b14
TY		 7020 /*
7021 * MAP_SHARED to prevent internal slot pages from being moved
7022 * by fork()/COW.
7023 */
7b6195a9 7024 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7025 PROT_READ | PROT_WRITE,
7026 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7027
7a905b14
TY		 7028 if (IS_ERR((void *)userspace_addr))
7029 return PTR_ERR((void *)userspace_addr);
604b38ac 7030
7a905b14 7031 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7032 }
7033
f7784b8e
MT		 7034 return 0;
7035}
7036
7037void kvm_arch_commit_memory_region(struct kvm *kvm,
7038 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7039 const struct kvm_memory_slot *old,
7040 enum kvm_mr_change change)
f7784b8e
MT		 7041{
7042
8482644a 7043 int nr_mmu_pages = 0;
f7784b8e 7044
8482644a 7045 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7046 int ret;
7047
8482644a
TY		 7048 ret = vm_munmap(old->userspace_addr,
7049 old->npages * PAGE_SIZE);
f7784b8e
MT		 7050 if (ret < 0)
7051 printk(KERN_WARNING
7052 "kvm_vm_ioctl_set_memory_region: "
7053 "failed to munmap memory\n");
7054 }
7055
48c0e4e9
XG		 7056 if (!kvm->arch.n_requested_mmu_pages)
7057 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7058
48c0e4e9 7059 if (nr_mmu_pages)
0de10343 7060 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7061 /*
7062 * Write protect all pages for dirty logging.
7063 * Existing largepage mappings are destroyed here and new ones will
7064 * not be created until the end of the logging.
7065 */
8482644a 7066 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7067 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 7068 /*
7069 * If memory slot is created, or moved, we need to clear all
7070 * mmio sptes.
7071 */
8482644a 7072 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
982b3394 7073 kvm_mmu_zap_mmio_sptes(kvm);
3b4dc3a0
MT		 7074 kvm_reload_remote_mmus(kvm);
7075 }
0de10343 7076}
1d737c8a 7077
2df72e9b 7078void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 7079{
7080 kvm_mmu_zap_all(kvm);
8986ecc0 7081 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 7082}
7083
2df72e9b
MT		 7084void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7085 struct kvm_memory_slot *slot)
7086{
7087 kvm_arch_flush_shadow_all(kvm);
7088}
7089
1d737c8a
ZX		 7090int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7091{
af585b92
GN		 7092 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7093 !vcpu->arch.apf.halted)
7094 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7095 || kvm_apic_has_events(vcpu)
7460fb4a 7096 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7097 (kvm_arch_interrupt_allowed(vcpu) &&
7098 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7099}
5736199a 7100
b6d33834 7101int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7102{
b6d33834 7103 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7104}
78646121
GN		 7105
7106int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7107{
7108 return kvm_x86_ops->interrupt_allowed(vcpu);
7109}
229456fc 7110
f92653ee
JK		 7111bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7112{
7113 unsigned long current_rip = kvm_rip_read(vcpu) +
7114 get_segment_base(vcpu, VCPU_SREG_CS);
7115
7116 return current_rip == linear_rip;
7117}
7118EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7119
94fe45da
JK		 7120unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7121{
7122 unsigned long rflags;
7123
7124 rflags = kvm_x86_ops->get_rflags(vcpu);
7125 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7126 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7127 return rflags;
7128}
7129EXPORT_SYMBOL_GPL(kvm_get_rflags);
7130
7131void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7132{
7133 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7134 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7135 rflags |= X86_EFLAGS_TF;
94fe45da 7136 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7137 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7138}
7139EXPORT_SYMBOL_GPL(kvm_set_rflags);
7140
56028d08
GN		 7141void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7142{
7143 int r;
7144
fb67e14f 7145 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7146 is_error_page(work->page))
56028d08
GN		 7147 return;
7148
7149 r = kvm_mmu_reload(vcpu);
7150 if (unlikely(r))
7151 return;
7152
fb67e14f
XG		 7153 if (!vcpu->arch.mmu.direct_map &&
7154 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7155 return;
7156
56028d08
GN		 7157 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7158}
7159
af585b92
GN		 7160static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7161{
7162 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7163}
7164
7165static inline u32 kvm_async_pf_next_probe(u32 key)
7166{
7167 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7168}
7169
7170static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7171{
7172 u32 key = kvm_async_pf_hash_fn(gfn);
7173
7174 while (vcpu->arch.apf.gfns[key] != ~0)
7175 key = kvm_async_pf_next_probe(key);
7176
7177 vcpu->arch.apf.gfns[key] = gfn;
7178}
7179
7180static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7181{
7182 int i;
7183 u32 key = kvm_async_pf_hash_fn(gfn);
7184
7185 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7186 (vcpu->arch.apf.gfns[key] != gfn &&
7187 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7188 key = kvm_async_pf_next_probe(key);
7189
7190 return key;
7191}
7192
7193bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7194{
7195 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7196}
7197
7198static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7199{
7200 u32 i, j, k;
7201
7202 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7203 while (true) {
7204 vcpu->arch.apf.gfns[i] = ~0;
7205 do {
7206 j = kvm_async_pf_next_probe(j);
7207 if (vcpu->arch.apf.gfns[j] == ~0)
7208 return;
7209 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7210 /*
7211 * k lies cyclically in ]i,j]
7212 * | i.k.j |
7213 * |....j i.k.| or |.k..j i...|
7214 */
7215 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7216 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7217 i = j;
7218 }
7219}
7220
7c90705b
GN		 7221static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7222{
7223
7224 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7225 sizeof(val));
7226}
7227
af585b92
GN		 7228void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7229 struct kvm_async_pf *work)
7230{
6389ee94
AK		 7231 struct x86_exception fault;
7232
7c90705b 7233 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7234 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7235
7236 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7237 (vcpu->arch.apf.send_user_only &&
7238 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7239 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7240 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7241 fault.vector = PF_VECTOR;
7242 fault.error_code_valid = true;
7243 fault.error_code = 0;
7244 fault.nested_page_fault = false;
7245 fault.address = work->arch.token;
7246 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7247 }
af585b92
GN		 7248}
7249
7250void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7251 struct kvm_async_pf *work)
7252{
6389ee94
AK		 7253 struct x86_exception fault;
7254
7c90705b
GN		 7255 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7256 if (is_error_page(work->page))
7257 work->arch.token = ~0; /* broadcast wakeup */
7258 else
7259 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7260
7261 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7262 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7263 fault.vector = PF_VECTOR;
7264 fault.error_code_valid = true;
7265 fault.error_code = 0;
7266 fault.nested_page_fault = false;
7267 fault.address = work->arch.token;
7268 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7269 }
e6d53e3b 7270 vcpu->arch.apf.halted = false;
a4fa1635 7271 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7272}
7273
7274bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7275{
7276 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7277 return true;
7278 else
7279 return !kvm_event_needs_reinjection(vcpu) &&
7280 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7281}
7282
229456fc
MT		 7283EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7284EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7285EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7286EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7287EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7288EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7289EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7290EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7291EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7292EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7293EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7294EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)