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Merge tag 'v3.10.107' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
\8dmáÅ\99, 2016-08-08 20:16:23 +0200">a0753a8c 369 bool change_vmcs01_virtual_x2apic_mode;
644d711a
NHE		 370 /* L2 must run next, and mustn't decide to exit to L1. */
371 bool nested_run_pending;
fe3ef05c
NHE		 372 /*
373 * Guest pages referred to in vmcs02 with host-physical pointers, so
374 * we must keep them pinned while L2 runs.
375 */
376 struct page *apic_access_page;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
747a43ad 442 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 443 } host_state;
9c8cba37 444 struct {
7ffd92c5 445 int vm86_active;
78ac8b47 446 ulong save_rflags;
f5f7b2fe
AK		 447 struct kvm_segment segs[8];
448 } rmode;
449 struct {
450 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 451 struct kvm_save_segment {
452 u16 selector;
453 unsigned long base;
454 u32 limit;
455 u32 ar;
f5f7b2fe 456 } seg[8];
2fb92db1 457 } segment_cache;
2384d2b3 458 int vpid;
04fa4d32 459 bool emulation_required;
3b86cd99
JK		 460
461 /* Support for vnmi-less CPUs */
462 int soft_vnmi_blocked;
463 ktime_t entry_time;
464 s64 vnmi_blocked_time;
a0861c02 465 u32 exit_reason;
4e47c7a6
SY		 466
467 bool rdtscp_enabled;
ec378aee 468
01e439be
YZ		 469 /* Posted interrupt descriptor */
470 struct pi_desc pi_desc;
471
ec378aee
NHE		 472 /* Support for a guest hypervisor (nested VMX) */
473 struct nested_vmx nested;
a2fa3e9f
GH		 474};
475
2fb92db1
AK		 476enum segment_cache_field {
477 SEG_FIELD_SEL = 0,
478 SEG_FIELD_BASE = 1,
479 SEG_FIELD_LIMIT = 2,
480 SEG_FIELD_AR = 3,
481
482 SEG_FIELD_NR = 4
483};
484
a2fa3e9f
GH		 485static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
486{
fb3f0f51 487 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 488}
489
22bd0358
NHE		 490#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
491#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
492#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
493 [number##_HIGH] = VMCS12_OFFSET(name)+4
494
4607c2d7
AG		 495
496static const unsigned long shadow_read_only_fields[] = {
497 /*
498 * We do NOT shadow fields that are modified when L0
499 * traps and emulates any vmx instruction (e.g. VMPTRLD,
500 * VMXON...) executed by L1.
501 * For example, VM_INSTRUCTION_ERROR is read
502 * by L1 if a vmx instruction fails (part of the error path).
503 * Note the code assumes this logic. If for some reason
504 * we start shadowing these fields then we need to
505 * force a shadow sync when L0 emulates vmx instructions
506 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
507 * by nested_vmx_failValid)
508 */
509 VM_EXIT_REASON,
510 VM_EXIT_INTR_INFO,
511 VM_EXIT_INSTRUCTION_LEN,
512 IDT_VECTORING_INFO_FIELD,
513 IDT_VECTORING_ERROR_CODE,
514 VM_EXIT_INTR_ERROR_CODE,
515 EXIT_QUALIFICATION,
516 GUEST_LINEAR_ADDRESS,
517 GUEST_PHYSICAL_ADDRESS
518};
519static const int max_shadow_read_only_fields =
520 ARRAY_SIZE(shadow_read_only_fields);
521
522static const unsigned long shadow_read_write_fields[] = {
523 GUEST_RIP,
524 GUEST_RSP,
525 GUEST_CR0,
526 GUEST_CR3,
527 GUEST_CR4,
528 GUEST_INTERRUPTIBILITY_INFO,
529 GUEST_RFLAGS,
530 GUEST_CS_SELECTOR,
531 GUEST_CS_AR_BYTES,
532 GUEST_CS_LIMIT,
533 GUEST_CS_BASE,
534 GUEST_ES_BASE,
535 CR0_GUEST_HOST_MASK,
536 CR0_READ_SHADOW,
537 CR4_READ_SHADOW,
538 TSC_OFFSET,
539 EXCEPTION_BITMAP,
540 CPU_BASED_VM_EXEC_CONTROL,
541 VM_ENTRY_EXCEPTION_ERROR_CODE,
542 VM_ENTRY_INTR_INFO_FIELD,
543 VM_ENTRY_INSTRUCTION_LEN,
544 VM_ENTRY_EXCEPTION_ERROR_CODE,
545 HOST_FS_BASE,
546 HOST_GS_BASE,
547 HOST_FS_SELECTOR,
548 HOST_GS_SELECTOR
549};
550static const int max_shadow_read_write_fields =
551 ARRAY_SIZE(shadow_read_write_fields);
552
772e0318 553static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 554 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
555 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
556 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
557 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
558 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
559 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
560 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
561 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
562 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
563 FIELD(HOST_ES_SELECTOR, host_es_selector),
564 FIELD(HOST_CS_SELECTOR, host_cs_selector),
565 FIELD(HOST_SS_SELECTOR, host_ss_selector),
566 FIELD(HOST_DS_SELECTOR, host_ds_selector),
567 FIELD(HOST_FS_SELECTOR, host_fs_selector),
568 FIELD(HOST_GS_SELECTOR, host_gs_selector),
569 FIELD(HOST_TR_SELECTOR, host_tr_selector),
570 FIELD64(IO_BITMAP_A, io_bitmap_a),
571 FIELD64(IO_BITMAP_B, io_bitmap_b),
572 FIELD64(MSR_BITMAP, msr_bitmap),
573 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
574 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
575 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
576 FIELD64(TSC_OFFSET, tsc_offset),
577 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
578 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
579 FIELD64(EPT_POINTER, ept_pointer),
580 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
581 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
582 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
583 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
584 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
585 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
586 FIELD64(GUEST_PDPTR0, guest_pdptr0),
587 FIELD64(GUEST_PDPTR1, guest_pdptr1),
588 FIELD64(GUEST_PDPTR2, guest_pdptr2),
589 FIELD64(GUEST_PDPTR3, guest_pdptr3),
590 FIELD64(HOST_IA32_PAT, host_ia32_pat),
591 FIELD64(HOST_IA32_EFER, host_ia32_efer),
592 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
593 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
594 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
595 FIELD(EXCEPTION_BITMAP, exception_bitmap),
596 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
597 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
598 FIELD(CR3_TARGET_COUNT, cr3_target_count),
599 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
600 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
601 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
602 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
603 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
604 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
605 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
606 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
607 FIELD(TPR_THRESHOLD, tpr_threshold),
608 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
609 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
610 FIELD(VM_EXIT_REASON, vm_exit_reason),
611 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
612 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
613 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
614 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
615 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
616 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
617 FIELD(GUEST_ES_LIMIT, guest_es_limit),
618 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
619 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
620 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
621 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
622 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
623 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
624 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
625 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
626 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
627 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
628 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
629 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
630 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
631 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
632 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
633 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
634 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
635 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
636 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
637 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
638 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 639 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 640 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
641 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
642 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
643 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
644 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
645 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
646 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
647 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
648 FIELD(EXIT_QUALIFICATION, exit_qualification),
649 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
650 FIELD(GUEST_CR0, guest_cr0),
651 FIELD(GUEST_CR3, guest_cr3),
652 FIELD(GUEST_CR4, guest_cr4),
653 FIELD(GUEST_ES_BASE, guest_es_base),
654 FIELD(GUEST_CS_BASE, guest_cs_base),
655 FIELD(GUEST_SS_BASE, guest_ss_base),
656 FIELD(GUEST_DS_BASE, guest_ds_base),
657 FIELD(GUEST_FS_BASE, guest_fs_base),
658 FIELD(GUEST_GS_BASE, guest_gs_base),
659 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
660 FIELD(GUEST_TR_BASE, guest_tr_base),
661 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
662 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
663 FIELD(GUEST_DR7, guest_dr7),
664 FIELD(GUEST_RSP, guest_rsp),
665 FIELD(GUEST_RIP, guest_rip),
666 FIELD(GUEST_RFLAGS, guest_rflags),
667 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
668 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
669 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
670 FIELD(HOST_CR0, host_cr0),
671 FIELD(HOST_CR3, host_cr3),
672 FIELD(HOST_CR4, host_cr4),
673 FIELD(HOST_FS_BASE, host_fs_base),
674 FIELD(HOST_GS_BASE, host_gs_base),
675 FIELD(HOST_TR_BASE, host_tr_base),
676 FIELD(HOST_GDTR_BASE, host_gdtr_base),
677 FIELD(HOST_IDTR_BASE, host_idtr_base),
678 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
679 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
680 FIELD(HOST_RSP, host_rsp),
681 FIELD(HOST_RIP, host_rip),
682};
683static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
684
685static inline short vmcs_field_to_offset(unsigned long field)
686{
687 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
688 return -1;
689 return vmcs_field_to_offset_table[field];
690}
691
a9d30f33
NHE		 692static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
693{
694 return to_vmx(vcpu)->nested.current_vmcs12;
695}
696
697static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
698{
699 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 700 if (is_error_page(page))
a9d30f33 701 return NULL;
32cad84f 702
a9d30f33
NHE		 703 return page;
704}
705
706static void nested_release_page(struct page *page)
707{
708 kvm_release_page_dirty(page);
709}
710
711static void nested_release_page_clean(struct page *page)
712{
713 kvm_release_page_clean(page);
714}
715
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
aff48baa 719static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 720static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 721static void vmx_set_segment(struct kvm_vcpu *vcpu,
722 struct kvm_segment *var, int seg);
723static void vmx_get_segment(struct kvm_vcpu *vcpu,
724 struct kvm_segment *var, int seg);
d99e4152
GN		 725static bool guest_state_valid(struct kvm_vcpu *vcpu);
726static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 727static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 728static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 729static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 730
6aa8b732
AK		 731static DEFINE_PER_CPU(struct vmcs *, vmxarea);
732static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 733/*
734 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
735 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
736 */
737static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 738static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 739
3e7c73e9
AK		 740static unsigned long *vmx_io_bitmap_a;
741static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 742static unsigned long *vmx_msr_bitmap_legacy;
743static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 744static unsigned long *vmx_msr_bitmap_legacy_x2apic;
745static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 746static unsigned long *vmx_vmread_bitmap;
747static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 748
110312c8 749static bool cpu_has_load_ia32_efer;
8bf00a52 750static bool cpu_has_load_perf_global_ctrl;
110312c8 751
2384d2b3
SY		 752static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
753static DEFINE_SPINLOCK(vmx_vpid_lock);
754
1c3d14fe 755static struct vmcs_config {
6aa8b732
AK		 756 int size;
757 int order;
758 u32 revision_id;
1c3d14fe
YS		 759 u32 pin_based_exec_ctrl;
760 u32 cpu_based_exec_ctrl;
f78e0e2e 761 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 762 u32 vmexit_ctrl;
763 u32 vmentry_ctrl;
764} vmcs_config;
6aa8b732 765
efff9e53 766static struct vmx_capability {
d56f546d
SY		 767 u32 ept;
768 u32 vpid;
769} vmx_capability;
770
6aa8b732
AK		 771#define VMX_SEGMENT_FIELD(seg) \
772 [VCPU_SREG_##seg] = { \
773 .selector = GUEST_##seg##_SELECTOR, \
774 .base = GUEST_##seg##_BASE, \
775 .limit = GUEST_##seg##_LIMIT, \
776 .ar_bytes = GUEST_##seg##_AR_BYTES, \
777 }
778
772e0318 779static const struct kvm_vmx_segment_field {
6aa8b732
AK		 780 unsigned selector;
781 unsigned base;
782 unsigned limit;
783 unsigned ar_bytes;
784} kvm_vmx_segment_fields[] = {
785 VMX_SEGMENT_FIELD(CS),
786 VMX_SEGMENT_FIELD(DS),
787 VMX_SEGMENT_FIELD(ES),
788 VMX_SEGMENT_FIELD(FS),
789 VMX_SEGMENT_FIELD(GS),
790 VMX_SEGMENT_FIELD(SS),
791 VMX_SEGMENT_FIELD(TR),
792 VMX_SEGMENT_FIELD(LDTR),
793};
794
26bb0981
AK		 795static u64 host_efer;
796
6de4f3ad
AK		 797static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
798
4d56c8a7 799/*
8c06585d 800 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 801 * away by decrementing the array size.
802 */
6aa8b732 803static const u32 vmx_msr_index[] = {
05b3e0c2 804#ifdef CONFIG_X86_64
44ea2b17 805 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 806#endif
8c06585d 807 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 808};
9d8f549d 809#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 810
31299944 811static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 812{
813 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
814 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 815 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 816}
817
31299944 818static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 819{
820 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
821 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 822 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 823}
824
31299944 825static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 829 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 830}
831
31299944 832static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 833{
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
835 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
836}
837
31299944 838static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 839{
840 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
841 INTR_INFO_VALID_MASK)) ==
842 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
843}
844
31299944 845static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 846{
04547156 847 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 848}
849
31299944 850static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 851{
04547156 852 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 853}
854
31299944 855static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 856{
04547156 857 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 858}
859
31299944 860static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 861{
04547156
SY		 862 return vmcs_config.cpu_based_exec_ctrl &
863 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 864}
865
774ead3a 866static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 867{
04547156
SY		 868 return vmcs_config.cpu_based_2nd_exec_ctrl &
869 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
870}
871
8d14695f
YZ		 872static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
873{
874 return vmcs_config.cpu_based_2nd_exec_ctrl &
875 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
876}
877
83d4c286
YZ		 878static inline bool cpu_has_vmx_apic_register_virt(void)
879{
880 return vmcs_config.cpu_based_2nd_exec_ctrl &
881 SECONDARY_EXEC_APIC_REGISTER_VIRT;
882}
883
c7c9c56c
YZ		 884static inline bool cpu_has_vmx_virtual_intr_delivery(void)
885{
886 return vmcs_config.cpu_based_2nd_exec_ctrl &
887 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
888}
889
01e439be
YZ		 890static inline bool cpu_has_vmx_posted_intr(void)
891{
892 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
893}
894
895static inline bool cpu_has_vmx_apicv(void)
896{
897 return cpu_has_vmx_apic_register_virt() &&
898 cpu_has_vmx_virtual_intr_delivery() &&
899 cpu_has_vmx_posted_intr();
900}
901
04547156
SY		 902static inline bool cpu_has_vmx_flexpriority(void)
903{
904 return cpu_has_vmx_tpr_shadow() &&
905 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 906}
907
e799794e
MT		 908static inline bool cpu_has_vmx_ept_execute_only(void)
909{
31299944 910 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 911}
912
913static inline bool cpu_has_vmx_eptp_uncacheable(void)
914{
31299944 915 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 916}
917
918static inline bool cpu_has_vmx_eptp_writeback(void)
919{
31299944 920 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 921}
922
923static inline bool cpu_has_vmx_ept_2m_page(void)
924{
31299944 925 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 926}
927
878403b7
SY		 928static inline bool cpu_has_vmx_ept_1g_page(void)
929{
31299944 930 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 931}
932
4bc9b982
SY		 933static inline bool cpu_has_vmx_ept_4levels(void)
934{
935 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
936}
937
83c3a331
XH		 938static inline bool cpu_has_vmx_ept_ad_bits(void)
939{
940 return vmx_capability.ept & VMX_EPT_AD_BIT;
941}
942
31299944 943static inline bool cpu_has_vmx_invept_context(void)
d56f546d 944{
31299944 945 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 946}
947
31299944 948static inline bool cpu_has_vmx_invept_global(void)
d56f546d 949{
31299944 950 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 951}
952
518c8aee
GJ		 953static inline bool cpu_has_vmx_invvpid_single(void)
954{
955 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
956}
957
b9d762fa
GJ		 958static inline bool cpu_has_vmx_invvpid_global(void)
959{
960 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
961}
962
31299944 963static inline bool cpu_has_vmx_ept(void)
d56f546d 964{
04547156
SY		 965 return vmcs_config.cpu_based_2nd_exec_ctrl &
966 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 967}
968
31299944 969static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 970{
971 return vmcs_config.cpu_based_2nd_exec_ctrl &
972 SECONDARY_EXEC_UNRESTRICTED_GUEST;
973}
974
31299944 975static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 976{
977 return vmcs_config.cpu_based_2nd_exec_ctrl &
978 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
979}
980
31299944 981static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 982{
6d3e435e 983 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 984}
985
31299944 986static inline bool cpu_has_vmx_vpid(void)
2384d2b3 987{
04547156
SY		 988 return vmcs_config.cpu_based_2nd_exec_ctrl &
989 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 990}
991
31299944 992static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 993{
994 return vmcs_config.cpu_based_2nd_exec_ctrl &
995 SECONDARY_EXEC_RDTSCP;
996}
997
ad756a16
MJ		 998static inline bool cpu_has_vmx_invpcid(void)
999{
1000 return vmcs_config.cpu_based_2nd_exec_ctrl &
1001 SECONDARY_EXEC_ENABLE_INVPCID;
1002}
1003
31299944 1004static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1005{
1006 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1007}
1008
f5f48ee1
SY		 1009static inline bool cpu_has_vmx_wbinvd_exit(void)
1010{
1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_WBINVD_EXITING;
1013}
1014
abc4fc58
AG		 1015static inline bool cpu_has_vmx_shadow_vmcs(void)
1016{
1017 u64 vmx_msr;
1018 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1019 /* check if the cpu supports writing r/o exit information fields */
1020 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1021 return false;
1022
1023 return vmcs_config.cpu_based_2nd_exec_ctrl &
1024 SECONDARY_EXEC_SHADOW_VMCS;
1025}
1026
04547156
SY		 1027static inline bool report_flexpriority(void)
1028{
1029 return flexpriority_enabled;
1030}
1031
fe3ef05c
NHE		 1032static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1033{
1034 return vmcs12->cpu_based_vm_exec_control & bit;
1035}
1036
1037static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1038{
1039 return (vmcs12->cpu_based_vm_exec_control &
1040 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1041 (vmcs12->secondary_vm_exec_control & bit);
1042}
1043
644d711a
NHE		 1044static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1045 struct kvm_vcpu *vcpu)
1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
58e4633a 1050static inline bool is_nmi(u32 intr_info)
644d711a
NHE		 1051{
1052 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
58e4633a 1053 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
644d711a
NHE		 1054}
1055
1056static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1057static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1058 struct vmcs12 *vmcs12,
1059 u32 reason, unsigned long qualification);
1060
8b9cf98c 1061static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1062{
1063 int i;
1064
a2fa3e9f 1065 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1066 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1067 return i;
1068 return -1;
1069}
1070
2384d2b3
SY		 1071static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1072{
1073 struct {
1074 u64 vpid : 16;
1075 u64 rsvd : 48;
1076 u64 gva;
1077 } operand = { vpid, 0, gva };
1078
4ecac3fd 1079 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1080 /* CF==1 or ZF==1 --> rc = -1 */
1081 "; ja 1f ; ud2 ; 1:"
1082 : : "a"(&operand), "c"(ext) : "cc", "memory");
1083}
1084
1439442c
SY		 1085static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1086{
1087 struct {
1088 u64 eptp, gpa;
1089 } operand = {eptp, gpa};
1090
4ecac3fd 1091 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1092 /* CF==1 or ZF==1 --> rc = -1 */
1093 "; ja 1f ; ud2 ; 1:\n"
1094 : : "a" (&operand), "c" (ext) : "cc", "memory");
1095}
1096
26bb0981 1097static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1098{
1099 int i;
1100
8b9cf98c 1101 i = __find_msr_index(vmx, msr);
a75beee6 1102 if (i >= 0)
a2fa3e9f 1103 return &vmx->guest_msrs[i];
8b6d44c7 1104 return NULL;
7725f0ba
AK		 1105}
1106
6aa8b732
AK		 1107static void vmcs_clear(struct vmcs *vmcs)
1108{
1109 u64 phys_addr = __pa(vmcs);
1110 u8 error;
1111
4ecac3fd 1112 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1113 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1114 : "cc", "memory");
1115 if (error)
1116 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1117 vmcs, phys_addr);
1118}
1119
d462b819
NHE		 1120static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1121{
1122 vmcs_clear(loaded_vmcs->vmcs);
1123 loaded_vmcs->cpu = -1;
1124 loaded_vmcs->launched = 0;
1125}
1126
7725b894
DX		 1127static void vmcs_load(struct vmcs *vmcs)
1128{
1129 u64 phys_addr = __pa(vmcs);
1130 u8 error;
1131
1132 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1133 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1134 : "cc", "memory");
1135 if (error)
2844d849 1136 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1137 vmcs, phys_addr);
1138}
1139
8f536b76
ZY		 1140#ifdef CONFIG_KEXEC
1141/*
1142 * This bitmap is used to indicate whether the vmclear
1143 * operation is enabled on all cpus. All disabled by
1144 * default.
1145 */
1146static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1147
1148static inline void crash_enable_local_vmclear(int cpu)
1149{
1150 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1151}
1152
1153static inline void crash_disable_local_vmclear(int cpu)
1154{
1155 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156}
1157
1158static inline int crash_local_vmclear_enabled(int cpu)
1159{
1160 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161}
1162
1163static void crash_vmclear_local_loaded_vmcss(void)
1164{
1165 int cpu = raw_smp_processor_id();
1166 struct loaded_vmcs *v;
1167
1168 if (!crash_local_vmclear_enabled(cpu))
1169 return;
1170
1171 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1172 loaded_vmcss_on_cpu_link)
1173 vmcs_clear(v->vmcs);
1174}
1175#else
1176static inline void crash_enable_local_vmclear(int cpu) { }
1177static inline void crash_disable_local_vmclear(int cpu) { }
1178#endif /* CONFIG_KEXEC */
1179
d462b819 1180static void __loaded_vmcs_clear(void *arg)
6aa8b732 1181{
d462b819 1182 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1183 int cpu = raw_smp_processor_id();
6aa8b732 1184
d462b819
NHE		 1185 if (loaded_vmcs->cpu != cpu)
1186 return; /* vcpu migration can race with cpu offline */
1187 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1188 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1189 crash_disable_local_vmclear(cpu);
d462b819 1190 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1191
1192 /*
1193 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1194 * is before setting loaded_vmcs->vcpu to -1 which is done in
1195 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1196 * then adds the vmcs into percpu list before it is deleted.
1197 */
1198 smp_wmb();
1199
d462b819 1200 loaded_vmcs_init(loaded_vmcs);
8f536b76 1201 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1202}
1203
d462b819 1204static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1205{
e6c7d321
XG		 1206 int cpu = loaded_vmcs->cpu;
1207
1208 if (cpu != -1)
1209 smp_call_function_single(cpu,
1210 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1211}
1212
1760dd49 1213static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1214{
1215 if (vmx->vpid == 0)
1216 return;
1217
518c8aee
GJ		 1218 if (cpu_has_vmx_invvpid_single())
1219 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1220}
1221
b9d762fa
GJ		 1222static inline void vpid_sync_vcpu_global(void)
1223{
1224 if (cpu_has_vmx_invvpid_global())
1225 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1226}
1227
1228static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1229{
1230 if (cpu_has_vmx_invvpid_single())
1760dd49 1231 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1232 else
1233 vpid_sync_vcpu_global();
1234}
1235
1439442c
SY		 1236static inline void ept_sync_global(void)
1237{
1238 if (cpu_has_vmx_invept_global())
1239 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1240}
1241
1242static inline void ept_sync_context(u64 eptp)
1243{
089d034e 1244 if (enable_ept) {
1439442c
SY		 1245 if (cpu_has_vmx_invept_context())
1246 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1247 else
1248 ept_sync_global();
1249 }
1250}
1251
96304217 1252static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1253{
5e520e62 1254 unsigned long value;
6aa8b732 1255
5e520e62
AK		 1256 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1257 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1258 return value;
1259}
1260
96304217 1261static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1262{
1263 return vmcs_readl(field);
1264}
1265
96304217 1266static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1267{
1268 return vmcs_readl(field);
1269}
1270
96304217 1271static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1272{
05b3e0c2 1273#ifdef CONFIG_X86_64
6aa8b732
AK		 1274 return vmcs_readl(field);
1275#else
1276 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1277#endif
1278}
1279
e52de1b8
AK		 1280static noinline void vmwrite_error(unsigned long field, unsigned long value)
1281{
1282 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1283 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1284 dump_stack();
1285}
1286
6aa8b732
AK		 1287static void vmcs_writel(unsigned long field, unsigned long value)
1288{
1289 u8 error;
1290
4ecac3fd 1291 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1292 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1293 if (unlikely(error))
1294 vmwrite_error(field, value);
6aa8b732
AK		 1295}
1296
1297static void vmcs_write16(unsigned long field, u16 value)
1298{
1299 vmcs_writel(field, value);
1300}
1301
1302static void vmcs_write32(unsigned long field, u32 value)
1303{
1304 vmcs_writel(field, value);
1305}
1306
1307static void vmcs_write64(unsigned long field, u64 value)
1308{
6aa8b732 1309 vmcs_writel(field, value);
7682f2d0 1310#ifndef CONFIG_X86_64
6aa8b732
AK		 1311 asm volatile ("");
1312 vmcs_writel(field+1, value >> 32);
1313#endif
1314}
1315
2ab455cc
AL		 1316static void vmcs_clear_bits(unsigned long field, u32 mask)
1317{
1318 vmcs_writel(field, vmcs_readl(field) & ~mask);
1319}
1320
1321static void vmcs_set_bits(unsigned long field, u32 mask)
1322{
1323 vmcs_writel(field, vmcs_readl(field) | mask);
1324}
1325
2fb92db1
AK		 1326static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1327{
1328 vmx->segment_cache.bitmask = 0;
1329}
1330
1331static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1332 unsigned field)
1333{
1334 bool ret;
1335 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1336
1337 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1338 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1339 vmx->segment_cache.bitmask = 0;
1340 }
1341 ret = vmx->segment_cache.bitmask & mask;
1342 vmx->segment_cache.bitmask |= mask;
1343 return ret;
1344}
1345
1346static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1347{
1348 u16 *p = &vmx->segment_cache.seg[seg].selector;
1349
1350 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1351 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1352 return *p;
1353}
1354
1355static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1356{
1357 ulong *p = &vmx->segment_cache.seg[seg].base;
1358
1359 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1360 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1361 return *p;
1362}
1363
1364static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1365{
1366 u32 *p = &vmx->segment_cache.seg[seg].limit;
1367
1368 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1369 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1370 return *p;
1371}
1372
1373static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1374{
1375 u32 *p = &vmx->segment_cache.seg[seg].ar;
1376
1377 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1378 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1379 return *p;
1380}
1381
abd3f2d6
AK		 1382static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1383{
1384 u32 eb;
1385
fd7373cc
JK		 1386 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1387 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1388 if ((vcpu->guest_debug &
1389 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1390 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1391 eb |= 1u << BP_VECTOR;
7ffd92c5 1392 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1393 eb = ~0;
089d034e 1394 if (enable_ept)
1439442c 1395 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1396 if (vcpu->fpu_active)
1397 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1398
1399 /* When we are running a nested L2 guest and L1 specified for it a
1400 * certain exception bitmap, we must trap the same exceptions and pass
1401 * them to L1. When running L2, we will only handle the exceptions
1402 * specified above if L1 did not want them.
1403 */
1404 if (is_guest_mode(vcpu))
1405 eb |= get_vmcs12(vcpu)->exception_bitmap;
1406
abd3f2d6
AK		 1407 vmcs_write32(EXCEPTION_BITMAP, eb);
1408}
1409
8bf00a52
GN		 1410static void clear_atomic_switch_msr_special(unsigned long entry,
1411 unsigned long exit)
1412{
1413 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1414 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1415}
1416
61d2ef2c
AK		 1417static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1418{
1419 unsigned i;
1420 struct msr_autoload *m = &vmx->msr_autoload;
1421
8bf00a52
GN		 1422 switch (msr) {
1423 case MSR_EFER:
1424 if (cpu_has_load_ia32_efer) {
1425 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1426 VM_EXIT_LOAD_IA32_EFER);
1427 return;
1428 }
1429 break;
1430 case MSR_CORE_PERF_GLOBAL_CTRL:
1431 if (cpu_has_load_perf_global_ctrl) {
1432 clear_atomic_switch_msr_special(
1433 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1434 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1435 return;
1436 }
1437 break;
110312c8
AK		 1438 }
1439
61d2ef2c
AK		 1440 for (i = 0; i < m->nr; ++i)
1441 if (m->guest[i].index == msr)
1442 break;
1443
1444 if (i == m->nr)
1445 return;
1446 --m->nr;
1447 m->guest[i] = m->guest[m->nr];
1448 m->host[i] = m->host[m->nr];
1449 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1450 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1451}
1452
8bf00a52
GN		 1453static void add_atomic_switch_msr_special(unsigned long entry,
1454 unsigned long exit, unsigned long guest_val_vmcs,
1455 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1456{
1457 vmcs_write64(guest_val_vmcs, guest_val);
1458 vmcs_write64(host_val_vmcs, host_val);
1459 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1460 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1461}
1462
61d2ef2c
AK		 1463static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1464 u64 guest_val, u64 host_val)
1465{
1466 unsigned i;
1467 struct msr_autoload *m = &vmx->msr_autoload;
1468
8bf00a52
GN		 1469 switch (msr) {
1470 case MSR_EFER:
1471 if (cpu_has_load_ia32_efer) {
1472 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1473 VM_EXIT_LOAD_IA32_EFER,
1474 GUEST_IA32_EFER,
1475 HOST_IA32_EFER,
1476 guest_val, host_val);
1477 return;
1478 }
1479 break;
1480 case MSR_CORE_PERF_GLOBAL_CTRL:
1481 if (cpu_has_load_perf_global_ctrl) {
1482 add_atomic_switch_msr_special(
1483 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1484 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1485 GUEST_IA32_PERF_GLOBAL_CTRL,
1486 HOST_IA32_PERF_GLOBAL_CTRL,
1487 guest_val, host_val);
1488 return;
1489 }
1490 break;
618fedd4
RK		 1491 case MSR_IA32_PEBS_ENABLE:
1492 /* PEBS needs a quiescent period after being disabled (to write
1493 * a record). Disabling PEBS through VMX MSR swapping doesn't
1494 * provide that period, so a CPU could write host's record into
1495 * guest's memory.
1496 */
1497 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 1498 }
1499
61d2ef2c
AK		 1500 for (i = 0; i < m->nr; ++i)
1501 if (m->guest[i].index == msr)
1502 break;
1503
e7fc6f93
GN		 1504 if (i == NR_AUTOLOAD_MSRS) {
1505 printk_once(KERN_WARNING"Not enough mst switch entries. "
1506 "Can't add msr %x\n", msr);
1507 return;
1508 } else if (i == m->nr) {
61d2ef2c
AK		 1509 ++m->nr;
1510 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1511 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1512 }
1513
1514 m->guest[i].index = msr;
1515 m->guest[i].value = guest_val;
1516 m->host[i].index = msr;
1517 m->host[i].value = host_val;
1518}
1519
33ed6329
AK		 1520static void reload_tss(void)
1521{
33ed6329
AK		 1522 /*
1523 * VT restores TR but not its size. Useless.
1524 */
d359192f 1525 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1526 struct desc_struct *descs;
33ed6329 1527
d359192f 1528 descs = (void *)gdt->address;
33ed6329
AK		 1529 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1530 load_TR_desc();
33ed6329
AK		 1531}
1532
92c0d900 1533static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1534{
3a34a881 1535 u64 guest_efer;
51c6cf66
AK		 1536 u64 ignore_bits;
1537
f6801dff 1538 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1539
51c6cf66 1540 /*
0fa06071 1541 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1542 * outside long mode
1543 */
1544 ignore_bits = EFER_NX | EFER_SCE;
1545#ifdef CONFIG_X86_64
1546 ignore_bits |= EFER_LMA | EFER_LME;
1547 /* SCE is meaningful only in long mode on Intel */
1548 if (guest_efer & EFER_LMA)
1549 ignore_bits &= ~(u64)EFER_SCE;
1550#endif
51c6cf66
AK		 1551 guest_efer &= ~ignore_bits;
1552 guest_efer |= host_efer & ignore_bits;
26bb0981 1553 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1554 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1555
1556 clear_atomic_switch_msr(vmx, MSR_EFER);
1557 /* On ept, can't emulate nx, and must switch nx atomically */
1558 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1559 guest_efer = vmx->vcpu.arch.efer;
1560 if (!(guest_efer & EFER_LMA))
1561 guest_efer &= ~EFER_LME;
1562 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1563 return false;
1564 }
1565
26bb0981 1566 return true;
51c6cf66
AK		 1567}
1568
2d49ec72
GN		 1569static unsigned long segment_base(u16 selector)
1570{
d359192f 1571 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1572 struct desc_struct *d;
1573 unsigned long table_base;
1574 unsigned long v;
1575
1576 if (!(selector & ~3))
1577 return 0;
1578
d359192f 1579 table_base = gdt->address;
2d49ec72
GN		 1580
1581 if (selector & 4) { /* from ldt */
1582 u16 ldt_selector = kvm_read_ldt();
1583
1584 if (!(ldt_selector & ~3))
1585 return 0;
1586
1587 table_base = segment_base(ldt_selector);
1588 }
1589 d = (struct desc_struct *)(table_base + (selector & ~7));
1590 v = get_desc_base(d);
1591#ifdef CONFIG_X86_64
1592 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1593 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1594#endif
1595 return v;
1596}
1597
1598static inline unsigned long kvm_read_tr_base(void)
1599{
1600 u16 tr;
1601 asm("str %0" : "=g"(tr));
1602 return segment_base(tr);
1603}
1604
04d2cc77 1605static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1606{
04d2cc77 1607 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1608 int i;
04d2cc77 1609
a2fa3e9f 1610 if (vmx->host_state.loaded)
33ed6329
AK		 1611 return;
1612
a2fa3e9f 1613 vmx->host_state.loaded = 1;
33ed6329
AK		 1614 /*
1615 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1616 * allow segment selectors with cpl > 0 or ti == 1.
1617 */
d6e88aec 1618 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1619 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1620 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1621 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1622 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1623 vmx->host_state.fs_reload_needed = 0;
1624 } else {
33ed6329 1625 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1626 vmx->host_state.fs_reload_needed = 1;
33ed6329 1627 }
9581d442 1628 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1629 if (!(vmx->host_state.gs_sel & 7))
1630 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1631 else {
1632 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1633 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1634 }
1635
b2da15ac
AK		 1636#ifdef CONFIG_X86_64
1637 savesegment(ds, vmx->host_state.ds_sel);
1638 savesegment(es, vmx->host_state.es_sel);
1639#endif
1640
33ed6329
AK		 1641#ifdef CONFIG_X86_64
1642 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1643 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1644#else
a2fa3e9f
GH		 1645 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1646 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1647#endif
707c0874
AK		 1648
1649#ifdef CONFIG_X86_64
c8770e7b
AK		 1650 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1651 if (is_long_mode(&vmx->vcpu))
44ea2b17 1652 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1653#endif
26bb0981
AK		 1654 for (i = 0; i < vmx->save_nmsrs; ++i)
1655 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1656 vmx->guest_msrs[i].data,
1657 vmx->guest_msrs[i].mask);
33ed6329
AK		 1658}
1659
a9b21b62 1660static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1661{
a2fa3e9f 1662 if (!vmx->host_state.loaded)
33ed6329
AK		 1663 return;
1664
e1beb1d3 1665 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1666 vmx->host_state.loaded = 0;
c8770e7b
AK		 1667#ifdef CONFIG_X86_64
1668 if (is_long_mode(&vmx->vcpu))
1669 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1670#endif
152d3f2f 1671 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1672 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1673#ifdef CONFIG_X86_64
9581d442 1674 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1675#else
1676 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1677#endif
33ed6329 1678 }
0a77fe4c
AK		 1679 if (vmx->host_state.fs_reload_needed)
1680 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1681#ifdef CONFIG_X86_64
1682 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1683 loadsegment(ds, vmx->host_state.ds_sel);
1684 loadsegment(es, vmx->host_state.es_sel);
1685 }
b2da15ac 1686#endif
152d3f2f 1687 reload_tss();
44ea2b17 1688#ifdef CONFIG_X86_64
c8770e7b 1689 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1690#endif
b1a74bf8
SS		 1691 /*
1692 * If the FPU is not active (through the host task or
1693 * the guest vcpu), then restore the cr0.TS bit.
1694 */
1695 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1696 stts();
3444d7da 1697 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1698}
1699
a9b21b62
AK		 1700static void vmx_load_host_state(struct vcpu_vmx *vmx)
1701{
1702 preempt_disable();
1703 __vmx_load_host_state(vmx);
1704 preempt_enable();
1705}
1706
6aa8b732
AK		 1707/*
1708 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1709 * vcpu mutex is already taken.
1710 */
15ad7146 1711static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1712{
a2fa3e9f 1713 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1714 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1715
4610c9cc
DX		 1716 if (!vmm_exclusive)
1717 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1718 else if (vmx->loaded_vmcs->cpu != cpu)
1719 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1720
d462b819
NHE		 1721 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1722 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1723 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1724 }
1725
d462b819 1726 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1727 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1728 unsigned long sysenter_esp;
1729
a8eeb04a 1730 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1731 local_irq_disable();
8f536b76 1732 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1733
1734 /*
1735 * Read loaded_vmcs->cpu should be before fetching
1736 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1737 * See the comments in __loaded_vmcs_clear().
1738 */
1739 smp_rmb();
1740
d462b819
NHE		 1741 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1742 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1743 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1744 local_irq_enable();
1745
6aa8b732
AK		 1746 /*
1747 * Linux uses per-cpu TSS and GDT, so set these when switching
1748 * processors.
1749 */
d6e88aec 1750 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1751 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1752
1753 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1754 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1755 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1756 }
6aa8b732
AK		 1757}
1758
1759static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1760{
a9b21b62 1761 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1762 if (!vmm_exclusive) {
d462b819
NHE		 1763 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1764 vcpu->cpu = -1;
4610c9cc
DX		 1765 kvm_cpu_vmxoff();
1766 }
6aa8b732
AK		 1767}
1768
5fd86fcf
AK		 1769static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1770{
81231c69
AK		 1771 ulong cr0;
1772
5fd86fcf
AK		 1773 if (vcpu->fpu_active)
1774 return;
1775 vcpu->fpu_active = 1;
81231c69
AK		 1776 cr0 = vmcs_readl(GUEST_CR0);
1777 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1778 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1779 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1780 update_exception_bitmap(vcpu);
edcafe3c 1781 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1782 if (is_guest_mode(vcpu))
1783 vcpu->arch.cr0_guest_owned_bits &=
1784 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1785 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1786}
1787
edcafe3c
AK		 1788static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1789
fe3ef05c
NHE		 1790/*
1791 * Return the cr0 value that a nested guest would read. This is a combination
1792 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1793 * its hypervisor (cr0_read_shadow).
1794 */
1795static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1796{
1797 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1798 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1799}
1800static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1801{
1802 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1803 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1804}
1805
5fd86fcf
AK		 1806static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1807{
36cf24e0
NHE		 1808 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1809 * set this *before* calling this function.
1810 */
edcafe3c 1811 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1812 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1813 update_exception_bitmap(vcpu);
edcafe3c
AK		 1814 vcpu->arch.cr0_guest_owned_bits = 0;
1815 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1816 if (is_guest_mode(vcpu)) {
1817 /*
1818 * L1's specified read shadow might not contain the TS bit,
1819 * so now that we turned on shadowing of this bit, we need to
1820 * set this bit of the shadow. Like in nested_vmx_run we need
1821 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1822 * up-to-date here because we just decached cr0.TS (and we'll
1823 * only update vmcs12->guest_cr0 on nested exit).
1824 */
1825 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1826 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1827 (vcpu->arch.cr0 & X86_CR0_TS);
1828 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1829 } else
1830 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1831}
1832
6aa8b732
AK		 1833static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1834{
78ac8b47 1835 unsigned long rflags, save_rflags;
345dcaa8 1836
6de12732
AK		 1837 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1838 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1839 rflags = vmcs_readl(GUEST_RFLAGS);
1840 if (to_vmx(vcpu)->rmode.vm86_active) {
1841 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1842 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1843 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1844 }
1845 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1846 }
6de12732 1847 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1848}
1849
1850static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1851{
6de12732
AK		 1852 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1853 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1854 if (to_vmx(vcpu)->rmode.vm86_active) {
1855 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1856 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1857 }
6aa8b732
AK		 1858 vmcs_writel(GUEST_RFLAGS, rflags);
1859}
1860
2809f5d2
GC		 1861static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1862{
1863 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1864 int ret = 0;
1865
1866 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1867 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1868 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1869 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1870
1871 return ret & mask;
1872}
1873
1874static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1875{
1876 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1877 u32 interruptibility = interruptibility_old;
1878
1879 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1880
48005f64 1881 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1882 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1883 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1884 interruptibility |= GUEST_INTR_STATE_STI;
1885
1886 if ((interruptibility != interruptibility_old))
1887 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1888}
1889
6aa8b732
AK		 1890static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1891{
1892 unsigned long rip;
6aa8b732 1893
5fdbf976 1894 rip = kvm_rip_read(vcpu);
6aa8b732 1895 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1896 kvm_rip_write(vcpu, rip);
6aa8b732 1897
2809f5d2
GC		 1898 /* skipping an emulated instruction also counts */
1899 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1900}
1901
0b6ac343
NHE		 1902/*
1903 * KVM wants to inject page-faults which it got to the guest. This function
1904 * checks whether in a nested guest, we need to inject them to L1 or L2.
1905 * This function assumes it is called with the exit reason in vmcs02 being
1906 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1907 * is running).
1908 */
1909static int nested_pf_handled(struct kvm_vcpu *vcpu)
1910{
1911 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1912
1913 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1914 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1915 return 0;
1916
1917 nested_vmx_vmexit(vcpu);
1918 return 1;
1919}
1920
298101da 1921static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1922 bool has_error_code, u32 error_code,
1923 bool reinject)
298101da 1924{
77ab6db0 1925 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1926 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1927
0b6ac343 1928 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1929 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1930 return;
1931
8ab2d2e2 1932 if (has_error_code) {
77ab6db0 1933 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1934 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1935 }
77ab6db0 1936
7ffd92c5 1937 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1938 int inc_eip = 0;
1939 if (kvm_exception_is_soft(nr))
1940 inc_eip = vcpu->arch.event_exit_inst_len;
1941 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1942 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1943 return;
1944 }
1945
66fd3f7f
GN		 1946 if (kvm_exception_is_soft(nr)) {
1947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1948 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1949 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1950 } else
1951 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1952
1953 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1954}
1955
4e47c7a6
SY		 1956static bool vmx_rdtscp_supported(void)
1957{
1958 return cpu_has_vmx_rdtscp();
1959}
1960
ad756a16
MJ		 1961static bool vmx_invpcid_supported(void)
1962{
1963 return cpu_has_vmx_invpcid() && enable_ept;
1964}
1965
a75beee6
ED		 1966/*
1967 * Swap MSR entry in host/guest MSR entry array.
1968 */
8b9cf98c 1969static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1970{
26bb0981 1971 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1972
1973 tmp = vmx->guest_msrs[to];
1974 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1975 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1976}
1977
8d14695f
YZ		 1978static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1979{
1980 unsigned long *msr_bitmap;
1981
1982 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1983 if (is_long_mode(vcpu))
1984 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1985 else
1986 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1987 } else {
1988 if (is_long_mode(vcpu))
1989 msr_bitmap = vmx_msr_bitmap_longmode;
1990 else
1991 msr_bitmap = vmx_msr_bitmap_legacy;
1992 }
1993
1994 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1995}
1996
e38aea3e
AK		 1997/*
1998 * Set up the vmcs to automatically save and restore system
1999 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2000 * mode, as fiddling with msrs is very expensive.
2001 */
8b9cf98c 2002static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2003{
26bb0981 2004 int save_nmsrs, index;
e38aea3e 2005
a75beee6
ED		 2006 save_nmsrs = 0;
2007#ifdef CONFIG_X86_64
8b9cf98c 2008 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2009 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2010 if (index >= 0)
8b9cf98c
RR		 2011 move_msr_up(vmx, index, save_nmsrs++);
2012 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2013 if (index >= 0)
8b9cf98c
RR		 2014 move_msr_up(vmx, index, save_nmsrs++);
2015 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2016 if (index >= 0)
8b9cf98c 2017 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2018 index = __find_msr_index(vmx, MSR_TSC_AUX);
2019 if (index >= 0 && vmx->rdtscp_enabled)
2020 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2021 /*
8c06585d 2022 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2023 * if efer.sce is enabled.
2024 */
8c06585d 2025 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2026 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2027 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2028 }
2029#endif
92c0d900
AK		 2030 index = __find_msr_index(vmx, MSR_EFER);
2031 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2032 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2033
26bb0981 2034 vmx->save_nmsrs = save_nmsrs;
5897297b 2035
8d14695f
YZ		 2036 if (cpu_has_vmx_msr_bitmap())
2037 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2038}
2039
6aa8b732
AK		 2040/*
2041 * reads and returns guest's timestamp counter "register"
2042 * guest_tsc = host_tsc + tsc_offset -- 21.3
2043 */
2044static u64 guest_read_tsc(void)
2045{
2046 u64 host_tsc, tsc_offset;
2047
2048 rdtscll(host_tsc);
2049 tsc_offset = vmcs_read64(TSC_OFFSET);
2050 return host_tsc + tsc_offset;
2051}
2052
d5c1785d
NHE		 2053/*
2054 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2055 * counter, even if a nested guest (L2) is currently running.
2056 */
886b470c 2057u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2058{
886b470c 2059 u64 tsc_offset;
d5c1785d 2060
d5c1785d
NHE		 2061 tsc_offset = is_guest_mode(vcpu) ?
2062 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2063 vmcs_read64(TSC_OFFSET);
2064 return host_tsc + tsc_offset;
2065}
2066
4051b188 2067/*
cc578287
ZA		 2068 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2069 * software catchup for faster rates on slower CPUs.
4051b188 2070 */
cc578287 2071static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2072{
cc578287
ZA		 2073 if (!scale)
2074 return;
2075
2076 if (user_tsc_khz > tsc_khz) {
2077 vcpu->arch.tsc_catchup = 1;
2078 vcpu->arch.tsc_always_catchup = 1;
2079 } else
2080 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2081}
2082
ba904635
WA		 2083static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2084{
2085 return vmcs_read64(TSC_OFFSET);
2086}
2087
6aa8b732 2088/*
99e3e30a 2089 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2090 */
99e3e30a 2091static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2092{
27fc51b2 2093 if (is_guest_mode(vcpu)) {
7991825b 2094 /*
27fc51b2
NHE		 2095 * We're here if L1 chose not to trap WRMSR to TSC. According
2096 * to the spec, this should set L1's TSC; The offset that L1
2097 * set for L2 remains unchanged, and still needs to be added
2098 * to the newly set TSC to get L2's TSC.
7991825b 2099 */
27fc51b2
NHE		 2100 struct vmcs12 *vmcs12;
2101 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2102 /* recalculate vmcs02.TSC_OFFSET: */
2103 vmcs12 = get_vmcs12(vcpu);
2104 vmcs_write64(TSC_OFFSET, offset +
2105 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2106 vmcs12->tsc_offset : 0));
2107 } else {
2108 vmcs_write64(TSC_OFFSET, offset);
2109 }
6aa8b732
AK		 2110}
2111
f1e2b260 2112static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2113{
2114 u64 offset = vmcs_read64(TSC_OFFSET);
2115 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2116 if (is_guest_mode(vcpu)) {
2117 /* Even when running L2, the adjustment needs to apply to L1 */
2118 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2119 }
e48672fa
ZA		 2120}
2121
857e4099
JR		 2122static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2123{
2124 return target_tsc - native_read_tsc();
2125}
2126
801d3424
NHE		 2127static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2128{
2129 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2130 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2131}
2132
2133/*
2134 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2135 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2136 * all guests if the "nested" module option is off, and can also be disabled
2137 * for a single guest by disabling its VMX cpuid bit.
2138 */
2139static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2140{
2141 return nested && guest_cpuid_has_vmx(vcpu);
2142}
2143
b87a51ae
NHE		 2144/*
2145 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2146 * returned for the various VMX controls MSRs when nested VMX is enabled.
2147 * The same values should also be used to verify that vmcs12 control fields are
2148 * valid during nested entry from L1 to L2.
2149 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2150 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2151 * bit in the high half is on if the corresponding bit in the control field
2152 * may be on. See also vmx_control_verify().
2153 * TODO: allow these variables to be modified (downgraded) by module options
2154 * or other means.
2155 */
2156static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2157static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2158static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2159static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2160static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2161static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2162static __init void nested_vmx_setup_ctls_msrs(void)
2163{
2164 /*
2165 * Note that as a general rule, the high half of the MSRs (bits in
2166 * the control fields which may be 1) should be initialized by the
2167 * intersection of the underlying hardware's MSR (i.e., features which
2168 * can be supported) and the list of features we want to expose -
2169 * because they are known to be properly supported in our code.
2170 * Also, usually, the low half of the MSRs (bits which must be 1) can
2171 * be set to 0, meaning that L1 may turn off any of these bits. The
2172 * reason is that if one of these bits is necessary, it will appear
2173 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2174 * fields of vmcs01 and vmcs02, will turn these bits off - and
2175 * nested_vmx_exit_handled() will not pass related exits to L1.
2176 * These rules have exceptions below.
2177 */
2178
2179 /* pin-based controls */
eabeaacc
JK		 2180 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2181 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2182 /*
2183 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2184 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2185 */
eabeaacc
JK		 2186 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2187 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2188 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2189 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2190 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2191
33fb20c3
JK		 2192 /*
2193 * Exit controls
2194 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2195 * 17 must be 1.
2196 */
2197 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2199#ifdef CONFIG_X86_64
2200 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2201#else
2202 nested_vmx_exit_ctls_high = 0;
2203#endif
33fb20c3 2204 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2205
2206 /* entry controls */
2207 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2208 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2209 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2210 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2211 nested_vmx_entry_ctls_high &=
2212 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2213 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2214
2215 /* cpu-based controls */
2216 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2217 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2218 nested_vmx_procbased_ctls_low = 0;
2219 nested_vmx_procbased_ctls_high &=
2220 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2221 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2222 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2223 CPU_BASED_CR3_STORE_EXITING |
2224#ifdef CONFIG_X86_64
2225 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2226#endif
2227 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2228 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2229 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2230 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2231 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2232 /*
2233 * We can allow some features even when not supported by the
2234 * hardware. For example, L1 can specify an MSR bitmap - and we
2235 * can use it to avoid exits to L1 - even when L0 runs L2
2236 * without MSR bitmaps.
2237 */
2238 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2239
2240 /* secondary cpu-based controls */
2241 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2242 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2243 nested_vmx_secondary_ctls_low = 0;
2244 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2245 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2246 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2247
2248 /* miscellaneous data */
2249 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2250 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2251 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2252 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2253}
2254
2255static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2256{
2257 /*
2258 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2259 */
2260 return ((control & high) | low) == control;
2261}
2262
2263static inline u64 vmx_control_msr(u32 low, u32 high)
2264{
2265 return low | ((u64)high << 32);
2266}
2267
2268/*
2269 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2270 * also let it use VMX-specific MSRs.
2271 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2272 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2273 * like all other MSRs).
2274 */
2275static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2276{
2277 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2278 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2279 /*
2280 * According to the spec, processors which do not support VMX
2281 * should throw a #GP(0) when VMX capability MSRs are read.
2282 */
2283 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2284 return 1;
2285 }
2286
2287 switch (msr_index) {
2288 case MSR_IA32_FEATURE_CONTROL:
2289 *pdata = 0;
2290 break;
2291 case MSR_IA32_VMX_BASIC:
2292 /*
2293 * This MSR reports some information about VMX support. We
2294 * should return information about the VMX we emulate for the
2295 * guest, and the VMCS structure we give it - not about the
2296 * VMX support of the underlying hardware.
2297 */
2298 *pdata = VMCS12_REVISION |
2299 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2300 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2301 break;
2302 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2303 case MSR_IA32_VMX_PINBASED_CTLS:
2304 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2305 nested_vmx_pinbased_ctls_high);
2306 break;
2307 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2308 case MSR_IA32_VMX_PROCBASED_CTLS:
2309 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2310 nested_vmx_procbased_ctls_high);
2311 break;
2312 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2313 case MSR_IA32_VMX_EXIT_CTLS:
2314 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2315 nested_vmx_exit_ctls_high);
2316 break;
2317 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2318 case MSR_IA32_VMX_ENTRY_CTLS:
2319 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2320 nested_vmx_entry_ctls_high);
2321 break;
2322 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2323 *pdata = vmx_control_msr(nested_vmx_misc_low,
2324 nested_vmx_misc_high);
b87a51ae
NHE		 2325 break;
2326 /*
2327 * These MSRs specify bits which the guest must keep fixed (on or off)
2328 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2329 * We picked the standard core2 setting.
2330 */
2331#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2332#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2333 case MSR_IA32_VMX_CR0_FIXED0:
2334 *pdata = VMXON_CR0_ALWAYSON;
2335 break;
2336 case MSR_IA32_VMX_CR0_FIXED1:
2337 *pdata = -1ULL;
2338 break;
2339 case MSR_IA32_VMX_CR4_FIXED0:
2340 *pdata = VMXON_CR4_ALWAYSON;
2341 break;
2342 case MSR_IA32_VMX_CR4_FIXED1:
2343 *pdata = -1ULL;
2344 break;
2345 case MSR_IA32_VMX_VMCS_ENUM:
2346 *pdata = 0x1f;
2347 break;
2348 case MSR_IA32_VMX_PROCBASED_CTLS2:
2349 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2350 nested_vmx_secondary_ctls_high);
2351 break;
2352 case MSR_IA32_VMX_EPT_VPID_CAP:
2353 /* Currently, no nested ept or nested vpid */
2354 *pdata = 0;
2355 break;
2356 default:
2357 return 0;
2358 }
2359
2360 return 1;
2361}
2362
2363static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2364{
2365 if (!nested_vmx_allowed(vcpu))
2366 return 0;
2367
2368 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2369 /* TODO: the right thing. */
2370 return 1;
2371 /*
2372 * No need to treat VMX capability MSRs specially: If we don't handle
2373 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2374 */
2375 return 0;
2376}
2377
6aa8b732
AK		 2378/*
2379 * Reads an msr value (of 'msr_index') into 'pdata'.
2380 * Returns 0 on success, non-0 otherwise.
2381 * Assumes vcpu_load() was already called.
2382 */
2383static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2384{
2385 u64 data;
26bb0981 2386 struct shared_msr_entry *msr;
6aa8b732
AK		 2387
2388 if (!pdata) {
2389 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2390 return -EINVAL;
2391 }
2392
2393 switch (msr_index) {
05b3e0c2 2394#ifdef CONFIG_X86_64
6aa8b732
AK		 2395 case MSR_FS_BASE:
2396 data = vmcs_readl(GUEST_FS_BASE);
2397 break;
2398 case MSR_GS_BASE:
2399 data = vmcs_readl(GUEST_GS_BASE);
2400 break;
44ea2b17
AK		 2401 case MSR_KERNEL_GS_BASE:
2402 vmx_load_host_state(to_vmx(vcpu));
2403 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2404 break;
26bb0981 2405#endif
6aa8b732 2406 case MSR_EFER:
3bab1f5d 2407 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2408 case MSR_IA32_TSC:
6aa8b732
AK		 2409 data = guest_read_tsc();
2410 break;
2411 case MSR_IA32_SYSENTER_CS:
2412 data = vmcs_read32(GUEST_SYSENTER_CS);
2413 break;
2414 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2415 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2416 break;
2417 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2418 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2419 break;
4e47c7a6
SY		 2420 case MSR_TSC_AUX:
2421 if (!to_vmx(vcpu)->rdtscp_enabled)
2422 return 1;
2423 /* Otherwise falls through */
6aa8b732 2424 default:
b87a51ae
NHE		 2425 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2426 return 0;
8b9cf98c 2427 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2428 if (msr) {
2429 data = msr->data;
2430 break;
6aa8b732 2431 }
3bab1f5d 2432 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2433 }
2434
2435 *pdata = data;
2436 return 0;
2437}
2438
2439/*
2440 * Writes msr value into into the appropriate "register".
2441 * Returns 0 on success, non-0 otherwise.
2442 * Assumes vcpu_load() was already called.
2443 */
8fe8ab46 2444static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2445{
a2fa3e9f 2446 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2447 struct shared_msr_entry *msr;
2cc51560 2448 int ret = 0;
8fe8ab46
WA		 2449 u32 msr_index = msr_info->index;
2450 u64 data = msr_info->data;
2cc51560 2451
6aa8b732 2452 switch (msr_index) {
3bab1f5d 2453 case MSR_EFER:
8fe8ab46 2454 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2455 break;
16175a79 2456#ifdef CONFIG_X86_64
6aa8b732 2457 case MSR_FS_BASE:
2fb92db1 2458 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2459 vmcs_writel(GUEST_FS_BASE, data);
2460 break;
2461 case MSR_GS_BASE:
2fb92db1 2462 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2463 vmcs_writel(GUEST_GS_BASE, data);
2464 break;
44ea2b17
AK		 2465 case MSR_KERNEL_GS_BASE:
2466 vmx_load_host_state(vmx);
2467 vmx->msr_guest_kernel_gs_base = data;
2468 break;
6aa8b732
AK		 2469#endif
2470 case MSR_IA32_SYSENTER_CS:
2471 vmcs_write32(GUEST_SYSENTER_CS, data);
2472 break;
2473 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2474 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2475 break;
2476 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2477 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2478 break;
af24a4e4 2479 case MSR_IA32_TSC:
8fe8ab46 2480 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2481 break;
468d472f
SY		 2482 case MSR_IA32_CR_PAT:
2483 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2484 vmcs_write64(GUEST_IA32_PAT, data);
2485 vcpu->arch.pat = data;
2486 break;
2487 }
8fe8ab46 2488 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2489 break;
ba904635
WA		 2490 case MSR_IA32_TSC_ADJUST:
2491 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2492 break;
2493 case MSR_TSC_AUX:
2494 if (!vmx->rdtscp_enabled)
2495 return 1;
2496 /* Check reserved bit, higher 32 bits should be zero */
2497 if ((data >> 32) != 0)
2498 return 1;
2499 /* Otherwise falls through */
6aa8b732 2500 default:
b87a51ae
NHE		 2501 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2502 break;
8b9cf98c 2503 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2504 if (msr) {
1bea37d6 2505 u64 old_msr_data = msr->data;
3bab1f5d 2506 msr->data = data;
2225fd56
AK		 2507 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2508 preempt_disable();
1bea37d6
AH		 2509 ret = kvm_set_shared_msr(msr->index, msr->data,
2510 msr->mask);
2225fd56 2511 preempt_enable();
1bea37d6
AH		 2512 if (ret)
2513 msr->data = old_msr_data;
2225fd56 2514 }
3bab1f5d 2515 break;
6aa8b732 2516 }
8fe8ab46 2517 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2518 }
2519
2cc51560 2520 return ret;
6aa8b732
AK		 2521}
2522
5fdbf976 2523static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2524{
5fdbf976
MT		 2525 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2526 switch (reg) {
2527 case VCPU_REGS_RSP:
2528 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2529 break;
2530 case VCPU_REGS_RIP:
2531 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2532 break;
6de4f3ad
AK		 2533 case VCPU_EXREG_PDPTR:
2534 if (enable_ept)
2535 ept_save_pdptrs(vcpu);
2536 break;
5fdbf976
MT		 2537 default:
2538 break;
2539 }
6aa8b732
AK		 2540}
2541
6aa8b732
AK		 2542static __init int cpu_has_kvm_support(void)
2543{
6210e37b 2544 return cpu_has_vmx();
6aa8b732
AK		 2545}
2546
2547static __init int vmx_disabled_by_bios(void)
2548{
2549 u64 msr;
2550
2551 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2552 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2553 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2554 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2555 && tboot_enabled())
2556 return 1;
23f3e991 2557 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2558 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2559 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2560 && !tboot_enabled()) {
2561 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2562 "activate TXT before enabling KVM\n");
cafd6659 2563 return 1;
f9335afe 2564 }
23f3e991
JC		 2565 /* launched w/o TXT and VMX disabled */
2566 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2567 && !tboot_enabled())
2568 return 1;
cafd6659
SW		 2569 }
2570
2571 return 0;
6aa8b732
AK		 2572}
2573
7725b894
DX		 2574static void kvm_cpu_vmxon(u64 addr)
2575{
2576 asm volatile (ASM_VMX_VMXON_RAX
2577 : : "a"(&addr), "m"(addr)
2578 : "memory", "cc");
2579}
2580
10474ae8 2581static int hardware_enable(void *garbage)
6aa8b732
AK		 2582{
2583 int cpu = raw_smp_processor_id();
2584 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2585 u64 old, test_bits;
6aa8b732 2586
10474ae8
AG		 2587 if (read_cr4() & X86_CR4_VMXE)
2588 return -EBUSY;
2589
d462b819 2590 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2591
2592 /*
2593 * Now we can enable the vmclear operation in kdump
2594 * since the loaded_vmcss_on_cpu list on this cpu
2595 * has been initialized.
2596 *
2597 * Though the cpu is not in VMX operation now, there
2598 * is no problem to enable the vmclear operation
2599 * for the loaded_vmcss_on_cpu list is empty!
2600 */
2601 crash_enable_local_vmclear(cpu);
2602
6aa8b732 2603 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2604
2605 test_bits = FEATURE_CONTROL_LOCKED;
2606 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2607 if (tboot_enabled())
2608 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2609
2610 if ((old & test_bits) != test_bits) {
6aa8b732 2611 /* enable and lock */
cafd6659
SW		 2612 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2613 }
66aee91a 2614 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2615
4610c9cc
DX		 2616 if (vmm_exclusive) {
2617 kvm_cpu_vmxon(phys_addr);
2618 ept_sync_global();
2619 }
10474ae8 2620
357d1226 2621 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2622
10474ae8 2623 return 0;
6aa8b732
AK		 2624}
2625
d462b819 2626static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2627{
2628 int cpu = raw_smp_processor_id();
d462b819 2629 struct loaded_vmcs *v, *n;
543e4243 2630
d462b819
NHE		 2631 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2632 loaded_vmcss_on_cpu_link)
2633 __loaded_vmcs_clear(v);
543e4243
AK		 2634}
2635
710ff4a8
EH		 2636
2637/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2638 * tricks.
2639 */
2640static void kvm_cpu_vmxoff(void)
6aa8b732 2641{
4ecac3fd 2642 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2643}
2644
710ff4a8
EH		 2645static void hardware_disable(void *garbage)
2646{
4610c9cc 2647 if (vmm_exclusive) {
d462b819 2648 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2649 kvm_cpu_vmxoff();
2650 }
7725b894 2651 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2652}
2653
1c3d14fe 2654static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2655 u32 msr, u32 *result)
1c3d14fe
YS		 2656{
2657 u32 vmx_msr_low, vmx_msr_high;
2658 u32 ctl = ctl_min | ctl_opt;
2659
2660 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2661
2662 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2663 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2664
2665 /* Ensure minimum (required) set of control bits are supported. */
2666 if (ctl_min & ~ctl)
002c7f7c 2667 return -EIO;
1c3d14fe
YS		 2668
2669 *result = ctl;
2670 return 0;
2671}
2672
110312c8
AK		 2673static __init bool allow_1_setting(u32 msr, u32 ctl)
2674{
2675 u32 vmx_msr_low, vmx_msr_high;
2676
2677 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2678 return vmx_msr_high & ctl;
2679}
2680
002c7f7c 2681static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2682{
2683 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2684 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2685 u32 _pin_based_exec_control = 0;
2686 u32 _cpu_based_exec_control = 0;
f78e0e2e 2687 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2688 u32 _vmexit_control = 0;
2689 u32 _vmentry_control = 0;
2690
10166744 2691 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2692#ifdef CONFIG_X86_64
2693 CPU_BASED_CR8_LOAD_EXITING |
2694 CPU_BASED_CR8_STORE_EXITING |
2695#endif
d56f546d
SY		 2696 CPU_BASED_CR3_LOAD_EXITING |
2697 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2698 CPU_BASED_USE_IO_BITMAPS |
2699 CPU_BASED_MOV_DR_EXITING |
a7052897 2700 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2701 CPU_BASED_MWAIT_EXITING |
2702 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2703 CPU_BASED_INVLPG_EXITING |
2704 CPU_BASED_RDPMC_EXITING;
443381a8 2705
f78e0e2e 2706 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2707 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2708 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2709 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2710 &_cpu_based_exec_control) < 0)
002c7f7c 2711 return -EIO;
6e5d865c
YS		 2712#ifdef CONFIG_X86_64
2713 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2714 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2715 ~CPU_BASED_CR8_STORE_EXITING;
2716#endif
f78e0e2e 2717 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2718 min2 = 0;
2719 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2720 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2721 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2722 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2723 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2724 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2725 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2726 SECONDARY_EXEC_RDTSCP |
83d4c286 2727 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2728 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2729 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2730 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2731 if (adjust_vmx_controls(min2, opt2,
2732 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2733 &_cpu_based_2nd_exec_control) < 0)
2734 return -EIO;
2735 }
2736#ifndef CONFIG_X86_64
2737 if (!(_cpu_based_2nd_exec_control &
2738 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2739 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2740#endif
83d4c286
YZ		 2741
2742 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2743 _cpu_based_2nd_exec_control &= ~(
8d14695f 2744 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2745 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2746 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2747
d56f546d 2748 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2749 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2750 enabled */
5fff7d27
GN		 2751 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2752 CPU_BASED_CR3_STORE_EXITING |
2753 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2754 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2755 vmx_capability.ept, vmx_capability.vpid);
2756 }
1c3d14fe
YS		 2757
2758 min = 0;
2759#ifdef CONFIG_X86_64
2760 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2761#endif
a547c6db
YZ		 2762 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2763 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2764 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2765 &_vmexit_control) < 0)
002c7f7c 2766 return -EIO;
1c3d14fe 2767
01e439be
YZ		 2768 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2769 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2770 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2771 &_pin_based_exec_control) < 0)
2772 return -EIO;
2773
2774 if (!(_cpu_based_2nd_exec_control &
2775 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2776 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2777 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2778
468d472f
SY		 2779 min = 0;
2780 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2781 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2782 &_vmentry_control) < 0)
002c7f7c 2783 return -EIO;
6aa8b732 2784
c68876fd 2785 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2786
2787 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2788 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2789 return -EIO;
1c3d14fe
YS		 2790
2791#ifdef CONFIG_X86_64
2792 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2793 if (vmx_msr_high & (1u<<16))
002c7f7c 2794 return -EIO;
1c3d14fe
YS		 2795#endif
2796
2797 /* Require Write-Back (WB) memory type for VMCS accesses. */
2798 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2799 return -EIO;
1c3d14fe 2800
002c7f7c
YS		 2801 vmcs_conf->size = vmx_msr_high & 0x1fff;
2802 vmcs_conf->order = get_order(vmcs_config.size);
2803 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2804
002c7f7c
YS		 2805 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2806 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2807 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2808 vmcs_conf->vmexit_ctrl = _vmexit_control;
2809 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2810
110312c8
AK		 2811 cpu_has_load_ia32_efer =
2812 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2813 VM_ENTRY_LOAD_IA32_EFER)
2814 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2815 VM_EXIT_LOAD_IA32_EFER);
2816
8bf00a52
GN		 2817 cpu_has_load_perf_global_ctrl =
2818 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2819 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2820 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2821 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2822
2823 /*
2824 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2825 * but due to arrata below it can't be used. Workaround is to use
2826 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2827 *
2828 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2829 *
2830 * AAK155 (model 26)
2831 * AAP115 (model 30)
2832 * AAT100 (model 37)
2833 * BC86,AAY89,BD102 (model 44)
2834 * BA97 (model 46)
2835 *
2836 */
2837 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2838 switch (boot_cpu_data.x86_model) {
2839 case 26:
2840 case 30:
2841 case 37:
2842 case 44:
2843 case 46:
2844 cpu_has_load_perf_global_ctrl = false;
2845 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2846 "does not work properly. Using workaround\n");
2847 break;
2848 default:
2849 break;
2850 }
2851 }
2852
1c3d14fe 2853 return 0;
c68876fd 2854}
6aa8b732
AK		 2855
2856static struct vmcs *alloc_vmcs_cpu(int cpu)
2857{
2858 int node = cpu_to_node(cpu);
2859 struct page *pages;
2860 struct vmcs *vmcs;
2861
6484eb3e 2862 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2863 if (!pages)
2864 return NULL;
2865 vmcs = page_address(pages);
1c3d14fe
YS		 2866 memset(vmcs, 0, vmcs_config.size);
2867 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2868 return vmcs;
2869}
2870
2871static struct vmcs *alloc_vmcs(void)
2872{
d3b2c338 2873 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2874}
2875
2876static void free_vmcs(struct vmcs *vmcs)
2877{
1c3d14fe 2878 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2879}
2880
d462b819
NHE		 2881/*
2882 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2883 */
2884static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2885{
2886 if (!loaded_vmcs->vmcs)
2887 return;
2888 loaded_vmcs_clear(loaded_vmcs);
2889 free_vmcs(loaded_vmcs->vmcs);
2890 loaded_vmcs->vmcs = NULL;
2891}
2892
39959588 2893static void free_kvm_area(void)
6aa8b732
AK		 2894{
2895 int cpu;
2896
3230bb47 2897 for_each_possible_cpu(cpu) {
6aa8b732 2898 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2899 per_cpu(vmxarea, cpu) = NULL;
2900 }
6aa8b732
AK		 2901}
2902
6aa8b732
AK		 2903static __init int alloc_kvm_area(void)
2904{
2905 int cpu;
2906
3230bb47 2907 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2908 struct vmcs *vmcs;
2909
2910 vmcs = alloc_vmcs_cpu(cpu);
2911 if (!vmcs) {
2912 free_kvm_area();
2913 return -ENOMEM;
2914 }
2915
2916 per_cpu(vmxarea, cpu) = vmcs;
2917 }
2918 return 0;
2919}
2920
2921static __init int hardware_setup(void)
2922{
002c7f7c
YS		 2923 if (setup_vmcs_config(&vmcs_config) < 0)
2924 return -EIO;
50a37eb4
JR		 2925
2926 if (boot_cpu_has(X86_FEATURE_NX))
2927 kvm_enable_efer_bits(EFER_NX);
2928
93ba03c2
SY		 2929 if (!cpu_has_vmx_vpid())
2930 enable_vpid = 0;
abc4fc58
AG		 2931 if (!cpu_has_vmx_shadow_vmcs())
2932 enable_shadow_vmcs = 0;
93ba03c2 2933
4bc9b982
SY		 2934 if (!cpu_has_vmx_ept() ||
2935 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2936 enable_ept = 0;
3a624e29 2937 enable_unrestricted_guest = 0;
83c3a331 2938 enable_ept_ad_bits = 0;
3a624e29
NK		 2939 }
2940
83c3a331
XH		 2941 if (!cpu_has_vmx_ept_ad_bits())
2942 enable_ept_ad_bits = 0;
2943
3a624e29
NK		 2944 if (!cpu_has_vmx_unrestricted_guest())
2945 enable_unrestricted_guest = 0;
93ba03c2
SY		 2946
2947 if (!cpu_has_vmx_flexpriority())
2948 flexpriority_enabled = 0;
2949
95ba8273
GN		 2950 if (!cpu_has_vmx_tpr_shadow())
2951 kvm_x86_ops->update_cr8_intercept = NULL;
2952
54dee993
MT		 2953 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2954 kvm_disable_largepages();
2955
4b8d54f9
ZE		 2956 if (!cpu_has_vmx_ple())
2957 ple_gap = 0;
2958
01e439be
YZ		 2959 if (!cpu_has_vmx_apicv())
2960 enable_apicv = 0;
c7c9c56c 2961
01e439be 2962 if (enable_apicv)
c7c9c56c 2963 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2964 else {
c7c9c56c 2965 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2966 kvm_x86_ops->deliver_posted_interrupt = NULL;
2967 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2968 }
83d4c286 2969
b87a51ae
NHE		 2970 if (nested)
2971 nested_vmx_setup_ctls_msrs();
2972
6aa8b732
AK		 2973 return alloc_kvm_area();
2974}
2975
2976static __exit void hardware_unsetup(void)
2977{
2978 free_kvm_area();
2979}
2980
14168786
GN		 2981static bool emulation_required(struct kvm_vcpu *vcpu)
2982{
2983 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2984}
2985
91b0aa2c 2986static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2987 struct kvm_segment *save)
6aa8b732 2988{
d99e4152
GN		 2989 if (!emulate_invalid_guest_state) {
2990 /*
2991 * CS and SS RPL should be equal during guest entry according
2992 * to VMX spec, but in reality it is not always so. Since vcpu
2993 * is in the middle of the transition from real mode to
2994 * protected mode it is safe to assume that RPL 0 is a good
2995 * default value.
2996 */
2997 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2998 save->selector &= ~SELECTOR_RPL_MASK;
2999 save->dpl = save->selector & SELECTOR_RPL_MASK;
3000 save->s = 1;
6aa8b732 3001 }
d99e4152 3002 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3003}
3004
3005static void enter_pmode(struct kvm_vcpu *vcpu)
3006{
3007 unsigned long flags;
a89a8fb9 3008 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3009
d99e4152
GN		 3010 /*
3011 * Update real mode segment cache. It may be not up-to-date if sement
3012 * register was written while vcpu was in a guest mode.
3013 */
3014 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3015 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3016 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3017 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3018 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3019 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3020
7ffd92c5 3021 vmx->rmode.vm86_active = 0;
6aa8b732 3022
2fb92db1
AK		 3023 vmx_segment_cache_clear(vmx);
3024
f5f7b2fe 3025 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3026
3027 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3028 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3029 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3030 vmcs_writel(GUEST_RFLAGS, flags);
3031
66aee91a
RR		 3032 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3033 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3034
3035 update_exception_bitmap(vcpu);
3036
91b0aa2c
GN		 3037 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3038 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3039 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3040 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3041 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3042 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3043
3044 /* CPL is always 0 when CPU enters protected mode */
3045 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3046 vmx->cpl = 0;
6aa8b732
AK		 3047}
3048
f5f7b2fe 3049static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3050{
772e0318 3051 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3052 struct kvm_segment var = *save;
3053
3054 var.dpl = 0x3;
3055 if (seg == VCPU_SREG_CS)
3056 var.type = 0x3;
3057
3058 if (!emulate_invalid_guest_state) {
3059 var.selector = var.base >> 4;
3060 var.base = var.base & 0xffff0;
3061 var.limit = 0xffff;
3062 var.g = 0;
3063 var.db = 0;
3064 var.present = 1;
3065 var.s = 1;
3066 var.l = 0;
3067 var.unusable = 0;
3068 var.type = 0x3;
3069 var.avl = 0;
3070 if (save->base & 0xf)
3071 printk_once(KERN_WARNING "kvm: segment base is not "
3072 "paragraph aligned when entering "
3073 "protected mode (seg=%d)", seg);
3074 }
6aa8b732 3075
d99e4152 3076 vmcs_write16(sf->selector, var.selector);
d1e71d5f 3077 vmcs_writel(sf->base, var.base);
d99e4152
GN		 3078 vmcs_write32(sf->limit, var.limit);
3079 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3080}
3081
3082static void enter_rmode(struct kvm_vcpu *vcpu)
3083{
3084 unsigned long flags;
a89a8fb9 3085 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3086
f5f7b2fe
AK		 3087 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3088 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3089 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3090 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3091 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3092 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3093 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3094
7ffd92c5 3095 vmx->rmode.vm86_active = 1;
6aa8b732 3096
776e58ea
GN		 3097 /*
3098 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3099 * vcpu. Warn the user that an update is overdue.
776e58ea 3100 */
4918c6ca 3101 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3102 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3103 "called before entering vcpu\n");
776e58ea 3104
2fb92db1
AK		 3105 vmx_segment_cache_clear(vmx);
3106
4918c6ca 3107 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3108 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3109 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3110
3111 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3112 vmx->rmode.save_rflags = flags;
6aa8b732 3113
053de044 3114 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3115
3116 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3117 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3118 update_exception_bitmap(vcpu);
3119
d99e4152
GN		 3120 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3121 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3122 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3123 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3124 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3125 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3126
8668a3c4 3127 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3128}
3129
401d10de
AS		 3130static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3131{
3132 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3133 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3134
3135 if (!msr)
3136 return;
401d10de 3137
44ea2b17
AK		 3138 /*
3139 * Force kernel_gs_base reloading before EFER changes, as control
3140 * of this msr depends on is_long_mode().
3141 */
3142 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3143 vcpu->arch.efer = efer;
401d10de
AS		 3144 if (efer & EFER_LMA) {
3145 vmcs_write32(VM_ENTRY_CONTROLS,
3146 vmcs_read32(VM_ENTRY_CONTROLS) |
3147 VM_ENTRY_IA32E_MODE);
3148 msr->data = efer;
3149 } else {
3150 vmcs_write32(VM_ENTRY_CONTROLS,
3151 vmcs_read32(VM_ENTRY_CONTROLS) &
3152 ~VM_ENTRY_IA32E_MODE);
3153
3154 msr->data = efer & ~EFER_LME;
3155 }
3156 setup_msrs(vmx);
3157}
3158
05b3e0c2 3159#ifdef CONFIG_X86_64
6aa8b732
AK		 3160
3161static void enter_lmode(struct kvm_vcpu *vcpu)
3162{
3163 u32 guest_tr_ar;
3164
2fb92db1
AK		 3165 vmx_segment_cache_clear(to_vmx(vcpu));
3166
6aa8b732
AK		 3167 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3168 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3169 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3170 __func__);
6aa8b732
AK		 3171 vmcs_write32(GUEST_TR_AR_BYTES,
3172 (guest_tr_ar & ~AR_TYPE_MASK)
3173 | AR_TYPE_BUSY_64_TSS);
3174 }
da38f438 3175 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3176}
3177
3178static void exit_lmode(struct kvm_vcpu *vcpu)
3179{
6aa8b732
AK		 3180 vmcs_write32(VM_ENTRY_CONTROLS,
3181 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3182 & ~VM_ENTRY_IA32E_MODE);
da38f438 3183 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3184}
3185
3186#endif
3187
2384d2b3
SY		 3188static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3189{
b9d762fa 3190 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3191 if (enable_ept) {
3192 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3193 return;
4e1096d2 3194 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3195 }
2384d2b3
SY		 3196}
3197
e8467fda
AK		 3198static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3199{
3200 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3201
3202 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3203 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3204}
3205
aff48baa
AK		 3206static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3207{
3208 if (enable_ept && is_paging(vcpu))
3209 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3210 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3211}
3212
25c4c276 3213static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3214{
fc78f519
AK		 3215 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3216
3217 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3218 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3219}
3220
1439442c
SY		 3221static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3222{
6de4f3ad
AK		 3223 if (!test_bit(VCPU_EXREG_PDPTR,
3224 (unsigned long *)&vcpu->arch.regs_dirty))
3225 return;
3226
1439442c 3227 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3228 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3229 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3230 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3231 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3232 }
3233}
3234
8f5d549f
AK		 3235static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3236{
3237 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3238 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3239 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3240 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3241 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3242 }
6de4f3ad
AK		 3243
3244 __set_bit(VCPU_EXREG_PDPTR,
3245 (unsigned long *)&vcpu->arch.regs_avail);
3246 __set_bit(VCPU_EXREG_PDPTR,
3247 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3248}
3249
5e1746d6 3250static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3251
3252static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3253 unsigned long cr0,
3254 struct kvm_vcpu *vcpu)
3255{
5233dd51
MT		 3256 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3257 vmx_decache_cr3(vcpu);
1439442c
SY		 3258 if (!(cr0 & X86_CR0_PG)) {
3259 /* From paging/starting to nonpaging */
3260 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3261 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3262 (CPU_BASED_CR3_LOAD_EXITING |
3263 CPU_BASED_CR3_STORE_EXITING));
3264 vcpu->arch.cr0 = cr0;
fc78f519 3265 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3266 } else if (!is_paging(vcpu)) {
3267 /* From nonpaging to paging */
3268 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3269 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3270 ~(CPU_BASED_CR3_LOAD_EXITING |
3271 CPU_BASED_CR3_STORE_EXITING));
3272 vcpu->arch.cr0 = cr0;
fc78f519 3273 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3274 }
95eb84a7
SY		 3275
3276 if (!(cr0 & X86_CR0_WP))
3277 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3278}
3279
6aa8b732
AK		 3280static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3281{
7ffd92c5 3282 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3283 unsigned long hw_cr0;
3284
5037878e 3285 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3286 if (enable_unrestricted_guest)
5037878e 3287 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3288 else {
5037878e 3289 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3290
218e763f
GN		 3291 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3292 enter_pmode(vcpu);
6aa8b732 3293
218e763f
GN		 3294 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3295 enter_rmode(vcpu);
3296 }
6aa8b732 3297
05b3e0c2 3298#ifdef CONFIG_X86_64
f6801dff 3299 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3300 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3301 enter_lmode(vcpu);
707d92fa 3302 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3303 exit_lmode(vcpu);
3304 }
3305#endif
3306
089d034e 3307 if (enable_ept)
1439442c
SY		 3308 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3309
02daab21 3310 if (!vcpu->fpu_active)
81231c69 3311 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3312
6aa8b732 3313 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3314 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3315 vcpu->arch.cr0 = cr0;
14168786
GN		 3316
3317 /* depends on vcpu->arch.cr0 to be set to a new value */
3318 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3319}
3320
1439442c
SY		 3321static u64 construct_eptp(unsigned long root_hpa)
3322{
3323 u64 eptp;
3324
3325 /* TODO write the value reading from MSR */
3326 eptp = VMX_EPT_DEFAULT_MT |
3327 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3328 if (enable_ept_ad_bits)
3329 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3330 eptp |= (root_hpa & PAGE_MASK);
3331
3332 return eptp;
3333}
3334
6aa8b732
AK		 3335static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3336{
1439442c
SY		 3337 unsigned long guest_cr3;
3338 u64 eptp;
3339
3340 guest_cr3 = cr3;
089d034e 3341 if (enable_ept) {
1439442c
SY		 3342 eptp = construct_eptp(cr3);
3343 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3344 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3345 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3346 ept_load_pdptrs(vcpu);
1439442c
SY		 3347 }
3348
2384d2b3 3349 vmx_flush_tlb(vcpu);
1439442c 3350 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3351}
3352
5e1746d6 3353static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3354{
7ffd92c5 3355 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3356 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3357
5e1746d6
NHE		 3358 if (cr4 & X86_CR4_VMXE) {
3359 /*
3360 * To use VMXON (and later other VMX instructions), a guest
3361 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3362 * So basically the check on whether to allow nested VMX
3363 * is here.
3364 */
3365 if (!nested_vmx_allowed(vcpu))
3366 return 1;
1a0d74e6
JK		 3367 }
3368 if (to_vmx(vcpu)->nested.vmxon &&
3369 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3370 return 1;
3371
ad312c7c 3372 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3373 if (enable_ept) {
3374 if (!is_paging(vcpu)) {
3375 hw_cr4 &= ~X86_CR4_PAE;
3376 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3377 /*
3378 * SMEP is disabled if CPU is in non-paging mode in
3379 * hardware. However KVM always uses paging mode to
3380 * emulate guest non-paging mode with TDP.
3381 * To emulate this behavior, SMEP needs to be manually
3382 * disabled when guest switches to non-paging mode.
3383 */
3384 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3385 } else if (!(cr4 & X86_CR4_PAE)) {
3386 hw_cr4 &= ~X86_CR4_PAE;
3387 }
3388 }
1439442c
SY		 3389
3390 vmcs_writel(CR4_READ_SHADOW, cr4);
3391 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3392 return 0;
6aa8b732
AK		 3393}
3394
6aa8b732
AK		 3395static void vmx_get_segment(struct kvm_vcpu *vcpu,
3396 struct kvm_segment *var, int seg)
3397{
a9179499 3398 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3399 u32 ar;
3400
c6ad1153 3401 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3402 *var = vmx->rmode.segs[seg];
a9179499 3403 if (seg == VCPU_SREG_TR
2fb92db1 3404 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3405 return;
1390a28b
AK		 3406 var->base = vmx_read_guest_seg_base(vmx, seg);
3407 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3408 return;
a9179499 3409 }
2fb92db1
AK		 3410 var->base = vmx_read_guest_seg_base(vmx, seg);
3411 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3412 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3413 ar = vmx_read_guest_seg_ar(vmx, seg);
096bff23 3414 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3415 var->type = ar & 15;
3416 var->s = (ar >> 4) & 1;
3417 var->dpl = (ar >> 5) & 3;
096bff23
GN		 3418 /*
3419 * Some userspaces do not preserve unusable property. Since usable
3420 * segment has to be present according to VMX spec we can use present
3421 * property to amend userspace bug by making unusable segment always
3422 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3423 * segment as unusable.
3424 */
3425 var->present = !var->unusable;
6aa8b732
AK		 3426 var->avl = (ar >> 12) & 1;
3427 var->l = (ar >> 13) & 1;
3428 var->db = (ar >> 14) & 1;
3429 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3430}
3431
a9179499
AK		 3432static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3433{
a9179499
AK		 3434 struct kvm_segment s;
3435
3436 if (to_vmx(vcpu)->rmode.vm86_active) {
3437 vmx_get_segment(vcpu, &s, seg);
3438 return s.base;
3439 }
2fb92db1 3440 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3441}
3442
b09408d0 3443static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3444{
b09408d0
MT		 3445 struct vcpu_vmx *vmx = to_vmx(vcpu);
3446
3eeb3288 3447 if (!is_protmode(vcpu))
2e4d2653
IE		 3448 return 0;
3449
f4c63e5d
AK		 3450 if (!is_long_mode(vcpu)
3451 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3452 return 3;
3453
69c73028
AK		 3454 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3455 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3456 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3457 }
d881e6f6
AK		 3458
3459 return vmx->cpl;
69c73028
AK		 3460}
3461
3462
653e3108 3463static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3464{
6aa8b732
AK		 3465 u32 ar;
3466
f0495f9b 3467 if (var->unusable || !var->present)
6aa8b732
AK		 3468 ar = 1 << 16;
3469 else {
3470 ar = var->type & 15;
3471 ar |= (var->s & 1) << 4;
3472 ar |= (var->dpl & 3) << 5;
3473 ar |= (var->present & 1) << 7;
3474 ar |= (var->avl & 1) << 12;
3475 ar |= (var->l & 1) << 13;
3476 ar |= (var->db & 1) << 14;
3477 ar |= (var->g & 1) << 15;
3478 }
653e3108
AK		 3479
3480 return ar;
3481}
3482
3483static void vmx_set_segment(struct kvm_vcpu *vcpu,
3484 struct kvm_segment *var, int seg)
3485{
7ffd92c5 3486 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3487 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3488
2fb92db1 3489 vmx_segment_cache_clear(vmx);
2f143240
GN		 3490 if (seg == VCPU_SREG_CS)
3491 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3492
1ecd50a9
GN		 3493 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3494 vmx->rmode.segs[seg] = *var;
3495 if (seg == VCPU_SREG_TR)
3496 vmcs_write16(sf->selector, var->selector);
3497 else if (var->s)
3498 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3499 goto out;
653e3108 3500 }
1ecd50a9 3501
653e3108
AK		 3502 vmcs_writel(sf->base, var->base);
3503 vmcs_write32(sf->limit, var->limit);
3504 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3505
3506 /*
3507 * Fix the "Accessed" bit in AR field of segment registers for older
3508 * qemu binaries.
3509 * IA32 arch specifies that at the time of processor reset the
3510 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3511 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3512 * state vmexit when "unrestricted guest" mode is turned on.
3513 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3514 * tree. Newer qemu binaries with that qemu fix would not need this
3515 * kvm hack.
3516 */
3517 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3518 var->type |= 0x1; /* Accessed */
3a624e29 3519
f924d66d 3520 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3521
3522out:
14168786 3523 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3524}
3525
6aa8b732
AK		 3526static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3527{
2fb92db1 3528 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3529
3530 *db = (ar >> 14) & 1;
3531 *l = (ar >> 13) & 1;
3532}
3533
89a27f4d 3534static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3535{
89a27f4d
GN		 3536 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3537 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3538}
3539
89a27f4d 3540static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3541{
89a27f4d
GN		 3542 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3543 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3544}
3545
89a27f4d 3546static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3547{
89a27f4d
GN		 3548 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3549 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3550}
3551
89a27f4d 3552static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3553{
89a27f4d
GN		 3554 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3555 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3556}
3557
648dfaa7
MG		 3558static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3559{
3560 struct kvm_segment var;
3561 u32 ar;
3562
3563 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3564 var.dpl = 0x3;
0647f4aa
GN		 3565 if (seg == VCPU_SREG_CS)
3566 var.type = 0x3;
648dfaa7
MG		 3567 ar = vmx_segment_access_rights(&var);
3568
3569 if (var.base != (var.selector << 4))
3570 return false;
89efbed0 3571 if (var.limit != 0xffff)
648dfaa7 3572 return false;
07f42f5f 3573 if (ar != 0xf3)
648dfaa7
MG		 3574 return false;
3575
3576 return true;
3577}
3578
3579static bool code_segment_valid(struct kvm_vcpu *vcpu)
3580{
3581 struct kvm_segment cs;
3582 unsigned int cs_rpl;
3583
3584 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3585 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3586
1872a3f4
AK		 3587 if (cs.unusable)
3588 return false;
648dfaa7
MG		 3589 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3590 return false;
3591 if (!cs.s)
3592 return false;
1872a3f4 3593 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3594 if (cs.dpl > cs_rpl)
3595 return false;
1872a3f4 3596 } else {
648dfaa7
MG		 3597 if (cs.dpl != cs_rpl)
3598 return false;
3599 }
3600 if (!cs.present)
3601 return false;
3602
3603 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3604 return true;
3605}
3606
3607static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3608{
3609 struct kvm_segment ss;
3610 unsigned int ss_rpl;
3611
3612 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3613 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3614
1872a3f4
AK		 3615 if (ss.unusable)
3616 return true;
3617 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3618 return false;
3619 if (!ss.s)
3620 return false;
3621 if (ss.dpl != ss_rpl) /* DPL != RPL */
3622 return false;
3623 if (!ss.present)
3624 return false;
3625
3626 return true;
3627}
3628
3629static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3630{
3631 struct kvm_segment var;
3632 unsigned int rpl;
3633
3634 vmx_get_segment(vcpu, &var, seg);
3635 rpl = var.selector & SELECTOR_RPL_MASK;
3636
1872a3f4
AK		 3637 if (var.unusable)
3638 return true;
648dfaa7
MG		 3639 if (!var.s)
3640 return false;
3641 if (!var.present)
3642 return false;
3643 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3644 if (var.dpl < rpl) /* DPL < RPL */
3645 return false;
3646 }
3647
3648 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3649 * rights flags
3650 */
3651 return true;
3652}
3653
3654static bool tr_valid(struct kvm_vcpu *vcpu)
3655{
3656 struct kvm_segment tr;
3657
3658 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3659
1872a3f4
AK		 3660 if (tr.unusable)
3661 return false;
648dfaa7
MG		 3662 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3663 return false;
1872a3f4 3664 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3665 return false;
3666 if (!tr.present)
3667 return false;
3668
3669 return true;
3670}
3671
3672static bool ldtr_valid(struct kvm_vcpu *vcpu)
3673{
3674 struct kvm_segment ldtr;
3675
3676 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3677
1872a3f4
AK		 3678 if (ldtr.unusable)
3679 return true;
648dfaa7
MG		 3680 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3681 return false;
3682 if (ldtr.type != 2)
3683 return false;
3684 if (!ldtr.present)
3685 return false;
3686
3687 return true;
3688}
3689
3690static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3691{
3692 struct kvm_segment cs, ss;
3693
3694 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3695 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3696
3697 return ((cs.selector & SELECTOR_RPL_MASK) ==
3698 (ss.selector & SELECTOR_RPL_MASK));
3699}
3700
3701/*
3702 * Check if guest state is valid. Returns true if valid, false if
3703 * not.
3704 * We assume that registers are always usable
3705 */
3706static bool guest_state_valid(struct kvm_vcpu *vcpu)
3707{
c5e97c80
GN		 3708 if (enable_unrestricted_guest)
3709 return true;
3710
648dfaa7 3711 /* real mode guest state checks */
f13882d8 3712 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3713 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3714 return false;
3715 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3716 return false;
3717 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3718 return false;
3719 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3720 return false;
3721 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3722 return false;
3723 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3724 return false;
3725 } else {
3726 /* protected mode guest state checks */
3727 if (!cs_ss_rpl_check(vcpu))
3728 return false;
3729 if (!code_segment_valid(vcpu))
3730 return false;
3731 if (!stack_segment_valid(vcpu))
3732 return false;
3733 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3734 return false;
3735 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3736 return false;
3737 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3738 return false;
3739 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3740 return false;
3741 if (!tr_valid(vcpu))
3742 return false;
3743 if (!ldtr_valid(vcpu))
3744 return false;
3745 }
3746 /* TODO:
3747 * - Add checks on RIP
3748 * - Add checks on RFLAGS
3749 */
3750
3751 return true;
3752}
3753
d77c26fc 3754static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3755{
40dcaa9f 3756 gfn_t fn;
195aefde 3757 u16 data = 0;
40dcaa9f 3758 int r, idx, ret = 0;
6aa8b732 3759
40dcaa9f 3760 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3761 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3762 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3763 if (r < 0)
10589a46 3764 goto out;
195aefde 3765 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3766 r = kvm_write_guest_page(kvm, fn++, &data,
3767 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3768 if (r < 0)
10589a46 3769 goto out;
195aefde
IE		 3770 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3771 if (r < 0)
10589a46 3772 goto out;
195aefde
IE		 3773 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3774 if (r < 0)
10589a46 3775 goto out;
195aefde 3776 data = ~0;
10589a46
MT		 3777 r = kvm_write_guest_page(kvm, fn, &data,
3778 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3779 sizeof(u8));
195aefde 3780 if (r < 0)
10589a46
MT		 3781 goto out;
3782
3783 ret = 1;
3784out:
40dcaa9f 3785 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3786 return ret;
6aa8b732
AK		 3787}
3788
b7ebfb05
SY		 3789static int init_rmode_identity_map(struct kvm *kvm)
3790{
40dcaa9f 3791 int i, idx, r, ret;
b7ebfb05
SY		 3792 pfn_t identity_map_pfn;
3793 u32 tmp;
3794
089d034e 3795 if (!enable_ept)
b7ebfb05
SY		 3796 return 1;
3797 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3798 printk(KERN_ERR "EPT: identity-mapping pagetable "
3799 "haven't been allocated!\n");
3800 return 0;
3801 }
3802 if (likely(kvm->arch.ept_identity_pagetable_done))
3803 return 1;
3804 ret = 0;
b927a3ce 3805 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3806 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3807 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3808 if (r < 0)
3809 goto out;
3810 /* Set up identity-mapping pagetable for EPT in real mode */
3811 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3812 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3813 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3814 r = kvm_write_guest_page(kvm, identity_map_pfn,
3815 &tmp, i * sizeof(tmp), sizeof(tmp));
3816 if (r < 0)
3817 goto out;
3818 }
3819 kvm->arch.ept_identity_pagetable_done = true;
3820 ret = 1;
3821out:
40dcaa9f 3822 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3823 return ret;
3824}
3825
6aa8b732
AK		 3826static void seg_setup(int seg)
3827{
772e0318 3828 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3829 unsigned int ar;
6aa8b732
AK		 3830
3831 vmcs_write16(sf->selector, 0);
3832 vmcs_writel(sf->base, 0);
3833 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3834 ar = 0x93;
3835 if (seg == VCPU_SREG_CS)
3836 ar |= 0x08; /* code segment */
3a624e29
NK		 3837
3838 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3839}
3840
f78e0e2e
SY		 3841static int alloc_apic_access_page(struct kvm *kvm)
3842{
4484141a 3843 struct page *page;
f78e0e2e
SY		 3844 struct kvm_userspace_memory_region kvm_userspace_mem;
3845 int r = 0;
3846
79fac95e 3847 mutex_lock(&kvm->slots_lock);
bfc6d222 3848 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3849 goto out;
3850 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3851 kvm_userspace_mem.flags = 0;
3852 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3853 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3854 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3855 if (r)
3856 goto out;
72dc67a6 3857
4484141a
XG		 3858 page = gfn_to_page(kvm, 0xfee00);
3859 if (is_error_page(page)) {
3860 r = -EFAULT;
3861 goto out;
3862 }
3863
3864 kvm->arch.apic_access_page = page;
f78e0e2e 3865out:
79fac95e 3866 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3867 return r;
3868}
3869
b7ebfb05
SY		 3870static int alloc_identity_pagetable(struct kvm *kvm)
3871{
4484141a 3872 struct page *page;
b7ebfb05
SY		 3873 struct kvm_userspace_memory_region kvm_userspace_mem;
3874 int r = 0;
3875
79fac95e 3876 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3877 if (kvm->arch.ept_identity_pagetable)
3878 goto out;
3879 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3880 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3881 kvm_userspace_mem.guest_phys_addr =
3882 kvm->arch.ept_identity_map_addr;
b7ebfb05 3883 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3884 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3885 if (r)
3886 goto out;
3887
4484141a
XG		 3888 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3889 if (is_error_page(page)) {
3890 r = -EFAULT;
3891 goto out;
3892 }
3893
3894 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3895out:
79fac95e 3896 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3897 return r;
3898}
3899
2384d2b3
SY		 3900static void allocate_vpid(struct vcpu_vmx *vmx)
3901{
3902 int vpid;
3903
3904 vmx->vpid = 0;
919818ab 3905 if (!enable_vpid)
2384d2b3
SY		 3906 return;
3907 spin_lock(&vmx_vpid_lock);
3908 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3909 if (vpid < VMX_NR_VPIDS) {
3910 vmx->vpid = vpid;
3911 __set_bit(vpid, vmx_vpid_bitmap);
3912 }
3913 spin_unlock(&vmx_vpid_lock);
3914}
3915
cdbecfc3
LJ		 3916static void free_vpid(struct vcpu_vmx *vmx)
3917{
3918 if (!enable_vpid)
3919 return;
3920 spin_lock(&vmx_vpid_lock);
3921 if (vmx->vpid != 0)
3922 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3923 spin_unlock(&vmx_vpid_lock);
3924}
3925
8d14695f
YZ		 3926#define MSR_TYPE_R 1
3927#define MSR_TYPE_W 2
3928static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3929 u32 msr, int type)
25c5f225 3930{
3e7c73e9 3931 int f = sizeof(unsigned long);
25c5f225
SY		 3932
3933 if (!cpu_has_vmx_msr_bitmap())
3934 return;
3935
3936 /*
3937 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3938 * have the write-low and read-high bitmap offsets the wrong way round.
3939 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3940 */
25c5f225 3941 if (msr <= 0x1fff) {
8d14695f
YZ		 3942 if (type & MSR_TYPE_R)
3943 /* read-low */
3944 __clear_bit(msr, msr_bitmap + 0x000 / f);
3945
3946 if (type & MSR_TYPE_W)
3947 /* write-low */
3948 __clear_bit(msr, msr_bitmap + 0x800 / f);
3949
25c5f225
SY		 3950 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3951 msr &= 0x1fff;
8d14695f
YZ		 3952 if (type & MSR_TYPE_R)
3953 /* read-high */
3954 __clear_bit(msr, msr_bitmap + 0x400 / f);
3955
3956 if (type & MSR_TYPE_W)
3957 /* write-high */
3958 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3959
3960 }
3961}
3962
3963static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3964 u32 msr, int type)
3965{
3966 int f = sizeof(unsigned long);
3967
3968 if (!cpu_has_vmx_msr_bitmap())
3969 return;
3970
3971 /*
3972 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3973 * have the write-low and read-high bitmap offsets the wrong way round.
3974 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3975 */
3976 if (msr <= 0x1fff) {
3977 if (type & MSR_TYPE_R)
3978 /* read-low */
3979 __set_bit(msr, msr_bitmap + 0x000 / f);
3980
3981 if (type & MSR_TYPE_W)
3982 /* write-low */
3983 __set_bit(msr, msr_bitmap + 0x800 / f);
3984
3985 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3986 msr &= 0x1fff;
3987 if (type & MSR_TYPE_R)
3988 /* read-high */
3989 __set_bit(msr, msr_bitmap + 0x400 / f);
3990
3991 if (type & MSR_TYPE_W)
3992 /* write-high */
3993 __set_bit(msr, msr_bitmap + 0xc00 / f);
3994
25c5f225 3995 }
25c5f225
SY		 3996}
3997
5897297b
AK		 3998static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3999{
4000 if (!longmode_only)
8d14695f
YZ		 4001 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4002 msr, MSR_TYPE_R | MSR_TYPE_W);
4003 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4004 msr, MSR_TYPE_R | MSR_TYPE_W);
4005}
4006
4007static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4008{
4009 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4010 msr, MSR_TYPE_R);
4011 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4012 msr, MSR_TYPE_R);
4013}
4014
4015static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4016{
4017 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4018 msr, MSR_TYPE_R);
4019 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4020 msr, MSR_TYPE_R);
4021}
4022
4023static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4024{
4025 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4026 msr, MSR_TYPE_W);
4027 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4028 msr, MSR_TYPE_W);
5897297b
AK		 4029}
4030
01e439be
YZ		 4031static int vmx_vm_has_apicv(struct kvm *kvm)
4032{
4033 return enable_apicv && irqchip_in_kernel(kvm);
4034}
4035
a20ed54d
YZ		 4036/*
4037 * Send interrupt to vcpu via posted interrupt way.
4038 * 1. If target vcpu is running(non-root mode), send posted interrupt
4039 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4040 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4041 * interrupt from PIR in next vmentry.
4042 */
4043static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4044{
4045 struct vcpu_vmx *vmx = to_vmx(vcpu);
4046 int r;
4047
4048 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4049 return;
4050
4051 r = pi_test_and_set_on(&vmx->pi_desc);
4052 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4053#ifdef CONFIG_SMP
a20ed54d
YZ		 4054 if (!r && (vcpu->mode == IN_GUEST_MODE))
4055 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4056 POSTED_INTR_VECTOR);
4057 else
6ffbbbba 4058#endif
a20ed54d
YZ		 4059 kvm_vcpu_kick(vcpu);
4060}
4061
4062static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4063{
4064 struct vcpu_vmx *vmx = to_vmx(vcpu);
4065
4066 if (!pi_test_and_clear_on(&vmx->pi_desc))
4067 return;
4068
4069 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4070}
4071
4072static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4073{
4074 return;
4075}
4076
a3a8ff8e
NHE		 4077/*
4078 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4079 * will not change in the lifetime of the guest.
4080 * Note that host-state that does change is set elsewhere. E.g., host-state
4081 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4082 */
a547c6db 4083static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4084{
4085 u32 low32, high32;
4086 unsigned long tmpl;
4087 struct desc_ptr dt;
747a43ad 4088 unsigned long cr4;
a3a8ff8e 4089
b1a74bf8 4090 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4091 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4092
747a43ad
AL		 4093 /* Save the most likely value for this task's CR4 in the VMCS. */
4094 cr4 = read_cr4();
4095 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4096 vmx->host_state.vmcs_host_cr4 = cr4;
4097
a3a8ff8e 4098 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4099#ifdef CONFIG_X86_64
4100 /*
4101 * Load null selectors, so we can avoid reloading them in
4102 * __vmx_load_host_state(), in case userspace uses the null selectors
4103 * too (the expected case).
4104 */
4105 vmcs_write16(HOST_DS_SELECTOR, 0);
4106 vmcs_write16(HOST_ES_SELECTOR, 0);
4107#else
a3a8ff8e
NHE		 4108 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4109 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4110#endif
a3a8ff8e
NHE		 4111 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4112 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4113
4114 native_store_idt(&dt);
4115 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4116 vmx->host_idt_base = dt.address;
a3a8ff8e 4117
83287ea4 4118 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4119
4120 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4121 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4122 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4123 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4124
4125 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4126 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4127 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4128 }
4129}
4130
bf8179a0
NHE		 4131static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4132{
4133 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4134 if (enable_ept)
4135 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4136 if (is_guest_mode(&vmx->vcpu))
4137 vmx->vcpu.arch.cr4_guest_owned_bits &=
4138 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4139 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4140}
4141
01e439be
YZ		 4142static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4143{
4144 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4145
4146 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4147 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4148 return pin_based_exec_ctrl;
4149}
4150
bf8179a0
NHE		 4151static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4152{
4153 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4154 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4155 exec_control &= ~CPU_BASED_TPR_SHADOW;
4156#ifdef CONFIG_X86_64
4157 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4158 CPU_BASED_CR8_LOAD_EXITING;
4159#endif
4160 }
4161 if (!enable_ept)
4162 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4163 CPU_BASED_CR3_LOAD_EXITING |
4164 CPU_BASED_INVLPG_EXITING;
4165 return exec_control;
4166}
4167
4168static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4169{
4170 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4171 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4172 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4173 if (vmx->vpid == 0)
4174 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4175 if (!enable_ept) {
4176 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4177 enable_unrestricted_guest = 0;
ad756a16
MJ		 4178 /* Enable INVPCID for non-ept guests may cause performance regression. */
4179 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4180 }
4181 if (!enable_unrestricted_guest)
4182 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4183 if (!ple_gap)
4184 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4185 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4186 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4187 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4188 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4189 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4190 (handle_vmptrld).
4191 We can NOT enable shadow_vmcs here because we don't have yet
4192 a current VMCS12
4193 */
4194 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4195 return exec_control;
4196}
4197
ce88decf
XG		 4198static void ept_set_mmio_spte_mask(void)
4199{
4200 /*
4201 * EPT Misconfigurations can be generated if the value of bits 2:0
4202 * of an EPT paging-structure entry is 110b (write/execute).
4203 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4204 * spte.
4205 */
4206 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4207}
4208
6aa8b732
AK		 4209/*
4210 * Sets up the vmcs for emulated real mode.
4211 */
8b9cf98c 4212static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4213{
2e4ce7f5 4214#ifdef CONFIG_X86_64
6aa8b732 4215 unsigned long a;
2e4ce7f5 4216#endif
6aa8b732 4217 int i;
6aa8b732 4218
6aa8b732 4219 /* I/O */
3e7c73e9
AK		 4220 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4221 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4222
4607c2d7
AG		 4223 if (enable_shadow_vmcs) {
4224 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4225 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4226 }
25c5f225 4227 if (cpu_has_vmx_msr_bitmap())
5897297b 4228 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4229
6aa8b732
AK		 4230 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4231
6aa8b732 4232 /* Control */
01e439be 4233 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4234
bf8179a0 4235 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4236
83ff3b9d 4237 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4238 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4239 vmx_secondary_exec_control(vmx));
83ff3b9d 4240 }
f78e0e2e 4241
01e439be 4242 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4243 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4244 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4245 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4246 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4247
4248 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4249
4250 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4251 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4252 }
4253
4b8d54f9
ZE		 4254 if (ple_gap) {
4255 vmcs_write32(PLE_GAP, ple_gap);
4256 vmcs_write32(PLE_WINDOW, ple_window);
4257 }
4258
c3707958
XG		 4259 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4260 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4261 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4262
9581d442
AK		 4263 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4264 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4265 vmx_set_constant_host_state(vmx);
05b3e0c2 4266#ifdef CONFIG_X86_64
6aa8b732
AK		 4267 rdmsrl(MSR_FS_BASE, a);
4268 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4269 rdmsrl(MSR_GS_BASE, a);
4270 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4271#else
4272 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4273 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4274#endif
4275
2cc51560
ED		 4276 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4277 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4278 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4279 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4280 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4281
468d472f 4282 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4283 u32 msr_low, msr_high;
4284 u64 host_pat;
468d472f
SY		 4285 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4286 host_pat = msr_low | ((u64) msr_high << 32);
4287 /* Write the default value follow host pat */
4288 vmcs_write64(GUEST_IA32_PAT, host_pat);
4289 /* Keep arch.pat sync with GUEST_IA32_PAT */
4290 vmx->vcpu.arch.pat = host_pat;
4291 }
4292
6aa8b732
AK		 4293 for (i = 0; i < NR_VMX_MSR; ++i) {
4294 u32 index = vmx_msr_index[i];
4295 u32 data_low, data_high;
a2fa3e9f 4296 int j = vmx->nmsrs;
6aa8b732
AK		 4297
4298 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4299 continue;
432bd6cb
AK		 4300 if (wrmsr_safe(index, data_low, data_high) < 0)
4301 continue;
26bb0981
AK		 4302 vmx->guest_msrs[j].index = i;
4303 vmx->guest_msrs[j].data = 0;
d5696725 4304 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4305 ++vmx->nmsrs;
6aa8b732 4306 }
6aa8b732 4307
1c3d14fe 4308 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4309
4310 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4311 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4312
e00c8cf2 4313 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4314 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4315
4316 return 0;
4317}
4318
57f252f2 4319static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4320{
4321 struct vcpu_vmx *vmx = to_vmx(vcpu);
4322 u64 msr;
e00c8cf2 4323
7ffd92c5 4324 vmx->rmode.vm86_active = 0;
e00c8cf2 4325
3b86cd99
JK		 4326 vmx->soft_vnmi_blocked = 0;
4327
ad312c7c 4328 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4329 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4330 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4331 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4332 msr |= MSR_IA32_APICBASE_BSP;
4333 kvm_set_apic_base(&vmx->vcpu, msr);
4334
2fb92db1
AK		 4335 vmx_segment_cache_clear(vmx);
4336
5706be0d 4337 seg_setup(VCPU_SREG_CS);
66450a21 4338 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4339 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4340
4341 seg_setup(VCPU_SREG_DS);
4342 seg_setup(VCPU_SREG_ES);
4343 seg_setup(VCPU_SREG_FS);
4344 seg_setup(VCPU_SREG_GS);
4345 seg_setup(VCPU_SREG_SS);
4346
4347 vmcs_write16(GUEST_TR_SELECTOR, 0);
4348 vmcs_writel(GUEST_TR_BASE, 0);
4349 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4350 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4351
4352 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4353 vmcs_writel(GUEST_LDTR_BASE, 0);
4354 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4355 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4356
4357 vmcs_write32(GUEST_SYSENTER_CS, 0);
4358 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4359 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4360
4361 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4362 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4363
e00c8cf2
AK		 4364 vmcs_writel(GUEST_GDTR_BASE, 0);
4365 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4366
4367 vmcs_writel(GUEST_IDTR_BASE, 0);
4368 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4369
443381a8 4370 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4371 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4372 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4373
e00c8cf2
AK		 4374 /* Special registers */
4375 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4376
4377 setup_msrs(vmx);
4378
6aa8b732
AK		 4379 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4380
f78e0e2e
SY		 4381 if (cpu_has_vmx_tpr_shadow()) {
4382 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4383 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4384 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4385 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4386 vmcs_write32(TPR_THRESHOLD, 0);
4387 }
4388
4389 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4390 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4391 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4392
01e439be
YZ		 4393 if (vmx_vm_has_apicv(vcpu->kvm))
4394 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4395
2384d2b3
SY		 4396 if (vmx->vpid != 0)
4397 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4398
fa40052c 4399 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4400 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4401 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4402 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4403 vmx_fpu_activate(&vmx->vcpu);
4404 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4405
b9d762fa 4406 vpid_sync_context(vmx);
6aa8b732
AK		 4407}
4408
b6f1250e
NHE		 4409/*
4410 * In nested virtualization, check if L1 asked to exit on external interrupts.
4411 * For most existing hypervisors, this will always return true.
4412 */
4413static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4414{
4415 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4416 PIN_BASED_EXT_INTR_MASK;
4417}
4418
ea8ceb83
JK		 4419static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4420{
4421 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4422 PIN_BASED_NMI_EXITING;
4423}
4424
730dca42 4425static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4426{
4427 u32 cpu_based_vm_exec_control;
730dca42
JK		 4428
4429 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4430 /*
4431 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4432 * inject to L1 now because L2 must run. The caller will have
4433 * to make L2 exit right after entry, so we can inject to L1
4434 * more promptly.
b6f1250e 4435 */
730dca42 4436 return -EBUSY;
3b86cd99
JK		 4437
4438 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4439 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4440 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4441 return 0;
3b86cd99
JK		 4442}
4443
03b28f81 4444static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4445{
4446 u32 cpu_based_vm_exec_control;
4447
03b28f81
JK		 4448 if (!cpu_has_virtual_nmis())
4449 return enable_irq_window(vcpu);
4450
4451 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4452 return enable_irq_window(vcpu);
3b86cd99
JK		 4453
4454 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4455 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4456 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4457 return 0;
3b86cd99
JK		 4458}
4459
66fd3f7f 4460static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4461{
9c8cba37 4462 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4463 uint32_t intr;
4464 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4465
229456fc 4466 trace_kvm_inj_virq(irq);
2714d1d3 4467
fa89a817 4468 ++vcpu->stat.irq_injections;
7ffd92c5 4469 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4470 int inc_eip = 0;
4471 if (vcpu->arch.interrupt.soft)
4472 inc_eip = vcpu->arch.event_exit_inst_len;
4473 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4474 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4475 return;
4476 }
66fd3f7f
GN		 4477 intr = irq | INTR_INFO_VALID_MASK;
4478 if (vcpu->arch.interrupt.soft) {
4479 intr |= INTR_TYPE_SOFT_INTR;
4480 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4481 vmx->vcpu.arch.event_exit_inst_len);
4482 } else
4483 intr |= INTR_TYPE_EXT_INTR;
4484 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4485}
4486
f08864b4
SY		 4487static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4488{
66a5a347
JK		 4489 struct vcpu_vmx *vmx = to_vmx(vcpu);
4490
0b6ac343
NHE		 4491 if (is_guest_mode(vcpu))
4492 return;
4493
3b86cd99
JK		 4494 if (!cpu_has_virtual_nmis()) {
4495 /*
4496 * Tracking the NMI-blocked state in software is built upon
4497 * finding the next open IRQ window. This, in turn, depends on
4498 * well-behaving guests: They have to keep IRQs disabled at
4499 * least as long as the NMI handler runs. Otherwise we may
4500 * cause NMI nesting, maybe breaking the guest. But as this is
4501 * highly unlikely, we can live with the residual risk.
4502 */
4503 vmx->soft_vnmi_blocked = 1;
4504 vmx->vnmi_blocked_time = 0;
4505 }
4506
487b391d 4507 ++vcpu->stat.nmi_injections;
9d58b931 4508 vmx->nmi_known_unmasked = false;
7ffd92c5 4509 if (vmx->rmode.vm86_active) {
71f9833b 4510 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4512 return;
4513 }
f08864b4
SY		 4514 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4515 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4516}
4517
3cfc3092
JK		 4518static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4519{
4520 if (!cpu_has_virtual_nmis())
4521 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4522 if (to_vmx(vcpu)->nmi_known_unmasked)
4523 return false;
c332c83a 4524 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4525}
4526
4527static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4528{
4529 struct vcpu_vmx *vmx = to_vmx(vcpu);
4530
4531 if (!cpu_has_virtual_nmis()) {
4532 if (vmx->soft_vnmi_blocked != masked) {
4533 vmx->soft_vnmi_blocked = masked;
4534 vmx->vnmi_blocked_time = 0;
4535 }
4536 } else {
9d58b931 4537 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4538 if (masked)
4539 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4540 GUEST_INTR_STATE_NMI);
4541 else
4542 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4543 GUEST_INTR_STATE_NMI);
4544 }
4545}
4546
2505dc9f
JK		 4547static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4548{
ea8ceb83
JK		 4549 if (is_guest_mode(vcpu)) {
4550 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4551
4552 if (to_vmx(vcpu)->nested.nested_run_pending)
4553 return 0;
4554 if (nested_exit_on_nmi(vcpu)) {
4555 nested_vmx_vmexit(vcpu);
4556 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4557 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4558 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4559 /*
4560 * The NMI-triggered VM exit counts as injection:
4561 * clear this one and block further NMIs.
4562 */
4563 vcpu->arch.nmi_pending = 0;
4564 vmx_set_nmi_mask(vcpu, true);
4565 return 0;
4566 }
4567 }
4568
2505dc9f
JK		 4569 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4570 return 0;
4571
4572 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4573 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4574 | GUEST_INTR_STATE_NMI));
4575}
4576
78646121
GN		 4577static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4578{
e8457c67 4579 if (is_guest_mode(vcpu)) {
51cfe38e 4580 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4581
4582 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4583 return 0;
e8457c67
JK		 4584 if (nested_exit_on_intr(vcpu)) {
4585 nested_vmx_vmexit(vcpu);
4586 vmcs12->vm_exit_reason =
4587 EXIT_REASON_EXTERNAL_INTERRUPT;
4588 vmcs12->vm_exit_intr_info = 0;
4589 /*
4590 * fall through to normal code, but now in L1, not L2
4591 */
4592 }
b6f1250e
NHE		 4593 }
4594
c4282df9
GN		 4595 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4596 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4597 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4598}
4599
cbc94022
IE		 4600static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4601{
4602 int ret;
4603 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4604 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4605 .guest_phys_addr = addr,
4606 .memory_size = PAGE_SIZE * 3,
4607 .flags = 0,
4608 };
4609
47ae31e2 4610 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4611 if (ret)
4612 return ret;
bfc6d222 4613 kvm->arch.tss_addr = addr;
93ea5388
GN		 4614 if (!init_rmode_tss(kvm))
4615 return -ENOMEM;
4616
cbc94022
IE		 4617 return 0;
4618}
4619
0ca1b4f4 4620static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4621{
77ab6db0 4622 switch (vec) {
77ab6db0 4623 case BP_VECTOR:
c573cd22
JK		 4624 /*
4625 * Update instruction length as we may reinject the exception
4626 * from user space while in guest debugging mode.
4627 */
4628 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4629 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4630 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4631 return false;
4632 /* fall through */
4633 case DB_VECTOR:
4634 if (vcpu->guest_debug &
4635 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4636 return false;
d0bfb940
JK		 4637 /* fall through */
4638 case DE_VECTOR:
77ab6db0
JK		 4639 case OF_VECTOR:
4640 case BR_VECTOR:
4641 case UD_VECTOR:
4642 case DF_VECTOR:
4643 case SS_VECTOR:
4644 case GP_VECTOR:
4645 case MF_VECTOR:
0ca1b4f4
GN		 4646 return true;
4647 break;
77ab6db0 4648 }
0ca1b4f4
GN		 4649 return false;
4650}
4651
4652static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4653 int vec, u32 err_code)
4654{
4655 /*
4656 * Instruction with address size override prefix opcode 0x67
4657 * Cause the #SS fault with 0 error code in VM86 mode.
4658 */
4659 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4660 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4661 if (vcpu->arch.halt_request) {
4662 vcpu->arch.halt_request = 0;
4663 return kvm_emulate_halt(vcpu);
4664 }
4665 return 1;
4666 }
4667 return 0;
4668 }
4669
4670 /*
4671 * Forward all other exceptions that are valid in real mode.
4672 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4673 * the required debugging infrastructure rework.
4674 */
4675 kvm_queue_exception(vcpu, vec);
4676 return 1;
6aa8b732
AK		 4677}
4678
a0861c02
AK		 4679/*
4680 * Trigger machine check on the host. We assume all the MSRs are already set up
4681 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4682 * We pass a fake environment to the machine check handler because we want
4683 * the guest to be always treated like user space, no matter what context
4684 * it used internally.
4685 */
4686static void kvm_machine_check(void)
4687{
4688#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4689 struct pt_regs regs = {
4690 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4691 .flags = X86_EFLAGS_IF,
4692 };
4693
4694 do_machine_check(&regs, 0);
4695#endif
4696}
4697
851ba692 4698static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4699{
4700 /* already handled by vcpu_run */
4701 return 1;
4702}
4703
851ba692 4704static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4705{
1155f76a 4706 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4707 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4708 u32 intr_info, ex_no, error_code;
42dbaa5a 4709 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4710 u32 vect_info;
4711 enum emulation_result er;
4712
1155f76a 4713 vect_info = vmx->idt_vectoring_info;
88786475 4714 intr_info = vmx->exit_intr_info;
6aa8b732 4715
a0861c02 4716 if (is_machine_check(intr_info))
851ba692 4717 return handle_machine_check(vcpu);
a0861c02 4718
58e4633a 4719 if (is_nmi(intr_info))
1b6269db 4720 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4721
4722 if (is_no_device(intr_info)) {
5fd86fcf 4723 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4724 return 1;
4725 }
4726
7aa81cc0 4727 if (is_invalid_opcode(intr_info)) {
51d8b661 4728 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4729 if (er != EMULATE_DONE)
7ee5d940 4730 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4731 return 1;
4732 }
4733
6aa8b732 4734 error_code = 0;
2e11384c 4735 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4736 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4737
4738 /*
4739 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4740 * MMIO, it is better to report an internal error.
4741 * See the comments in vmx_handle_exit.
4742 */
4743 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4744 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4745 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4746 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4747 vcpu->run->internal.ndata = 2;
4748 vcpu->run->internal.data[0] = vect_info;
4749 vcpu->run->internal.data[1] = intr_info;
4750 return 0;
4751 }
4752
6aa8b732 4753 if (is_page_fault(intr_info)) {
1439442c 4754 /* EPT won't cause page fault directly */
cf3ace79 4755 BUG_ON(enable_ept);
6aa8b732 4756 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4757 trace_kvm_page_fault(cr2, error_code);
4758
3298b75c 4759 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4760 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4761 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4762 }
4763
d0bfb940 4764 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4765
4766 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4767 return handle_rmode_exception(vcpu, ex_no, error_code);
4768
42dbaa5a
JK		 4769 switch (ex_no) {
4770 case DB_VECTOR:
4771 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4772 if (!(vcpu->guest_debug &
4773 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4774 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4775 kvm_queue_exception(vcpu, DB_VECTOR);
4776 return 1;
4777 }
4778 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4779 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4780 /* fall through */
4781 case BP_VECTOR:
c573cd22
JK		 4782 /*
4783 * Update instruction length as we may reinject #BP from
4784 * user space while in guest debugging mode. Reading it for
4785 * #DB as well causes no harm, it is not used in that case.
4786 */
4787 vmx->vcpu.arch.event_exit_inst_len =
4788 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4789 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4790 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4791 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4792 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4793 break;
4794 default:
d0bfb940
JK		 4795 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4796 kvm_run->ex.exception = ex_no;
4797 kvm_run->ex.error_code = error_code;
42dbaa5a 4798 break;
6aa8b732 4799 }
6aa8b732
AK		 4800 return 0;
4801}
4802
851ba692 4803static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4804{
1165f5fe 4805 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4806 return 1;
4807}
4808
851ba692 4809static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4810{
851ba692 4811 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4812 return 0;
4813}
6aa8b732 4814
851ba692 4815static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4816{
bfdaab09 4817 unsigned long exit_qualification;
34c33d16 4818 int size, in, string;
039576c0 4819 unsigned port;
6aa8b732 4820
bfdaab09 4821 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4822 string = (exit_qualification & 16) != 0;
cf8f70bf 4823 in = (exit_qualification & 8) != 0;
e70669ab 4824
cf8f70bf 4825 ++vcpu->stat.io_exits;
e70669ab 4826
cf8f70bf 4827 if (string || in)
51d8b661 4828 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4829
cf8f70bf
GN		 4830 port = exit_qualification >> 16;
4831 size = (exit_qualification & 7) + 1;
e93f36bc 4832 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4833
4834 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4835}
4836
102d8325
IM		 4837static void
4838vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4839{
4840 /*
4841 * Patch in the VMCALL instruction:
4842 */
4843 hypercall[0] = 0x0f;
4844 hypercall[1] = 0x01;
4845 hypercall[2] = 0xc1;
102d8325
IM		 4846}
4847
0fa06071 4848/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4849static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4850{
eeadf9e7 4851 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4852 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4853 unsigned long orig_val = val;
4854
eeadf9e7
NHE		 4855 /*
4856 * We get here when L2 changed cr0 in a way that did not change
4857 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4858 * but did change L0 shadowed bits. So we first calculate the
4859 * effective cr0 value that L1 would like to write into the
4860 * hardware. It consists of the L2-owned bits from the new
4861 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4862 */
1a0d74e6
JK		 4863 val = (val & ~vmcs12->cr0_guest_host_mask) |
4864 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4865
4866 /* TODO: will have to take unrestricted guest mode into
4867 * account */
4868 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4869 return 1;
1a0d74e6
JK		 4870
4871 if (kvm_set_cr0(vcpu, val))
4872 return 1;
4873 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4874 return 0;
1a0d74e6
JK		 4875 } else {
4876 if (to_vmx(vcpu)->nested.vmxon &&
4877 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4878 return 1;
eeadf9e7 4879 return kvm_set_cr0(vcpu, val);
1a0d74e6 4880 }
eeadf9e7
NHE		 4881}
4882
4883static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4884{
4885 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4886 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4887 unsigned long orig_val = val;
4888
4889 /* analogously to handle_set_cr0 */
4890 val = (val & ~vmcs12->cr4_guest_host_mask) |
4891 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4892 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4893 return 1;
1a0d74e6 4894 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4895 return 0;
4896 } else
4897 return kvm_set_cr4(vcpu, val);
4898}
4899
4900/* called to set cr0 as approriate for clts instruction exit. */
4901static void handle_clts(struct kvm_vcpu *vcpu)
4902{
4903 if (is_guest_mode(vcpu)) {
4904 /*
4905 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4906 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4907 * just pretend it's off (also in arch.cr0 for fpu_activate).
4908 */
4909 vmcs_writel(CR0_READ_SHADOW,
4910 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4911 vcpu->arch.cr0 &= ~X86_CR0_TS;
4912 } else
4913 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4914}
4915
851ba692 4916static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4917{
229456fc 4918 unsigned long exit_qualification, val;
6aa8b732
AK		 4919 int cr;
4920 int reg;
49a9b07e 4921 int err;
6aa8b732 4922
bfdaab09 4923 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4924 cr = exit_qualification & 15;
4925 reg = (exit_qualification >> 8) & 15;
4926 switch ((exit_qualification >> 4) & 3) {
4927 case 0: /* mov to cr */
229456fc
MT		 4928 val = kvm_register_read(vcpu, reg);
4929 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4930 switch (cr) {
4931 case 0:
eeadf9e7 4932 err = handle_set_cr0(vcpu, val);
db8fcefa 4933 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4934 return 1;
4935 case 3:
2390218b 4936 err = kvm_set_cr3(vcpu, val);
db8fcefa 4937 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4938 return 1;
4939 case 4:
eeadf9e7 4940 err = handle_set_cr4(vcpu, val);
db8fcefa 4941 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4942 return 1;
0a5fff19
GN		 4943 case 8: {
4944 u8 cr8_prev = kvm_get_cr8(vcpu);
4945 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4946 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4947 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4948 if (irqchip_in_kernel(vcpu->kvm))
4949 return 1;
4950 if (cr8_prev <= cr8)
4951 return 1;
851ba692 4952 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4953 return 0;
4954 }
4b8073e4 4955 }
6aa8b732 4956 break;
25c4c276 4957 case 2: /* clts */
eeadf9e7 4958 handle_clts(vcpu);
4d4ec087 4959 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4960 skip_emulated_instruction(vcpu);
6b52d186 4961 vmx_fpu_activate(vcpu);
25c4c276 4962 return 1;
6aa8b732
AK		 4963 case 1: /*mov from cr*/
4964 switch (cr) {
4965 case 3:
9f8fe504
AK		 4966 val = kvm_read_cr3(vcpu);
4967 kvm_register_write(vcpu, reg, val);
4968 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4969 skip_emulated_instruction(vcpu);
4970 return 1;
4971 case 8:
229456fc
MT		 4972 val = kvm_get_cr8(vcpu);
4973 kvm_register_write(vcpu, reg, val);
4974 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4975 skip_emulated_instruction(vcpu);
4976 return 1;
4977 }
4978 break;
4979 case 3: /* lmsw */
a1f83a74 4980 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4981 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4982 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4983
4984 skip_emulated_instruction(vcpu);
4985 return 1;
4986 default:
4987 break;
4988 }
851ba692 4989 vcpu->run->exit_reason = 0;
a737f256 4990 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4991 (int)(exit_qualification >> 4) & 3, cr);
4992 return 0;
4993}
4994
851ba692 4995static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4996{
bfdaab09 4997 unsigned long exit_qualification;
6aa8b732
AK		 4998 int dr, reg;
4999
f2483415 5000 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5001 if (!kvm_require_cpl(vcpu, 0))
5002 return 1;
42dbaa5a
JK		 5003 dr = vmcs_readl(GUEST_DR7);
5004 if (dr & DR7_GD) {
5005 /*
5006 * As the vm-exit takes precedence over the debug trap, we
5007 * need to emulate the latter, either for the host or the
5008 * guest debugging itself.
5009 */
5010 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5011 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5012 vcpu->run->debug.arch.dr7 = dr;
5013 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5014 vmcs_readl(GUEST_CS_BASE) +
5015 vmcs_readl(GUEST_RIP);
851ba692
AK		 5016 vcpu->run->debug.arch.exception = DB_VECTOR;
5017 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5018 return 0;
5019 } else {
5020 vcpu->arch.dr7 &= ~DR7_GD;
5021 vcpu->arch.dr6 |= DR6_BD;
5022 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5023 kvm_queue_exception(vcpu, DB_VECTOR);
5024 return 1;
5025 }
5026 }
5027
bfdaab09 5028 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5029 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5030 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5031 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5032 unsigned long val;
5033 if (!kvm_get_dr(vcpu, dr, &val))
5034 kvm_register_write(vcpu, reg, val);
5035 } else
5036 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5037 skip_emulated_instruction(vcpu);
5038 return 1;
5039}
5040
020df079
GN		 5041static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5042{
5043 vmcs_writel(GUEST_DR7, val);
5044}
5045
851ba692 5046static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5047{
06465c5a
AK		 5048 kvm_emulate_cpuid(vcpu);
5049 return 1;
6aa8b732
AK		 5050}
5051
851ba692 5052static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5053{
ad312c7c 5054 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5055 u64 data;
5056
5057 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5058 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5059 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5060 return 1;
5061 }
5062
229456fc 5063 trace_kvm_msr_read(ecx, data);
2714d1d3 5064
6aa8b732 5065 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5066 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5067 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5068 skip_emulated_instruction(vcpu);
5069 return 1;
5070}
5071
851ba692 5072static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5073{
8fe8ab46 5074 struct msr_data msr;
ad312c7c
ZX		 5075 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5076 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5077 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5078
8fe8ab46
WA		 5079 msr.data = data;
5080 msr.index = ecx;
5081 msr.host_initiated = false;
ea306147 5082 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5083 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5084 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5085 return 1;
5086 }
5087
59200273 5088 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5089 skip_emulated_instruction(vcpu);
5090 return 1;
5091}
5092
851ba692 5093static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5094{
3842d135 5095 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5096 return 1;
5097}
5098
851ba692 5099static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5100{
85f455f7
ED		 5101 u32 cpu_based_vm_exec_control;
5102
5103 /* clear pending irq */
5104 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5105 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5106 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5107
3842d135
AK		 5108 kvm_make_request(KVM_REQ_EVENT, vcpu);
5109
a26bf12a 5110 ++vcpu->stat.irq_window_exits;
2714d1d3 5111
c1150d8c
DL		 5112 /*
5113 * If the user space waits to inject interrupts, exit as soon as
5114 * possible
5115 */
8061823a 5116 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5117 vcpu->run->request_interrupt_window &&
8061823a 5118 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5119 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5120 return 0;
5121 }
6aa8b732
AK		 5122 return 1;
5123}
5124
851ba692 5125static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5126{
5127 skip_emulated_instruction(vcpu);
d3bef15f 5128 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5129}
5130
851ba692 5131static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5132{
510043da 5133 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5134 kvm_emulate_hypercall(vcpu);
5135 return 1;
c21415e8
IM		 5136}
5137
ec25d5e6
GN		 5138static int handle_invd(struct kvm_vcpu *vcpu)
5139{
51d8b661 5140 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5141}
5142
851ba692 5143static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5144{
f9c617f6 5145 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5146
5147 kvm_mmu_invlpg(vcpu, exit_qualification);
5148 skip_emulated_instruction(vcpu);
5149 return 1;
5150}
5151
fee84b07
AK		 5152static int handle_rdpmc(struct kvm_vcpu *vcpu)
5153{
5154 int err;
5155
5156 err = kvm_rdpmc(vcpu);
5157 kvm_complete_insn_gp(vcpu, err);
5158
5159 return 1;
5160}
5161
851ba692 5162static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5163{
5164 skip_emulated_instruction(vcpu);
f5f48ee1 5165 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5166 return 1;
5167}
5168
2acf923e
DC		 5169static int handle_xsetbv(struct kvm_vcpu *vcpu)
5170{
5171 u64 new_bv = kvm_read_edx_eax(vcpu);
5172 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5173
5174 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5175 skip_emulated_instruction(vcpu);
5176 return 1;
5177}
5178
851ba692 5179static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5180{
58fbbf26
KT		 5181 if (likely(fasteoi)) {
5182 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5183 int access_type, offset;
5184
5185 access_type = exit_qualification & APIC_ACCESS_TYPE;
5186 offset = exit_qualification & APIC_ACCESS_OFFSET;
5187 /*
5188 * Sane guest uses MOV to write EOI, with written value
5189 * not cared. So make a short-circuit here by avoiding
5190 * heavy instruction emulation.
5191 */
5192 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5193 (offset == APIC_EOI)) {
5194 kvm_lapic_set_eoi(vcpu);
5195 skip_emulated_instruction(vcpu);
5196 return 1;
5197 }
5198 }
51d8b661 5199 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5200}
5201
c7c9c56c
YZ		 5202static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5203{
5204 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5205 int vector = exit_qualification & 0xff;
5206
5207 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5208 kvm_apic_set_eoi_accelerated(vcpu, vector);
5209 return 1;
5210}
5211
83d4c286
YZ		 5212static int handle_apic_write(struct kvm_vcpu *vcpu)
5213{
5214 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5215 u32 offset = exit_qualification & 0xfff;
5216
5217 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5218 kvm_apic_write_nodecode(vcpu, offset);
5219 return 1;
5220}
5221
851ba692 5222static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5223{
60637aac 5224 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5225 unsigned long exit_qualification;
e269fb21
JK		 5226 bool has_error_code = false;
5227 u32 error_code = 0;
37817f29 5228 u16 tss_selector;
7f3d35fd 5229 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5230
5231 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5232 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5233 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5234
5235 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5236
5237 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5238 if (reason == TASK_SWITCH_GATE && idt_v) {
5239 switch (type) {
5240 case INTR_TYPE_NMI_INTR:
5241 vcpu->arch.nmi_injected = false;
654f06fc 5242 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5243 break;
5244 case INTR_TYPE_EXT_INTR:
66fd3f7f 5245 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5246 kvm_clear_interrupt_queue(vcpu);
5247 break;
5248 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5249 if (vmx->idt_vectoring_info &
5250 VECTORING_INFO_DELIVER_CODE_MASK) {
5251 has_error_code = true;
5252 error_code =
5253 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5254 }
5255 /* fall through */
64a7ec06
GN		 5256 case INTR_TYPE_SOFT_EXCEPTION:
5257 kvm_clear_exception_queue(vcpu);
5258 break;
5259 default:
5260 break;
5261 }
60637aac 5262 }
37817f29
IE		 5263 tss_selector = exit_qualification;
5264
64a7ec06
GN		 5265 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5266 type != INTR_TYPE_EXT_INTR &&
5267 type != INTR_TYPE_NMI_INTR))
5268 skip_emulated_instruction(vcpu);
5269
7f3d35fd
KW		 5270 if (kvm_task_switch(vcpu, tss_selector,
5271 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5272 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5273 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5274 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5275 vcpu->run->internal.ndata = 0;
42dbaa5a 5276 return 0;
acb54517 5277 }
42dbaa5a
JK		 5278
5279 /* clear all local breakpoint enable flags */
5280 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5281
5282 /*
5283 * TODO: What about debug traps on tss switch?
5284 * Are we supposed to inject them and update dr6?
5285 */
5286
5287 return 1;
37817f29
IE		 5288}
5289
851ba692 5290static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5291{
f9c617f6 5292 unsigned long exit_qualification;
1439442c 5293 gpa_t gpa;
4f5982a5 5294 u32 error_code;
1439442c 5295 int gla_validity;
1439442c 5296
f9c617f6 5297 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5298
1439442c
SY		 5299 gla_validity = (exit_qualification >> 7) & 0x3;
5300 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5301 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5302 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5303 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5304 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5305 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5306 (long unsigned int)exit_qualification);
851ba692
AK		 5307 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5308 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5309 return 0;
1439442c
SY		 5310 }
5311
5312 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5313 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5314
5315 /* It is a write fault? */
5316 error_code = exit_qualification & (1U << 1);
5317 /* ept page table is present? */
5318 error_code |= (exit_qualification >> 3) & 0x1;
5319
5320 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5321}
5322
68f89400
MT		 5323static u64 ept_rsvd_mask(u64 spte, int level)
5324{
5325 int i;
5326 u64 mask = 0;
5327
5328 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5329 mask |= (1ULL << i);
5330
5331 if (level > 2)
5332 /* bits 7:3 reserved */
5333 mask |= 0xf8;
5334 else if (level == 2) {
5335 if (spte & (1ULL << 7))
5336 /* 2MB ref, bits 20:12 reserved */
5337 mask |= 0x1ff000;
5338 else
5339 /* bits 6:3 reserved */
5340 mask |= 0x78;
5341 }
5342
5343 return mask;
5344}
5345
5346static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5347 int level)
5348{
5349 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5350
5351 /* 010b (write-only) */
5352 WARN_ON((spte & 0x7) == 0x2);
5353
5354 /* 110b (write/execute) */
5355 WARN_ON((spte & 0x7) == 0x6);
5356
5357 /* 100b (execute-only) and value not supported by logical processor */
5358 if (!cpu_has_vmx_ept_execute_only())
5359 WARN_ON((spte & 0x7) == 0x4);
5360
5361 /* not 000b */
5362 if ((spte & 0x7)) {
5363 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5364
5365 if (rsvd_bits != 0) {
5366 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5367 __func__, rsvd_bits);
5368 WARN_ON(1);
5369 }
5370
5371 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5372 u64 ept_mem_type = (spte & 0x38) >> 3;
5373
5374 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5375 ept_mem_type == 7) {
5376 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5377 __func__, ept_mem_type);
5378 WARN_ON(1);
5379 }
5380 }
5381 }
5382}
5383
851ba692 5384static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5385{
5386 u64 sptes[4];
ce88decf 5387 int nr_sptes, i, ret;
68f89400
MT		 5388 gpa_t gpa;
5389
5390 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5391
ce88decf
XG		 5392 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5393 if (likely(ret == 1))
5394 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5395 EMULATE_DONE;
5396 if (unlikely(!ret))
5397 return 1;
5398
5399 /* It is the real ept misconfig */
68f89400
MT		 5400 printk(KERN_ERR "EPT: Misconfiguration.\n");
5401 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5402
5403 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5404
5405 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5406 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5407
851ba692
AK		 5408 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5409 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5410
5411 return 0;
5412}
5413
851ba692 5414static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5415{
5416 u32 cpu_based_vm_exec_control;
5417
5418 /* clear pending NMI */
5419 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5420 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5421 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5422 ++vcpu->stat.nmi_window_exits;
3842d135 5423 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5424
5425 return 1;
5426}
5427
80ced186 5428static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5429{
8b3079a5
AK		 5430 struct vcpu_vmx *vmx = to_vmx(vcpu);
5431 enum emulation_result err = EMULATE_DONE;
80ced186 5432 int ret = 1;
49e9d557
AK		 5433 u32 cpu_exec_ctrl;
5434 bool intr_window_requested;
b8405c18 5435 unsigned count = 130;
49e9d557
AK		 5436
5437 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5438 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5439
b8405c18 5440 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5441 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5442 return handle_interrupt_window(&vmx->vcpu);
5443
de87dcdd
AK		 5444 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5445 return 1;
5446
991eebf9 5447 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5448
80ced186
MG		 5449 if (err == EMULATE_DO_MMIO) {
5450 ret = 0;
5451 goto out;
5452 }
1d5a4d9b 5453
de5f70e0
AK		 5454 if (err != EMULATE_DONE) {
5455 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5456 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5457 vcpu->run->internal.ndata = 0;
6d77dbfc 5458 return 0;
de5f70e0 5459 }
ea953ef0 5460
8d76c49e
GN		 5461 if (vcpu->arch.halt_request) {
5462 vcpu->arch.halt_request = 0;
5463 ret = kvm_emulate_halt(vcpu);
5464 goto out;
5465 }
5466
ea953ef0 5467 if (signal_pending(current))
80ced186 5468 goto out;
ea953ef0
MG		 5469 if (need_resched())
5470 schedule();
5471 }
5472
14168786 5473 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5474out:
5475 return ret;
ea953ef0
MG		 5476}
5477
4b8d54f9
ZE		 5478/*
5479 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5480 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5481 */
9fb41ba8 5482static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5483{
5484 skip_emulated_instruction(vcpu);
5485 kvm_vcpu_on_spin(vcpu);
5486
5487 return 1;
5488}
5489
59708670
SY		 5490static int handle_invalid_op(struct kvm_vcpu *vcpu)
5491{
5492 kvm_queue_exception(vcpu, UD_VECTOR);
5493 return 1;
5494}
5495
ff2f6fe9
NHE		 5496/*
5497 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5498 * We could reuse a single VMCS for all the L2 guests, but we also want the
5499 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5500 * allows keeping them loaded on the processor, and in the future will allow
5501 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5502 * every entry if they never change.
5503 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5504 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5505 *
5506 * The following functions allocate and free a vmcs02 in this pool.
5507 */
5508
5509/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5510static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5511{
5512 struct vmcs02_list *item;
5513 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5514 if (item->vmptr == vmx->nested.current_vmptr) {
5515 list_move(&item->list, &vmx->nested.vmcs02_pool);
5516 return &item->vmcs02;
5517 }
5518
5519 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5520 /* Recycle the least recently used VMCS. */
5521 item = list_entry(vmx->nested.vmcs02_pool.prev,
5522 struct vmcs02_list, list);
5523 item->vmptr = vmx->nested.current_vmptr;
5524 list_move(&item->list, &vmx->nested.vmcs02_pool);
5525 return &item->vmcs02;
5526 }
5527
5528 /* Create a new VMCS */
0fa24ce3 5529 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5530 if (!item)
5531 return NULL;
5532 item->vmcs02.vmcs = alloc_vmcs();
5533 if (!item->vmcs02.vmcs) {
5534 kfree(item);
5535 return NULL;
5536 }
5537 loaded_vmcs_init(&item->vmcs02);
5538 item->vmptr = vmx->nested.current_vmptr;
5539 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5540 vmx->nested.vmcs02_num++;
5541 return &item->vmcs02;
5542}
5543
5544/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5545static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5546{
5547 struct vmcs02_list *item;
5548 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5549 if (item->vmptr == vmptr) {
5550 free_loaded_vmcs(&item->vmcs02);
5551 list_del(&item->list);
5552 kfree(item);
5553 vmx->nested.vmcs02_num--;
5554 return;
5555 }
5556}
5557
5558/*
5559 * Free all VMCSs saved for this vcpu, except the one pointed by
5560 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5561 * currently used, if running L2), and vmcs01 when running L2.
5562 */
5563static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5564{
5565 struct vmcs02_list *item, *n;
5566 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5567 if (vmx->loaded_vmcs != &item->vmcs02)
5568 free_loaded_vmcs(&item->vmcs02);
5569 list_del(&item->list);
5570 kfree(item);
5571 }
5572 vmx->nested.vmcs02_num = 0;
5573
5574 if (vmx->loaded_vmcs != &vmx->vmcs01)
5575 free_loaded_vmcs(&vmx->vmcs01);
5576}
5577
145c28dd
AG		 5578static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5579 u32 vm_instruction_error);
5580
ec378aee
NHE		 5581/*
5582 * Emulate the VMXON instruction.
5583 * Currently, we just remember that VMX is active, and do not save or even
5584 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5585 * do not currently need to store anything in that guest-allocated memory
5586 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5587 * argument is different from the VMXON pointer (which the spec says they do).
5588 */
5589static int handle_vmon(struct kvm_vcpu *vcpu)
5590{
5591 struct kvm_segment cs;
5592 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5593 struct vmcs *shadow_vmcs;
ec378aee
NHE		 5594
5595 /* The Intel VMX Instruction Reference lists a bunch of bits that
5596 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5597 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5598 * Otherwise, we should fail with #UD. We test these now:
5599 */
5600 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5601 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5602 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5603 kvm_queue_exception(vcpu, UD_VECTOR);
5604 return 1;
5605 }
5606
5607 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5608 if (is_long_mode(vcpu) && !cs.l) {
5609 kvm_queue_exception(vcpu, UD_VECTOR);
5610 return 1;
5611 }
5612
5613 if (vmx_get_cpl(vcpu)) {
5614 kvm_inject_gp(vcpu, 0);
5615 return 1;
5616 }
145c28dd
AG		 5617 if (vmx->nested.vmxon) {
5618 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5619 skip_emulated_instruction(vcpu);
5620 return 1;
5621 }
8de48833
AG		 5622 if (enable_shadow_vmcs) {
5623 shadow_vmcs = alloc_vmcs();
5624 if (!shadow_vmcs)
5625 return -ENOMEM;
5626 /* mark vmcs as shadow */
5627 shadow_vmcs->revision_id |= (1u << 31);
5628 /* init shadow vmcs */
5629 vmcs_clear(shadow_vmcs);
5630 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5631 }
ec378aee 5632
ff2f6fe9
NHE		 5633 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5634 vmx->nested.vmcs02_num = 0;
5635
ec378aee
NHE		 5636 vmx->nested.vmxon = true;
5637
5638 skip_emulated_instruction(vcpu);
5639 return 1;
5640}
5641
5642/*
5643 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5644 * for running VMX instructions (except VMXON, whose prerequisites are
5645 * slightly different). It also specifies what exception to inject otherwise.
5646 */
5647static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5648{
5649 struct kvm_segment cs;
5650 struct vcpu_vmx *vmx = to_vmx(vcpu);
5651
5652 if (!vmx->nested.vmxon) {
5653 kvm_queue_exception(vcpu, UD_VECTOR);
5654 return 0;
5655 }
5656
5657 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5658 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5659 (is_long_mode(vcpu) && !cs.l)) {
5660 kvm_queue_exception(vcpu, UD_VECTOR);
5661 return 0;
5662 }
5663
5664 if (vmx_get_cpl(vcpu)) {
5665 kvm_inject_gp(vcpu, 0);
5666 return 0;
5667 }
5668
5669 return 1;
5670}
5671
e7953d7f
AG		 5672static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5673{
8a1b9dd0 5674 u32 exec_control;
012f83cb
AG		 5675 if (enable_shadow_vmcs) {
5676 if (vmx->nested.current_vmcs12 != NULL) {
5677 /* copy to memory all shadowed fields in case
5678 they were modified */
5679 copy_shadow_to_vmcs12(vmx);
5680 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5681 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5682 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5683 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5684 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5685 }
5686 }
e7953d7f
AG		 5687 kunmap(vmx->nested.current_vmcs12_page);
5688 nested_release_page(vmx->nested.current_vmcs12_page);
5689}
5690
ec378aee
NHE		 5691/*
5692 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5693 * just stops using VMX.
5694 */
5695static void free_nested(struct vcpu_vmx *vmx)
5696{
5697 if (!vmx->nested.vmxon)
5698 return;
5699 vmx->nested.vmxon = false;
a9d30f33 5700 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5701 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5702 vmx->nested.current_vmptr = -1ull;
5703 vmx->nested.current_vmcs12 = NULL;
5704 }
e7953d7f
AG		 5705 if (enable_shadow_vmcs)
5706 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5707 /* Unpin physical memory we referred to in current vmcs02 */
5708 if (vmx->nested.apic_access_page) {
5709 nested_release_page(vmx->nested.apic_access_page);
5710 vmx->nested.apic_access_page = 0;
5711 }
ff2f6fe9
NHE		 5712
5713 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5714}
5715
5716/* Emulate the VMXOFF instruction */
5717static int handle_vmoff(struct kvm_vcpu *vcpu)
5718{
5719 if (!nested_vmx_check_permission(vcpu))
5720 return 1;
5721 free_nested(to_vmx(vcpu));
5722 skip_emulated_instruction(vcpu);
5723 return 1;
5724}
5725
064aea77
NHE		 5726/*
5727 * Decode the memory-address operand of a vmx instruction, as recorded on an
5728 * exit caused by such an instruction (run by a guest hypervisor).
5729 * On success, returns 0. When the operand is invalid, returns 1 and throws
5730 * #UD or #GP.
5731 */
5732static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5733 unsigned long exit_qualification,
5734 u32 vmx_instruction_info, gva_t *ret)
5735{
5736 /*
5737 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5738 * Execution", on an exit, vmx_instruction_info holds most of the
5739 * addressing components of the operand. Only the displacement part
5740 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5741 * For how an actual address is calculated from all these components,
5742 * refer to Vol. 1, "Operand Addressing".
5743 */
5744 int scaling = vmx_instruction_info & 3;
5745 int addr_size = (vmx_instruction_info >> 7) & 7;
5746 bool is_reg = vmx_instruction_info & (1u << 10);
5747 int seg_reg = (vmx_instruction_info >> 15) & 7;
5748 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5749 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5750 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5751 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5752
5753 if (is_reg) {
5754 kvm_queue_exception(vcpu, UD_VECTOR);
5755 return 1;
5756 }
5757
5758 /* Addr = segment_base + offset */
5759 /* offset = base + [index * scale] + displacement */
5760 *ret = vmx_get_segment_base(vcpu, seg_reg);
5761 if (base_is_valid)
5762 *ret += kvm_register_read(vcpu, base_reg);
5763 if (index_is_valid)
5764 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5765 *ret += exit_qualification; /* holds the displacement */
5766
5767 if (addr_size == 1) /* 32 bit */
5768 *ret &= 0xffffffff;
5769
5770 /*
5771 * TODO: throw #GP (and return 1) in various cases that the VM*
5772 * instructions require it - e.g., offset beyond segment limit,
5773 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5774 * address, and so on. Currently these are not checked.
5775 */
5776 return 0;
5777}
5778
0140caea
NHE		 5779/*
5780 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5781 * set the success or error code of an emulated VMX instruction, as specified
5782 * by Vol 2B, VMX Instruction Reference, "Conventions".
5783 */
5784static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5785{
5786 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5787 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5788 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5789}
5790
5791static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5792{
5793 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5794 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5795 X86_EFLAGS_SF | X86_EFLAGS_OF))
5796 | X86_EFLAGS_CF);
5797}
5798
5799static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5800 u32 vm_instruction_error)
5801{
5802 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5803 /*
5804 * failValid writes the error number to the current VMCS, which
5805 * can't be done there isn't a current VMCS.
5806 */
5807 nested_vmx_failInvalid(vcpu);
5808 return;
5809 }
5810 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5811 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5812 X86_EFLAGS_SF | X86_EFLAGS_OF))
5813 | X86_EFLAGS_ZF);
5814 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
012f83cb
AG		 5815 /*
5816 * We don't need to force a shadow sync because
5817 * VM_INSTRUCTION_ERROR is not shadowed
5818 */
0140caea
NHE		 5819}
5820
27d6c865
NHE		 5821/* Emulate the VMCLEAR instruction */
5822static int handle_vmclear(struct kvm_vcpu *vcpu)
5823{
5824 struct vcpu_vmx *vmx = to_vmx(vcpu);
5825 gva_t gva;
5826 gpa_t vmptr;
5827 struct vmcs12 *vmcs12;
5828 struct page *page;
5829 struct x86_exception e;
5830
5831 if (!nested_vmx_check_permission(vcpu))
5832 return 1;
5833
5834 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5835 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5836 return 1;
5837
5838 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5839 sizeof(vmptr), &e)) {
5840 kvm_inject_page_fault(vcpu, &e);
5841 return 1;
5842 }
5843
5844 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5845 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5846 skip_emulated_instruction(vcpu);
5847 return 1;
5848 }
5849
5850 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5851 nested_release_vmcs12(vmx);
27d6c865
NHE		 5852 vmx->nested.current_vmptr = -1ull;
5853 vmx->nested.current_vmcs12 = NULL;
5854 }
5855
5856 page = nested_get_page(vcpu, vmptr);
5857 if (page == NULL) {
5858 /*
5859 * For accurate processor emulation, VMCLEAR beyond available
5860 * physical memory should do nothing at all. However, it is
5861 * possible that a nested vmx bug, not a guest hypervisor bug,
5862 * resulted in this case, so let's shut down before doing any
5863 * more damage:
5864 */
5865 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5866 return 1;
5867 }
5868 vmcs12 = kmap(page);
5869 vmcs12->launch_state = 0;
5870 kunmap(page);
5871 nested_release_page(page);
5872
5873 nested_free_vmcs02(vmx, vmptr);
5874
5875 skip_emulated_instruction(vcpu);
5876 nested_vmx_succeed(vcpu);
5877 return 1;
5878}
5879
cd232ad0
NHE		 5880static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5881
5882/* Emulate the VMLAUNCH instruction */
5883static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5884{
5885 return nested_vmx_run(vcpu, true);
5886}
5887
5888/* Emulate the VMRESUME instruction */
5889static int handle_vmresume(struct kvm_vcpu *vcpu)
5890{
5891
5892 return nested_vmx_run(vcpu, false);
5893}
5894
49f705c5
NHE		 5895enum vmcs_field_type {
5896 VMCS_FIELD_TYPE_U16 = 0,
5897 VMCS_FIELD_TYPE_U64 = 1,
5898 VMCS_FIELD_TYPE_U32 = 2,
5899 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5900};
5901
5902static inline int vmcs_field_type(unsigned long field)
5903{
5904 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5905 return VMCS_FIELD_TYPE_U32;
5906 return (field >> 13) & 0x3 ;
5907}
5908
5909static inline int vmcs_field_readonly(unsigned long field)
5910{
5911 return (((field >> 10) & 0x3) == 1);
5912}
5913
5914/*
5915 * Read a vmcs12 field. Since these can have varying lengths and we return
5916 * one type, we chose the biggest type (u64) and zero-extend the return value
5917 * to that size. Note that the caller, handle_vmread, might need to use only
5918 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5919 * 64-bit fields are to be returned).
5920 */
5921static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5922 unsigned long field, u64 *ret)
5923{
5924 short offset = vmcs_field_to_offset(field);
5925 char *p;
5926
5927 if (offset < 0)
5928 return 0;
5929
5930 p = ((char *)(get_vmcs12(vcpu))) + offset;
5931
5932 switch (vmcs_field_type(field)) {
5933 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5934 *ret = *((natural_width *)p);
5935 return 1;
5936 case VMCS_FIELD_TYPE_U16:
5937 *ret = *((u16 *)p);
5938 return 1;
5939 case VMCS_FIELD_TYPE_U32:
5940 *ret = *((u32 *)p);
5941 return 1;
5942 case VMCS_FIELD_TYPE_U64:
5943 *ret = *((u64 *)p);
5944 return 1;
5945 default:
5946 return 0; /* can never happen. */
5947 }
5948}
5949
20b97fea
AG		 5950
5951static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5952 unsigned long field, u64 field_value){
5953 short offset = vmcs_field_to_offset(field);
5954 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5955 if (offset < 0)
5956 return false;
5957
5958 switch (vmcs_field_type(field)) {
5959 case VMCS_FIELD_TYPE_U16:
5960 *(u16 *)p = field_value;
5961 return true;
5962 case VMCS_FIELD_TYPE_U32:
5963 *(u32 *)p = field_value;
5964 return true;
5965 case VMCS_FIELD_TYPE_U64:
5966 *(u64 *)p = field_value;
5967 return true;
5968 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5969 *(natural_width *)p = field_value;
5970 return true;
5971 default:
5972 return false; /* can never happen. */
5973 }
5974
5975}
5976
16f5b903
AG		 5977static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5978{
5979 int i;
5980 unsigned long field;
5981 u64 field_value;
5982 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5983 unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5984 int num_fields = max_shadow_read_write_fields;
5985
5986 vmcs_load(shadow_vmcs);
5987
5988 for (i = 0; i < num_fields; i++) {
5989 field = fields[i];
5990 switch (vmcs_field_type(field)) {
5991 case VMCS_FIELD_TYPE_U16:
5992 field_value = vmcs_read16(field);
5993 break;
5994 case VMCS_FIELD_TYPE_U32:
5995 field_value = vmcs_read32(field);
5996 break;
5997 case VMCS_FIELD_TYPE_U64:
5998 field_value = vmcs_read64(field);
5999 break;
6000 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6001 field_value = vmcs_readl(field);
6002 break;
6003 }
6004 vmcs12_write_any(&vmx->vcpu, field, field_value);
6005 }
6006
6007 vmcs_clear(shadow_vmcs);
6008 vmcs_load(vmx->loaded_vmcs->vmcs);
6009}
6010
c3114420
AG		 6011static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6012{
6013 unsigned long *fields[] = {
6014 (unsigned long *)shadow_read_write_fields,
6015 (unsigned long *)shadow_read_only_fields
6016 };
6017 int num_lists = ARRAY_SIZE(fields);
6018 int max_fields[] = {
6019 max_shadow_read_write_fields,
6020 max_shadow_read_only_fields
6021 };
6022 int i, q;
6023 unsigned long field;
6024 u64 field_value = 0;
6025 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6026
6027 vmcs_load(shadow_vmcs);
6028
6029 for (q = 0; q < num_lists; q++) {
6030 for (i = 0; i < max_fields[q]; i++) {
6031 field = fields[q][i];
6032 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6033
6034 switch (vmcs_field_type(field)) {
6035 case VMCS_FIELD_TYPE_U16:
6036 vmcs_write16(field, (u16)field_value);
6037 break;
6038 case VMCS_FIELD_TYPE_U32:
6039 vmcs_write32(field, (u32)field_value);
6040 break;
6041 case VMCS_FIELD_TYPE_U64:
6042 vmcs_write64(field, (u64)field_value);
6043 break;
6044 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6045 vmcs_writel(field, (long)field_value);
6046 break;
6047 }
6048 }
6049 }
6050
6051 vmcs_clear(shadow_vmcs);
6052 vmcs_load(vmx->loaded_vmcs->vmcs);
6053}
6054
49f705c5
NHE		 6055/*
6056 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6057 * used before) all generate the same failure when it is missing.
6058 */
6059static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6060{
6061 struct vcpu_vmx *vmx = to_vmx(vcpu);
6062 if (vmx->nested.current_vmptr == -1ull) {
6063 nested_vmx_failInvalid(vcpu);
6064 skip_emulated_instruction(vcpu);
6065 return 0;
6066 }
6067 return 1;
6068}
6069
6070static int handle_vmread(struct kvm_vcpu *vcpu)
6071{
6072 unsigned long field;
6073 u64 field_value;
6074 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6075 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6076 gva_t gva = 0;
6077
6078 if (!nested_vmx_check_permission(vcpu) ||
6079 !nested_vmx_check_vmcs12(vcpu))
6080 return 1;
6081
6082 /* Decode instruction info and find the field to read */
6083 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6084 /* Read the field, zero-extended to a u64 field_value */
6085 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6086 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6087 skip_emulated_instruction(vcpu);
6088 return 1;
6089 }
6090 /*
6091 * Now copy part of this value to register or memory, as requested.
6092 * Note that the number of bits actually copied is 32 or 64 depending
6093 * on the guest's mode (32 or 64 bit), not on the given field's length.
6094 */
6095 if (vmx_instruction_info & (1u << 10)) {
6096 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6097 field_value);
6098 } else {
6099 if (get_vmx_mem_address(vcpu, exit_qualification,
6100 vmx_instruction_info, &gva))
6101 return 1;
6102 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6103 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6104 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6105 }
6106
6107 nested_vmx_succeed(vcpu);
6108 skip_emulated_instruction(vcpu);
6109 return 1;
6110}
6111
6112
6113static int handle_vmwrite(struct kvm_vcpu *vcpu)
6114{
6115 unsigned long field;
6116 gva_t gva;
6117 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6118 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6119 /* The value to write might be 32 or 64 bits, depending on L1's long
6120 * mode, and eventually we need to write that into a field of several
6121 * possible lengths. The code below first zero-extends the value to 64
6122 * bit (field_value), and then copies only the approriate number of
6123 * bits into the vmcs12 field.
6124 */
6125 u64 field_value = 0;
6126 struct x86_exception e;
6127
6128 if (!nested_vmx_check_permission(vcpu) ||
6129 !nested_vmx_check_vmcs12(vcpu))
6130 return 1;
6131
6132 if (vmx_instruction_info & (1u << 10))
6133 field_value = kvm_register_read(vcpu,
6134 (((vmx_instruction_info) >> 3) & 0xf));
6135 else {
6136 if (get_vmx_mem_address(vcpu, exit_qualification,
6137 vmx_instruction_info, &gva))
6138 return 1;
6139 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6140 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6141 kvm_inject_page_fault(vcpu, &e);
6142 return 1;
6143 }
6144 }
6145
6146
6147 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6148 if (vmcs_field_readonly(field)) {
6149 nested_vmx_failValid(vcpu,
6150 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6151 skip_emulated_instruction(vcpu);
6152 return 1;
6153 }
6154
20b97fea 6155 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6156 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6157 skip_emulated_instruction(vcpu);
6158 return 1;
6159 }
6160
6161 nested_vmx_succeed(vcpu);
6162 skip_emulated_instruction(vcpu);
6163 return 1;
6164}
6165
63846663
NHE		 6166/* Emulate the VMPTRLD instruction */
6167static int handle_vmptrld(struct kvm_vcpu *vcpu)
6168{
6169 struct vcpu_vmx *vmx = to_vmx(vcpu);
6170 gva_t gva;
6171 gpa_t vmptr;
6172 struct x86_exception e;
8a1b9dd0 6173 u32 exec_control;
63846663
NHE		 6174
6175 if (!nested_vmx_check_permission(vcpu))
6176 return 1;
6177
6178 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6179 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6180 return 1;
6181
6182 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6183 sizeof(vmptr), &e)) {
6184 kvm_inject_page_fault(vcpu, &e);
6185 return 1;
6186 }
6187
6188 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6189 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6190 skip_emulated_instruction(vcpu);
6191 return 1;
6192 }
6193
6194 if (vmx->nested.current_vmptr != vmptr) {
6195 struct vmcs12 *new_vmcs12;
6196 struct page *page;
6197 page = nested_get_page(vcpu, vmptr);
6198 if (page == NULL) {
6199 nested_vmx_failInvalid(vcpu);
6200 skip_emulated_instruction(vcpu);
6201 return 1;
6202 }
6203 new_vmcs12 = kmap(page);
6204 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6205 kunmap(page);
6206 nested_release_page_clean(page);
6207 nested_vmx_failValid(vcpu,
6208 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6209 skip_emulated_instruction(vcpu);
6210 return 1;
6211 }
e7953d7f
AG		 6212 if (vmx->nested.current_vmptr != -1ull)
6213 nested_release_vmcs12(vmx);
63846663
NHE		 6214
6215 vmx->nested.current_vmptr = vmptr;
6216 vmx->nested.current_vmcs12 = new_vmcs12;
6217 vmx->nested.current_vmcs12_page = page;
012f83cb 6218 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6219 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6220 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6221 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6222 vmcs_write64(VMCS_LINK_POINTER,
6223 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6224 vmx->nested.sync_shadow_vmcs = true;
6225 }
63846663
NHE		 6226 }
6227
6228 nested_vmx_succeed(vcpu);
6229 skip_emulated_instruction(vcpu);
6230 return 1;
6231}
6232
6a4d7550
NHE		 6233/* Emulate the VMPTRST instruction */
6234static int handle_vmptrst(struct kvm_vcpu *vcpu)
6235{
6236 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6237 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6238 gva_t vmcs_gva;
6239 struct x86_exception e;
6240
6241 if (!nested_vmx_check_permission(vcpu))
6242 return 1;
6243
6244 if (get_vmx_mem_address(vcpu, exit_qualification,
6245 vmx_instruction_info, &vmcs_gva))
6246 return 1;
6247 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6248 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6249 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6250 sizeof(u64), &e)) {
6251 kvm_inject_page_fault(vcpu, &e);
6252 return 1;
6253 }
6254 nested_vmx_succeed(vcpu);
6255 skip_emulated_instruction(vcpu);
6256 return 1;
6257}
6258
4ca178ae
NHE		 6259static int handle_invept(struct kvm_vcpu *vcpu)
6260{
6261 kvm_queue_exception(vcpu, UD_VECTOR);
6262 return 1;
6263}
6264
f9e5b0de
PM		 6265static int handle_invvpid(struct kvm_vcpu *vcpu)
6266{
6267 kvm_queue_exception(vcpu, UD_VECTOR);
6268 return 1;
6269}
6270
6aa8b732
AK		 6271/*
6272 * The exit handlers return 1 if the exit was handled fully and guest execution
6273 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6274 * to be done to userspace and return 0.
6275 */
772e0318 6276static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6277 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6278 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6279 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6280 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6281 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6282 [EXIT_REASON_CR_ACCESS] = handle_cr,
6283 [EXIT_REASON_DR_ACCESS] = handle_dr,
6284 [EXIT_REASON_CPUID] = handle_cpuid,
6285 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6286 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6287 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6288 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6289 [EXIT_REASON_INVD] = handle_invd,
a7052897 6290 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6291 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6292 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6293 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6294 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6295 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6296 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6297 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6298 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6299 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6300 [EXIT_REASON_VMOFF] = handle_vmoff,
6301 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6302 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6303 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6304 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6305 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6306 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6307 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6308 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6309 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6310 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6311 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6312 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6313 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6314 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
4ca178ae 6315 [EXIT_REASON_INVEPT] = handle_invept,
f9e5b0de 6316 [EXIT_REASON_INVVPID] = handle_invvpid,
6aa8b732
AK		 6317};
6318
6319static const int kvm_vmx_max_exit_handlers =
50a3485c 6320 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6321
908a7bdd
JK		 6322static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6323 struct vmcs12 *vmcs12)
6324{
6325 unsigned long exit_qualification;
6326 gpa_t bitmap, last_bitmap;
6327 unsigned int port;
6328 int size;
6329 u8 b;
6330
6331 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6332 return 1;
6333
6334 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6335 return 0;
6336
6337 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6338
6339 port = exit_qualification >> 16;
6340 size = (exit_qualification & 7) + 1;
6341
6342 last_bitmap = (gpa_t)-1;
6343 b = -1;
6344
6345 while (size > 0) {
6346 if (port < 0x8000)
6347 bitmap = vmcs12->io_bitmap_a;
6348 else if (port < 0x10000)
6349 bitmap = vmcs12->io_bitmap_b;
6350 else
6351 return 1;
6352 bitmap += (port & 0x7fff) / 8;
6353
6354 if (last_bitmap != bitmap)
6355 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6356 return 1;
6357 if (b & (1 << (port & 7)))
6358 return 1;
6359
6360 port++;
6361 size--;
6362 last_bitmap = bitmap;
6363 }
6364
6365 return 0;
6366}
6367
644d711a
NHE		 6368/*
6369 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6370 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6371 * disinterest in the current event (read or write a specific MSR) by using an
6372 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6373 */
6374static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6375 struct vmcs12 *vmcs12, u32 exit_reason)
6376{
6377 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6378 gpa_t bitmap;
6379
cbd29cb6 6380 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6381 return 1;
6382
6383 /*
6384 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6385 * for the four combinations of read/write and low/high MSR numbers.
6386 * First we need to figure out which of the four to use:
6387 */
6388 bitmap = vmcs12->msr_bitmap;
6389 if (exit_reason == EXIT_REASON_MSR_WRITE)
6390 bitmap += 2048;
6391 if (msr_index >= 0xc0000000) {
6392 msr_index -= 0xc0000000;
6393 bitmap += 1024;
6394 }
6395
6396 /* Then read the msr_index'th bit from this bitmap: */
6397 if (msr_index < 1024*8) {
6398 unsigned char b;
bd31a7f5
JK		 6399 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6400 return 1;
644d711a
NHE		 6401 return 1 & (b >> (msr_index & 7));
6402 } else
6403 return 1; /* let L1 handle the wrong parameter */
6404}
6405
6406/*
6407 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6408 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6409 * intercept (via guest_host_mask etc.) the current event.
6410 */
6411static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6412 struct vmcs12 *vmcs12)
6413{
6414 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6415 int cr = exit_qualification & 15;
6416 int reg = (exit_qualification >> 8) & 15;
6417 unsigned long val = kvm_register_read(vcpu, reg);
6418
6419 switch ((exit_qualification >> 4) & 3) {
6420 case 0: /* mov to cr */
6421 switch (cr) {
6422 case 0:
6423 if (vmcs12->cr0_guest_host_mask &
6424 (val ^ vmcs12->cr0_read_shadow))
6425 return 1;
6426 break;
6427 case 3:
6428 if ((vmcs12->cr3_target_count >= 1 &&
6429 vmcs12->cr3_target_value0 == val) ||
6430 (vmcs12->cr3_target_count >= 2 &&
6431 vmcs12->cr3_target_value1 == val) ||
6432 (vmcs12->cr3_target_count >= 3 &&
6433 vmcs12->cr3_target_value2 == val) ||
6434 (vmcs12->cr3_target_count >= 4 &&
6435 vmcs12->cr3_target_value3 == val))
6436 return 0;
6437 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6438 return 1;
6439 break;
6440 case 4:
6441 if (vmcs12->cr4_guest_host_mask &
6442 (vmcs12->cr4_read_shadow ^ val))
6443 return 1;
6444 break;
6445 case 8:
6446 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6447 return 1;
6448 break;
6449 }
6450 break;
6451 case 2: /* clts */
6452 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6453 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6454 return 1;
6455 break;
6456 case 1: /* mov from cr */
6457 switch (cr) {
6458 case 3:
6459 if (vmcs12->cpu_based_vm_exec_control &
6460 CPU_BASED_CR3_STORE_EXITING)
6461 return 1;
6462 break;
6463 case 8:
6464 if (vmcs12->cpu_based_vm_exec_control &
6465 CPU_BASED_CR8_STORE_EXITING)
6466 return 1;
6467 break;
6468 }
6469 break;
6470 case 3: /* lmsw */
6471 /*
6472 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6473 * cr0. Other attempted changes are ignored, with no exit.
6474 */
6475 if (vmcs12->cr0_guest_host_mask & 0xe &
6476 (val ^ vmcs12->cr0_read_shadow))
6477 return 1;
6478 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6479 !(vmcs12->cr0_read_shadow & 0x1) &&
6480 (val & 0x1))
6481 return 1;
6482 break;
6483 }
6484 return 0;
6485}
6486
6487/*
6488 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6489 * should handle it ourselves in L0 (and then continue L2). Only call this
6490 * when in is_guest_mode (L2).
6491 */
6492static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6493{
644d711a
NHE		 6494 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6495 struct vcpu_vmx *vmx = to_vmx(vcpu);
6496 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6497 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6498
6499 if (vmx->nested.nested_run_pending)
6500 return 0;
6501
6502 if (unlikely(vmx->fail)) {
bd80158a
JK		 6503 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6504 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6505 return 1;
6506 }
6507
6508 switch (exit_reason) {
6509 case EXIT_REASON_EXCEPTION_NMI:
58e4633a 6510 if (is_nmi(intr_info))
644d711a
NHE		 6511 return 0;
6512 else if (is_page_fault(intr_info))
6513 return enable_ept;
6514 return vmcs12->exception_bitmap &
6515 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6516 case EXIT_REASON_EXTERNAL_INTERRUPT:
6517 return 0;
6518 case EXIT_REASON_TRIPLE_FAULT:
6519 return 1;
6520 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6521 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6522 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6523 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6524 case EXIT_REASON_TASK_SWITCH:
6525 return 1;
6526 case EXIT_REASON_CPUID:
6527 return 1;
6528 case EXIT_REASON_HLT:
6529 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6530 case EXIT_REASON_INVD:
6531 return 1;
6532 case EXIT_REASON_INVLPG:
6533 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6534 case EXIT_REASON_RDPMC:
6535 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6536 case EXIT_REASON_RDTSC:
6537 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6538 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6539 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6540 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6541 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6542 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
f9e5b0de 6543 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 6544 /*
6545 * VMX instructions trap unconditionally. This allows L1 to
6546 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6547 */
6548 return 1;
6549 case EXIT_REASON_CR_ACCESS:
6550 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6551 case EXIT_REASON_DR_ACCESS:
6552 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6553 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6554 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6555 case EXIT_REASON_MSR_READ:
6556 case EXIT_REASON_MSR_WRITE:
6557 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6558 case EXIT_REASON_INVALID_STATE:
6559 return 1;
6560 case EXIT_REASON_MWAIT_INSTRUCTION:
6561 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6562 case EXIT_REASON_MONITOR_INSTRUCTION:
6563 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6564 case EXIT_REASON_PAUSE_INSTRUCTION:
6565 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6566 nested_cpu_has2(vmcs12,
6567 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6568 case EXIT_REASON_MCE_DURING_VMENTRY:
6569 return 0;
6570 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6571 return 1;
6572 case EXIT_REASON_APIC_ACCESS:
6573 return nested_cpu_has2(vmcs12,
6574 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6575 case EXIT_REASON_EPT_VIOLATION:
6576 case EXIT_REASON_EPT_MISCONFIG:
6577 return 0;
0238ea91
JK		 6578 case EXIT_REASON_PREEMPTION_TIMER:
6579 return vmcs12->pin_based_vm_exec_control &
6580 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6581 case EXIT_REASON_WBINVD:
6582 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6583 case EXIT_REASON_XSETBV:
6584 return 1;
6585 default:
6586 return 1;
6587 }
6588}
6589
586f9607
AK		 6590static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6591{
6592 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6593 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6594}
6595
6aa8b732
AK		 6596/*
6597 * The guest has exited. See if we can fix it or if we need userspace
6598 * assistance.
6599 */
851ba692 6600static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6601{
29bd8a78 6602 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6603 u32 exit_reason = vmx->exit_reason;
1155f76a 6604 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6605
80ced186 6606 /* If guest state is invalid, start emulating */
14168786 6607 if (vmx->emulation_required)
80ced186 6608 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6609
b6f1250e
NHE		 6610 /*
6611 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6612 * we did not inject a still-pending event to L1 now because of
6613 * nested_run_pending, we need to re-enable this bit.
6614 */
6615 if (vmx->nested.nested_run_pending)
6616 kvm_make_request(KVM_REQ_EVENT, vcpu);
6617
509c75ea
NHE		 6618 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6619 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6620 vmx->nested.nested_run_pending = 1;
6621 else
6622 vmx->nested.nested_run_pending = 0;
6623
6624 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6625 nested_vmx_vmexit(vcpu);
6626 return 1;
6627 }
6628
5120702e
MG		 6629 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6630 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6631 vcpu->run->fail_entry.hardware_entry_failure_reason
6632 = exit_reason;
6633 return 0;
6634 }
6635
29bd8a78 6636 if (unlikely(vmx->fail)) {
851ba692
AK		 6637 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6638 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6639 = vmcs_read32(VM_INSTRUCTION_ERROR);
6640 return 0;
6641 }
6aa8b732 6642
b9bf6882
XG		 6643 /*
6644 * Note:
6645 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6646 * delivery event since it indicates guest is accessing MMIO.
6647 * The vm-exit can be triggered again after return to guest that
6648 * will cause infinite loop.
6649 */
d77c26fc 6650 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6651 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6652 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6653 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6654 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6655 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6656 vcpu->run->internal.ndata = 2;
6657 vcpu->run->internal.data[0] = vectoring_info;
6658 vcpu->run->internal.data[1] = exit_reason;
6659 return 0;
6660 }
3b86cd99 6661
644d711a
NHE		 6662 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6663 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6664 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6665 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6666 vmx->soft_vnmi_blocked = 0;
3b86cd99 6667 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6668 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6669 /*
6670 * This CPU don't support us in finding the end of an
6671 * NMI-blocked window if the guest runs with IRQs
6672 * disabled. So we pull the trigger after 1 s of
6673 * futile waiting, but inform the user about this.
6674 */
6675 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6676 "state on VCPU %d after 1 s timeout\n",
6677 __func__, vcpu->vcpu_id);
6678 vmx->soft_vnmi_blocked = 0;
3b86cd99 6679 }
3b86cd99
JK		 6680 }
6681
6aa8b732
AK		 6682 if (exit_reason < kvm_vmx_max_exit_handlers
6683 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6684 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6685 else {
e56b9c47
MT		 6686 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6687 kvm_queue_exception(vcpu, UD_VECTOR);
6688 return 1;
6aa8b732 6689 }
6aa8b732
AK		 6690}
6691
95ba8273 6692static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6693{
95ba8273 6694 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6695 vmcs_write32(TPR_THRESHOLD, 0);
6696 return;
6697 }
6698
95ba8273 6699 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6700}
6701
8d14695f
YZ		 6702static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6703{
6704 u32 sec_exec_control;
6705
\8dmáÅ\99, 2016-08-08 20:16:23 +0200" rowspan="6">a0753a8c
RK		 6706 /* Postpone execution until vmcs01 is the current VMCS. */
6707 if (is_guest_mode(vcpu)) {
6708 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
6709 return;
6710 }
6711
8d14695f
YZ		 6712 /*
6713 * There is not point to enable virtualize x2apic without enable
6714 * apicv
6715 */
c7c9c56c
YZ		 6716 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6717 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6718 return;
6719
6720 if (!vm_need_tpr_shadow(vcpu->kvm))
6721 return;
6722
6723 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6724
6725 if (set) {
6726 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6727 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6728 } else {
6729 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6730 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6731 }
6732 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6733
6734 vmx_set_msr_bitmap(vcpu);
6735}
6736
c7c9c56c
YZ		 6737static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6738{
6739 u16 status;
6740 u8 old;
6741
6742 if (!vmx_vm_has_apicv(kvm))
6743 return;
6744
6745 if (isr == -1)
6746 isr = 0;
6747
6748 status = vmcs_read16(GUEST_INTR_STATUS);
6749 old = status >> 8;
6750 if (isr != old) {
6751 status &= 0xff;
6752 status |= isr << 8;
6753 vmcs_write16(GUEST_INTR_STATUS, status);
6754 }
6755}
6756
6757static void vmx_set_rvi(int vector)
6758{
6759 u16 status;
6760 u8 old;
6761
6762 status = vmcs_read16(GUEST_INTR_STATUS);
6763 old = (u8)status & 0xff;
6764 if ((u8)vector != old) {
6765 status &= ~0xff;
6766 status |= (u8)vector;
6767 vmcs_write16(GUEST_INTR_STATUS, status);
6768 }
6769}
6770
6771static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6772{
6773 if (max_irr == -1)
6774 return;
6775
6776 vmx_set_rvi(max_irr);
6777}
6778
6779static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6780{
3d81bc7e
YZ		 6781 if (!vmx_vm_has_apicv(vcpu->kvm))
6782 return;
6783
c7c9c56c
YZ		 6784 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6785 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6786 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6787 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6788}
6789
51aa01d1 6790static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6791{
00eba012
AK		 6792 u32 exit_intr_info;
6793
6794 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6795 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6796 return;
6797
c5ca8e57 6798 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6799 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6800
6801 /* Handle machine checks before interrupts are enabled */
00eba012 6802 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6803 kvm_machine_check();
6804
20f65983 6805 /* We need to handle NMIs before interrupts are enabled */
58e4633a 6806 if (is_nmi(exit_intr_info)) {
ff9d07a0 6807 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6808 asm("int $2");
ff9d07a0
ZY		 6809 kvm_after_handle_nmi(&vmx->vcpu);
6810 }
51aa01d1 6811}
20f65983 6812
a547c6db
YZ		 6813static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6814{
6815 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6816
6817 /*
6818 * If external interrupt exists, IF bit is set in rflags/eflags on the
6819 * interrupt stack frame, and interrupt will be enabled on a return
6820 * from interrupt handler.
6821 */
6822 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6823 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6824 unsigned int vector;
6825 unsigned long entry;
6826 gate_desc *desc;
6827 struct vcpu_vmx *vmx = to_vmx(vcpu);
6828#ifdef CONFIG_X86_64
6829 unsigned long tmp;
6830#endif
6831
6832 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6833 desc = (gate_desc *)vmx->host_idt_base + vector;
6834 entry = gate_offset(*desc);
6835 asm volatile(
6836#ifdef CONFIG_X86_64
6837 "mov %%" _ASM_SP ", %[sp]\n\t"
6838 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6839 "push $%c[ss]\n\t"
6840 "push %[sp]\n\t"
6841#endif
6842 "pushf\n\t"
6843 "orl $0x200, (%%" _ASM_SP ")\n\t"
6844 __ASM_SIZE(push) " $%c[cs]\n\t"
6845 "call *%[entry]\n\t"
6846 :
6847#ifdef CONFIG_X86_64
6848 [sp]"=&r"(tmp)
6849#endif
6850 :
6851 [entry]"r"(entry),
6852 [ss]"i"(__KERNEL_DS),
6853 [cs]"i"(__KERNEL_CS)
6854 );
6855 } else
6856 local_irq_enable();
6857}
6858
51aa01d1
AK		 6859static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6860{
c5ca8e57 6861 u32 exit_intr_info;
51aa01d1
AK		 6862 bool unblock_nmi;
6863 u8 vector;
6864 bool idtv_info_valid;
6865
6866 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6867
cf393f75 6868 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6869 if (vmx->nmi_known_unmasked)
6870 return;
c5ca8e57
AK		 6871 /*
6872 * Can't use vmx->exit_intr_info since we're not sure what
6873 * the exit reason is.
6874 */
6875 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6876 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6877 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6878 /*
7b4a25cb 6879 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6880 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6881 * a guest IRET fault.
7b4a25cb
GN		 6882 * SDM 3: 23.2.2 (September 2008)
6883 * Bit 12 is undefined in any of the following cases:
6884 * If the VM exit sets the valid bit in the IDT-vectoring
6885 * information field.
6886 * If the VM exit is due to a double fault.
cf393f75 6887 */
7b4a25cb
GN		 6888 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6889 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6890 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6891 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6892 else
6893 vmx->nmi_known_unmasked =
6894 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6895 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6896 } else if (unlikely(vmx->soft_vnmi_blocked))
6897 vmx->vnmi_blocked_time +=
6898 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6899}
6900
3ab66e8a 6901static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6902 u32 idt_vectoring_info,
6903 int instr_len_field,
6904 int error_code_field)
51aa01d1 6905{
51aa01d1
AK		 6906 u8 vector;
6907 int type;
6908 bool idtv_info_valid;
6909
6910 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6911
3ab66e8a
JK		 6912 vcpu->arch.nmi_injected = false;
6913 kvm_clear_exception_queue(vcpu);
6914 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6915
6916 if (!idtv_info_valid)
6917 return;
6918
3ab66e8a 6919 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6920
668f612f
AK		 6921 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6922 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6923
64a7ec06 6924 switch (type) {
37b96e98 6925 case INTR_TYPE_NMI_INTR:
3ab66e8a 6926 vcpu->arch.nmi_injected = true;
668f612f 6927 /*
7b4a25cb 6928 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6929 * Clear bit "block by NMI" before VM entry if a NMI
6930 * delivery faulted.
668f612f 6931 */
3ab66e8a 6932 vmx_set_nmi_mask(vcpu, false);
37b96e98 6933 break;
37b96e98 6934 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6935 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6936 /* fall through */
6937 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6938 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6939 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6940 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6941 } else
3ab66e8a 6942 kvm_queue_exception(vcpu, vector);
37b96e98 6943 break;
66fd3f7f 6944 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6945 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6946 /* fall through */
37b96e98 6947 case INTR_TYPE_EXT_INTR:
3ab66e8a 6948 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6949 break;
6950 default:
6951 break;
f7d9238f 6952 }
cf393f75
AK		 6953}
6954
83422e17
AK		 6955static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6956{
3ab66e8a 6957 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6958 VM_EXIT_INSTRUCTION_LEN,
6959 IDT_VECTORING_ERROR_CODE);
6960}
6961
b463a6f7
AK		 6962static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6963{
3ab66e8a 6964 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6965 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6966 VM_ENTRY_INSTRUCTION_LEN,
6967 VM_ENTRY_EXCEPTION_ERROR_CODE);
6968
6969 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6970}
6971
d7cd9796
GN		 6972static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6973{
6974 int i, nr_msrs;
6975 struct perf_guest_switch_msr *msrs;
6976
6977 msrs = perf_guest_get_msrs(&nr_msrs);
6978
6979 if (!msrs)
6980 return;
6981
6982 for (i = 0; i < nr_msrs; i++)
6983 if (msrs[i].host == msrs[i].guest)
6984 clear_atomic_switch_msr(vmx, msrs[i].msr);
6985 else
6986 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6987 msrs[i].host);
6988}
6989
a3b5ba49 6990static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6991{
a2fa3e9f 6992 struct vcpu_vmx *vmx = to_vmx(vcpu);
747a43ad 6993 unsigned long debugctlmsr, cr4;
104f226b
AK		 6994
6995 /* Record the guest's net vcpu time for enforced NMI injections. */
6996 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6997 vmx->entry_time = ktime_get();
6998
6999 /* Don't enter VMX if guest state is invalid, let the exit handler
7000 start emulation until we arrive back to a valid state */
14168786 7001 if (vmx->emulation_required)
104f226b
AK		 7002 return;
7003
012f83cb
AG		 7004 if (vmx->nested.sync_shadow_vmcs) {
7005 copy_vmcs12_to_shadow(vmx);
7006 vmx->nested.sync_shadow_vmcs = false;
7007 }
7008
104f226b
AK		 7009 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7010 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7011 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7012 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7013
747a43ad
AL		 7014 cr4 = read_cr4();
7015 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7016 vmcs_writel(HOST_CR4, cr4);
7017 vmx->host_state.vmcs_host_cr4 = cr4;
7018 }
7019
104f226b
AK		 7020 /* When single-stepping over STI and MOV SS, we must clear the
7021 * corresponding interruptibility bits in the guest state. Otherwise
7022 * vmentry fails as it then expects bit 14 (BS) in pending debug
7023 * exceptions being set, but that's not correct for the guest debugging
7024 * case. */
7025 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7026 vmx_set_interrupt_shadow(vcpu, 0);
7027
d7cd9796 7028 atomic_switch_perf_msrs(vmx);
2a7921b7 7029 debugctlmsr = get_debugctlmsr();
d7cd9796 7030
d462b819 7031 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7032 asm(
6aa8b732 7033 /* Store host registers */
b188c81f
AK		 7034 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7035 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7036 "push %%" _ASM_CX " \n\t"
7037 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7038 "je 1f \n\t"
b188c81f 7039 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7040 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7041 "1: \n\t"
d3edefc0 7042 /* Reload cr2 if changed */
b188c81f
AK		 7043 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7044 "mov %%cr2, %%" _ASM_DX " \n\t"
7045 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7046 "je 2f \n\t"
b188c81f 7047 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7048 "2: \n\t"
6aa8b732 7049 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7050 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7051 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7052 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7053 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7054 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7055 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7056 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7057 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7058#ifdef CONFIG_X86_64
e08aa78a
AK		 7059 "mov %c[r8](%0), %%r8 \n\t"
7060 "mov %c[r9](%0), %%r9 \n\t"
7061 "mov %c[r10](%0), %%r10 \n\t"
7062 "mov %c[r11](%0), %%r11 \n\t"
7063 "mov %c[r12](%0), %%r12 \n\t"
7064 "mov %c[r13](%0), %%r13 \n\t"
7065 "mov %c[r14](%0), %%r14 \n\t"
7066 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7067#endif
b188c81f 7068 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7069
6aa8b732 7070 /* Enter guest mode */
83287ea4 7071 "jne 1f \n\t"
4ecac3fd 7072 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7073 "jmp 2f \n\t"
7074 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7075 "2: "
6aa8b732 7076 /* Save guest registers, load host registers, keep flags */
b188c81f 7077 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7078 "pop %0 \n\t"
b188c81f
AK		 7079 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7080 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7081 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7082 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7083 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7084 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7085 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7086#ifdef CONFIG_X86_64
e08aa78a
AK		 7087 "mov %%r8, %c[r8](%0) \n\t"
7088 "mov %%r9, %c[r9](%0) \n\t"
7089 "mov %%r10, %c[r10](%0) \n\t"
7090 "mov %%r11, %c[r11](%0) \n\t"
7091 "mov %%r12, %c[r12](%0) \n\t"
7092 "mov %%r13, %c[r13](%0) \n\t"
7093 "mov %%r14, %c[r14](%0) \n\t"
7094 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7095#endif
b188c81f
AK		 7096 "mov %%cr2, %%" _ASM_AX " \n\t"
7097 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7098
b188c81f 7099 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7100 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7101 ".pushsection .rodata \n\t"
7102 ".global vmx_return \n\t"
7103 "vmx_return: " _ASM_PTR " 2b \n\t"
7104 ".popsection"
e08aa78a 7105 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7106 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7107 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7108 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7109 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7110 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7111 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7112 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7113 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7114 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7115 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7116#ifdef CONFIG_X86_64
ad312c7c
ZX		 7117 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7118 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7119 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7120 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7121 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7122 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7123 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7124 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7125#endif
40712fae
AK		 7126 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7127 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7128 : "cc", "memory"
7129#ifdef CONFIG_X86_64
b188c81f 7130 , "rax", "rbx", "rdi", "rsi"
c2036300 7131 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7132#else
7133 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7134#endif
7135 );
6aa8b732 7136
2a7921b7
GN		 7137 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7138 if (debugctlmsr)
7139 update_debugctlmsr(debugctlmsr);
7140
aa67f609
AK		 7141#ifndef CONFIG_X86_64
7142 /*
7143 * The sysexit path does not restore ds/es, so we must set them to
7144 * a reasonable value ourselves.
7145 *
7146 * We can't defer this to vmx_load_host_state() since that function
7147 * may be executed in interrupt context, which saves and restore segments
7148 * around it, nullifying its effect.
7149 */
7150 loadsegment(ds, __USER_DS);
7151 loadsegment(es, __USER_DS);
7152#endif
7153
6de4f3ad 7154 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7155 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7156 | (1 << VCPU_EXREG_CPL)
aff48baa 7157 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7158 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7159 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7160 vcpu->arch.regs_dirty = 0;
7161
1155f76a
AK		 7162 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7163
d462b819 7164 vmx->loaded_vmcs->launched = 1;
1b6269db 7165
51aa01d1 7166 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7167 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7168
7169 vmx_complete_atomic_exit(vmx);
7170 vmx_recover_nmi_blocking(vmx);
cf393f75 7171 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7172}
7173
6aa8b732
AK		 7174static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7175{
fb3f0f51
RR		 7176 struct vcpu_vmx *vmx = to_vmx(vcpu);
7177
cdbecfc3 7178 free_vpid(vmx);
d462b819 7179 free_loaded_vmcs(vmx->loaded_vmcs);
8705bd42 7180 free_nested(vmx);
fb3f0f51
RR		 7181 kfree(vmx->guest_msrs);
7182 kvm_vcpu_uninit(vcpu);
a4770347 7183 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7184}
7185
fb3f0f51 7186static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7187{
fb3f0f51 7188 int err;
c16f862d 7189 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7190 int cpu;
6aa8b732 7191
a2fa3e9f 7192 if (!vmx)
fb3f0f51
RR		 7193 return ERR_PTR(-ENOMEM);
7194
2384d2b3
SY		 7195 allocate_vpid(vmx);
7196
fb3f0f51
RR		 7197 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7198 if (err)
7199 goto free_vcpu;
965b58a5 7200
a2fa3e9f 7201 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7202 err = -ENOMEM;
fb3f0f51 7203 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7204 goto uninit_vcpu;
7205 }
965b58a5 7206
d462b819
NHE		 7207 vmx->loaded_vmcs = &vmx->vmcs01;
7208 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7209 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7210 goto free_msrs;
d462b819
NHE		 7211 if (!vmm_exclusive)
7212 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7213 loaded_vmcs_init(vmx->loaded_vmcs);
7214 if (!vmm_exclusive)
7215 kvm_cpu_vmxoff();
a2fa3e9f 7216
15ad7146
AK		 7217 cpu = get_cpu();
7218 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7219 vmx->vcpu.cpu = cpu;
8b9cf98c 7220 err = vmx_vcpu_setup(vmx);
fb3f0f51 7221 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7222 put_cpu();
fb3f0f51
RR		 7223 if (err)
7224 goto free_vmcs;
a63cb560 7225 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7226 err = alloc_apic_access_page(kvm);
7227 if (err)
5e4a0b3c 7228 goto free_vmcs;
a63cb560 7229 }
fb3f0f51 7230
b927a3ce
SY		 7231 if (enable_ept) {
7232 if (!kvm->arch.ept_identity_map_addr)
7233 kvm->arch.ept_identity_map_addr =
7234 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7235 err = -ENOMEM;
b7ebfb05
SY		 7236 if (alloc_identity_pagetable(kvm) != 0)
7237 goto free_vmcs;
93ea5388
GN		 7238 if (!init_rmode_identity_map(kvm))
7239 goto free_vmcs;
b927a3ce 7240 }
b7ebfb05 7241
a9d30f33
NHE		 7242 vmx->nested.current_vmptr = -1ull;
7243 vmx->nested.current_vmcs12 = NULL;
7244
fb3f0f51
RR		 7245 return &vmx->vcpu;
7246
7247free_vmcs:
5f3fbc34 7248 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7249free_msrs:
fb3f0f51
RR		 7250 kfree(vmx->guest_msrs);
7251uninit_vcpu:
7252 kvm_vcpu_uninit(&vmx->vcpu);
7253free_vcpu:
cdbecfc3 7254 free_vpid(vmx);
a4770347 7255 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7256 return ERR_PTR(err);
6aa8b732
AK		 7257}
7258
002c7f7c
YS		 7259static void __init vmx_check_processor_compat(void *rtn)
7260{
7261 struct vmcs_config vmcs_conf;
7262
7263 *(int *)rtn = 0;
7264 if (setup_vmcs_config(&vmcs_conf) < 0)
7265 *(int *)rtn = -EIO;
7266 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7267 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7268 smp_processor_id());
7269 *(int *)rtn = -EIO;
7270 }
7271}
7272
67253af5
SY		 7273static int get_ept_level(void)
7274{
7275 return VMX_EPT_DEFAULT_GAW + 1;
7276}
7277
4b12f0de 7278static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7279{
4b12f0de
SY		 7280 u64 ret;
7281
522c68c4
SY		 7282 /* For VT-d and EPT combination
7283 * 1. MMIO: always map as UC
7284 * 2. EPT with VT-d:
7285 * a. VT-d without snooping control feature: can't guarantee the
7286 * result, try to trust guest.
7287 * b. VT-d with snooping control feature: snooping control feature of
7288 * VT-d engine can guarantee the cache correctness. Just set it
7289 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7290 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7291 * consistent with host MTRR
7292 */
4b12f0de
SY		 7293 if (is_mmio)
7294 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7295 else if (vcpu->kvm->arch.iommu_domain &&
7296 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7297 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7298 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7299 else
522c68c4 7300 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7301 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7302
7303 return ret;
64d4d521
SY		 7304}
7305
17cc3935 7306static int vmx_get_lpage_level(void)
344f414f 7307{
878403b7
SY		 7308 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7309 return PT_DIRECTORY_LEVEL;
7310 else
7311 /* For shadow and EPT supported 1GB page */
7312 return PT_PDPE_LEVEL;
344f414f
JR		 7313}
7314
0e851880
SY		 7315static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7316{
4e47c7a6
SY		 7317 struct kvm_cpuid_entry2 *best;
7318 struct vcpu_vmx *vmx = to_vmx(vcpu);
7319 u32 exec_control;
7320
7321 vmx->rdtscp_enabled = false;
7322 if (vmx_rdtscp_supported()) {
7323 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7324 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7325 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7326 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7327 vmx->rdtscp_enabled = true;
7328 else {
7329 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7330 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7331 exec_control);
7332 }
7333 }
7334 }
ad756a16 7335
ad756a16
MJ		 7336 /* Exposing INVPCID only when PCID is exposed */
7337 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7338 if (vmx_invpcid_supported() &&
4f977045 7339 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7340 guest_cpuid_has_pcid(vcpu)) {
29282fde 7341 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7342 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7343 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7344 exec_control);
7345 } else {
29282fde
TI		 7346 if (cpu_has_secondary_exec_ctrls()) {
7347 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7348 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7349 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7350 exec_control);
7351 }
ad756a16 7352 if (best)
4f977045 7353 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7354 }
0e851880
SY		 7355}
7356
d4330ef2
JR		 7357static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7358{
7b8050f5
NHE		 7359 if (func == 1 && nested)
7360 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7361}
7362
fe3ef05c
NHE		 7363/*
7364 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7365 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7366 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7367 * guest in a way that will both be appropriate to L1's requests, and our
7368 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7369 * function also has additional necessary side-effects, like setting various
7370 * vcpu->arch fields.
7371 */
7372static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7373{
7374 struct vcpu_vmx *vmx = to_vmx(vcpu);
7375 u32 exec_control;
7376
7377 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7378 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7379 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7380 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7381 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7382 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7383 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7384 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7385 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7386 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7387 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7388 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7389 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7390 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7391 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7392 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7393 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7394 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7395 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7396 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7397 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7398 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7399 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7400 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7401 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7402 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7403 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7404 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7405 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7406 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7407 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7408 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7409 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7410 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7411 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7412 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7413
7414 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7415 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7416 vmcs12->vm_entry_intr_info_field);
7417 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7418 vmcs12->vm_entry_exception_error_code);
7419 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7420 vmcs12->vm_entry_instruction_len);
7421 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7422 vmcs12->guest_interruptibility_info);
fe3ef05c 7423 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7424 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7425 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7426 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7427 vmcs12->guest_pending_dbg_exceptions);
7428 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7429 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7430
7431 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7432
7433 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7434 (vmcs_config.pin_based_exec_ctrl |
7435 vmcs12->pin_based_vm_exec_control));
7436
0238ea91
JK		 7437 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7438 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7439 vmcs12->vmx_preemption_timer_value);
7440
fe3ef05c
NHE		 7441 /*
7442 * Whether page-faults are trapped is determined by a combination of
7443 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7444 * If enable_ept, L0 doesn't care about page faults and we should
7445 * set all of these to L1's desires. However, if !enable_ept, L0 does
7446 * care about (at least some) page faults, and because it is not easy
7447 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7448 * to exit on each and every L2 page fault. This is done by setting
7449 * MASK=MATCH=0 and (see below) EB.PF=1.
7450 * Note that below we don't need special code to set EB.PF beyond the
7451 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7452 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7453 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7454 *
7455 * A problem with this approach (when !enable_ept) is that L1 may be
7456 * injected with more page faults than it asked for. This could have
7457 * caused problems, but in practice existing hypervisors don't care.
7458 * To fix this, we will need to emulate the PFEC checking (on the L1
7459 * page tables), using walk_addr(), when injecting PFs to L1.
7460 */
7461 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7462 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7463 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7464 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7465
7466 if (cpu_has_secondary_exec_ctrls()) {
7467 u32 exec_control = vmx_secondary_exec_control(vmx);
7468 if (!vmx->rdtscp_enabled)
7469 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7470 /* Take the following fields only from vmcs12 */
7471 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7472 if (nested_cpu_has(vmcs12,
7473 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7474 exec_control |= vmcs12->secondary_vm_exec_control;
7475
7476 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7477 /*
7478 * Translate L1 physical address to host physical
7479 * address for vmcs02. Keep the page pinned, so this
7480 * physical address remains valid. We keep a reference
7481 * to it so we can release it later.
7482 */
7483 if (vmx->nested.apic_access_page) /* shouldn't happen */
7484 nested_release_page(vmx->nested.apic_access_page);
7485 vmx->nested.apic_access_page =
7486 nested_get_page(vcpu, vmcs12->apic_access_addr);
7487 /*
7488 * If translation failed, no matter: This feature asks
7489 * to exit when accessing the given address, and if it
7490 * can never be accessed, this feature won't do
7491 * anything anyway.
7492 */
7493 if (!vmx->nested.apic_access_page)
7494 exec_control &=
7495 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7496 else
7497 vmcs_write64(APIC_ACCESS_ADDR,
7498 page_to_phys(vmx->nested.apic_access_page));
7499 }
7500
7501 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7502 }
7503
7504
7505 /*
7506 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7507 * Some constant fields are set here by vmx_set_constant_host_state().
7508 * Other fields are different per CPU, and will be set later when
7509 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7510 */
a547c6db 7511 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7512
7513 /*
7514 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7515 * entry, but only if the current (host) sp changed from the value
7516 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7517 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7518 * here we just force the write to happen on entry.
7519 */
7520 vmx->host_rsp = 0;
7521
7522 exec_control = vmx_exec_control(vmx); /* L0's desires */
7523 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7524 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7525 exec_control &= ~CPU_BASED_TPR_SHADOW;
7526 exec_control |= vmcs12->cpu_based_vm_exec_control;
7527 /*
7528 * Merging of IO and MSR bitmaps not currently supported.
7529 * Rather, exit every time.
7530 */
7531 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7532 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7533 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7534
7535 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7536
7537 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7538 * bitwise-or of what L1 wants to trap for L2, and what we want to
7539 * trap. Note that CR0.TS also needs updating - we do this later.
7540 */
7541 update_exception_bitmap(vcpu);
7542 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7543 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7544
7545 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7546 vmcs_write32(VM_EXIT_CONTROLS,
7547 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7548 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7549 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7550
7551 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7552 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7553 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7554 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7555
7556
7557 set_cr4_guest_host_mask(vmx);
7558
27fc51b2
NHE		 7559 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7560 vmcs_write64(TSC_OFFSET,
7561 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7562 else
7563 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7564
7565 if (enable_vpid) {
7566 /*
7567 * Trivially support vpid by letting L2s share their parent
7568 * L1's vpid. TODO: move to a more elaborate solution, giving
7569 * each L2 its own vpid and exposing the vpid feature to L1.
7570 */
7571 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7572 vmx_flush_tlb(vcpu);
7573 }
7574
7575 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7576 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7577 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7578 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7579 else
7580 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7581 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7582 vmx_set_efer(vcpu, vcpu->arch.efer);
7583
7584 /*
7585 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7586 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7587 * The CR0_READ_SHADOW is what L2 should have expected to read given
7588 * the specifications by L1; It's not enough to take
7589 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7590 * have more bits than L1 expected.
7591 */
7592 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7593 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7594
7595 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7596 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7597
7598 /* shadow page tables on either EPT or shadow page tables */
7599 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7600 kvm_mmu_reset_context(vcpu);
7601
7602 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7603 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7604}
7605
cd232ad0
NHE		 7606/*
7607 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7608 * for running an L2 nested guest.
7609 */
7610static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7611{
7612 struct vmcs12 *vmcs12;
7613 struct vcpu_vmx *vmx = to_vmx(vcpu);
7614 int cpu;
7615 struct loaded_vmcs *vmcs02;
384bb783 7616 bool ia32e;
cd232ad0
NHE		 7617
7618 if (!nested_vmx_check_permission(vcpu) ||
7619 !nested_vmx_check_vmcs12(vcpu))
7620 return 1;
7621
7622 skip_emulated_instruction(vcpu);
7623 vmcs12 = get_vmcs12(vcpu);
7624
012f83cb
AG		 7625 if (enable_shadow_vmcs)
7626 copy_shadow_to_vmcs12(vmx);
7627
7c177938
NHE		 7628 /*
7629 * The nested entry process starts with enforcing various prerequisites
7630 * on vmcs12 as required by the Intel SDM, and act appropriately when
7631 * they fail: As the SDM explains, some conditions should cause the
7632 * instruction to fail, while others will cause the instruction to seem
7633 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7634 * To speed up the normal (success) code path, we should avoid checking
7635 * for misconfigurations which will anyway be caught by the processor
7636 * when using the merged vmcs02.
7637 */
7638 if (vmcs12->launch_state == launch) {
7639 nested_vmx_failValid(vcpu,
7640 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7641 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7642 return 1;
7643 }
7644
26539bd0
PB		 7645 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7646 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7647 return 1;
7648 }
7649
7c177938
NHE		 7650 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7651 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7652 /*TODO: Also verify bits beyond physical address width are 0*/
7653 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7654 return 1;
7655 }
7656
7657 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7658 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7659 /*TODO: Also verify bits beyond physical address width are 0*/
7660 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7661 return 1;
7662 }
7663
7664 if (vmcs12->vm_entry_msr_load_count > 0 ||
7665 vmcs12->vm_exit_msr_load_count > 0 ||
7666 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7667 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7668 __func__);
7c177938
NHE		 7669 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7670 return 1;
7671 }
7672
7673 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7674 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7675 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7676 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7677 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7678 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7679 !vmx_control_verify(vmcs12->vm_exit_controls,
7680 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7681 !vmx_control_verify(vmcs12->vm_entry_controls,
7682 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7683 {
7684 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7685 return 1;
7686 }
7687
7688 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7689 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7690 nested_vmx_failValid(vcpu,
7691 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7692 return 1;
7693 }
7694
7695 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7696 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7697 nested_vmx_entry_failure(vcpu, vmcs12,
7698 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7699 return 1;
7700 }
7701 if (vmcs12->vmcs_link_pointer != -1ull) {
7702 nested_vmx_entry_failure(vcpu, vmcs12,
7703 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7704 return 1;
7705 }
7706
384bb783 7707 /*
cb0c8cda 7708 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7709 * are performed on the field for the IA32_EFER MSR:
7710 * - Bits reserved in the IA32_EFER MSR must be 0.
7711 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7712 * the IA-32e mode guest VM-exit control. It must also be identical
7713 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7714 * CR0.PG) is 1.
7715 */
7716 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7717 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7718 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7719 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7720 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7721 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7722 nested_vmx_entry_failure(vcpu, vmcs12,
7723 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7724 return 1;
7725 }
7726 }
7727
7728 /*
7729 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7730 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7731 * the values of the LMA and LME bits in the field must each be that of
7732 * the host address-space size VM-exit control.
7733 */
7734 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7735 ia32e = (vmcs12->vm_exit_controls &
7736 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7737 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7738 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7739 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7740 nested_vmx_entry_failure(vcpu, vmcs12,
7741 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7742 return 1;
7743 }
7744 }
7745
7c177938
NHE		 7746 /*
7747 * We're finally done with prerequisite checking, and can start with
7748 * the nested entry.
7749 */
7750
cd232ad0
NHE		 7751 vmcs02 = nested_get_current_vmcs02(vmx);
7752 if (!vmcs02)
7753 return -ENOMEM;
7754
7755 enter_guest_mode(vcpu);
7756
7757 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7758
7759 cpu = get_cpu();
7760 vmx->loaded_vmcs = vmcs02;
7761 vmx_vcpu_put(vcpu);
7762 vmx_vcpu_load(vcpu, cpu);
7763 vcpu->cpu = cpu;
7764 put_cpu();
7765
36c3cc42
JK		 7766 vmx_segment_cache_clear(vmx);
7767
cd232ad0
NHE		 7768 vmcs12->launch_state = 1;
7769
7770 prepare_vmcs02(vcpu, vmcs12);
7771
7772 /*
7773 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7774 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7775 * returned as far as L1 is concerned. It will only return (and set
7776 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7777 */
7778 return 1;
7779}
7780
4704d0be
NHE		 7781/*
7782 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7783 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7784 * This function returns the new value we should put in vmcs12.guest_cr0.
7785 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7786 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7787 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7788 * didn't trap the bit, because if L1 did, so would L0).
7789 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7790 * been modified by L2, and L1 knows it. So just leave the old value of
7791 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7792 * isn't relevant, because if L0 traps this bit it can set it to anything.
7793 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7794 * changed these bits, and therefore they need to be updated, but L0
7795 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7796 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7797 */
7798static inline unsigned long
7799vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7800{
7801 return
7802 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7803 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7804 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7805 vcpu->arch.cr0_guest_owned_bits));
7806}
7807
7808static inline unsigned long
7809vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7810{
7811 return
7812 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7813 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7814 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7815 vcpu->arch.cr4_guest_owned_bits));
7816}
7817
5f3d5799
JK		 7818static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7819 struct vmcs12 *vmcs12)
7820{
7821 u32 idt_vectoring;
7822 unsigned int nr;
7823
7824 if (vcpu->arch.exception.pending) {
7825 nr = vcpu->arch.exception.nr;
7826 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7827
7828 if (kvm_exception_is_soft(nr)) {
7829 vmcs12->vm_exit_instruction_len =
7830 vcpu->arch.event_exit_inst_len;
7831 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7832 } else
7833 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7834
7835 if (vcpu->arch.exception.has_error_code) {
7836 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7837 vmcs12->idt_vectoring_error_code =
7838 vcpu->arch.exception.error_code;
7839 }
7840
7841 vmcs12->idt_vectoring_info_field = idt_vectoring;
7842 } else if (vcpu->arch.nmi_pending) {
7843 vmcs12->idt_vectoring_info_field =
7844 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7845 } else if (vcpu->arch.interrupt.pending) {
7846 nr = vcpu->arch.interrupt.nr;
7847 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7848
7849 if (vcpu->arch.interrupt.soft) {
7850 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7851 vmcs12->vm_entry_instruction_len =
7852 vcpu->arch.event_exit_inst_len;
7853 } else
7854 idt_vectoring |= INTR_TYPE_EXT_INTR;
7855
7856 vmcs12->idt_vectoring_info_field = idt_vectoring;
7857 }
7858}
7859
4704d0be
NHE		 7860/*
7861 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7862 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7863 * and this function updates it to reflect the changes to the guest state while
7864 * L2 was running (and perhaps made some exits which were handled directly by L0
7865 * without going back to L1), and to reflect the exit reason.
7866 * Note that we do not have to copy here all VMCS fields, just those that
7867 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7868 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7869 * which already writes to vmcs12 directly.
7870 */
733568f9 7871static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7872{
7873 /* update guest state fields: */
7874 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7875 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7876
7877 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7878 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7879 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7880 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7881
7882 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7883 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7884 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7885 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7886 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7887 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7888 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7889 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7890 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7891 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7892 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7893 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7894 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7895 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7896 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7897 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7898 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7899 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7900 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7901 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7902 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7903 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7904 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7905 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7906 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7907 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7908 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7909 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7910 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7911 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7912 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7913 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7914 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7915 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7916 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7917 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7918
4704d0be
NHE		 7919 vmcs12->guest_interruptibility_info =
7920 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7921 vmcs12->guest_pending_dbg_exceptions =
7922 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7923
c18911a2
JK		 7924 vmcs12->vm_entry_controls =
7925 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7926 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7927
4704d0be
NHE		 7928 /* TODO: These cannot have changed unless we have MSR bitmaps and
7929 * the relevant bit asks not to trap the change */
7930 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7931 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7932 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7933 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7934 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7935 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7936
7937 /* update exit information fields: */
7938
957c897e 7939 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7940 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7941
7942 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7943 if ((vmcs12->vm_exit_intr_info &
7944 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7945 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7946 vmcs12->vm_exit_intr_error_code =
7947 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7948 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7949 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7950 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7951
5f3d5799
JK		 7952 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7953 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7954 * instead of reading the real value. */
4704d0be 7955 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7956
7957 /*
7958 * Transfer the event that L0 or L1 may wanted to inject into
7959 * L2 to IDT_VECTORING_INFO_FIELD.
7960 */
7961 vmcs12_save_pending_event(vcpu, vmcs12);
7962 }
7963
7964 /*
7965 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7966 * preserved above and would only end up incorrectly in L1.
7967 */
7968 vcpu->arch.nmi_injected = false;
7969 kvm_clear_exception_queue(vcpu);
7970 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7971}
7972
7973/*
7974 * A part of what we need to when the nested L2 guest exits and we want to
7975 * run its L1 parent, is to reset L1's guest state to the host state specified
7976 * in vmcs12.
7977 * This function is to be called not only on normal nested exit, but also on
7978 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7979 * Failures During or After Loading Guest State").
7980 * This function should be called when the active VMCS is L1's (vmcs01).
7981 */
733568f9
JK		 7982static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7983 struct vmcs12 *vmcs12)
4704d0be
NHE		 7984{
7985 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7986 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 7987 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 7988 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7989 else
7990 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7991 vmx_set_efer(vcpu, vcpu->arch.efer);
7992
7993 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7994 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9f03d6fe 7995 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 7996 /*
7997 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7998 * actually changed, because it depends on the current state of
7999 * fpu_active (which may have changed).
8000 * Note that vmx_set_cr0 refers to efer set above.
8001 */
8002 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8003 /*
8004 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8005 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8006 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8007 */
8008 update_exception_bitmap(vcpu);
8009 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8010 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8011
8012 /*
8013 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8014 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8015 */
8016 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8017 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8018
8019 /* shadow page tables on either EPT or shadow page tables */
8020 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8021 kvm_mmu_reset_context(vcpu);
8022
8023 if (enable_vpid) {
8024 /*
8025 * Trivially support vpid by letting L2s share their parent
8026 * L1's vpid. TODO: move to a more elaborate solution, giving
8027 * each L2 its own vpid and exposing the vpid feature to L1.
8028 */
8029 vmx_flush_tlb(vcpu);
8030 }
8031
8032
8033 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8034 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8035 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8036 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8037 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8038 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
8039 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
8040 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
8041 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
8042 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
8043 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
8044 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
8045 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
8046 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
8047 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
8048
8049 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8050 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8051 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8052 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8053 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 8054
8055 kvm_set_dr(vcpu, 7, 0x400);
8056 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8057}
8058
8059/*
8060 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8061 * and modify vmcs12 to make it see what it would expect to see there if
8062 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8063 */
8064static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8065{
8066 struct vcpu_vmx *vmx = to_vmx(vcpu);
8067 int cpu;
8068 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8069
5f3d5799
JK		 8070 /* trying to cancel vmlaunch/vmresume is a bug */
8071 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8072
4704d0be
NHE		 8073 leave_guest_mode(vcpu);
8074 prepare_vmcs12(vcpu, vmcs12);
8075
8076 cpu = get_cpu();
8077 vmx->loaded_vmcs = &vmx->vmcs01;
8078 vmx_vcpu_put(vcpu);
8079 vmx_vcpu_load(vcpu, cpu);
8080 vcpu->cpu = cpu;
8081 put_cpu();
8082
36c3cc42
JK		 8083 vmx_segment_cache_clear(vmx);
8084
4704d0be
NHE		 8085 /* if no vmcs02 cache requested, remove the one we used */
8086 if (VMCS02_POOL_SIZE == 0)
8087 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8088
8089 load_vmcs12_host_state(vcpu, vmcs12);
8090
27fc51b2 8091 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8092 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8093
\8dmáÅ\99, 2016-08-08 20:16:23 +0200" rowspan="6">a0753a8c
RK		 8094 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
8095 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
8096 vmx_set_virtual_x2apic_mode(vcpu,
8097 vcpu->arch.apic_base & X2APIC_ENABLE);
8098 }
8099
4704d0be
NHE		 8100 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8101 vmx->host_rsp = 0;
8102
8103 /* Unpin physical memory we referred to in vmcs02 */
8104 if (vmx->nested.apic_access_page) {
8105 nested_release_page(vmx->nested.apic_access_page);
8106 vmx->nested.apic_access_page = 0;
8107 }
8108
8109 /*
8110 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8111 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8112 * success or failure flag accordingly.
8113 */
8114 if (unlikely(vmx->fail)) {
8115 vmx->fail = 0;
8116 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8117 } else
8118 nested_vmx_succeed(vcpu);
012f83cb
AG		 8119 if (enable_shadow_vmcs)
8120 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8121}
8122
7c177938
NHE		 8123/*
8124 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8125 * 23.7 "VM-entry failures during or after loading guest state" (this also
8126 * lists the acceptable exit-reason and exit-qualification parameters).
8127 * It should only be called before L2 actually succeeded to run, and when
8128 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8129 */
8130static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8131 struct vmcs12 *vmcs12,
8132 u32 reason, unsigned long qualification)
8133{
8134 load_vmcs12_host_state(vcpu, vmcs12);
8135 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8136 vmcs12->exit_qualification = qualification;
8137 nested_vmx_succeed(vcpu);
012f83cb
AG		 8138 if (enable_shadow_vmcs)
8139 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8140}
8141
8a76d7f2
JR		 8142static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8143 struct x86_instruction_info *info,
8144 enum x86_intercept_stage stage)
8145{
8146 return X86EMUL_CONTINUE;
8147}
8148
cbdd1bea 8149static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8150 .cpu_has_kvm_support = cpu_has_kvm_support,
8151 .disabled_by_bios = vmx_disabled_by_bios,
8152 .hardware_setup = hardware_setup,
8153 .hardware_unsetup = hardware_unsetup,
002c7f7c 8154 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8155 .hardware_enable = hardware_enable,
8156 .hardware_disable = hardware_disable,
04547156 8157 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8158
8159 .vcpu_create = vmx_create_vcpu,
8160 .vcpu_free = vmx_free_vcpu,
04d2cc77 8161 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8162
04d2cc77 8163 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8164 .vcpu_load = vmx_vcpu_load,
8165 .vcpu_put = vmx_vcpu_put,
8166
c8639010 8167 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8168 .get_msr = vmx_get_msr,
8169 .set_msr = vmx_set_msr,
8170 .get_segment_base = vmx_get_segment_base,
8171 .get_segment = vmx_get_segment,
8172 .set_segment = vmx_set_segment,
2e4d2653 8173 .get_cpl = vmx_get_cpl,
6aa8b732 8174 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8175 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8176 .decache_cr3 = vmx_decache_cr3,
25c4c276 8177 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8178 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8179 .set_cr3 = vmx_set_cr3,
8180 .set_cr4 = vmx_set_cr4,
6aa8b732 8181 .set_efer = vmx_set_efer,
6aa8b732
AK		 8182 .get_idt = vmx_get_idt,
8183 .set_idt = vmx_set_idt,
8184 .get_gdt = vmx_get_gdt,
8185 .set_gdt = vmx_set_gdt,
020df079 8186 .set_dr7 = vmx_set_dr7,
5fdbf976 8187 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8188 .get_rflags = vmx_get_rflags,
8189 .set_rflags = vmx_set_rflags,
ebcbab4c 8190 .fpu_activate = vmx_fpu_activate,
02daab21 8191 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8192
8193 .tlb_flush = vmx_flush_tlb,
6aa8b732 8194
6aa8b732 8195 .run = vmx_vcpu_run,
6062d012 8196 .handle_exit = vmx_handle_exit,
6aa8b732 8197 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8198 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8199 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8200 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8201 .set_irq = vmx_inject_irq,
95ba8273 8202 .set_nmi = vmx_inject_nmi,
298101da 8203 .queue_exception = vmx_queue_exception,
b463a6f7 8204 .cancel_injection = vmx_cancel_injection,
78646121 8205 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8206 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8207 .get_nmi_mask = vmx_get_nmi_mask,
8208 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8209 .enable_nmi_window = enable_nmi_window,
8210 .enable_irq_window = enable_irq_window,
8211 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8212 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8213 .vm_has_apicv = vmx_vm_has_apicv,
8214 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8215 .hwapic_irr_update = vmx_hwapic_irr_update,
8216 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8217 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8218 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8219
cbc94022 8220 .set_tss_addr = vmx_set_tss_addr,
67253af5 8221 .get_tdp_level = get_ept_level,
4b12f0de 8222 .get_mt_mask = vmx_get_mt_mask,
229456fc 8223
586f9607 8224 .get_exit_info = vmx_get_exit_info,
586f9607 8225
17cc3935 8226 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8227
8228 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8229
8230 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8231 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8232
8233 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8234
8235 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8236
4051b188 8237 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8238 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8239 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8240 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8241 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8242 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8243
8244 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8245
8246 .check_intercept = vmx_check_intercept,
a547c6db 8247 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8248};
8249
8250static int __init vmx_init(void)
8251{
8d14695f 8252 int r, i, msr;
26bb0981
AK		 8253
8254 rdmsrl_safe(MSR_EFER, &host_efer);
8255
8256 for (i = 0; i < NR_VMX_MSR; ++i)
8257 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8258
3e7c73e9 8259 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8260 if (!vmx_io_bitmap_a)
8261 return -ENOMEM;
8262
2106a548
GC		 8263 r = -ENOMEM;
8264
3e7c73e9 8265 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8266 if (!vmx_io_bitmap_b)
fdef3ad1 8267 goto out;
fdef3ad1 8268
5897297b 8269 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8270 if (!vmx_msr_bitmap_legacy)
25c5f225 8271 goto out1;
2106a548 8272
8d14695f
YZ		 8273 vmx_msr_bitmap_legacy_x2apic =
8274 (unsigned long *)__get_free_page(GFP_KERNEL);
8275 if (!vmx_msr_bitmap_legacy_x2apic)
8276 goto out2;
25c5f225 8277
5897297b 8278 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8279 if (!vmx_msr_bitmap_longmode)
8d14695f 8280 goto out3;
2106a548 8281
8d14695f
YZ		 8282 vmx_msr_bitmap_longmode_x2apic =
8283 (unsigned long *)__get_free_page(GFP_KERNEL);
8284 if (!vmx_msr_bitmap_longmode_x2apic)
8285 goto out4;
4607c2d7
AG		 8286 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8287 if (!vmx_vmread_bitmap)
8288 goto out5;
8289
8290 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8291 if (!vmx_vmwrite_bitmap)
8292 goto out6;
8293
8294 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8295 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8296 /* shadowed read/write fields */
8297 for (i = 0; i < max_shadow_read_write_fields; i++) {
8298 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8299 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8300 }
8301 /* shadowed read only fields */
8302 for (i = 0; i < max_shadow_read_only_fields; i++)
8303 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8304
fdef3ad1
HQ		 8305 /*
8306 * Allow direct access to the PC debug port (it is often used for I/O
8307 * delays, but the vmexits simply slow things down).
8308 */
3e7c73e9
AK		 8309 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8310 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8311
3e7c73e9 8312 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8313
5897297b
AK		 8314 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8315 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8316
2384d2b3
SY		 8317 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8318
0ee75bea
AK		 8319 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8320 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8321 if (r)
4607c2d7 8322 goto out7;
25c5f225 8323
8f536b76
ZY		 8324#ifdef CONFIG_KEXEC
8325 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8326 crash_vmclear_local_loaded_vmcss);
8327#endif
8328
5897297b
AK		 8329 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8330 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8331 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8332 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8333 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8334 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8335 memcpy(vmx_msr_bitmap_legacy_x2apic,
8336 vmx_msr_bitmap_legacy, PAGE_SIZE);
8337 memcpy(vmx_msr_bitmap_longmode_x2apic,
8338 vmx_msr_bitmap_longmode, PAGE_SIZE);
8339
01e439be 8340 if (enable_apicv) {
8d14695f
YZ		 8341 for (msr = 0x800; msr <= 0x8ff; msr++)
8342 vmx_disable_intercept_msr_read_x2apic(msr);
8343
8344 /* According SDM, in x2apic mode, the whole id reg is used.
8345 * But in KVM, it only use the highest eight bits. Need to
8346 * intercept it */
8347 vmx_enable_intercept_msr_read_x2apic(0x802);
8348 /* TMCCT */
8349 vmx_enable_intercept_msr_read_x2apic(0x839);
8350 /* TPR */
8351 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8352 /* EOI */
8353 vmx_disable_intercept_msr_write_x2apic(0x80b);
8354 /* SELF-IPI */
8355 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8356 }
fdef3ad1 8357
089d034e 8358 if (enable_ept) {
3f6d8c8a
XH		 8359 kvm_mmu_set_mask_ptes(0ull,
8360 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8361 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8362 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8363 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8364 kvm_enable_tdp();
8365 } else
8366 kvm_disable_tdp();
1439442c 8367
fdef3ad1
HQ		 8368 return 0;
8369
4607c2d7
AG		 8370out7:
8371 free_page((unsigned long)vmx_vmwrite_bitmap);
8372out6:
8373 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8374out5:
8375 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8376out4:
5897297b 8377 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8378out3:
8379 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8380out2:
5897297b 8381 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8382out1:
3e7c73e9 8383 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8384out:
3e7c73e9 8385 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8386 return r;
6aa8b732
AK		 8387}
8388
8389static void __exit vmx_exit(void)
8390{
8d14695f
YZ		 8391 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8392 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8393 free_page((unsigned long)vmx_msr_bitmap_legacy);
8394 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8395 free_page((unsigned long)vmx_io_bitmap_b);
8396 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8397 free_page((unsigned long)vmx_vmwrite_bitmap);
8398 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8399
8f536b76
ZY		 8400#ifdef CONFIG_KEXEC
8401 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8402 synchronize_rcu();
8403#endif
8404
cb498ea2 8405 kvm_exit();
6aa8b732
AK		 8406}
8407
8408module_init(vmx_init)
8409module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)