Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
5 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
6 | * | |
7 | * Derived from "include/asm-i386/processor.h" | |
8 | * Copyright (C) 1994, Linus Torvalds | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_S390_PROCESSOR_H | |
12 | #define __ASM_S390_PROCESSOR_H | |
13 | ||
eb608fb3 HC |
14 | #ifndef __ASSEMBLY__ |
15 | ||
edd53787 | 16 | #include <linux/linkage.h> |
a0616cde | 17 | #include <linux/irqflags.h> |
e86a6ed6 | 18 | #include <asm/cpu.h> |
25097bf1 | 19 | #include <asm/page.h> |
1da177e4 | 20 | #include <asm/ptrace.h> |
25097bf1 | 21 | #include <asm/setup.h> |
e4b8b3f3 | 22 | #include <asm/runtime_instr.h> |
1da177e4 | 23 | |
1da177e4 LT |
24 | /* |
25 | * Default implementation of macro that returns current | |
26 | * instruction pointer ("program counter"). | |
27 | */ | |
94c12cc7 | 28 | #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) |
1da177e4 | 29 | |
e86a6ed6 | 30 | static inline void get_cpu_id(struct cpuid *ptr) |
72960a02 | 31 | { |
987bcdac | 32 | asm volatile("stidp %0" : "=Q" (*ptr)); |
72960a02 MH |
33 | } |
34 | ||
31ee4b2f | 35 | extern void s390_adjust_jiffies(void); |
638ad34a MS |
36 | extern const struct seq_operations cpuinfo_op; |
37 | extern int sysctl_ieee_emulation_warnings; | |
65f22a90 | 38 | extern void execve_tail(void); |
1da177e4 | 39 | |
1da177e4 | 40 | /* |
f481bfaf | 41 | * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. |
1da177e4 | 42 | */ |
f4815ac6 | 43 | #ifndef CONFIG_64BIT |
1da177e4 | 44 | |
5a216a20 | 45 | #define TASK_SIZE (1UL << 31) |
f7bbcabc | 46 | #define TASK_MAX_SIZE (1UL << 31) |
5a216a20 | 47 | #define TASK_UNMAPPED_BASE (1UL << 30) |
1da177e4 | 48 | |
f4815ac6 | 49 | #else /* CONFIG_64BIT */ |
1da177e4 | 50 | |
71116d6a MS |
51 | #define TASK_SIZE_OF(tsk) ((tsk)->mm ? \ |
52 | (tsk)->mm->context.asce_limit : TASK_MAX_SIZE) | |
5a216a20 MS |
53 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ |
54 | (1UL << 30) : (1UL << 41)) | |
55 | #define TASK_SIZE TASK_SIZE_OF(current) | |
f7bbcabc | 56 | #define TASK_MAX_SIZE (1UL << 53) |
1da177e4 | 57 | |
f4815ac6 | 58 | #endif /* CONFIG_64BIT */ |
1da177e4 | 59 | |
f4815ac6 | 60 | #ifndef CONFIG_64BIT |
5a216a20 | 61 | #define STACK_TOP (1UL << 31) |
6252d702 | 62 | #define STACK_TOP_MAX (1UL << 31) |
f4815ac6 | 63 | #else /* CONFIG_64BIT */ |
6252d702 MS |
64 | #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) |
65 | #define STACK_TOP_MAX (1UL << 42) | |
f4815ac6 | 66 | #endif /* CONFIG_64BIT */ |
922a70d3 | 67 | |
1da177e4 LT |
68 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
69 | ||
70 | typedef struct { | |
71 | __u32 ar4; | |
72 | } mm_segment_t; | |
73 | ||
74 | /* | |
75 | * Thread structure | |
76 | */ | |
77 | struct thread_struct { | |
78 | s390_fp_regs fp_regs; | |
79 | unsigned int acrs[NUM_ACRS]; | |
80 | unsigned long ksp; /* kernel stack pointer */ | |
1da177e4 | 81 | mm_segment_t mm_segment; |
e5992f2e | 82 | unsigned long gmap_addr; /* address of last gmap fault. */ |
5e9a2692 MS |
83 | struct per_regs per_user; /* User specified PER registers */ |
84 | struct per_event per_event; /* Cause of the last PER trap */ | |
d35339a4 | 85 | unsigned long per_flags; /* Flags to control debug behavior */ |
1da177e4 LT |
86 | /* pfault_wait is used to block the process on a pfault event */ |
87 | unsigned long pfault_wait; | |
f2db2e6c | 88 | struct list_head list; |
e4b8b3f3 JG |
89 | /* cpu runtime instrumentation */ |
90 | struct runtime_instr_cb *ri_cb; | |
91 | int ri_signum; | |
d35339a4 MS |
92 | #ifdef CONFIG_64BIT |
93 | unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ | |
94 | #endif | |
1da177e4 LT |
95 | }; |
96 | ||
d35339a4 MS |
97 | #define PER_FLAG_NO_TE 1UL /* Flag to disable transactions. */ |
98 | ||
1da177e4 LT |
99 | typedef struct thread_struct thread_struct; |
100 | ||
101 | /* | |
102 | * Stack layout of a C stack frame. | |
103 | */ | |
104 | #ifndef __PACK_STACK | |
105 | struct stack_frame { | |
106 | unsigned long back_chain; | |
107 | unsigned long empty1[5]; | |
108 | unsigned long gprs[10]; | |
109 | unsigned int empty2[8]; | |
110 | }; | |
111 | #else | |
112 | struct stack_frame { | |
113 | unsigned long empty1[5]; | |
114 | unsigned int empty2[8]; | |
115 | unsigned long gprs[10]; | |
116 | unsigned long back_chain; | |
117 | }; | |
118 | #endif | |
119 | ||
120 | #define ARCH_MIN_TASKALIGN 8 | |
121 | ||
6f3fa3f0 MS |
122 | #define INIT_THREAD { \ |
123 | .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ | |
124 | } | |
1da177e4 LT |
125 | |
126 | /* | |
127 | * Do necessary setup to start up a new thread. | |
128 | */ | |
b50511e4 MS |
129 | #define start_thread(regs, new_psw, new_stackp) do { \ |
130 | regs->psw.mask = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA; \ | |
131 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ | |
132 | regs->gprs[15] = new_stackp; \ | |
65f22a90 | 133 | execve_tail(); \ |
63506c41 MS |
134 | } while (0) |
135 | ||
b50511e4 MS |
136 | #define start_thread31(regs, new_psw, new_stackp) do { \ |
137 | regs->psw.mask = psw_user_bits | PSW_MASK_BA; \ | |
138 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ | |
139 | regs->gprs[15] = new_stackp; \ | |
0f6f281b | 140 | __tlb_flush_mm(current->mm); \ |
b50511e4 | 141 | crst_table_downgrade(current->mm, 1UL << 31); \ |
0f6f281b | 142 | update_mm(current->mm, current); \ |
65f22a90 | 143 | execve_tail(); \ |
1da177e4 LT |
144 | } while (0) |
145 | ||
1da177e4 LT |
146 | /* Forward declaration, a strange C thing */ |
147 | struct task_struct; | |
148 | struct mm_struct; | |
df5f8314 | 149 | struct seq_file; |
1da177e4 | 150 | |
6668022c HC |
151 | #ifdef CONFIG_64BIT |
152 | extern void show_cacheinfo(struct seq_file *m); | |
153 | #else | |
154 | static inline void show_cacheinfo(struct seq_file *m) { } | |
155 | #endif | |
156 | ||
1da177e4 LT |
157 | /* Free all resources held by a thread. */ |
158 | extern void release_thread(struct task_struct *); | |
1da177e4 | 159 | |
1da177e4 LT |
160 | /* |
161 | * Return saved PC of a blocked thread. | |
162 | */ | |
163 | extern unsigned long thread_saved_pc(struct task_struct *t); | |
164 | ||
bb11e3bd | 165 | extern void show_code(struct pt_regs *regs); |
c10302ef | 166 | extern void print_fn_code(unsigned char *code, unsigned long len); |
0bcc94ba SR |
167 | extern int insn_to_mnemonic(unsigned char *instruction, char *buf, |
168 | unsigned int len); | |
1da177e4 LT |
169 | |
170 | unsigned long get_wchan(struct task_struct *p); | |
c7584fb6 | 171 | #define task_pt_regs(tsk) ((struct pt_regs *) \ |
30af7120 | 172 | (task_stack_page(tsk) + THREAD_SIZE) - 1) |
c7584fb6 AV |
173 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) |
174 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) | |
1da177e4 | 175 | |
a0616cde DH |
176 | static inline unsigned short stap(void) |
177 | { | |
178 | unsigned short cpu_address; | |
179 | ||
180 | asm volatile("stap %0" : "=m" (cpu_address)); | |
181 | return cpu_address; | |
182 | } | |
183 | ||
1da177e4 LT |
184 | /* |
185 | * Give up the time slice of the virtual PU. | |
186 | */ | |
abdba61a HC |
187 | static inline void cpu_relax(void) |
188 | { | |
189 | if (MACHINE_HAS_DIAG44) | |
c48e0913 HC |
190 | asm volatile("diag 0,0,68"); |
191 | barrier(); | |
abdba61a | 192 | } |
1da177e4 | 193 | |
dc74d7f9 HC |
194 | static inline void psw_set_key(unsigned int key) |
195 | { | |
196 | asm volatile("spka 0(%0)" : : "d" (key)); | |
197 | } | |
198 | ||
77fa2245 HC |
199 | /* |
200 | * Set PSW to specified value. | |
201 | */ | |
202 | static inline void __load_psw(psw_t psw) | |
203 | { | |
f4815ac6 | 204 | #ifndef CONFIG_64BIT |
987bcdac | 205 | asm volatile("lpsw %0" : : "Q" (psw) : "cc"); |
77fa2245 | 206 | #else |
987bcdac | 207 | asm volatile("lpswe %0" : : "Q" (psw) : "cc"); |
77fa2245 HC |
208 | #endif |
209 | } | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * Set PSW mask to specified value, while leaving the | |
213 | * PSW addr pointing to the next instruction. | |
214 | */ | |
1da177e4 LT |
215 | static inline void __load_psw_mask (unsigned long mask) |
216 | { | |
217 | unsigned long addr; | |
1da177e4 | 218 | psw_t psw; |
77fa2245 | 219 | |
1da177e4 LT |
220 | psw.mask = mask; |
221 | ||
f4815ac6 | 222 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
223 | asm volatile( |
224 | " basr %0,0\n" | |
225 | "0: ahi %0,1f-0b\n" | |
987bcdac MS |
226 | " st %0,%O1+4(%R1)\n" |
227 | " lpsw %1\n" | |
1da177e4 | 228 | "1:" |
987bcdac | 229 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 230 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
231 | asm volatile( |
232 | " larl %0,1f\n" | |
987bcdac MS |
233 | " stg %0,%O1+8(%R1)\n" |
234 | " lpswe %1\n" | |
1da177e4 | 235 | "1:" |
987bcdac | 236 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 237 | #endif /* CONFIG_64BIT */ |
1da177e4 | 238 | } |
ccf45caf MS |
239 | |
240 | /* | |
241 | * Rewind PSW instruction address by specified number of bytes. | |
242 | */ | |
243 | static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) | |
244 | { | |
f4815ac6 | 245 | #ifndef CONFIG_64BIT |
ccf45caf MS |
246 | if (psw.addr & PSW_ADDR_AMODE) |
247 | /* 31 bit mode */ | |
248 | return (psw.addr - ilc) | PSW_ADDR_AMODE; | |
249 | /* 24 bit mode */ | |
250 | return (psw.addr - ilc) & ((1UL << 24) - 1); | |
251 | #else | |
252 | unsigned long mask; | |
253 | ||
254 | mask = (psw.mask & PSW_MASK_EA) ? -1UL : | |
255 | (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : | |
256 | (1UL << 24) - 1; | |
257 | return (psw.addr - ilc) & mask; | |
258 | #endif | |
259 | } | |
1da177e4 | 260 | |
1da177e4 LT |
261 | /* |
262 | * Function to drop a processor into disabled wait state | |
263 | */ | |
ff2d8b19 | 264 | static inline void __noreturn disabled_wait(unsigned long code) |
1da177e4 | 265 | { |
1da177e4 | 266 | unsigned long ctl_buf; |
77fa2245 | 267 | psw_t dw_psw; |
1da177e4 | 268 | |
b50511e4 | 269 | dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; |
77fa2245 | 270 | dw_psw.addr = code; |
1da177e4 LT |
271 | /* |
272 | * Store status and then load disabled wait psw, | |
273 | * the processor is dead afterwards | |
274 | */ | |
f4815ac6 | 275 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
276 | asm volatile( |
277 | " stctl 0,0,0(%2)\n" | |
278 | " ni 0(%2),0xef\n" /* switch off protection */ | |
279 | " lctl 0,0,0(%2)\n" | |
280 | " stpt 0xd8\n" /* store timer */ | |
281 | " stckc 0xe0\n" /* store clock comparator */ | |
282 | " stpx 0x108\n" /* store prefix register */ | |
283 | " stam 0,15,0x120\n" /* store access registers */ | |
284 | " std 0,0x160\n" /* store f0 */ | |
285 | " std 2,0x168\n" /* store f2 */ | |
286 | " std 4,0x170\n" /* store f4 */ | |
287 | " std 6,0x178\n" /* store f6 */ | |
288 | " stm 0,15,0x180\n" /* store general registers */ | |
289 | " stctl 0,15,0x1c0\n" /* store control registers */ | |
290 | " oi 0x1c0,0x10\n" /* fake protection bit */ | |
291 | " lpsw 0(%1)" | |
292 | : "=m" (ctl_buf) | |
293 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); | |
f4815ac6 | 294 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
295 | asm volatile( |
296 | " stctg 0,0,0(%2)\n" | |
297 | " ni 4(%2),0xef\n" /* switch off protection */ | |
298 | " lctlg 0,0,0(%2)\n" | |
299 | " lghi 1,0x1000\n" | |
300 | " stpt 0x328(1)\n" /* store timer */ | |
301 | " stckc 0x330(1)\n" /* store clock comparator */ | |
302 | " stpx 0x318(1)\n" /* store prefix register */ | |
303 | " stam 0,15,0x340(1)\n"/* store access registers */ | |
304 | " stfpc 0x31c(1)\n" /* store fpu control */ | |
305 | " std 0,0x200(1)\n" /* store f0 */ | |
306 | " std 1,0x208(1)\n" /* store f1 */ | |
307 | " std 2,0x210(1)\n" /* store f2 */ | |
308 | " std 3,0x218(1)\n" /* store f3 */ | |
309 | " std 4,0x220(1)\n" /* store f4 */ | |
310 | " std 5,0x228(1)\n" /* store f5 */ | |
311 | " std 6,0x230(1)\n" /* store f6 */ | |
312 | " std 7,0x238(1)\n" /* store f7 */ | |
313 | " std 8,0x240(1)\n" /* store f8 */ | |
314 | " std 9,0x248(1)\n" /* store f9 */ | |
315 | " std 10,0x250(1)\n" /* store f10 */ | |
316 | " std 11,0x258(1)\n" /* store f11 */ | |
317 | " std 12,0x260(1)\n" /* store f12 */ | |
318 | " std 13,0x268(1)\n" /* store f13 */ | |
319 | " std 14,0x270(1)\n" /* store f14 */ | |
320 | " std 15,0x278(1)\n" /* store f15 */ | |
321 | " stmg 0,15,0x280(1)\n"/* store general registers */ | |
322 | " stctg 0,15,0x380(1)\n"/* store control registers */ | |
323 | " oi 0x384(1),0x10\n"/* fake protection bit */ | |
324 | " lpswe 0(%1)" | |
325 | : "=m" (ctl_buf) | |
bdd42b28 | 326 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); |
f4815ac6 | 327 | #endif /* CONFIG_64BIT */ |
edd53787 | 328 | while (1); |
1da177e4 LT |
329 | } |
330 | ||
a0616cde DH |
331 | /* |
332 | * Use to set psw mask except for the first byte which | |
333 | * won't be changed by this function. | |
334 | */ | |
335 | static inline void | |
336 | __set_psw_mask(unsigned long mask) | |
337 | { | |
338 | __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); | |
339 | } | |
340 | ||
341 | #define local_mcck_enable() \ | |
342 | __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK) | |
343 | #define local_mcck_disable() \ | |
344 | __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT) | |
345 | ||
ab14de6c HC |
346 | /* |
347 | * Basic Machine Check/Program Check Handler. | |
348 | */ | |
349 | ||
350 | extern void s390_base_mcck_handler(void); | |
351 | extern void s390_base_pgm_handler(void); | |
352 | extern void s390_base_ext_handler(void); | |
353 | ||
354 | extern void (*s390_base_mcck_handler_fn)(void); | |
355 | extern void (*s390_base_pgm_handler_fn)(void); | |
356 | extern void (*s390_base_ext_handler_fn)(void); | |
357 | ||
dfd54cbc HC |
358 | #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL |
359 | ||
fbe76568 HC |
360 | extern int memcpy_real(void *, void *, size_t); |
361 | extern void memcpy_absolute(void *, void *, size_t); | |
362 | ||
363 | #define mem_assign_absolute(dest, val) { \ | |
364 | __typeof__(dest) __tmp = (val); \ | |
365 | \ | |
366 | BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ | |
367 | memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ | |
368 | } | |
369 | ||
eb608fb3 HC |
370 | /* |
371 | * Helper macro for exception table entries | |
372 | */ | |
373 | #define EX_TABLE(_fault, _target) \ | |
374 | ".section __ex_table,\"a\"\n" \ | |
375 | ".align 4\n" \ | |
376 | ".long (" #_fault ") - .\n" \ | |
377 | ".long (" #_target ") - .\n" \ | |
378 | ".previous\n" | |
379 | ||
380 | #else /* __ASSEMBLY__ */ | |
381 | ||
382 | #define EX_TABLE(_fault, _target) \ | |
383 | .section __ex_table,"a" ; \ | |
384 | .align 4 ; \ | |
385 | .long (_fault) - . ; \ | |
386 | .long (_target) - . ; \ | |
387 | .previous | |
388 | ||
389 | #endif /* __ASSEMBLY__ */ | |
390 | ||
391 | #endif /* __ASM_S390_PROCESSOR_H */ |