[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / irq-gic.c

#undef DEBUG

#include <linux/bitmap.h>
#include <linux/init.h>
#include <linux/smp.h>

#include <asm/io.h>
#include <asm/gic.h>
#include <asm/gcmpregs.h>
#include <asm/irq.h>
#include <linux/hardirq.h>
#include <asm-generic/bitops/find.h>


static unsigned long _gic_base;
static unsigned int _irqbase;
static unsigned int gic_irq_flags[GIC_NUM_INTRS];
#define GIC_IRQ_FLAG_EDGE      0x0001

struct gic_pcpu_mask pcpu_masks[NR_CPUS];
static struct gic_pending_regs pending_regs[NR_CPUS];
static struct gic_intrmask_regs intrmask_regs[NR_CPUS];

void gic_send_ipi(unsigned int intr)
{
	pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
		 read_c0_status());
	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
}

/* This is Malta specific and needs to be exported */
static void __init vpe_local_setup(unsigned int numvpes)
{
	int i;
	unsigned long timer_interrupt = 5, perf_interrupt = 5;
	unsigned int vpe_ctl;

	/*
	 * Setup the default performance counter timer interrupts
	 * for all VPEs
	 */
	for (i = 0; i < numvpes; i++) {
		GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);

		/* Are Interrupts locally routable? */
		GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
		if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
				 GIC_MAP_TO_PIN_MSK | timer_interrupt);

		if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
				 GIC_MAP_TO_PIN_MSK | perf_interrupt);
	}
}

unsigned int gic_get_int(void)
{
	unsigned int i;
	unsigned long *pending, *intrmask, *pcpu_mask;
	unsigned long *pending_abs, *intrmask_abs;

	/* Get per-cpu bitmaps */
	pending = pending_regs[smp_processor_id()].pending;
	intrmask = intrmask_regs[smp_processor_id()].intrmask;
	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;

	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
							 GIC_SH_PEND_31_0_OFS);
	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
							  GIC_SH_MASK_31_0_OFS);

	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
		GICREAD(*pending_abs, pending[i]);
		GICREAD(*intrmask_abs, intrmask[i]);
		pending_abs++;
		intrmask_abs++;
	}

	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);

	i = find_first_bit(pending, GIC_NUM_INTRS);

	pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);

	return i;
}

static unsigned int gic_irq_startup(unsigned int irq)
{
	irq -= _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_SET_INTR_MASK(irq);
	return 0;
}

static void gic_irq_ack(unsigned int irq)
{
	irq -= _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_CLR_INTR_MASK(irq);

	if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
		GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
}

static void gic_mask_irq(unsigned int irq)
{
	irq -= _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_CLR_INTR_MASK(irq);
}

static void gic_unmask_irq(unsigned int irq)
{
	irq -= _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_SET_INTR_MASK(irq);
}

#ifdef CONFIG_SMP

static DEFINE_SPINLOCK(gic_lock);

static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
{
	cpumask_t	tmp = CPU_MASK_NONE;
	unsigned long	flags;
	int		i;

	irq -= _irqbase;
	pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
	cpumask_and(&tmp, cpumask, cpu_online_mask);
	if (cpus_empty(tmp))
		return -1;

	/* Assumption : cpumask refers to a single CPU */
	spin_lock_irqsave(&gic_lock, flags);
	for (;;) {
		/* Re-route this IRQ */
		GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));

		/* Update the pcpu_masks */
		for (i = 0; i < NR_CPUS; i++)
			clear_bit(irq, pcpu_masks[i].pcpu_mask);
		set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);

	}
	cpumask_copy(irq_desc[irq].affinity, cpumask);
	spin_unlock_irqrestore(&gic_lock, flags);

	return 0;
}
#endif

static struct irq_chip gic_irq_controller = {
	.name		=	"MIPS GIC",
	.startup	=	gic_irq_startup,
	.ack		=	gic_irq_ack,
	.mask		=	gic_mask_irq,
	.mask_ack	=	gic_mask_irq,
	.unmask		=	gic_unmask_irq,
	.eoi		=	gic_unmask_irq,
#ifdef CONFIG_SMP
	.set_affinity	=	gic_set_affinity,
#endif
};

static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	unsigned int flags)
{
	/* Setup Intr to Pin mapping */
	if (pin & GIC_MAP_TO_NMI_MSK) {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
		/* FIXME: hack to route NMI to all cpu's */
		for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
			GICWRITE(GIC_REG_ADDR(SHARED,
					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
				 0xffffffff);
		}
	} else {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
			 GIC_MAP_TO_PIN_MSK | pin);
		/* Setup Intr to CPU mapping */
		GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
	}

	/* Setup Intr Polarity */
	GIC_SET_POLARITY(intr, polarity);

	/* Setup Intr Trigger Type */
	GIC_SET_TRIGGER(intr, trigtype);

	/* Init Intr Masks */
	GIC_CLR_INTR_MASK(intr);
	/* Initialise per-cpu Interrupt software masks */
	if (flags & GIC_FLAG_IPI)
		set_bit(intr, pcpu_masks[cpu].pcpu_mask);
	if (flags & GIC_FLAG_TRANSPARENT)
		GIC_SET_INTR_MASK(intr);
	if (trigtype == GIC_TRIG_EDGE)
		gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
}

static void __init gic_basic_init(int numintrs, int numvpes,
			struct gic_intr_map *intrmap, int mapsize)
{
	unsigned int i, cpu;

	/* Setup defaults */
	for (i = 0; i < numintrs; i++) {
		GIC_SET_POLARITY(i, GIC_POL_POS);
		GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
		GIC_CLR_INTR_MASK(i);
		if (i < GIC_NUM_INTRS)
			gic_irq_flags[i] = 0;
	}

	/* Setup specifics */
	for (i = 0; i < mapsize; i++) {
		cpu = intrmap[i].cpunum;
		if (cpu == GIC_UNUSED)
			continue;
		if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
			continue;
		gic_setup_intr(i,
			intrmap[i].cpunum,
			intrmap[i].pin,
			intrmap[i].polarity,
			intrmap[i].trigtype,
			intrmap[i].flags);
	}

	vpe_local_setup(numvpes);

	for (i = _irqbase; i < (_irqbase + numintrs); i++)
		set_irq_chip(i, &gic_irq_controller);
}

void __init gic_init(unsigned long gic_base_addr,
		     unsigned long gic_addrspace_size,
		     struct gic_intr_map *intr_map, unsigned int intr_map_size,
		     unsigned int irqbase)
{
	unsigned int gicconfig;
	int numvpes, numintrs;

	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
						    gic_addrspace_size);
	_irqbase = irqbase;

	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
		   GIC_SH_CONFIG_NUMINTRS_SHF;
	numintrs = ((numintrs + 1) * 8);

	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
		  GIC_SH_CONFIG_NUMVPES_SHF;

	pr_debug("%s called\n", __func__);

	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
}
Commit	Line	Data
39b8d525 RB	1	#undef DEBUG
	2
	3	#include <linux/bitmap.h>
	4	#include <linux/init.h>
631330f5	5	#include <linux/smp.h>
39b8d525 RB	6
	7	#include <asm/io.h>
	8	#include <asm/gic.h>
	9	#include <asm/gcmpregs.h>
39b8d525 RB	10	#include <asm/irq.h>
	11	#include <linux/hardirq.h>
	12	#include <asm-generic/bitops/find.h>
	13
	14
	15	static unsigned long _gic_base;
7098f748 CD	16	static unsigned int _irqbase;
	17	static unsigned int gic_irq_flags[GIC_NUM_INTRS];
	18	#define GIC_IRQ_FLAG_EDGE 0x0001
39b8d525	19
7098f748	20	struct gic_pcpu_mask pcpu_masks[NR_CPUS];
39b8d525 RB	21	static struct gic_pending_regs pending_regs[NR_CPUS];
	22	static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
	23
39b8d525 RB	24	void gic_send_ipi(unsigned int intr)
39b8d525 RB	25	{
39b8d525 RB	26	pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
39b8d525 RB	27	read_c0_status());
39b8d525	28	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 \| intr);
39b8d525 RB	29	}
	30
	31	/* This is Malta specific and needs to be exported */
7098f748	32	static void __init vpe_local_setup(unsigned int numvpes)
39b8d525 RB	33	{
	34	int i;
	35	unsigned long timer_interrupt = 5, perf_interrupt = 5;
	36	unsigned int vpe_ctl;
	37
	38	/*
	39	* Setup the default performance counter timer interrupts
	40	* for all VPEs
	41	*/
	42	for (i = 0; i < numvpes; i++) {
	43	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
	44
	45	/* Are Interrupts locally routable? */
	46	GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
	47	if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
	48	GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
	49	GIC_MAP_TO_PIN_MSK \| timer_interrupt);
	50
	51	if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
	52	GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
	53	GIC_MAP_TO_PIN_MSK \| perf_interrupt);
	54	}
	55	}
	56
	57	unsigned int gic_get_int(void)
	58	{
	59	unsigned int i;
	60	unsigned long pending, intrmask, *pcpu_mask;
	61	unsigned long pending_abs, intrmask_abs;
	62
	63	/* Get per-cpu bitmaps */
	64	pending = pending_regs[smp_processor_id()].pending;
	65	intrmask = intrmask_regs[smp_processor_id()].intrmask;
	66	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
	67
	68	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
	69	GIC_SH_PEND_31_0_OFS);
	70	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
	71	GIC_SH_MASK_31_0_OFS);
	72
	73	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
	74	GICREAD(*pending_abs, pending[i]);
	75	GICREAD(*intrmask_abs, intrmask[i]);
	76	pending_abs++;
	77	intrmask_abs++;
	78	}
	79
	80	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
	81	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
	82
	83	i = find_first_bit(pending, GIC_NUM_INTRS);
	84
	85	pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
	86
	87	return i;
	88	}
	89
	90	static unsigned int gic_irq_startup(unsigned int irq)
	91	{
39b8d525	92	irq -= _irqbase;
7098f748 CD	93	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
7098f748 CD	94	GIC_SET_INTR_MASK(irq);
39b8d525 RB	95	return 0;
	96	}
	97
	98	static void gic_irq_ack(unsigned int irq)
	99	{
39b8d525	100	irq -= _irqbase;
7098f748 CD	101	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
7098f748 CD	102	GIC_CLR_INTR_MASK(irq);
39b8d525	103
7098f748	104	if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
39b8d525	105	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
39b8d525 RB	106	}
	107
	108	static void gic_mask_irq(unsigned int irq)
	109	{
39b8d525	110	irq -= _irqbase;
7098f748 CD	111	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
7098f748 CD	112	GIC_CLR_INTR_MASK(irq);
39b8d525 RB	113	}
	114
	115	static void gic_unmask_irq(unsigned int irq)
	116	{
39b8d525	117	irq -= _irqbase;
7098f748 CD	118	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
7098f748 CD	119	GIC_SET_INTR_MASK(irq);
39b8d525 RB	120	}
	121
	122	#ifdef CONFIG_SMP
	123
	124	static DEFINE_SPINLOCK(gic_lock);
	125
d5dedd45	126	static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
39b8d525 RB	127	{
	128	cpumask_t tmp = CPU_MASK_NONE;
	129	unsigned long flags;
	130	int i;
	131
39b8d525	132	irq -= _irqbase;
7098f748	133	pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
0de26520	134	cpumask_and(&tmp, cpumask, cpu_online_mask);
39b8d525	135	if (cpus_empty(tmp))
d5dedd45	136	return -1;
39b8d525 RB	137
	138	/* Assumption : cpumask refers to a single CPU */
	139	spin_lock_irqsave(&gic_lock, flags);
	140	for (;;) {
	141	/* Re-route this IRQ */
	142	GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
	143
39b8d525 RB	144	/* Update the pcpu_masks */
	145	for (i = 0; i < NR_CPUS; i++)
	146	clear_bit(irq, pcpu_masks[i].pcpu_mask);
	147	set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
	148
	149	}
e65e49d0	150	cpumask_copy(irq_desc[irq].affinity, cpumask);
39b8d525 RB	151	spin_unlock_irqrestore(&gic_lock, flags);
39b8d525 RB	152
d5dedd45	153	return 0;
39b8d525 RB	154	}
	155	#endif
	156
	157	static struct irq_chip gic_irq_controller = {
	158	.name = "MIPS GIC",
	159	.startup = gic_irq_startup,
	160	.ack = gic_irq_ack,
	161	.mask = gic_mask_irq,
	162	.mask_ack = gic_mask_irq,
	163	.unmask = gic_unmask_irq,
	164	.eoi = gic_unmask_irq,
	165	#ifdef CONFIG_SMP
	166	.set_affinity = gic_set_affinity,
	167	#endif
	168	};
	169
7098f748 CD	170	static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	171	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	172	unsigned int flags)
39b8d525 RB	173	{
	174	/* Setup Intr to Pin mapping */
	175	if (pin & GIC_MAP_TO_NMI_MSK) {
	176	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
	177	/* FIXME: hack to route NMI to all cpu's */
	178	for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
	179	GICWRITE(GIC_REG_ADDR(SHARED,
	180	GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
	181	0xffffffff);
	182	}
	183	} else {
	184	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
	185	GIC_MAP_TO_PIN_MSK \| pin);
	186	/* Setup Intr to CPU mapping */
	187	GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
	188	}
	189
	190	/* Setup Intr Polarity */
	191	GIC_SET_POLARITY(intr, polarity);
	192
	193	/* Setup Intr Trigger Type */
	194	GIC_SET_TRIGGER(intr, trigtype);
	195
	196	/* Init Intr Masks */
7098f748 CD	197	GIC_CLR_INTR_MASK(intr);
	198	/* Initialise per-cpu Interrupt software masks */
	199	if (flags & GIC_FLAG_IPI)
	200	set_bit(intr, pcpu_masks[cpu].pcpu_mask);
	201	if (flags & GIC_FLAG_TRANSPARENT)
	202	GIC_SET_INTR_MASK(intr);
	203	if (trigtype == GIC_TRIG_EDGE)
	204	gic_irq_flags[intr] \|= GIC_IRQ_FLAG_EDGE;
39b8d525 RB	205	}
39b8d525 RB	206
7098f748 CD	207	static void __init gic_basic_init(int numintrs, int numvpes,
7098f748 CD	208	struct gic_intr_map *intrmap, int mapsize)
39b8d525 RB	209	{
	210	unsigned int i, cpu;
	211
	212	/* Setup defaults */
7098f748	213	for (i = 0; i < numintrs; i++) {
39b8d525 RB	214	GIC_SET_POLARITY(i, GIC_POL_POS);
39b8d525 RB	215	GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
7098f748 CD	216	GIC_CLR_INTR_MASK(i);
	217	if (i < GIC_NUM_INTRS)
	218	gic_irq_flags[i] = 0;
39b8d525 RB	219	}
	220
	221	/* Setup specifics */
7098f748 CD	222	for (i = 0; i < mapsize; i++) {
7098f748 CD	223	cpu = intrmap[i].cpunum;
863cb9ba	224	if (cpu == GIC_UNUSED)
39b8d525	225	continue;
7098f748	226	if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
a214cef9	227	continue;
7098f748 CD	228	gic_setup_intr(i,
	229	intrmap[i].cpunum,
	230	intrmap[i].pin,
	231	intrmap[i].polarity,
	232	intrmap[i].trigtype,
	233	intrmap[i].flags);
39b8d525 RB	234	}
	235
	236	vpe_local_setup(numvpes);
	237
	238	for (i = _irqbase; i < (_irqbase + numintrs); i++)
	239	set_irq_chip(i, &gic_irq_controller);
	240	}
	241
	242	void __init gic_init(unsigned long gic_base_addr,
	243	unsigned long gic_addrspace_size,
	244	struct gic_intr_map *intr_map, unsigned int intr_map_size,
	245	unsigned int irqbase)
	246	{
	247	unsigned int gicconfig;
7098f748	248	int numvpes, numintrs;
39b8d525 RB	249
	250	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
	251	gic_addrspace_size);
	252	_irqbase = irqbase;
39b8d525 RB	253
	254	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
	255	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
	256	GIC_SH_CONFIG_NUMINTRS_SHF;
	257	numintrs = ((numintrs + 1) * 8);
	258
	259	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
	260	GIC_SH_CONFIG_NUMVPES_SHF;
	261
	262	pr_debug("%s called\n", __func__);
	263
7098f748	264	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
39b8d525	265	}