[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / branch.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
 * Copyright (C) 2001 MIPS Technologies, Inc.
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/module.h>
#include <asm/branch.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/fpu.h>
#include <asm/fpu_emulator.h>
#include <asm/inst.h>
#include <asm/ptrace.h>
#include <asm/uaccess.h>

/*
 * Calculate and return exception PC in case of branch delay slot
 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
 */
int __isa_exception_epc(struct pt_regs *regs)
{
	unsigned short inst;
	long epc = regs->cp0_epc;

	/* Calculate exception PC in branch delay slot. */
	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
		/* This should never happen because delay slot was checked. */
		force_sig(SIGSEGV, current);
		return epc;
	}
	if (cpu_has_mips16) {
		if (((union mips16e_instruction)inst).ri.opcode
				== MIPS16e_jal_op)
			epc += 4;
		else
			epc += 2;
	} else if (mm_insn_16bit(inst))
		epc += 2;
	else
		epc += 4;

	return epc;
}

/*
 * Compute return address and emulate branch in microMIPS mode after an
 * exception only. It does not handle compact branches/jumps and cannot
 * be used in interrupt context. (Compact branches/jumps do not cause
 * exceptions.)
 */
int __microMIPS_compute_return_epc(struct pt_regs *regs)
{
	u16 __user *pc16;
	u16 halfword;
	unsigned int word;
	unsigned long contpc;
	struct mm_decoded_insn mminsn = { 0 };

	mminsn.micro_mips_mode = 1;

	/* This load never faults. */
	pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
	__get_user(halfword, pc16);
	pc16++;
	contpc = regs->cp0_epc + 2;
	word = ((unsigned int)halfword << 16);
	mminsn.pc_inc = 2;

	if (!mm_insn_16bit(halfword)) {
		__get_user(halfword, pc16);
		pc16++;
		contpc = regs->cp0_epc + 4;
		mminsn.pc_inc = 4;
		word |= halfword;
	}
	mminsn.insn = word;

	if (get_user(halfword, pc16))
		goto sigsegv;
	mminsn.next_pc_inc = 2;
	word = ((unsigned int)halfword << 16);

	if (!mm_insn_16bit(halfword)) {
		pc16++;
		if (get_user(halfword, pc16))
			goto sigsegv;
		mminsn.next_pc_inc = 4;
		word |= halfword;
	}
	mminsn.next_insn = word;

	mm_isBranchInstr(regs, mminsn, &contpc);

	regs->cp0_epc = contpc;

	return 0;

sigsegv:
	force_sig(SIGSEGV, current);
	return -EFAULT;
}

/*
 * Compute return address and emulate branch in MIPS16e mode after an
 * exception only. It does not handle compact branches/jumps and cannot
 * be used in interrupt context. (Compact branches/jumps do not cause
 * exceptions.)
 */
int __MIPS16e_compute_return_epc(struct pt_regs *regs)
{
	u16 __user *addr;
	union mips16e_instruction inst;
	u16 inst2;
	u32 fullinst;
	long epc;

	epc = regs->cp0_epc;

	/* Read the instruction. */
	addr = (u16 __user *)msk_isa16_mode(epc);
	if (__get_user(inst.full, addr)) {
		force_sig(SIGSEGV, current);
		return -EFAULT;
	}

	switch (inst.ri.opcode) {
	case MIPS16e_extend_op:
		regs->cp0_epc += 4;
		return 0;

		/*
		 *  JAL and JALX in MIPS16e mode
		 */
	case MIPS16e_jal_op:
		addr += 1;
		if (__get_user(inst2, addr)) {
			force_sig(SIGSEGV, current);
			return -EFAULT;
		}
		fullinst = ((unsigned)inst.full << 16) | inst2;
		regs->regs[31] = epc + 6;
		epc += 4;
		epc >>= 28;
		epc <<= 28;
		/*
		 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
		 *
		 * ......TARGET[15:0].................TARGET[20:16]...........
		 * ......TARGET[25:21]
		 */
		epc |=
		    ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
		    ((fullinst & 0x1f0000) << 7);
		if (!inst.jal.x)
			set_isa16_mode(epc);	/* Set ISA mode bit. */
		regs->cp0_epc = epc;
		return 0;

		/*
		 *  J(AL)R(C)
		 */
	case MIPS16e_rr_op:
		if (inst.rr.func == MIPS16e_jr_func) {

			if (inst.rr.ra)
				regs->cp0_epc = regs->regs[31];
			else
				regs->cp0_epc =
				    regs->regs[reg16to32[inst.rr.rx]];

			if (inst.rr.l) {
				if (inst.rr.nd)
					regs->regs[31] = epc + 2;
				else
					regs->regs[31] = epc + 4;
			}
			return 0;
		}
		break;
	}

	/*
	 * All other cases have no branch delay slot and are 16-bits.
	 * Branches do not cause an exception.
	 */
	regs->cp0_epc += 2;

	return 0;
}

/**
 * __compute_return_epc_for_insn - Computes the return address and do emulate
 *				    branch simulation, if required.
 *
 * @regs:	Pointer to pt_regs
 * @insn:	branch instruction to decode
 * @returns:	-EFAULT on error and forces SIGILL, and on success
 *		returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
 *		evaluating the branch.
 */
int __compute_return_epc_for_insn(struct pt_regs *regs,
				   union mips_instruction insn)
{
	unsigned int bit, fcr31, dspcontrol;
	long epc = regs->cp0_epc;
	int ret = 0;

	switch (insn.i_format.opcode) {
	/*
	 * jr and jalr are in r_format format.
	 */
	case spec_op:
		switch (insn.r_format.func) {
		case jalr_op:
			regs->regs[insn.r_format.rd] = epc + 8;
			/* Fall through */
		case jr_op:
			regs->cp0_epc = regs->regs[insn.r_format.rs];
			break;
		}
		break;

	/*
	 * This group contains:
	 * bltz_op, bgez_op, bltzl_op, bgezl_op,
	 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
	 */
	case bcond_op:
		switch (insn.i_format.rt) {
		case bltz_op:
		case bltzl_op:
			if ((long)regs->regs[insn.i_format.rs] < 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bltzl_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bgez_op:
		case bgezl_op:
			if ((long)regs->regs[insn.i_format.rs] >= 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bgezl_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bltzal_op:
		case bltzall_op:
			regs->regs[31] = epc + 8;
			if ((long)regs->regs[insn.i_format.rs] < 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bltzall_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bgezal_op:
		case bgezall_op:
			regs->regs[31] = epc + 8;
			if ((long)regs->regs[insn.i_format.rs] >= 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bgezall_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bposge32_op:
			if (!cpu_has_dsp)
				goto sigill;

			dspcontrol = rddsp(0x01);

			if (dspcontrol >= 32) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;
		}
		break;

	/*
	 * These are unconditional and in j_format.
	 */
	case jalx_op:
	case jal_op:
		regs->regs[31] = regs->cp0_epc + 8;
	case j_op:
		epc += 4;
		epc >>= 28;
		epc <<= 28;
		epc |= (insn.j_format.target << 2);
		regs->cp0_epc = epc;
		if (insn.i_format.opcode == jalx_op)
			set_isa16_mode(regs->cp0_epc);
		break;

	/*
	 * These are conditional and in i_format.
	 */
	case beq_op:
	case beql_op:
		if (regs->regs[insn.i_format.rs] ==
		    regs->regs[insn.i_format.rt]) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.rt == beql_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	case bne_op:
	case bnel_op:
		if (regs->regs[insn.i_format.rs] !=
		    regs->regs[insn.i_format.rt]) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.rt == bnel_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	case blez_op: /* not really i_format */
	case blezl_op:
		/* rt field assumed to be zero */
		if ((long)regs->regs[insn.i_format.rs] <= 0) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.rt == bnel_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	case bgtz_op:
	case bgtzl_op:
		/* rt field assumed to be zero */
		if ((long)regs->regs[insn.i_format.rs] > 0) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.rt == bnel_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	/*
	 * And now the FPA/cp1 branch instructions.
	 */
	case cop1_op:
		preempt_disable();
		if (is_fpu_owner())
			asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
		else
			fcr31 = current->thread.fpu.fcr31;
		preempt_enable();

		bit = (insn.i_format.rt >> 2);
		bit += (bit != 0);
		bit += 23;
		switch (insn.i_format.rt & 3) {
		case 0: /* bc1f */
		case 2: /* bc1fl */
			if (~fcr31 & (1 << bit)) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == 2)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case 1: /* bc1t */
		case 3: /* bc1tl */
			if (fcr31 & (1 << bit)) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == 3)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;
		}
		break;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	case lwc2_op: /* This is bbit0 on Octeon */
		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
		     == 0)
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
	case ldc2_op: /* This is bbit032 on Octeon */
		if ((regs->regs[insn.i_format.rs] &
		    (1ull<<(insn.i_format.rt+32))) == 0)
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
	case swc2_op: /* This is bbit1 on Octeon */
		if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
	case sdc2_op: /* This is bbit132 on Octeon */
		if (regs->regs[insn.i_format.rs] &
		    (1ull<<(insn.i_format.rt+32)))
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
#endif
	}

	return ret;

sigill:
	pr_info("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
		current->comm);
	force_sig(SIGILL, current);
	return -EFAULT;
}
EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);

int __compute_return_epc(struct pt_regs *regs)
{
	unsigned int __user *addr;
	long epc;
	union mips_instruction insn;

	epc = regs->cp0_epc;
	if (epc & 3)
		goto unaligned;

	/*
	 * Read the instruction
	 */
	addr = (unsigned int __user *) epc;
	if (__get_user(insn.word, addr)) {
		force_sig(SIGSEGV, current);
		return -EFAULT;
	}

	return __compute_return_epc_for_insn(regs, insn);

unaligned:
	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
	force_sig(SIGBUS, current);
	return -EFAULT;

}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
	7	* Copyright (C) 2001 MIPS Technologies, Inc.
	8	*/
	9	#include <linux/kernel.h>
	10	#include <linux/sched.h>
	11	#include <linux/signal.h>
d8d4e3ae	12	#include <linux/module.h>
1da177e4 LT	13	#include <asm/branch.h>
	14	#include <asm/cpu.h>
	15	#include <asm/cpu-features.h>
1d74f6bc	16	#include <asm/fpu.h>
fb6883e5	17	#include <asm/fpu_emulator.h>
1da177e4 LT	18	#include <asm/inst.h>
	19	#include <asm/ptrace.h>
	20	#include <asm/uaccess.h>
	21
fb6883e5	22	/*
8508488f SH	23	* Calculate and return exception PC in case of branch delay slot
8508488f SH	24	* for microMIPS and MIPS16e. It does not clear the ISA mode bit.
fb6883e5 LY	25	*/
	26	int __isa_exception_epc(struct pt_regs *regs)
	27	{
fb6883e5	28	unsigned short inst;
8508488f	29	long epc = regs->cp0_epc;
fb6883e5 LY	30
	31	/* Calculate exception PC in branch delay slot. */
	32	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
	33	/* This should never happen because delay slot was checked. */
	34	force_sig(SIGSEGV, current);
	35	return epc;
	36	}
8508488f SH	37	if (cpu_has_mips16) {
	38	if (((union mips16e_instruction)inst).ri.opcode
	39	== MIPS16e_jal_op)
	40	epc += 4;
	41	else
	42	epc += 2;
	43	} else if (mm_insn_16bit(inst))
fb6883e5 LY	44	epc += 2;
	45	else
	46	epc += 4;
	47
	48	return epc;
	49	}
	50
	51	/*
	52	* Compute return address and emulate branch in microMIPS mode after an
	53	* exception only. It does not handle compact branches/jumps and cannot
	54	* be used in interrupt context. (Compact branches/jumps do not cause
	55	* exceptions.)
	56	*/
	57	int __microMIPS_compute_return_epc(struct pt_regs *regs)
	58	{
	59	u16 __user *pc16;
	60	u16 halfword;
	61	unsigned int word;
	62	unsigned long contpc;
	63	struct mm_decoded_insn mminsn = { 0 };
	64
	65	mminsn.micro_mips_mode = 1;
	66
	67	/* This load never faults. */
	68	pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
	69	__get_user(halfword, pc16);
	70	pc16++;
	71	contpc = regs->cp0_epc + 2;
	72	word = ((unsigned int)halfword << 16);
	73	mminsn.pc_inc = 2;
	74
	75	if (!mm_insn_16bit(halfword)) {
	76	__get_user(halfword, pc16);
	77	pc16++;
	78	contpc = regs->cp0_epc + 4;
	79	mminsn.pc_inc = 4;
	80	word \|= halfword;
	81	}
	82	mminsn.insn = word;
	83
	84	if (get_user(halfword, pc16))
	85	goto sigsegv;
	86	mminsn.next_pc_inc = 2;
	87	word = ((unsigned int)halfword << 16);
	88
	89	if (!mm_insn_16bit(halfword)) {
	90	pc16++;
	91	if (get_user(halfword, pc16))
	92	goto sigsegv;
	93	mminsn.next_pc_inc = 4;
	94	word \|= halfword;
	95	}
	96	mminsn.next_insn = word;
	97
	98	mm_isBranchInstr(regs, mminsn, &contpc);
	99
	100	regs->cp0_epc = contpc;
	101
	102	return 0;
	103
	104	sigsegv:
	105	force_sig(SIGSEGV, current);
	106	return -EFAULT;
	107	}
108
8508488f SH	109	/*
	110	* Compute return address and emulate branch in MIPS16e mode after an
	111	* exception only. It does not handle compact branches/jumps and cannot
	112	* be used in interrupt context. (Compact branches/jumps do not cause
	113	* exceptions.)
	114	*/
	115	int __MIPS16e_compute_return_epc(struct pt_regs *regs)
	116	{
	117	u16 __user *addr;
	118	union mips16e_instruction inst;
	119	u16 inst2;
	120	u32 fullinst;
	121	long epc;
	122
	123	epc = regs->cp0_epc;
	124
	125	/* Read the instruction. */
	126	addr = (u16 __user *)msk_isa16_mode(epc);
	127	if (__get_user(inst.full, addr)) {
	128	force_sig(SIGSEGV, current);
	129	return -EFAULT;
	130	}
	131
	132	switch (inst.ri.opcode) {
	133	case MIPS16e_extend_op:
	134	regs->cp0_epc += 4;
	135	return 0;
	136
	137	/*
	138	* JAL and JALX in MIPS16e mode
	139	*/
	140	case MIPS16e_jal_op:
	141	addr += 1;
	142	if (__get_user(inst2, addr)) {
	143	force_sig(SIGSEGV, current);
	144	return -EFAULT;
	145	}
	146	fullinst = ((unsigned)inst.full << 16) \| inst2;
	147	regs->regs[31] = epc + 6;
	148	epc += 4;
	149	epc >>= 28;
	150	epc <<= 28;
	151	/*
	152	* JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
	153	*
	154	* ......TARGET[15:0].................TARGET[20:16]...........
	155	* ......TARGET[25:21]
	156	*/
	157	epc \|=
	158	((fullinst & 0xffff) << 2) \| ((fullinst & 0x3e00000) >> 3) \|
	159	((fullinst & 0x1f0000) << 7);
	160	if (!inst.jal.x)
	161	set_isa16_mode(epc); /* Set ISA mode bit. */
	162	regs->cp0_epc = epc;
	163	return 0;
	164
	165	/*
	166	* J(AL)R(C)
	167	*/
	168	case MIPS16e_rr_op:
	169	if (inst.rr.func == MIPS16e_jr_func) {
	170
	171	if (inst.rr.ra)
	172	regs->cp0_epc = regs->regs[31];
173	else
174	regs->cp0_epc =
175	regs->regs[reg16to32[inst.rr.rx]];
176
177	if (inst.rr.l) {
178	if (inst.rr.nd)
179	regs->regs[31] = epc + 2;
180	else
181	regs->regs[31] = epc + 4;
182	}
183	return 0;
184	}
185	break;
186	}
187
188	/*
189	* All other cases have no branch delay slot and are 16-bits.
190	* Branches do not cause an exception.
191	*/
192	regs->cp0_epc += 2;
193
194	return 0;
195	}
196
d8d4e3ae MS	197	/**
	198	* __compute_return_epc_for_insn - Computes the return address and do emulate
	199	* branch simulation, if required.
	200	*
	201	* @regs: Pointer to pt_regs
	202	* @insn: branch instruction to decode
6c176369	203	* @returns: -EFAULT on error and forces SIGILL, and on success
d8d4e3ae MS	204	* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
d8d4e3ae MS	205	* evaluating the branch.
1da177e4	206	*/
d8d4e3ae MS	207	int __compute_return_epc_for_insn(struct pt_regs *regs,
d8d4e3ae MS	208	union mips_instruction insn)
1da177e4	209	{
5e0373b8	210	unsigned int bit, fcr31, dspcontrol;
d8d4e3ae MS	211	long epc = regs->cp0_epc;
d8d4e3ae MS	212	int ret = 0;
1da177e4	213
1da177e4 LT	214	switch (insn.i_format.opcode) {
	215	/*
	216	* jr and jalr are in r_format format.
	217	*/
	218	case spec_op:
	219	switch (insn.r_format.func) {
	220	case jalr_op:
	221	regs->regs[insn.r_format.rd] = epc + 8;
	222	/* Fall through */
	223	case jr_op:
	224	regs->cp0_epc = regs->regs[insn.r_format.rs];
	225	break;
	226	}
	227	break;
	228
	229	/*
	230	* This group contains:
	231	* bltz_op, bgez_op, bltzl_op, bgezl_op,
	232	* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
	233	*/
	234	case bcond_op:
	235	switch (insn.i_format.rt) {
70342287	236	case bltz_op:
1da177e4	237	case bltzl_op:
d8d4e3ae	238	if ((long)regs->regs[insn.i_format.rs] < 0) {
1da177e4	239	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	240	if (insn.i_format.rt == bltzl_op)
	241	ret = BRANCH_LIKELY_TAKEN;
	242	} else
1da177e4 LT	243	epc += 8;
	244	regs->cp0_epc = epc;
	245	break;
	246
	247	case bgez_op:
	248	case bgezl_op:
d8d4e3ae	249	if ((long)regs->regs[insn.i_format.rs] >= 0) {
1da177e4	250	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	251	if (insn.i_format.rt == bgezl_op)
	252	ret = BRANCH_LIKELY_TAKEN;
	253	} else
1da177e4 LT	254	epc += 8;
	255	regs->cp0_epc = epc;
	256	break;
	257
	258	case bltzal_op:
	259	case bltzall_op:
	260	regs->regs[31] = epc + 8;
d8d4e3ae	261	if ((long)regs->regs[insn.i_format.rs] < 0) {
1da177e4	262	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	263	if (insn.i_format.rt == bltzall_op)
	264	ret = BRANCH_LIKELY_TAKEN;
	265	} else
1da177e4 LT	266	epc += 8;
	267	regs->cp0_epc = epc;
	268	break;
	269
	270	case bgezal_op:
	271	case bgezall_op:
	272	regs->regs[31] = epc + 8;
d8d4e3ae	273	if ((long)regs->regs[insn.i_format.rs] >= 0) {
1da177e4	274	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	275	if (insn.i_format.rt == bgezall_op)
	276	ret = BRANCH_LIKELY_TAKEN;
	277	} else
1da177e4 LT	278	epc += 8;
	279	regs->cp0_epc = epc;
	280	break;
d8d4e3ae	281
e50c0a8f RB	282	case bposge32_op:
	283	if (!cpu_has_dsp)
	284	goto sigill;
	285
	286	dspcontrol = rddsp(0x01);
	287
	288	if (dspcontrol >= 32) {
	289	epc = epc + 4 + (insn.i_format.simmediate << 2);
	290	} else
	291	epc += 8;
	292	regs->cp0_epc = epc;
	293	break;
1da177e4 LT	294	}
	295	break;
	296
	297	/*
	298	* These are unconditional and in j_format.
	299	*/
6aa23d16	300	case jalx_op:
1da177e4 LT	301	case jal_op:
	302	regs->regs[31] = regs->cp0_epc + 8;
	303	case j_op:
	304	epc += 4;
	305	epc >>= 28;
	306	epc <<= 28;
	307	epc \|= (insn.j_format.target << 2);
	308	regs->cp0_epc = epc;
fb6883e5 LY	309	if (insn.i_format.opcode == jalx_op)
fb6883e5 LY	310	set_isa16_mode(regs->cp0_epc);
1da177e4 LT	311	break;
	312
	313	/*
	314	* These are conditional and in i_format.
	315	*/
	316	case beq_op:
	317	case beql_op:
	318	if (regs->regs[insn.i_format.rs] ==
d8d4e3ae	319	regs->regs[insn.i_format.rt]) {
1da177e4	320	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	321	if (insn.i_format.rt == beql_op)
	322	ret = BRANCH_LIKELY_TAKEN;
	323	} else
1da177e4 LT	324	epc += 8;
	325	regs->cp0_epc = epc;
	326	break;
	327
	328	case bne_op:
	329	case bnel_op:
	330	if (regs->regs[insn.i_format.rs] !=
d8d4e3ae	331	regs->regs[insn.i_format.rt]) {
1da177e4	332	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	333	if (insn.i_format.rt == bnel_op)
	334	ret = BRANCH_LIKELY_TAKEN;
	335	} else
1da177e4 LT	336	epc += 8;
	337	regs->cp0_epc = epc;
	338	break;
	339
	340	case blez_op: /* not really i_format */
	341	case blezl_op:
	342	/* rt field assumed to be zero */
d8d4e3ae	343	if ((long)regs->regs[insn.i_format.rs] <= 0) {
1da177e4	344	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	345	if (insn.i_format.rt == bnel_op)
	346	ret = BRANCH_LIKELY_TAKEN;
	347	} else
1da177e4 LT	348	epc += 8;
	349	regs->cp0_epc = epc;
	350	break;
	351
	352	case bgtz_op:
	353	case bgtzl_op:
	354	/* rt field assumed to be zero */
d8d4e3ae	355	if ((long)regs->regs[insn.i_format.rs] > 0) {
1da177e4	356	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	357	if (insn.i_format.rt == bnel_op)
	358	ret = BRANCH_LIKELY_TAKEN;
	359	} else
1da177e4 LT	360	epc += 8;
	361	regs->cp0_epc = epc;
	362	break;
	363
	364	/*
	365	* And now the FPA/cp1 branch instructions.
	366	*/
	367	case cop1_op:
1d74f6bc RB	368	preempt_disable();
1d74f6bc RB	369	if (is_fpu_owner())
1da177e4	370	asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
1d74f6bc	371	else
eae89076	372	fcr31 = current->thread.fpu.fcr31;
1d74f6bc RB	373	preempt_enable();
1d74f6bc RB	374
1da177e4 LT	375	bit = (insn.i_format.rt >> 2);
	376	bit += (bit != 0);
	377	bit += 23;
ee1cca1b	378	switch (insn.i_format.rt & 3) {
70342287 RB	379	case 0: /* bc1f */
70342287 RB	380	case 2: /* bc1fl */
d8d4e3ae	381	if (~fcr31 & (1 << bit)) {
1da177e4	382	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	383	if (insn.i_format.rt == 2)
	384	ret = BRANCH_LIKELY_TAKEN;
	385	} else
1da177e4 LT	386	epc += 8;
	387	regs->cp0_epc = epc;
	388	break;
	389
70342287 RB	390	case 1: /* bc1t */
70342287 RB	391	case 3: /* bc1tl */
d8d4e3ae	392	if (fcr31 & (1 << bit)) {
1da177e4	393	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	394	if (insn.i_format.rt == 3)
	395	ret = BRANCH_LIKELY_TAKEN;
	396	} else
1da177e4 LT	397	epc += 8;
	398	regs->cp0_epc = epc;
	399	break;
	400	}
	401	break;
126336f0 DD	402	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	403	case lwc2_op: /* This is bbit0 on Octeon */
	404	if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
	405	== 0)
	406	epc = epc + 4 + (insn.i_format.simmediate << 2);
	407	else
	408	epc += 8;
	409	regs->cp0_epc = epc;
	410	break;
	411	case ldc2_op: /* This is bbit032 on Octeon */
	412	if ((regs->regs[insn.i_format.rs] &
	413	(1ull<<(insn.i_format.rt+32))) == 0)
	414	epc = epc + 4 + (insn.i_format.simmediate << 2);
	415	else
	416	epc += 8;
	417	regs->cp0_epc = epc;
	418	break;
	419	case swc2_op: /* This is bbit1 on Octeon */
	420	if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
	421	epc = epc + 4 + (insn.i_format.simmediate << 2);
	422	else
	423	epc += 8;
	424	regs->cp0_epc = epc;
	425	break;
	426	case sdc2_op: /* This is bbit132 on Octeon */
	427	if (regs->regs[insn.i_format.rs] &
	428	(1ull<<(insn.i_format.rt+32)))
	429	epc = epc + 4 + (insn.i_format.simmediate << 2);
	430	else
	431	epc += 8;
	432	regs->cp0_epc = epc;
	433	break;
	434	#endif
1da177e4 LT	435	}
1da177e4 LT	436
d8d4e3ae	437	return ret;
1da177e4	438
d8d4e3ae	439	sigill:
6c176369 MR	440	pr_info("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
	441	current->comm);
	442	force_sig(SIGILL, current);
1da177e4	443	return -EFAULT;
d8d4e3ae MS	444	}
d8d4e3ae MS	445	EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
e50c0a8f	446
d8d4e3ae MS	447	int __compute_return_epc(struct pt_regs *regs)
	448	{
	449	unsigned int __user *addr;
	450	long epc;
	451	union mips_instruction insn;
	452
	453	epc = regs->cp0_epc;
	454	if (epc & 3)
	455	goto unaligned;
	456
	457	/*
	458	* Read the instruction
	459	*/
	460	addr = (unsigned int __user *) epc;
	461	if (__get_user(insn.word, addr)) {
	462	force_sig(SIGSEGV, current);
	463	return -EFAULT;
	464	}
	465
	466	return __compute_return_epc_for_insn(regs, insn);
	467
	468	unaligned:
	469	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
e50c0a8f RB	470	force_sig(SIGBUS, current);
e50c0a8f RB	471	return -EFAULT;
d8d4e3ae	472
1da177e4	473	}