Commit | Line | Data |
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382266ad CM |
1 | /* |
2 | * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support | |
3 | * | |
4 | * Copyright (C) 2007 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | #include <linux/init.h> | |
07620976 | 20 | #include <linux/spinlock.h> |
fced80c7 | 21 | #include <linux/io.h> |
382266ad CM |
22 | |
23 | #include <asm/cacheflush.h> | |
382266ad CM |
24 | #include <asm/hardware/cache-l2x0.h> |
25 | ||
26 | #define CACHE_LINE_SIZE 32 | |
27 | ||
28 | static void __iomem *l2x0_base; | |
bd31b859 | 29 | static DEFINE_RAW_SPINLOCK(l2x0_lock); |
64039be8 | 30 | static uint32_t l2x0_way_mask; /* Bitmask of active ways */ |
5ba70372 | 31 | static uint32_t l2x0_size; |
382266ad | 32 | |
9a6655e4 | 33 | static inline void cache_wait_way(void __iomem *reg, unsigned long mask) |
382266ad | 34 | { |
9a6655e4 | 35 | /* wait for cache operation by line or way to complete */ |
6775a558 | 36 | while (readl_relaxed(reg) & mask) |
382266ad CM |
37 | ; |
38 | } | |
39 | ||
9a6655e4 CM |
40 | #ifdef CONFIG_CACHE_PL310 |
41 | static inline void cache_wait(void __iomem *reg, unsigned long mask) | |
42 | { | |
43 | /* cache operations by line are atomic on PL310 */ | |
44 | } | |
45 | #else | |
46 | #define cache_wait cache_wait_way | |
47 | #endif | |
48 | ||
382266ad CM |
49 | static inline void cache_sync(void) |
50 | { | |
3d107434 | 51 | void __iomem *base = l2x0_base; |
885028e4 SK |
52 | |
53 | #ifdef CONFIG_ARM_ERRATA_753970 | |
54 | /* write to an unmmapped register */ | |
55 | writel_relaxed(0, base + L2X0_DUMMY_REG); | |
56 | #else | |
6775a558 | 57 | writel_relaxed(0, base + L2X0_CACHE_SYNC); |
885028e4 | 58 | #endif |
3d107434 | 59 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
382266ad CM |
60 | } |
61 | ||
424d6b14 SS |
62 | static inline void l2x0_clean_line(unsigned long addr) |
63 | { | |
64 | void __iomem *base = l2x0_base; | |
65 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | |
6775a558 | 66 | writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); |
424d6b14 SS |
67 | } |
68 | ||
69 | static inline void l2x0_inv_line(unsigned long addr) | |
70 | { | |
71 | void __iomem *base = l2x0_base; | |
72 | cache_wait(base + L2X0_INV_LINE_PA, 1); | |
6775a558 | 73 | writel_relaxed(addr, base + L2X0_INV_LINE_PA); |
424d6b14 SS |
74 | } |
75 | ||
2839e06c | 76 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
9e65582a | 77 | |
2839e06c SS |
78 | #define debug_writel(val) outer_cache.set_debug(val) |
79 | ||
80 | static void l2x0_set_debug(unsigned long val) | |
81 | { | |
82 | writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); | |
9e65582a | 83 | } |
2839e06c SS |
84 | #else |
85 | /* Optimised out for non-errata case */ | |
86 | static inline void debug_writel(unsigned long val) | |
87 | { | |
88 | } | |
89 | ||
90 | #define l2x0_set_debug NULL | |
91 | #endif | |
9e65582a | 92 | |
2839e06c | 93 | #ifdef CONFIG_PL310_ERRATA_588369 |
9e65582a SS |
94 | static inline void l2x0_flush_line(unsigned long addr) |
95 | { | |
96 | void __iomem *base = l2x0_base; | |
97 | ||
98 | /* Clean by PA followed by Invalidate by PA */ | |
99 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | |
6775a558 | 100 | writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); |
9e65582a | 101 | cache_wait(base + L2X0_INV_LINE_PA, 1); |
6775a558 | 102 | writel_relaxed(addr, base + L2X0_INV_LINE_PA); |
9e65582a SS |
103 | } |
104 | #else | |
105 | ||
424d6b14 SS |
106 | static inline void l2x0_flush_line(unsigned long addr) |
107 | { | |
108 | void __iomem *base = l2x0_base; | |
109 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
6775a558 | 110 | writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); |
424d6b14 | 111 | } |
9e65582a | 112 | #endif |
424d6b14 | 113 | |
23107c54 CM |
114 | static void l2x0_cache_sync(void) |
115 | { | |
116 | unsigned long flags; | |
117 | ||
bd31b859 | 118 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
23107c54 | 119 | cache_sync(); |
bd31b859 | 120 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
23107c54 CM |
121 | } |
122 | ||
38a8914f | 123 | static void __l2x0_flush_all(void) |
2fd86589 | 124 | { |
2839e06c | 125 | debug_writel(0x03); |
2fd86589 TG |
126 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); |
127 | cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); | |
128 | cache_sync(); | |
2839e06c | 129 | debug_writel(0x00); |
38a8914f WD |
130 | } |
131 | ||
132 | static void l2x0_flush_all(void) | |
133 | { | |
134 | unsigned long flags; | |
135 | ||
136 | /* clean all ways */ | |
bd31b859 | 137 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
38a8914f | 138 | __l2x0_flush_all(); |
bd31b859 | 139 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
2fd86589 TG |
140 | } |
141 | ||
444457c1 SS |
142 | static void l2x0_clean_all(void) |
143 | { | |
144 | unsigned long flags; | |
145 | ||
146 | /* clean all ways */ | |
bd31b859 | 147 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
444457c1 SS |
148 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); |
149 | cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); | |
150 | cache_sync(); | |
bd31b859 | 151 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
444457c1 SS |
152 | } |
153 | ||
2fd86589 | 154 | static void l2x0_inv_all(void) |
382266ad | 155 | { |
0eb948dd RK |
156 | unsigned long flags; |
157 | ||
382266ad | 158 | /* invalidate all ways */ |
bd31b859 | 159 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
2fd86589 TG |
160 | /* Invalidating when L2 is enabled is a nono */ |
161 | BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1); | |
6775a558 | 162 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); |
9a6655e4 | 163 | cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); |
382266ad | 164 | cache_sync(); |
bd31b859 | 165 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
166 | } |
167 | ||
168 | static void l2x0_inv_range(unsigned long start, unsigned long end) | |
169 | { | |
3d107434 | 170 | void __iomem *base = l2x0_base; |
0eb948dd | 171 | unsigned long flags; |
382266ad | 172 | |
bd31b859 | 173 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
4f6627ac RS |
174 | if (start & (CACHE_LINE_SIZE - 1)) { |
175 | start &= ~(CACHE_LINE_SIZE - 1); | |
9e65582a | 176 | debug_writel(0x03); |
424d6b14 | 177 | l2x0_flush_line(start); |
9e65582a | 178 | debug_writel(0x00); |
4f6627ac RS |
179 | start += CACHE_LINE_SIZE; |
180 | } | |
181 | ||
182 | if (end & (CACHE_LINE_SIZE - 1)) { | |
183 | end &= ~(CACHE_LINE_SIZE - 1); | |
9e65582a | 184 | debug_writel(0x03); |
424d6b14 | 185 | l2x0_flush_line(end); |
9e65582a | 186 | debug_writel(0x00); |
4f6627ac RS |
187 | } |
188 | ||
0eb948dd RK |
189 | while (start < end) { |
190 | unsigned long blk_end = start + min(end - start, 4096UL); | |
191 | ||
192 | while (start < blk_end) { | |
424d6b14 | 193 | l2x0_inv_line(start); |
0eb948dd RK |
194 | start += CACHE_LINE_SIZE; |
195 | } | |
196 | ||
197 | if (blk_end < end) { | |
bd31b859 TG |
198 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
199 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
0eb948dd RK |
200 | } |
201 | } | |
3d107434 | 202 | cache_wait(base + L2X0_INV_LINE_PA, 1); |
382266ad | 203 | cache_sync(); |
bd31b859 | 204 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
205 | } |
206 | ||
207 | static void l2x0_clean_range(unsigned long start, unsigned long end) | |
208 | { | |
3d107434 | 209 | void __iomem *base = l2x0_base; |
0eb948dd | 210 | unsigned long flags; |
382266ad | 211 | |
444457c1 SS |
212 | if ((end - start) >= l2x0_size) { |
213 | l2x0_clean_all(); | |
214 | return; | |
215 | } | |
216 | ||
bd31b859 | 217 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
382266ad | 218 | start &= ~(CACHE_LINE_SIZE - 1); |
0eb948dd RK |
219 | while (start < end) { |
220 | unsigned long blk_end = start + min(end - start, 4096UL); | |
221 | ||
222 | while (start < blk_end) { | |
424d6b14 | 223 | l2x0_clean_line(start); |
0eb948dd RK |
224 | start += CACHE_LINE_SIZE; |
225 | } | |
226 | ||
227 | if (blk_end < end) { | |
bd31b859 TG |
228 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
229 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
0eb948dd RK |
230 | } |
231 | } | |
3d107434 | 232 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); |
382266ad | 233 | cache_sync(); |
bd31b859 | 234 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
235 | } |
236 | ||
237 | static void l2x0_flush_range(unsigned long start, unsigned long end) | |
238 | { | |
3d107434 | 239 | void __iomem *base = l2x0_base; |
0eb948dd | 240 | unsigned long flags; |
382266ad | 241 | |
444457c1 SS |
242 | if ((end - start) >= l2x0_size) { |
243 | l2x0_flush_all(); | |
244 | return; | |
245 | } | |
246 | ||
bd31b859 | 247 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
382266ad | 248 | start &= ~(CACHE_LINE_SIZE - 1); |
0eb948dd RK |
249 | while (start < end) { |
250 | unsigned long blk_end = start + min(end - start, 4096UL); | |
251 | ||
9e65582a | 252 | debug_writel(0x03); |
0eb948dd | 253 | while (start < blk_end) { |
424d6b14 | 254 | l2x0_flush_line(start); |
0eb948dd RK |
255 | start += CACHE_LINE_SIZE; |
256 | } | |
9e65582a | 257 | debug_writel(0x00); |
0eb948dd RK |
258 | |
259 | if (blk_end < end) { | |
bd31b859 TG |
260 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
261 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
0eb948dd RK |
262 | } |
263 | } | |
3d107434 | 264 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); |
382266ad | 265 | cache_sync(); |
bd31b859 | 266 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
267 | } |
268 | ||
2fd86589 TG |
269 | static void l2x0_disable(void) |
270 | { | |
271 | unsigned long flags; | |
272 | ||
bd31b859 | 273 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
38a8914f WD |
274 | __l2x0_flush_all(); |
275 | writel_relaxed(0, l2x0_base + L2X0_CTRL); | |
276 | dsb(); | |
bd31b859 | 277 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
2fd86589 TG |
278 | } |
279 | ||
bac7e6ec LW |
280 | static void __init l2x0_unlock(__u32 cache_id) |
281 | { | |
282 | int lockregs; | |
283 | int i; | |
284 | ||
285 | if (cache_id == L2X0_CACHE_ID_PART_L310) | |
286 | lockregs = 8; | |
287 | else | |
288 | /* L210 and unknown types */ | |
289 | lockregs = 1; | |
290 | ||
291 | for (i = 0; i < lockregs; i++) { | |
292 | writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + | |
293 | i * L2X0_LOCKDOWN_STRIDE); | |
294 | writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + | |
295 | i * L2X0_LOCKDOWN_STRIDE); | |
296 | } | |
297 | } | |
298 | ||
382266ad CM |
299 | void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) |
300 | { | |
301 | __u32 aux; | |
64039be8 | 302 | __u32 cache_id; |
5ba70372 | 303 | __u32 way_size = 0; |
64039be8 JM |
304 | int ways; |
305 | const char *type; | |
382266ad CM |
306 | |
307 | l2x0_base = base; | |
308 | ||
6775a558 CM |
309 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); |
310 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | |
64039be8 | 311 | |
4082cfa7 SH |
312 | aux &= aux_mask; |
313 | aux |= aux_val; | |
314 | ||
64039be8 JM |
315 | /* Determine the number of ways */ |
316 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { | |
317 | case L2X0_CACHE_ID_PART_L310: | |
318 | if (aux & (1 << 16)) | |
319 | ways = 16; | |
320 | else | |
321 | ways = 8; | |
322 | type = "L310"; | |
323 | break; | |
324 | case L2X0_CACHE_ID_PART_L210: | |
325 | ways = (aux >> 13) & 0xf; | |
326 | type = "L210"; | |
327 | break; | |
328 | default: | |
329 | /* Assume unknown chips have 8 ways */ | |
330 | ways = 8; | |
331 | type = "L2x0 series"; | |
332 | break; | |
333 | } | |
334 | ||
335 | l2x0_way_mask = (1 << ways) - 1; | |
336 | ||
5ba70372 SS |
337 | /* |
338 | * L2 cache Size = Way size * Number of ways | |
339 | */ | |
340 | way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; | |
341 | way_size = 1 << (way_size + 3); | |
342 | l2x0_size = ways * way_size * SZ_1K; | |
343 | ||
48371cd3 SK |
344 | /* |
345 | * Check if l2x0 controller is already enabled. | |
346 | * If you are booting from non-secure mode | |
347 | * accessing the below registers will fault. | |
348 | */ | |
6775a558 | 349 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { |
bac7e6ec LW |
350 | /* Make sure that I&D is not locked down when starting */ |
351 | l2x0_unlock(cache_id); | |
382266ad | 352 | |
48371cd3 | 353 | /* l2x0 controller is disabled */ |
6775a558 | 354 | writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); |
382266ad | 355 | |
48371cd3 SK |
356 | l2x0_inv_all(); |
357 | ||
358 | /* enable L2X0 */ | |
6775a558 | 359 | writel_relaxed(1, l2x0_base + L2X0_CTRL); |
48371cd3 | 360 | } |
382266ad CM |
361 | |
362 | outer_cache.inv_range = l2x0_inv_range; | |
363 | outer_cache.clean_range = l2x0_clean_range; | |
364 | outer_cache.flush_range = l2x0_flush_range; | |
23107c54 | 365 | outer_cache.sync = l2x0_cache_sync; |
2fd86589 TG |
366 | outer_cache.flush_all = l2x0_flush_all; |
367 | outer_cache.inv_all = l2x0_inv_all; | |
368 | outer_cache.disable = l2x0_disable; | |
2839e06c | 369 | outer_cache.set_debug = l2x0_set_debug; |
382266ad | 370 | |
64039be8 | 371 | printk(KERN_INFO "%s cache controller enabled\n", type); |
5ba70372 SS |
372 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |
373 | ways, cache_id, aux, l2x0_size); | |
382266ad | 374 | } |