[GitHub/LineageOS/android_hardware_samsung_slsi_exynos.git] / libhwc / ExynosHWC.h

/*
 * Copyright (C) 2012 The Android Open Source Project
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef ANDROID_EXYNOS_HWC_H_
#define ANDROID_EXYNOS_HWC_H_
#include <errno.h>
#include <fcntl.h>
#include <math.h>
#include <poll.h>
#include <pthread.h>
#include <stdio.h>
#include <stdlib.h>

#include <sys/ioctl.h>
#include <sys/mman.h>
#include <sys/time.h>
#include <sys/resource.h>

#ifdef USES_VPP
#ifdef USES_VPP_V2
#include <decon_8890.h>
#else
#include <decon-fb.h>
#endif
#include "ExynosDisplayResourceManagerModule.h"
#else
#include <decon-fb.h>
#endif

#include <EGL/egl.h>

#define HWC_REMOVE_DEPRECATED_VERSIONS 1

#include <cutils/compiler.h>
#include <cutils/log.h>
#include <cutils/properties.h>
#include <hardware/gralloc.h>
#include <hardware/hardware.h>
#include <hardware/hwcomposer.h>
#include <hardware_legacy/uevent.h>
#include <utils/String8.h>
#include <utils/Vector.h>
#include <utils/Timers.h>

#include <sync/sync.h>

#include "gralloc_priv.h"
#ifndef USES_FIMC
#include "exynos_gscaler.h"
#else
#include "exynos_fimc.h"
#endif
#include "exynos_format.h"
#include "exynos_v4l2.h"
#include "s5p_tvout_v4l2.h"
#include "ExynosHWCModule.h"
#include "ExynosRect.h"
#include <linux/videodev2.h>

#ifdef USE_FB_PHY_LINEAR
const size_t NUM_HW_WIN_FB_PHY = 5;
#undef DUAL_VIDEO_OVERLAY_SUPPORT
#define G2D_COMPOSITION
#ifdef G2D_COMPOSITION
#define USE_FIMG2D_API
#endif
#endif

#if defined(DUAL_VIDEO_OVERLAY_SUPPORT)
#define MAX_VIDEO_LAYERS 2
#else
#define MAX_VIDEO_LAYERS 1
#endif

#ifndef FIMD_WORD_SIZE_BYTES
#define FIMD_WORD_SIZE_BYTES   8
#endif

#ifndef FIMD_BURSTLEN
#define FIMD_BURSTLEN   16
#endif

#ifndef DRM_FIMD_BURSTLEN
#define DRM_FIMD_BURSTLEN   8
#endif

#ifndef FIMD_ADDED_BURSTLEN_BYTES
#define FIMD_ADDED_BURSTLEN_BYTES     0
#endif

#ifndef FIMD_TOTAL_BW_LIMIT
#define FIMD_TOTAL_BW_LIMIT (2560 * 1600 * 5)
#endif

#ifndef WINUPDATE_X_ALIGNMENT
#define WINUPDATE_X_ALIGNMENT (8)
#endif

#ifndef WINUPDATE_W_ALIGNMENT
#define WINUPDATE_W_ALIGNMENT (8)
#endif

#ifndef WINUPDATE_DSC_H_SLICE_NUM
#define WINUPDATE_DSC_H_SLICE_NUM (4)
#endif

#ifndef WINUPDATE_DSC_Y_SLICE_SIZE
#define WINUPDATE_DSC_Y_SLICE_SIZE (64)
#endif

#ifndef WINUPDATE_THRESHOLD
#define WINUPDATE_THRESHOLD (75)
#endif

#ifndef WINUPDATE_MIN_HEIGHT
#define WINUPDATE_MIN_HEIGHT (1)
#endif

#define MEDIA_PROCESSOR_GSC  0
#define MEDIA_PROCESSOR_FIMC 1
#define MEDIA_PROCESSOR_G2D  2

#ifdef USES_FIMC
#define DEFAULT_MEDIA_PROCESSOR MEDIA_PROCESSOR_FIMC
#else
#define DEFAULT_MEDIA_PROCESSOR MEDIA_PROCESSOR_GSC
#endif

#ifdef NUM_AVAILABLE_HW_WINDOWS
/*
 * NUM_AVAILABLE_HW_WINDOWS can be optionally provided by
 * soc specific header file which is generally present at
 * $SoC\libhwcmodule\ExynosHWCModule.h. This is useful when
 * same display controller driver is used by SoCs having
 * different number of windows.
 * S3C_FB_MAX_WIN: max number of hardware windows supported
 * by the display controller driver.
 * NUM_AVAILABLE_HW_WINDOWS: max windows in the given SoC.
 */
const size_t NUM_HW_WINDOWS = NUM_AVAILABLE_HW_WINDOWS;
#else
#ifdef USES_VPP
const size_t NUM_HW_WINDOWS = MAX_DECON_WIN;
#else
const size_t NUM_HW_WINDOWS = S3C_FB_MAX_WIN;
#endif
#endif

#ifndef HWC_VERSION
#define HWC_VERSION HWC_DEVICE_API_VERSION_1_3
#endif

#ifndef IDMA_SECURE
#define IDMA_SECURE IDMA_G2
#endif

const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1;

#ifndef FIMD_BW_OVERLAP_CHECK
const size_t MAX_NUM_FIMD_DMA_CH = 2;
const int FIMD_DMA_CH_IDX[S3C_FB_MAX_WIN] = {0, 1, 1, 1, 0};
#endif

#define MAX_DEV_NAME 128
#ifndef VSYNC_DEV_PREFIX
#define VSYNC_DEV_PREFIX ""
#endif
#ifndef VSYNC_DEV_MIDDLE
#define VSYNC_DEV_MIDDLE ""
#endif

#ifdef TRY_SECOND_VSYNC_DEV
#ifndef VSYNC_DEV_NAME2
#define VSYNC_DEV_NAME2 ""
#endif
#ifndef VSYNC_DEV_MIDDLE2
#define VSYNC_DEV_MIDDLE2 ""
#endif
#endif

#ifdef USES_VPP
#ifndef MPP_VPP_G
#define MPP_VPP_G       10
const uint32_t VPP_ASSIGN_ORDER[] = {MPP_VG, MPP_VGR};
#else
const uint32_t VPP_ASSIGN_ORDER[] = {MPP_VPP_G, MPP_VG, MPP_VGR};
#endif
#endif

const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) /
        sizeof(AVAILABLE_GSC_UNITS[0]);

const size_t BURSTLEN_BYTES = FIMD_BURSTLEN * FIMD_WORD_SIZE_BYTES + FIMD_ADDED_BURSTLEN_BYTES;
const size_t DRM_BURSTLEN_BYTES = DRM_FIMD_BURSTLEN * FIMD_WORD_SIZE_BYTES + FIMD_ADDED_BURSTLEN_BYTES;
#if defined(NOT_USE_TRIPLE_BUFFER)
const size_t NUM_HDMI_BUFFERS = 4;
#else
const size_t NUM_HDMI_BUFFERS = 3;
#endif

#define NUM_VIRT_OVER   5

#define NUM_VIRT_OVER_HDMI 5

#define HWC_PAGE_MISS_TH  5

#define S3D_ERROR -1
#ifndef HDMI_INCAPABLE
#define HDMI_PRESET_DEFAULT V4L2_DV_1080P60
#else
#define HDMI_PRESET_DEFAULT 0
#endif
#define HDMI_PRESET_ERROR -1

#define HWC_FIMD_BW_TH  1   /* valid range 1 to 5 */
#define HWC_FPS_TH          5    /* valid range 1 to 60 */
#define VSYNC_INTERVAL (1000000000.0 / 60)
#define NUM_CONFIG_STABLE   10

#define OTF_SWITCH_THRESHOLD 2

#ifndef HLOG_CODE
#define HLOG_CODE 0
#endif

extern int hwcDebug;

inline bool hwcPrintDebugMessages()
{
    return hwcDebug & (1 << HLOG_CODE);
}

#if defined(DISABLE_HWC_DEBUG)
#define HLOGD(...)
#define HLOGV(...)
#define HLOGE(...)
#else
#define HLOGD(...) \
    if (hwcPrintDebugMessages()) \
        ALOGD(__VA_ARGS__);
#define HLOGV(...) \
    if (hwcPrintDebugMessages()) \
        ALOGV(__VA_ARGS__);
#define HLOGE(...) \
    if (hwcPrintDebugMessages()) \
        ALOGE(__VA_ARGS__);
#endif

typedef enum _COMPOS_MODE_SWITCH {
    NO_MODE_SWITCH,
    HWC_2_GLES = 1,
    GLES_2_HWC,
} HWC_COMPOS_MODE_SWITCH;

struct exynos5_hwc_composer_device_1_t;

typedef struct {
    uint32_t x;
    uint32_t y;
    uint32_t w;
    uint32_t h;
    uint32_t fw;
    uint32_t fh;
    uint32_t format;
    uint32_t rot;
    uint32_t cacheable;
    uint32_t drmMode;
    uint32_t index;
} video_layer_config;

struct exynos5_gsc_map_t {
    enum {
        GSC_NONE = 0,
        GSC_M2M,
        // TODO: GSC_LOCAL_PATH
        GSC_LOCAL,
    } mode;
    int idx;
};

struct exynos5_hwc_post_data_t {
    int                 overlay_map[NUM_HW_WINDOWS];
    exynos5_gsc_map_t   gsc_map[NUM_HW_WINDOWS];
    size_t              fb_window;
};

const size_t NUM_GSC_DST_BUFS = 3;
const size_t NUM_DRM_GSC_DST_BUFS = 2;
struct exynos5_gsc_data_t {
    void            *gsc;
    exynos_mpp_img  src_cfg;
    exynos_mpp_img  mid_cfg;
    exynos_mpp_img  dst_cfg;
    buffer_handle_t dst_buf[NUM_GSC_DST_BUFS];
    buffer_handle_t mid_buf[NUM_GSC_DST_BUFS];
    int             dst_buf_fence[NUM_GSC_DST_BUFS];
    int             mid_buf_fence[NUM_GSC_DST_BUFS];
    size_t          current_buf;
    int             gsc_mode;
    uint32_t    last_gsc_lay_hnd;
};

struct hdmi_layer_t {
    int     id;
    int     fd;
    bool    enabled;
    exynos_mpp_img  cfg;

    bool    streaming;
    size_t  current_buf;
    size_t  queued_buf;
};

struct hwc_ctrl_t {
    int     max_num_ovly;
    int     num_of_video_ovly;
    int     dynamic_recomp_mode;
    int     skip_static_layer_mode;
    int     dma_bw_balance_mode;
};

#if defined(G2D_COMPOSITION) || defined(USE_GRALLOC_FLAG_FOR_HDMI)
#include "FimgApi.h"
#endif

#ifdef G2D_COMPOSITION
struct exynos5_g2d_data_t {
     int    ovly_lay_idx[NUM_HW_WIN_FB_PHY];
     int    win_used[NUM_HW_WINDOWS];
};
#endif

class ExynosPrimaryDisplay;
class ExynosExternalDisplay;
class ExynosVirtualDisplay;
#if defined(USES_DUAL_DISPLAY)
class ExynosSecondaryDisplayModule;
#endif
#ifdef USES_VPP
class ExynosDisplayResourceManagerModule;
#endif

struct exynos5_hwc_composer_device_1_t {
    hwc_composer_device_1_t base;

    ExynosPrimaryDisplay    *primaryDisplay;
#if defined(USES_DUAL_DISPLAY)
    ExynosSecondaryDisplayModule    *secondaryDisplay;
#endif
    ExynosExternalDisplay    *externalDisplay;
    ExynosVirtualDisplay    *virtualDisplay;
    struct v4l2_rect        mVirtualDisplayRect;
#ifdef USES_VPP
    ExynosDisplayResourceManagerModule *mDisplayResourceManager;
#endif

    int                     vsync_fd;
    FILE                    *psrInfoFd;
    int                     psrMode;
    int                     panelType;

    const hwc_procs_t       *procs;
    pthread_t               vsync_thread;
    int                     force_gpu;

    bool hdmi_hpd;

    int mHdmiPreset;
    int mHdmiCurrentPreset;
    bool mHdmiResolutionChanged;
    bool mHdmiResolutionHandled;
    int mS3DMode;
    bool mUseSubtitles;
    int video_playback_status;

    int VsyncInterruptStatus;
    int CompModeSwitch;
    uint64_t LastUpdateTimeStamp;
    uint64_t LastModeSwitchTimeStamp;
    int totPixels;
    int incomingPixels;
    int updateCallCnt;
    pthread_t   update_stat_thread;
    int update_event_cnt;
    volatile bool update_stat_thread_flag;

    struct hwc_ctrl_t    hwc_ctrl;

    int mCecFd;
    int mCecPaddr;
    int mCecLaddr;

    bool                    force_mirror_mode;
    int                     ext_fbt_transform;                  /* HAL_TRANSFORM_ROT_XXX */
    bool                    external_display_pause;
    bool                    local_external_display_pause;

    bool notifyPSRExit;
    bool allowOTF;
    int setCount;
    bool debugMessages;
};

void exynos5_create_update_stat_thread(struct exynos5_hwc_composer_device_1_t *dev);

enum {
    OTF_OFF = 0,
    OTF_RUNNING,
    OTF_TO_M2M,
    SEC_M2M,
};

enum {
    S3D_MODE_DISABLED = 0,
    S3D_MODE_READY,
    S3D_MODE_RUNNING,
    S3D_MODE_STOPPING,
};

enum {
    S3D_FB = 0,
    S3D_SBS,
    S3D_TB,
    S3D_NONE,
};

enum {
    NO_DRM = 0,
    NORMAL_DRM,
    SECURE_DRM,
};

enum {
    PSR_NONE = 0,
    PSR_DP,
    PSR_MIPI,
};

enum {
    PANEL_LEGACY = 0,
    PANEL_DSC,
};
#endif
Commit	Line	Data
5763fb39 T	1	/*
	2	* Copyright (C) 2012 The Android Open Source Project
	3	*
	4	* Licensed under the Apache License, Version 2.0 (the "License");
	5	* you may not use this file except in compliance with the License.
	6	* You may obtain a copy of the License at
	7	*
	8	* http://www.apache.org/licenses/LICENSE-2.0
	9	*
	10	* Unless required by applicable law or agreed to in writing, software
	11	* distributed under the License is distributed on an "AS IS" BASIS,
	12	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	* See the License for the specific language governing permissions and
	14	* limitations under the License.
	15	*/
	16
	17	#ifndef ANDROID_EXYNOS_HWC_H_
	18	#define ANDROID_EXYNOS_HWC_H_
	19	#include <errno.h>
	20	#include <fcntl.h>
	21	#include <math.h>
	22	#include <poll.h>
	23	#include <pthread.h>
	24	#include <stdio.h>
	25	#include <stdlib.h>
	26
	27	#include <sys/ioctl.h>
	28	#include <sys/mman.h>
	29	#include <sys/time.h>
	30	#include <sys/resource.h>
	31
	32	#ifdef USES_VPP
	33	#ifdef USES_VPP_V2
	34	#include <decon_8890.h>
	35	#else
	36	#include <decon-fb.h>
	37	#endif
	38	#include "ExynosDisplayResourceManagerModule.h"
	39	#else
1f145ce6	40	#include <decon-fb.h>
5763fb39 T	41	#endif
	42
	43	#include <EGL/egl.h>
	44
	45	#define HWC_REMOVE_DEPRECATED_VERSIONS 1
	46
	47	#include <cutils/compiler.h>
	48	#include <cutils/log.h>
	49	#include <cutils/properties.h>
	50	#include <hardware/gralloc.h>
	51	#include <hardware/hardware.h>
	52	#include <hardware/hwcomposer.h>
	53	#include <hardware_legacy/uevent.h>
	54	#include <utils/String8.h>
	55	#include <utils/Vector.h>
	56	#include <utils/Timers.h>
	57
	58	#include <sync/sync.h>
	59
	60	#include "gralloc_priv.h"
	61	#ifndef USES_FIMC
	62	#include "exynos_gscaler.h"
	63	#else
	64	#include "exynos_fimc.h"
	65	#endif
	66	#include "exynos_format.h"
	67	#include "exynos_v4l2.h"
	68	#include "s5p_tvout_v4l2.h"
	69	#include "ExynosHWCModule.h"
	70	#include "ExynosRect.h"
a4e95a20	71	#include <linux/videodev2.h>
5763fb39 T	72
	73	#ifdef USE_FB_PHY_LINEAR
	74	const size_t NUM_HW_WIN_FB_PHY = 5;
	75	#undef DUAL_VIDEO_OVERLAY_SUPPORT
	76	#define G2D_COMPOSITION
	77	#ifdef G2D_COMPOSITION
	78	#define USE_FIMG2D_API
	79	#endif
	80	#endif
	81
	82	#if defined(DUAL_VIDEO_OVERLAY_SUPPORT)
	83	#define MAX_VIDEO_LAYERS 2
	84	#else
	85	#define MAX_VIDEO_LAYERS 1
	86	#endif
	87
	88	#ifndef FIMD_WORD_SIZE_BYTES
	89	#define FIMD_WORD_SIZE_BYTES 8
	90	#endif
	91
	92	#ifndef FIMD_BURSTLEN
	93	#define FIMD_BURSTLEN 16
	94	#endif
	95
	96	#ifndef DRM_FIMD_BURSTLEN
	97	#define DRM_FIMD_BURSTLEN 8
	98	#endif
	99
	100	#ifndef FIMD_ADDED_BURSTLEN_BYTES
	101	#define FIMD_ADDED_BURSTLEN_BYTES 0
	102	#endif
	103
	104	#ifndef FIMD_TOTAL_BW_LIMIT
	105	#define FIMD_TOTAL_BW_LIMIT (2560 * 1600 * 5)
	106	#endif
	107
	108	#ifndef WINUPDATE_X_ALIGNMENT
	109	#define WINUPDATE_X_ALIGNMENT (8)
	110	#endif
	111
	112	#ifndef WINUPDATE_W_ALIGNMENT
	113	#define WINUPDATE_W_ALIGNMENT (8)
	114	#endif
	115
	116	#ifndef WINUPDATE_DSC_H_SLICE_NUM
	117	#define WINUPDATE_DSC_H_SLICE_NUM (4)
	118	#endif
	119
	120	#ifndef WINUPDATE_DSC_Y_SLICE_SIZE
	121	#define WINUPDATE_DSC_Y_SLICE_SIZE (64)
	122	#endif
	123
	124	#ifndef WINUPDATE_THRESHOLD
	125	#define WINUPDATE_THRESHOLD (75)
	126	#endif
	127
	128	#ifndef WINUPDATE_MIN_HEIGHT
	129	#define WINUPDATE_MIN_HEIGHT (1)
	130	#endif
	131
	132	#define MEDIA_PROCESSOR_GSC 0
	133	#define MEDIA_PROCESSOR_FIMC 1
	134	#define MEDIA_PROCESSOR_G2D 2
	135
136	#ifdef USES_FIMC
137	#define DEFAULT_MEDIA_PROCESSOR MEDIA_PROCESSOR_FIMC
138	#else
139	#define DEFAULT_MEDIA_PROCESSOR MEDIA_PROCESSOR_GSC
140	#endif
141
142	#ifdef NUM_AVAILABLE_HW_WINDOWS
143	/*
144	* NUM_AVAILABLE_HW_WINDOWS can be optionally provided by
145	* soc specific header file which is generally present at
146	* $SoC\libhwcmodule\ExynosHWCModule.h. This is useful when
147	* same display controller driver is used by SoCs having
148	* different number of windows.
149	* S3C_FB_MAX_WIN: max number of hardware windows supported
150	* by the display controller driver.
151	* NUM_AVAILABLE_HW_WINDOWS: max windows in the given SoC.
152	*/
153	const size_t NUM_HW_WINDOWS = NUM_AVAILABLE_HW_WINDOWS;
154	#else
51e84723 CH	155	#ifdef USES_VPP
	156	const size_t NUM_HW_WINDOWS = MAX_DECON_WIN;
	157	#else
5763fb39 T	158	const size_t NUM_HW_WINDOWS = S3C_FB_MAX_WIN;
5763fb39 T	159	#endif
51e84723	160	#endif
5763fb39 T	161
	162	#ifndef HWC_VERSION
	163	#define HWC_VERSION HWC_DEVICE_API_VERSION_1_3
	164	#endif
	165
	166	#ifndef IDMA_SECURE
	167	#define IDMA_SECURE IDMA_G2
	168	#endif
	169
	170	const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1;
	171
	172	#ifndef FIMD_BW_OVERLAP_CHECK
	173	const size_t MAX_NUM_FIMD_DMA_CH = 2;
	174	const int FIMD_DMA_CH_IDX[S3C_FB_MAX_WIN] = {0, 1, 1, 1, 0};
	175	#endif
	176
	177	#define MAX_DEV_NAME 128
	178	#ifndef VSYNC_DEV_PREFIX
	179	#define VSYNC_DEV_PREFIX ""
	180	#endif
	181	#ifndef VSYNC_DEV_MIDDLE
	182	#define VSYNC_DEV_MIDDLE ""
	183	#endif
	184
	185	#ifdef TRY_SECOND_VSYNC_DEV
	186	#ifndef VSYNC_DEV_NAME2
	187	#define VSYNC_DEV_NAME2 ""
	188	#endif
	189	#ifndef VSYNC_DEV_MIDDLE2
	190	#define VSYNC_DEV_MIDDLE2 ""
	191	#endif
	192	#endif
	193
	194	#ifdef USES_VPP
	195	#ifndef MPP_VPP_G
	196	#define MPP_VPP_G 10
	197	const uint32_t VPP_ASSIGN_ORDER[] = {MPP_VG, MPP_VGR};
	198	#else
	199	const uint32_t VPP_ASSIGN_ORDER[] = {MPP_VPP_G, MPP_VG, MPP_VGR};
	200	#endif
	201	#endif
	202
	203	const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) /
	204	sizeof(AVAILABLE_GSC_UNITS[0]);
	205
	206	const size_t BURSTLEN_BYTES = FIMD_BURSTLEN * FIMD_WORD_SIZE_BYTES + FIMD_ADDED_BURSTLEN_BYTES;
	207	const size_t DRM_BURSTLEN_BYTES = DRM_FIMD_BURSTLEN * FIMD_WORD_SIZE_BYTES + FIMD_ADDED_BURSTLEN_BYTES;
	208	#if defined(NOT_USE_TRIPLE_BUFFER)
	209	const size_t NUM_HDMI_BUFFERS = 4;
	210	#else
	211	const size_t NUM_HDMI_BUFFERS = 3;
	212	#endif
	213
	214	#define NUM_VIRT_OVER 5
	215
	216	#define NUM_VIRT_OVER_HDMI 5
	217
	218	#define HWC_PAGE_MISS_TH 5
	219
	220	#define S3D_ERROR -1
	221	#ifndef HDMI_INCAPABLE
	222	#define HDMI_PRESET_DEFAULT V4L2_DV_1080P60
	223	#else
	224	#define HDMI_PRESET_DEFAULT 0
225	#endif
226	#define HDMI_PRESET_ERROR -1
227
228	#define HWC_FIMD_BW_TH 1 /* valid range 1 to 5 */
229	#define HWC_FPS_TH 5 /* valid range 1 to 60 */
230	#define VSYNC_INTERVAL (1000000000.0 / 60)
231	#define NUM_CONFIG_STABLE 10
232
233	#define OTF_SWITCH_THRESHOLD 2
234
235	#ifndef HLOG_CODE
236	#define HLOG_CODE 0
237	#endif
238
239	extern int hwcDebug;
240
241	inline bool hwcPrintDebugMessages()
242	{
243	return hwcDebug & (1 << HLOG_CODE);
244	}
245
246	#if defined(DISABLE_HWC_DEBUG)
247	#define HLOGD(...)
248	#define HLOGV(...)
249	#define HLOGE(...)
250	#else
251	#define HLOGD(...) \
252	if (hwcPrintDebugMessages()) \
253	ALOGD(__VA_ARGS__);
254	#define HLOGV(...) \
255	if (hwcPrintDebugMessages()) \
256	ALOGV(__VA_ARGS__);
257	#define HLOGE(...) \
258	if (hwcPrintDebugMessages()) \
259	ALOGE(__VA_ARGS__);
260	#endif
261
262	typedef enum _COMPOS_MODE_SWITCH {
263	NO_MODE_SWITCH,
264	HWC_2_GLES = 1,
265	GLES_2_HWC,
266	} HWC_COMPOS_MODE_SWITCH;
267
268	struct exynos5_hwc_composer_device_1_t;
269
270	typedef struct {
271	uint32_t x;
272	uint32_t y;
273	uint32_t w;
274	uint32_t h;
275	uint32_t fw;
276	uint32_t fh;
277	uint32_t format;
278	uint32_t rot;
279	uint32_t cacheable;
280	uint32_t drmMode;
281	uint32_t index;
282	} video_layer_config;
283
284	struct exynos5_gsc_map_t {
285	enum {
286	GSC_NONE = 0,
287	GSC_M2M,
288	// TODO: GSC_LOCAL_PATH
289	GSC_LOCAL,
290	} mode;
291	int idx;
292	};
293
294	struct exynos5_hwc_post_data_t {
295	int overlay_map[NUM_HW_WINDOWS];
296	exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS];
297	size_t fb_window;
298	};
299
300	const size_t NUM_GSC_DST_BUFS = 3;
301	const size_t NUM_DRM_GSC_DST_BUFS = 2;
302	struct exynos5_gsc_data_t {
303	void *gsc;
304	exynos_mpp_img src_cfg;
305	exynos_mpp_img mid_cfg;
306	exynos_mpp_img dst_cfg;
307	buffer_handle_t dst_buf[NUM_GSC_DST_BUFS];
308	buffer_handle_t mid_buf[NUM_GSC_DST_BUFS];
309	int dst_buf_fence[NUM_GSC_DST_BUFS];
310	int mid_buf_fence[NUM_GSC_DST_BUFS];
311	size_t current_buf;
312	int gsc_mode;
313	uint32_t last_gsc_lay_hnd;
314	};
315
316	struct hdmi_layer_t {
317	int id;
318	int fd;
319	bool enabled;
320	exynos_mpp_img cfg;
321
322	bool streaming;
323	size_t current_buf;
324	size_t queued_buf;
325	};
326
327	struct hwc_ctrl_t {
328	int max_num_ovly;
329	int num_of_video_ovly;
330	int dynamic_recomp_mode;
331	int skip_static_layer_mode;
332	int dma_bw_balance_mode;
333	};
334
335	#if defined(G2D_COMPOSITION) \|\| defined(USE_GRALLOC_FLAG_FOR_HDMI)
336	#include "FimgApi.h"
337	#endif
338
339	#ifdef G2D_COMPOSITION
340	struct exynos5_g2d_data_t {
341	int ovly_lay_idx[NUM_HW_WIN_FB_PHY];
342	int win_used[NUM_HW_WINDOWS];
343	};
344	#endif
345
346	class ExynosPrimaryDisplay;
347	class ExynosExternalDisplay;
348	class ExynosVirtualDisplay;
349	#if defined(USES_DUAL_DISPLAY)
350	class ExynosSecondaryDisplayModule;
351	#endif
352	#ifdef USES_VPP
353	class ExynosDisplayResourceManagerModule;
354	#endif
355
356	struct exynos5_hwc_composer_device_1_t {
357	hwc_composer_device_1_t base;
358
359	ExynosPrimaryDisplay *primaryDisplay;
360	#if defined(USES_DUAL_DISPLAY)
361	ExynosSecondaryDisplayModule *secondaryDisplay;
362	#endif
363	ExynosExternalDisplay *externalDisplay;
364	ExynosVirtualDisplay *virtualDisplay;
365	struct v4l2_rect mVirtualDisplayRect;
366	#ifdef USES_VPP
367	ExynosDisplayResourceManagerModule *mDisplayResourceManager;
368	#endif
369
370	int vsync_fd;
371	FILE *psrInfoFd;
372	int psrMode;
373	int panelType;
374
375	const hwc_procs_t *procs;
376	pthread_t vsync_thread;
377	int force_gpu;
378
379	bool hdmi_hpd;
380
381	int mHdmiPreset;
382	int mHdmiCurrentPreset;
383	bool mHdmiResolutionChanged;
384	bool mHdmiResolutionHandled;
385	int mS3DMode;
386	bool mUseSubtitles;
387	int video_playback_status;
388
389	int VsyncInterruptStatus;
390	int CompModeSwitch;
391	uint64_t LastUpdateTimeStamp;
392	uint64_t LastModeSwitchTimeStamp;
393	int totPixels;
394	int incomingPixels;
395	int updateCallCnt;
396	pthread_t update_stat_thread;
397	int update_event_cnt;
398	volatile bool update_stat_thread_flag;
399
400	struct hwc_ctrl_t hwc_ctrl;
401
402	int mCecFd;
403	int mCecPaddr;
404	int mCecLaddr;
405
406	bool force_mirror_mode;
407	int ext_fbt_transform; /* HAL_TRANSFORM_ROT_XXX */
408	bool external_display_pause;
409	bool local_external_display_pause;
410
411	bool notifyPSRExit;
412	bool allowOTF;
413	int setCount;
414	bool debugMessages;
415	};
416
417	void exynos5_create_update_stat_thread(struct exynos5_hwc_composer_device_1_t *dev);
418
419	enum {
420	OTF_OFF = 0,
421	OTF_RUNNING,
422	OTF_TO_M2M,
423	SEC_M2M,
424	};
425
426	enum {
427	S3D_MODE_DISABLED = 0,
428	S3D_MODE_READY,
429	S3D_MODE_RUNNING,
430	S3D_MODE_STOPPING,
431	};
432
433	enum {
434	S3D_FB = 0,
435	S3D_SBS,
436	S3D_TB,
437	S3D_NONE,
438	};
439
440	enum {
441	NO_DRM = 0,
442	NORMAL_DRM,
443	SECURE_DRM,
444	};
445
446	enum {
447	PSR_NONE = 0,
448	PSR_DP,
449	PSR_MIPI,
450	};
451
452	enum {
453	PANEL_LEGACY = 0,
454	PANEL_DSC,
455	};
456	#endif