projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_dhd-driver.git / blame
projects / GitHub / LineageOS / G12 / android_hardware_amlogic_kernel-modules_dhd-driver.git / blame
| Commit | Line | Data |
|---|---|---|
| 1b4a7c03 LJ |
1 | /* |
| 2 | * SiliconBackplane Chipcommon core hardware definitions. | |
| 3 | * | |
| 4 | * The chipcommon core provides chip identification, SB control, | |
| 5 | * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, | |
| 6 | * GPIO interface, extbus, and support for serial and parallel flashes. | |
| 7 | * | |
| 8 | * Copyright (C) 2020, Broadcom. | |
| 9 | * | |
| 10 | * Unless you and Broadcom execute a separate written software license | |
| 11 | * agreement governing use of this software, this software is licensed to you | |
| 12 | * under the terms of the GNU General Public License version 2 (the "GPL"), | |
| 13 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | |
| 14 | * following added to such license: | |
| 15 | * | |
| 16 | * As a special exception, the copyright holders of this software give you | |
| 17 | * permission to link this software with independent modules, and to copy and | |
| 18 | * distribute the resulting executable under terms of your choice, provided that | |
| 19 | * you also meet, for each linked independent module, the terms and conditions of | |
| 20 | * the license of that module. An independent module is a module which is not | |
| 21 | * derived from this software. The special exception does not apply to any | |
| 22 | * modifications of the software. | |
| 23 | * | |
| 24 | * | |
| 25 | * <<Broadcom-WL-IPTag/Dual:>> | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef _SBCHIPC_H | |
| 29 | #define _SBCHIPC_H | |
| 30 | ||
| 31 | #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) | |
| 32 | ||
| 33 | /* cpp contortions to concatenate w/arg prescan */ | |
| 34 | #ifndef PAD | |
| 35 | #define _PADLINE(line) pad ## line | |
| 36 | #define _XSTR(line) _PADLINE(line) | |
| 37 | #define PAD _XSTR(__LINE__) | |
| 38 | #endif /* PAD */ | |
| 39 | ||
| 40 | #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb))) | |
| 41 | #include <bcmutils.h> | |
| 42 | ||
| 43 | /** | |
| 44 | * In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the | |
| 45 | * 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to | |
| 46 | * [pmu|gci|sreng] register interface is deprecated and removed. These register blocks would instead | |
| 47 | * be assigned their respective chipc-specific address space and connected to the Always On | |
| 48 | * Backplane via the APB interface. | |
| 49 | */ | |
| 50 | typedef volatile struct { | |
| 51 | uint32 PAD[384]; | |
| 52 | uint32 pmucontrol; /* 0x600 */ | |
| 53 | uint32 pmucapabilities; /* 0x604 */ | |
| 54 | uint32 pmustatus; /* 0x608 */ | |
| 55 | uint32 res_state; /* 0x60C */ | |
| 56 | uint32 res_pending; /* 0x610 */ | |
| 57 | uint32 pmutimer; /* 0x614 */ | |
| 58 | uint32 min_res_mask; /* 0x618 */ | |
| 59 | uint32 max_res_mask; /* 0x61C */ | |
| 60 | uint32 res_table_sel; /* 0x620 */ | |
| 61 | uint32 res_dep_mask; | |
| 62 | uint32 res_updn_timer; | |
| 63 | uint32 res_timer; | |
| 64 | uint32 clkstretch; | |
| 65 | uint32 pmuwatchdog; | |
| 66 | uint32 gpiosel; /* 0x638, rev >= 1 */ | |
| 67 | uint32 gpioenable; /* 0x63c, rev >= 1 */ | |
| 68 | uint32 res_req_timer_sel; /* 0x640 */ | |
| 69 | uint32 res_req_timer; /* 0x644 */ | |
| 70 | uint32 res_req_mask; /* 0x648 */ | |
| 71 | uint32 core_cap_ext; /* 0x64C */ | |
| 72 | uint32 chipcontrol_addr; /* 0x650 */ | |
| 73 | uint32 chipcontrol_data; /* 0x654 */ | |
| 74 | uint32 regcontrol_addr; | |
| 75 | uint32 regcontrol_data; | |
| 76 | uint32 pllcontrol_addr; | |
| 77 | uint32 pllcontrol_data; | |
| 78 | uint32 pmustrapopt; /* 0x668, corerev >= 28 */ | |
| 79 | uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ | |
| 80 | uint32 retention_ctl; /* 0x670 */ | |
| 81 | uint32 ILPPeriod; /* 0x674 */ | |
| 82 | uint32 PAD[2]; | |
| 83 | uint32 retention_grpidx; /* 0x680 */ | |
| 84 | uint32 retention_grpctl; /* 0x684 */ | |
| 85 | uint32 mac_res_req_timer; /* 0x688 */ | |
| 86 | uint32 mac_res_req_mask; /* 0x68c */ | |
| 87 | uint32 spm_ctrl; /* 0x690 */ | |
| 88 | uint32 spm_cap; /* 0x694 */ | |
| 89 | uint32 spm_clk_ctrl; /* 0x698 */ | |
| 90 | uint32 int_hi_status; /* 0x69c */ | |
| 91 | uint32 int_lo_status; /* 0x6a0 */ | |
| 92 | uint32 mon_table_addr; /* 0x6a4 */ | |
| 93 | uint32 mon_ctrl_n; /* 0x6a8 */ | |
| 94 | uint32 mon_status_n; /* 0x6ac */ | |
| 95 | uint32 int_treshold_n; /* 0x6b0 */ | |
| 96 | uint32 watermarks_n; /* 0x6b4 */ | |
| 97 | uint32 spm_debug; /* 0x6b8 */ | |
| 98 | uint32 PAD[1]; | |
| 99 | uint32 vtrim_ctrl; /* 0x6c0 */ | |
| 100 | uint32 vtrim_status; /* 0x6c4 */ | |
| 101 | uint32 usec_timer; /* 0x6c8 */ | |
| 102 | uint32 usec_timer_frac; /* 0x6cc */ | |
| 103 | uint32 pcie_tpower_on; /* 0x6d0 */ | |
| 104 | uint32 pcie_tport_cnt; /* 0x6d4 */ | |
| 105 | uint32 pmucontrol_ext; /* 0x6d8 */ | |
| 106 | uint32 slowclkperiod; /* 0x6dc */ | |
| 107 | uint32 pmu_statstimer_addr; /* 0x6e0 */ | |
| 108 | uint32 pmu_statstimer_ctrl; /* 0x6e4 */ | |
| 109 | uint32 pmu_statstimer_N; /* 0x6e8 */ | |
| 110 | uint32 PAD[1]; | |
| 111 | uint32 mac_res_req_timer1; /* 0x6f0 */ | |
| 112 | uint32 mac_res_req_mask1; /* 0x6f4 */ | |
| 113 | uint32 PAD[2]; | |
| 114 | uint32 pmuintmask0; /* 0x700 */ | |
| 115 | uint32 pmuintmask1; /* 0x704 */ | |
| 116 | uint32 PAD[2]; | |
| 117 | uint32 fis_start_min_res_mask; /* 0x710 */ | |
| 118 | uint32 PAD[3]; | |
| 119 | uint32 rsrc_event0; /* 0x720 */ | |
| 120 | uint32 PAD[3]; | |
| 121 | uint32 slowtimer2; /* 0x730 */ | |
| 122 | uint32 slowtimerfrac2; /* 0x734 */ | |
| 123 | uint32 mac_res_req_timer2; /* 0x738 */ | |
| 124 | uint32 mac_res_req_mask2; /* 0x73c */ | |
| 125 | uint32 pmuintstatus; /* 0x740 */ | |
| 126 | uint32 extwakeupstatus; /* 0x744 */ | |
| 127 | uint32 watchdog_res_mask; /* 0x748 */ | |
| 128 | uint32 PAD[1]; /* 0x74C */ | |
| 129 | uint32 swscratch; /* 0x750 */ | |
| 130 | uint32 PAD[3]; /* 0x754-0x75C */ | |
| 131 | uint32 extwakemask0; /* 0x760 */ | |
| 132 | uint32 extwakemask1; /* 0x764 */ | |
| 133 | uint32 PAD[2]; /* 0x768-0x76C */ | |
| 134 | uint32 extwakereqmask[2]; /* 0x770-0x774 */ | |
| 135 | uint32 PAD[2]; /* 0x778-0x77C */ | |
| 136 | uint32 pmuintctrl0; /* 0x780 */ | |
| 137 | uint32 pmuintctrl1; /* 0x784 */ | |
| 138 | uint32 PAD[2]; | |
| 139 | uint32 extwakectrl[2]; /* 0x790 */ | |
| 140 | uint32 PAD[7]; | |
| 141 | uint32 fis_ctrl_status; /* 0x7b4 */ | |
| 142 | uint32 fis_min_res_mask; /* 0x7b8 */ | |
| 143 | uint32 PAD[1]; | |
| 144 | uint32 precision_tmr_ctrl_status; /* 0x7c0 */ | |
| 145 | uint32 precision_tmr_capture_low; /* 0x7c4 */ | |
| 146 | uint32 precision_tmr_capture_high; /* 0x7c8 */ | |
| 147 | uint32 precision_tmr_capture_frac; /* 0x7cc */ | |
| 148 | uint32 precision_tmr_running_low; /* 0x7d0 */ | |
| 149 | uint32 precision_tmr_running_high; /* 0x7d4 */ | |
| 150 | uint32 precision_tmr_running_frac; /* 0x7d8 */ | |
| 151 | uint32 PAD[3]; | |
| 152 | uint32 core_cap_ext1; /* 0x7e8 */ | |
| 153 | uint32 PAD[5]; | |
| 154 | uint32 rsrc_substate_ctl_sts; /* 0x800 */ | |
| 155 | uint32 rsrc_substate_trans_tmr; /* 0x804 */ | |
| 156 | uint32 PAD[2]; | |
| 157 | uint32 dvfs_ctrl1; /* 0x810 */ | |
| 158 | uint32 dvfs_ctrl2; /* 0x814 */ | |
| 159 | uint32 dvfs_voltage; /* 0x818 */ | |
| 160 | uint32 dvfs_status; /* 0x81c */ | |
| 161 | uint32 dvfs_core_table_address; /* 0x820 */ | |
| 162 | uint32 dvfs_core_ctrl; /* 0x824 */ | |
| 163 | } pmuregs_t; | |
| 164 | ||
| 165 | typedef struct eci_prerev35 { | |
| 166 | uint32 eci_output; | |
| 167 | uint32 eci_control; | |
| 168 | uint32 eci_inputlo; | |
| 169 | uint32 eci_inputmi; | |
| 170 | uint32 eci_inputhi; | |
| 171 | uint32 eci_inputintpolaritylo; | |
| 172 | uint32 eci_inputintpolaritymi; | |
| 173 | uint32 eci_inputintpolarityhi; | |
| 174 | uint32 eci_intmasklo; | |
| 175 | uint32 eci_intmaskmi; | |
| 176 | uint32 eci_intmaskhi; | |
| 177 | uint32 eci_eventlo; | |
| 178 | uint32 eci_eventmi; | |
| 179 | uint32 eci_eventhi; | |
| 180 | uint32 eci_eventmasklo; | |
| 181 | uint32 eci_eventmaskmi; | |
| 182 | uint32 eci_eventmaskhi; | |
| 183 | uint32 PAD[3]; | |
| 184 | } eci_prerev35_t; | |
| 185 | ||
| 186 | typedef struct eci_rev35 { | |
| 187 | uint32 eci_outputlo; | |
| 188 | uint32 eci_outputhi; | |
| 189 | uint32 eci_controllo; | |
| 190 | uint32 eci_controlhi; | |
| 191 | uint32 eci_inputlo; | |
| 192 | uint32 eci_inputhi; | |
| 193 | uint32 eci_inputintpolaritylo; | |
| 194 | uint32 eci_inputintpolarityhi; | |
| 195 | uint32 eci_intmasklo; | |
| 196 | uint32 eci_intmaskhi; | |
| 197 | uint32 eci_eventlo; | |
| 198 | uint32 eci_eventhi; | |
| 199 | uint32 eci_eventmasklo; | |
| 200 | uint32 eci_eventmaskhi; | |
| 201 | uint32 eci_auxtx; | |
| 202 | uint32 eci_auxrx; | |
| 203 | uint32 eci_datatag; | |
| 204 | uint32 eci_uartescvalue; | |
| 205 | uint32 eci_autobaudctr; | |
| 206 | uint32 eci_uartfifolevel; | |
| 207 | } eci_rev35_t; | |
| 208 | ||
| 209 | typedef struct flash_config { | |
| 210 | uint32 PAD[19]; | |
| 211 | /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */ | |
| 212 | uint32 flashstrconfig; | |
| 213 | } flash_config_t; | |
| 214 | ||
| 215 | typedef volatile struct { | |
| 216 | uint32 chipid; /* 0x0 */ | |
| 217 | uint32 capabilities; | |
| 218 | uint32 corecontrol; /* corerev >= 1 */ | |
| 219 | uint32 bist; | |
| 220 | ||
| 221 | /* OTP */ | |
| 222 | uint32 otpstatus; /* 0x10, corerev >= 10 */ | |
| 223 | uint32 otpcontrol; | |
| 224 | uint32 otpprog; | |
| 225 | uint32 otplayout; /* corerev >= 23 */ | |
| 226 | ||
| 227 | /* Interrupt control */ | |
| 228 | uint32 intstatus; /* 0x20 */ | |
| 229 | uint32 intmask; | |
| 230 | ||
| 231 | /* Chip specific regs */ | |
| 232 | uint32 chipcontrol; /* 0x28, rev >= 11 */ | |
| 233 | uint32 chipstatus; /* 0x2c, rev >= 11 */ | |
| 234 | ||
| 235 | /* Jtag Master */ | |
| 236 | uint32 jtagcmd; /* 0x30, rev >= 10 */ | |
| 237 | uint32 jtagir; | |
| 238 | uint32 jtagdr; | |
| 239 | uint32 jtagctrl; | |
| 240 | ||
| 241 | /* serial flash interface registers */ | |
| 242 | uint32 flashcontrol; /* 0x40 */ | |
| 243 | uint32 flashaddress; | |
| 244 | uint32 flashdata; | |
| 245 | uint32 otplayoutextension; /* rev >= 35 */ | |
| 246 | ||
| 247 | /* Silicon backplane configuration broadcast control */ | |
| 248 | uint32 broadcastaddress; /* 0x50 */ | |
| 249 | uint32 broadcastdata; | |
| 250 | ||
| 251 | /* gpio - cleared only by power-on-reset */ | |
| 252 | uint32 gpiopullup; /* 0x58, corerev >= 20 */ | |
| 253 | uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ | |
| 254 | uint32 gpioin; /* 0x60 */ | |
| 255 | uint32 gpioout; /* 0x64 */ | |
| 256 | uint32 gpioouten; /* 0x68 */ | |
| 257 | uint32 gpiocontrol; /* 0x6C */ | |
| 258 | uint32 gpiointpolarity; /* 0x70 */ | |
| 259 | uint32 gpiointmask; /* 0x74 */ | |
| 260 | ||
| 261 | /* GPIO events corerev >= 11 */ | |
| 262 | uint32 gpioevent; | |
| 263 | uint32 gpioeventintmask; | |
| 264 | ||
| 265 | /* Watchdog timer */ | |
| 266 | uint32 watchdog; /* 0x80 */ | |
| 267 | ||
| 268 | /* GPIO events corerev >= 11 */ | |
| 269 | uint32 gpioeventintpolarity; | |
| 270 | ||
| 271 | /* GPIO based LED powersave regs corerev >= 16 */ | |
| 272 | uint32 gpiotimerval; /* 0x88 */ /* Obsolete and unused now */ | |
| 273 | uint32 gpiotimeroutmask; /* Obsolete and unused now */ | |
| 274 | ||
| 275 | /* clock control */ | |
| 276 | uint32 clockcontrol_n; /* 0x90 */ | |
| 277 | uint32 clockcontrol_sb; /* aka m0 */ | |
| 278 | uint32 clockcontrol_pci; /* aka m1 */ | |
| 279 | uint32 clockcontrol_m2; /* mii/uart/mipsref */ | |
| 280 | uint32 clockcontrol_m3; /* cpu */ | |
| 281 | uint32 clkdiv; /* corerev >= 3 */ | |
| 282 | uint32 gpiodebugsel; /* corerev >= 28 */ | |
| 283 | uint32 capabilities_ext; /* 0xac */ | |
| 284 | ||
| 285 | /* pll delay registers (corerev >= 4) */ | |
| 286 | uint32 pll_on_delay; /* 0xb0 */ | |
| 287 | uint32 fref_sel_delay; | |
| 288 | uint32 slow_clk_ctl; /* 5 < corerev < 10 */ | |
| 289 | uint32 PAD; | |
| 290 | ||
| 291 | /* Instaclock registers (corerev >= 10) */ | |
| 292 | uint32 system_clk_ctl; /* 0xc0 */ | |
| 293 | uint32 clkstatestretch; | |
| 294 | uint32 PAD[2]; | |
| 295 | ||
| 296 | /* Indirect backplane access (corerev >= 22) */ | |
| 297 | uint32 bp_addrlow; /* 0xd0 */ | |
| 298 | uint32 bp_addrhigh; | |
| 299 | uint32 bp_data; | |
| 300 | uint32 PAD; | |
| 301 | uint32 bp_indaccess; | |
| 302 | /* SPI registers, corerev >= 37 */ | |
| 303 | uint32 gsioctrl; | |
| 304 | uint32 gsioaddress; | |
| 305 | uint32 gsiodata; | |
| 306 | ||
| 307 | /* More clock dividers (corerev >= 32) */ | |
| 308 | uint32 clkdiv2; | |
| 309 | /* FAB ID (corerev >= 40) */ | |
| 310 | uint32 otpcontrol1; | |
| 311 | uint32 fabid; /* 0xf8 */ | |
| 312 | ||
| 313 | /* In AI chips, pointer to erom */ | |
| 314 | uint32 eromptr; /* 0xfc */ | |
| 315 | ||
| 316 | /* ExtBus control registers (corerev >= 3) */ | |
| 317 | uint32 pcmcia_config; /* 0x100 */ | |
| 318 | uint32 pcmcia_memwait; | |
| 319 | uint32 pcmcia_attrwait; | |
| 320 | uint32 pcmcia_iowait; | |
| 321 | uint32 ide_config; | |
| 322 | uint32 ide_memwait; | |
| 323 | uint32 ide_attrwait; | |
| 324 | uint32 ide_iowait; | |
| 325 | uint32 prog_config; | |
| 326 | uint32 prog_waitcount; | |
| 327 | uint32 flash_config; | |
| 328 | uint32 flash_waitcount; | |
| 329 | uint32 SECI_config; /* 0x130 SECI configuration */ | |
| 330 | uint32 SECI_status; | |
| 331 | uint32 SECI_statusmask; | |
| 332 | uint32 SECI_rxnibchanged; | |
| 333 | ||
| 334 | uint32 PAD[20]; | |
| 335 | ||
| 336 | /* SROM interface (corerev >= 32) */ | |
| 337 | uint32 sromcontrol; /* 0x190 */ | |
| 338 | uint32 sromaddress; | |
| 339 | uint32 sromdata; | |
| 340 | uint32 PAD[1]; /* 0x19C */ | |
| 341 | /* NAND flash registers for BCM4706 (corerev = 31) */ | |
| 342 | uint32 nflashctrl; /* 0x1a0 */ | |
| 343 | uint32 nflashconf; | |
| 344 | uint32 nflashcoladdr; | |
| 345 | uint32 nflashrowaddr; | |
| 346 | uint32 nflashdata; | |
| 347 | uint32 nflashwaitcnt0; /* 0x1b4 */ | |
| 348 | uint32 PAD[2]; | |
| 349 | ||
| 350 | uint32 seci_uart_data; /* 0x1C0 */ | |
| 351 | uint32 seci_uart_bauddiv; | |
| 352 | uint32 seci_uart_fcr; | |
| 353 | uint32 seci_uart_lcr; | |
| 354 | uint32 seci_uart_mcr; | |
| 355 | uint32 seci_uart_lsr; | |
| 356 | uint32 seci_uart_msr; | |
| 357 | uint32 seci_uart_baudadj; | |
| 358 | /* Clock control and hardware workarounds (corerev >= 20) */ | |
| 359 | uint32 clk_ctl_st; /* 0x1e0 */ | |
| 360 | uint32 hw_war; | |
| 361 | uint32 powerctl; /* 0x1e8 */ | |
| 362 | uint32 powerctl2; /* 0x1ec */ | |
| 363 | uint32 PAD[68]; | |
| 364 | ||
| 365 | /* UARTs */ | |
| 366 | uint8 uart0data; /* 0x300 */ | |
| 367 | uint8 uart0imr; | |
| 368 | uint8 uart0fcr; | |
| 369 | uint8 uart0lcr; | |
| 370 | uint8 uart0mcr; | |
| 371 | uint8 uart0lsr; | |
| 372 | uint8 uart0msr; | |
| 373 | uint8 uart0scratch; | |
| 374 | uint8 PAD[184]; /* corerev >= 65 */ | |
| 375 | uint32 rng_ctrl_0; /* 0x3c0 */ | |
| 376 | uint32 rng_rng_soft_reset; /* 0x3c4 */ | |
| 377 | uint32 rng_rbg_soft_reset; /* 0x3c8 */ | |
| 378 | uint32 rng_total_bit_cnt; /* 0x3cc */ | |
| 379 | uint32 rng_total_bit_thrshld; /* 0x3d0 */ | |
| 380 | uint32 rng_rev_id; /* 0x3d4 */ | |
| 381 | uint32 rng_int_status_0; /* 0x3d8 */ | |
| 382 | uint32 rng_int_enable_0; /* 0x3dc */ | |
| 383 | uint32 rng_fifo_data; /* 0x3e0 */ | |
| 384 | uint32 rng_fifo_cnt; /* 0x3e4 */ | |
| 385 | uint8 PAD[24]; /* corerev >= 65 */ | |
| 386 | ||
| 387 | uint8 uart1data; /* 0x400 */ | |
| 388 | uint8 uart1imr; | |
| 389 | uint8 uart1fcr; | |
| 390 | uint8 uart1lcr; | |
| 391 | uint8 uart1mcr; | |
| 392 | uint8 uart1lsr; | |
| 393 | uint8 uart1msr; | |
| 394 | uint8 uart1scratch; /* 0x407 */ | |
| 395 | uint32 PAD[50]; | |
| 396 | uint32 sr_memrw_addr; /* 0x4d0 */ | |
| 397 | uint32 sr_memrw_data; /* 0x4d4 */ | |
| 398 | uint32 PAD[10]; | |
| 399 | ||
| 400 | /* save/restore, corerev >= 48 */ | |
| 401 | uint32 sr_capability; /* 0x500 */ | |
| 402 | uint32 sr_control0; /* 0x504 */ | |
| 403 | uint32 sr_control1; /* 0x508 */ | |
| 404 | uint32 gpio_control; /* 0x50C */ | |
| 405 | uint32 PAD[29]; | |
| 406 | /* 2 SR engines case */ | |
| 407 | uint32 sr1_control0; /* 0x584 */ | |
| 408 | uint32 sr1_control1; /* 0x588 */ | |
| 409 | uint32 PAD[29]; | |
| 410 | /* PMU registers (corerev >= 20) */ | |
| 411 | /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP. | |
| 412 | * The CPU must read them twice, compare, and retry if different. | |
| 413 | */ | |
| 414 | uint32 pmucontrol; /* 0x600 */ | |
| 415 | uint32 pmucapabilities; | |
| 416 | uint32 pmustatus; | |
| 417 | uint32 res_state; | |
| 418 | uint32 res_pending; | |
| 419 | uint32 pmutimer; | |
| 420 | uint32 min_res_mask; | |
| 421 | uint32 max_res_mask; | |
| 422 | uint32 res_table_sel; | |
| 423 | uint32 res_dep_mask; | |
| 424 | uint32 res_updn_timer; | |
| 425 | uint32 res_timer; | |
| 426 | uint32 clkstretch; | |
| 427 | uint32 pmuwatchdog; | |
| 428 | uint32 gpiosel; /* 0x638, rev >= 1 */ | |
| 429 | uint32 gpioenable; /* 0x63c, rev >= 1 */ | |
| 430 | uint32 res_req_timer_sel; | |
| 431 | uint32 res_req_timer; | |
| 432 | uint32 res_req_mask; | |
| 433 | uint32 core_cap_ext; /* 0x64c */ | |
| 434 | uint32 chipcontrol_addr; /* 0x650 */ | |
| 435 | uint32 chipcontrol_data; /* 0x654 */ | |
| 436 | uint32 regcontrol_addr; | |
| 437 | uint32 regcontrol_data; | |
| 438 | uint32 pllcontrol_addr; | |
| 439 | uint32 pllcontrol_data; | |
| 440 | uint32 pmustrapopt; /* 0x668, corerev >= 28 */ | |
| 441 | uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ | |
| 442 | uint32 retention_ctl; /* 0x670 */ | |
| 443 | uint32 ILPPeriod; /* 0x674 */ | |
| 444 | uint32 PAD[2]; | |
| 445 | uint32 retention_grpidx; /* 0x680 */ | |
| 446 | uint32 retention_grpctl; /* 0x684 */ | |
| 447 | uint32 mac_res_req_timer; /* 0x688 */ | |
| 448 | uint32 mac_res_req_mask; /* 0x68c */ | |
| 449 | uint32 PAD[18]; | |
| 450 | uint32 pmucontrol_ext; /* 0x6d8 */ | |
| 451 | uint32 slowclkperiod; /* 0x6dc */ | |
| 452 | uint32 pmu_statstimer_addr; /* 0x6e0 */ | |
| 453 | uint32 pmu_statstimer_ctrl; /* 0x6e4 */ | |
| 454 | uint32 pmu_statstimer_N; /* 0x6e8 */ | |
| 455 | uint32 PAD[1]; | |
| 456 | uint32 mac_res_req_timer1; /* 0x6f0 */ | |
| 457 | uint32 mac_res_req_mask1; /* 0x6f4 */ | |
| 458 | uint32 PAD[2]; | |
| 459 | uint32 pmuintmask0; /* 0x700 */ | |
| 460 | uint32 pmuintmask1; /* 0x704 */ | |
| 461 | uint32 PAD[14]; | |
| 462 | uint32 pmuintstatus; /* 0x740 */ | |
| 463 | uint32 extwakeupstatus; /* 0x744 */ | |
| 464 | uint32 PAD[6]; | |
| 465 | uint32 extwakemask0; /* 0x760 */ | |
| 466 | uint32 extwakemask1; /* 0x764 */ | |
| 467 | uint32 PAD[2]; /* 0x768-0x76C */ | |
| 468 | uint32 extwakereqmask[2]; /* 0x770-0x774 */ | |
| 469 | uint32 PAD[2]; /* 0x778-0x77C */ | |
| 470 | uint32 pmuintctrl0; /* 0x780 */ | |
| 471 | uint32 PAD[3]; /* 0x784 - 0x78c */ | |
| 472 | uint32 extwakectrl[1]; /* 0x790 */ | |
| 473 | uint32 PAD[PADSZ(0x794u, 0x7b0u)]; /* 0x794 - 0x7b0 */ | |
| 474 | uint32 fis_ctrl_status; /* 0x7b4 */ | |
| 475 | uint32 fis_min_res_mask; /* 0x7b8 */ | |
| 476 | uint32 PAD[PADSZ(0x7bcu, 0x7bcu)]; /* 0x7bc */ | |
| 477 | uint32 precision_tmr_ctrl_status; /* 0x7c0 */ | |
| 478 | uint32 precision_tmr_capture_low; /* 0x7c4 */ | |
| 479 | uint32 precision_tmr_capture_high; /* 0x7c8 */ | |
| 480 | uint32 precision_tmr_capture_frac; /* 0x7cc */ | |
| 481 | uint32 precision_tmr_running_low; /* 0x7d0 */ | |
| 482 | uint32 precision_tmr_running_high; /* 0x7d4 */ | |
| 483 | uint32 precision_tmr_running_frac; /* 0x7d8 */ | |
| 484 | uint32 PAD[PADSZ(0x7dcu, 0x7e4u)]; /* 0x7dc - 0x7e4 */ | |
| 485 | uint32 core_cap_ext1; /* 0x7e8 */ | |
| 486 | uint32 PAD[PADSZ(0x7ecu, 0x7fcu)]; /* 0x7ec - 0x7fc */ | |
| 487 | ||
| 488 | uint16 sromotp[512]; /* 0x800 */ | |
| 489 | #ifdef CCNFLASH_SUPPORT | |
| 490 | /* Nand flash MLC controller registers (corerev >= 38) */ | |
| 491 | uint32 nand_revision; /* 0xC00 */ | |
| 492 | uint32 nand_cmd_start; | |
| 493 | uint32 nand_cmd_addr_x; | |
| 494 | uint32 nand_cmd_addr; | |
| 495 | uint32 nand_cmd_end_addr; | |
| 496 | uint32 nand_cs_nand_select; | |
| 497 | uint32 nand_cs_nand_xor; | |
| 498 | uint32 PAD; | |
| 499 | uint32 nand_spare_rd0; | |
| 500 | uint32 nand_spare_rd4; | |
| 501 | uint32 nand_spare_rd8; | |
| 502 | uint32 nand_spare_rd12; | |
| 503 | uint32 nand_spare_wr0; | |
| 504 | uint32 nand_spare_wr4; | |
| 505 | uint32 nand_spare_wr8; | |
| 506 | uint32 nand_spare_wr12; | |
| 507 | uint32 nand_acc_control; | |
| 508 | uint32 PAD; | |
| 509 | uint32 nand_config; | |
| 510 | uint32 PAD; | |
| 511 | uint32 nand_timing_1; | |
| 512 | uint32 nand_timing_2; | |
| 513 | uint32 nand_semaphore; | |
| 514 | uint32 PAD; | |
| 515 | uint32 nand_devid; | |
| 516 | uint32 nand_devid_x; | |
| 517 | uint32 nand_block_lock_status; | |
| 518 | uint32 nand_intfc_status; | |
| 519 | uint32 nand_ecc_corr_addr_x; | |
| 520 | uint32 nand_ecc_corr_addr; | |
| 521 | uint32 nand_ecc_unc_addr_x; | |
| 522 | uint32 nand_ecc_unc_addr; | |
| 523 | uint32 nand_read_error_count; | |
| 524 | uint32 nand_corr_stat_threshold; | |
| 525 | uint32 PAD[2]; | |
| 526 | uint32 nand_read_addr_x; | |
| 527 | uint32 nand_read_addr; | |
| 528 | uint32 nand_page_program_addr_x; | |
| 529 | uint32 nand_page_program_addr; | |
| 530 | uint32 nand_copy_back_addr_x; | |
| 531 | uint32 nand_copy_back_addr; | |
| 532 | uint32 nand_block_erase_addr_x; | |
| 533 | uint32 nand_block_erase_addr; | |
| 534 | uint32 nand_inv_read_addr_x; | |
| 535 | uint32 nand_inv_read_addr; | |
| 536 | uint32 PAD[2]; | |
| 537 | uint32 nand_blk_wr_protect; | |
| 538 | uint32 PAD[3]; | |
| 539 | uint32 nand_acc_control_cs1; | |
| 540 | uint32 nand_config_cs1; | |
| 541 | uint32 nand_timing_1_cs1; | |
| 542 | uint32 nand_timing_2_cs1; | |
| 543 | uint32 PAD[20]; | |
| 544 | uint32 nand_spare_rd16; | |
| 545 | uint32 nand_spare_rd20; | |
| 546 | uint32 nand_spare_rd24; | |
| 547 | uint32 nand_spare_rd28; | |
| 548 | uint32 nand_cache_addr; | |
| 549 | uint32 nand_cache_data; | |
| 550 | uint32 nand_ctrl_config; | |
| 551 | uint32 nand_ctrl_status; | |
| 552 | #endif /* CCNFLASH_SUPPORT */ | |
| 553 | /* Note: there is a clash between GCI and NFLASH. So, | |
| 554 | * we decided to have it like below. the functions accessing following | |
| 555 | * have to be protected with NFLASH_SUPPORT. The functions will | |
| 556 | * assert in case the clash happens. | |
| 557 | */ | |
| 558 | uint32 gci_corecaps0; /* GCI starting at 0xC00 */ | |
| 559 | uint32 gci_corecaps1; | |
| 560 | uint32 gci_corecaps2; | |
| 561 | uint32 gci_corectrl; | |
| 562 | uint32 gci_corestat; /* 0xC10 */ | |
| 563 | uint32 gci_intstat; /* 0xC14 */ | |
| 564 | uint32 gci_intmask; /* 0xC18 */ | |
| 565 | uint32 gci_wakemask; /* 0xC1C */ | |
| 566 | uint32 gci_levelintstat; /* 0xC20 */ | |
| 567 | uint32 gci_eventintstat; /* 0xC24 */ | |
| 568 | uint32 PAD[6]; | |
| 569 | uint32 gci_indirect_addr; /* 0xC40 */ | |
| 570 | uint32 gci_gpioctl; /* 0xC44 */ | |
| 571 | uint32 gci_gpiostatus; | |
| 572 | uint32 gci_gpiomask; /* 0xC4C */ | |
| 573 | uint32 gci_eventsummary; /* 0xC50 */ | |
| 574 | uint32 gci_miscctl; /* 0xC54 */ | |
| 575 | uint32 gci_gpiointmask; | |
| 576 | uint32 gci_gpiowakemask; | |
| 577 | uint32 gci_input[32]; /* C60 */ | |
| 578 | uint32 gci_event[32]; /* CE0 */ | |
| 579 | uint32 gci_output[4]; /* D60 */ | |
| 580 | uint32 gci_control_0; /* 0xD70 */ | |
| 581 | uint32 gci_control_1; /* 0xD74 */ | |
| 582 | uint32 gci_intpolreg; /* 0xD78 */ | |
| 583 | uint32 gci_levelintmask; /* 0xD7C */ | |
| 584 | uint32 gci_eventintmask; /* 0xD80 */ | |
| 585 | uint32 PAD[3]; | |
| 586 | uint32 gci_inbandlevelintmask; /* 0xD90 */ | |
| 587 | uint32 gci_inbandeventintmask; /* 0xD94 */ | |
| 588 | uint32 PAD[2]; | |
| 589 | uint32 gci_seciauxtx; /* 0xDA0 */ | |
| 590 | uint32 gci_seciauxrx; /* 0xDA4 */ | |
| 591 | uint32 gci_secitx_datatag; /* 0xDA8 */ | |
| 592 | uint32 gci_secirx_datatag; /* 0xDAC */ | |
| 593 | uint32 gci_secitx_datamask; /* 0xDB0 */ | |
| 594 | uint32 gci_seciusef0tx_reg; /* 0xDB4 */ | |
| 595 | uint32 gci_secif0tx_offset; /* 0xDB8 */ | |
| 596 | uint32 gci_secif0rx_offset; /* 0xDBC */ | |
| 597 | uint32 gci_secif1tx_offset; /* 0xDC0 */ | |
| 598 | uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */ | |
| 599 | uint32 gci_rxfifoctrl; /* 0xDC8 */ | |
| 600 | uint32 gci_uartreadid; /* DCC */ | |
| 601 | uint32 gci_seciuartescval; /* DD0 */ | |
| 602 | uint32 PAD; | |
| 603 | uint32 gci_secififolevel; /* DD8 */ | |
| 604 | uint32 gci_seciuartdata; /* DDC */ | |
| 605 | uint32 gci_secibauddiv; /* DE0 */ | |
| 606 | uint32 gci_secifcr; /* DE4 */ | |
| 607 | uint32 gci_secilcr; /* DE8 */ | |
| 608 | uint32 gci_secimcr; /* DEC */ | |
| 609 | uint32 gci_secilsr; /* DF0 */ | |
| 610 | uint32 gci_secimsr; /* DF4 */ | |
| 611 | uint32 gci_baudadj; /* DF8 */ | |
| 612 | uint32 PAD; | |
| 613 | uint32 gci_chipctrl; /* 0xE00 */ | |
| 614 | uint32 gci_chipsts; /* 0xE04 */ | |
| 615 | uint32 gci_gpioout; /* 0xE08 */ | |
| 616 | uint32 gci_gpioout_read; /* 0xE0C */ | |
| 617 | uint32 gci_mpwaketx; /* 0xE10 */ | |
| 618 | uint32 gci_mpwakedetect; /* 0xE14 */ | |
| 619 | uint32 gci_seciin_ctrl; /* 0xE18 */ | |
| 620 | uint32 gci_seciout_ctrl; /* 0xE1C */ | |
| 621 | uint32 gci_seciin_auxfifo_en; /* 0xE20 */ | |
| 622 | uint32 gci_seciout_txen_txbr; /* 0xE24 */ | |
| 623 | uint32 gci_seciin_rxbrstatus; /* 0xE28 */ | |
| 624 | uint32 gci_seciin_rxerrstatus; /* 0xE2C */ | |
| 625 | uint32 gci_seciin_fcstatus; /* 0xE30 */ | |
| 626 | uint32 gci_seciout_txstatus; /* 0xE34 */ | |
| 627 | uint32 gci_seciout_txbrstatus; /* 0xE38 */ | |
| 628 | } chipcregs_t; | |
| 629 | ||
| 630 | #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ | |
| 631 | ||
| 632 | #define CC_CHIPID 0 | |
| 633 | #define CC_CAPABILITIES 4 | |
| 634 | #define CC_CHIPST 0x2c | |
| 635 | #define CC_EROMPTR 0xfc | |
| 636 | ||
| 637 | #define CC_OTPST 0x10 | |
| 638 | #define CC_INTSTATUS 0x20 | |
| 639 | #define CC_INTMASK 0x24 | |
| 640 | #define CC_JTAGCMD 0x30 | |
| 641 | #define CC_JTAGIR 0x34 | |
| 642 | #define CC_JTAGDR 0x38 | |
| 643 | #define CC_JTAGCTRL 0x3c | |
| 644 | #define CC_GPIOPU 0x58 | |
| 645 | #define CC_GPIOPD 0x5c | |
| 646 | #define CC_GPIOIN 0x60 | |
| 647 | #define CC_GPIOOUT 0x64 | |
| 648 | #define CC_GPIOOUTEN 0x68 | |
| 649 | #define CC_GPIOCTRL 0x6c | |
| 650 | #define CC_GPIOPOL 0x70 | |
| 651 | #define CC_GPIOINTM 0x74 | |
| 652 | #define CC_GPIOEVENT 0x78 | |
| 653 | #define CC_GPIOEVENTMASK 0x7c | |
| 654 | #define CC_WATCHDOG 0x80 | |
| 655 | #define CC_GPIOEVENTPOL 0x84 | |
| 656 | #define CC_CLKC_N 0x90 | |
| 657 | #define CC_CLKC_M0 0x94 | |
| 658 | #define CC_CLKC_M1 0x98 | |
| 659 | #define CC_CLKC_M2 0x9c | |
| 660 | #define CC_CLKC_M3 0xa0 | |
| 661 | #define CC_CLKDIV 0xa4 | |
| 662 | #define CC_CAP_EXT 0xac | |
| 663 | #define CC_SYS_CLK_CTL 0xc0 | |
| 664 | #define CC_BP_ADRLOW 0xd0 | |
| 665 | #define CC_BP_ADRHI 0xd4 | |
| 666 | #define CC_BP_DATA 0xd8 | |
| 667 | #define CC_SCR_DHD_TO_BL CC_BP_ADRHI | |
| 668 | #define CC_SCR_BL_TO_DHD CC_BP_ADRLOW | |
| 669 | #define CC_CLKDIV2 0xf0 | |
| 670 | #define CC_CLK_CTL_ST SI_CLK_CTL_ST | |
| 671 | #define PMU_CTL 0x600 | |
| 672 | #define PMU_CAP 0x604 | |
| 673 | #define PMU_ST 0x608 | |
| 674 | #define PMU_RES_STATE 0x60c | |
| 675 | #define PMU_RES_PENDING 0x610 | |
| 676 | #define PMU_TIMER 0x614 | |
| 677 | #define PMU_MIN_RES_MASK 0x618 | |
| 678 | #define PMU_MAX_RES_MASK 0x61c | |
| 679 | #define CC_CHIPCTL_ADDR 0x650 | |
| 680 | #define CC_CHIPCTL_DATA 0x654 | |
| 681 | #define PMU_REG_CONTROL_ADDR 0x658 | |
| 682 | #define PMU_REG_CONTROL_DATA 0x65C | |
| 683 | #define PMU_PLL_CONTROL_ADDR 0x660 | |
| 684 | #define PMU_PLL_CONTROL_DATA 0x664 | |
| 685 | #define PMU_RSRC_CONTROL_MASK 0x7B0 | |
| 686 | ||
| 687 | #define CC_SROM_CTRL 0x190 | |
| 688 | #define CC_SROM_ADDRESS 0x194u | |
| 689 | #define CC_SROM_DATA 0x198u | |
| 690 | #define CC_SROM_OTP 0x0800 | |
| 691 | #define CC_GCI_INDIRECT_ADDR_REG 0xC40 | |
| 692 | #define CC_GCI_CHIP_CTRL_REG 0xE00 | |
| 693 | #define CC_GCI_CC_OFFSET_2 2 | |
| 694 | #define CC_GCI_CC_OFFSET_5 5 | |
| 695 | #define CC_SWD_CTRL 0x380 | |
| 696 | #define CC_SWD_REQACK 0x384 | |
| 697 | #define CC_SWD_DATA 0x388 | |
| 698 | #define GPIO_SEL_0 0x00001111 | |
| 699 | #define GPIO_SEL_1 0x11110000 | |
| 700 | #define GPIO_SEL_8 0x00001111 | |
| 701 | #define GPIO_SEL_9 0x11110000 | |
| 702 | ||
| 703 | #define CHIPCTRLREG0 0x0 | |
| 704 | #define CHIPCTRLREG1 0x1 | |
| 705 | #define CHIPCTRLREG2 0x2 | |
| 706 | #define CHIPCTRLREG3 0x3 | |
| 707 | #define CHIPCTRLREG4 0x4 | |
| 708 | #define CHIPCTRLREG5 0x5 | |
| 709 | #define CHIPCTRLREG6 0x6 | |
| 710 | #define CHIPCTRLREG13 0xd | |
| 711 | #define CHIPCTRLREG16 0x10 | |
| 712 | #define REGCTRLREG4 0x4 | |
| 713 | #define REGCTRLREG5 0x5 | |
| 714 | #define REGCTRLREG6 0x6 | |
| 715 | #define MINRESMASKREG 0x618 | |
| 716 | #define MAXRESMASKREG 0x61c | |
| 717 | #define CHIPCTRLADDR 0x650 | |
| 718 | #define CHIPCTRLDATA 0x654 | |
| 719 | #define RSRCTABLEADDR 0x620 | |
| 720 | #define PMU_RES_DEP_MASK 0x624 | |
| 721 | #define RSRCUPDWNTIME 0x628 | |
| 722 | #define PMUREG_RESREQ_MASK 0x68c | |
| 723 | #define PMUREG_RESREQ_TIMER 0x688 | |
| 724 | #define PMUREG_RESREQ_MASK1 0x6f4 | |
| 725 | #define PMUREG_RESREQ_TIMER1 0x6f0 | |
| 726 | #define EXT_LPO_AVAIL 0x100 | |
| 727 | #define LPO_SEL (1 << 0) | |
| 728 | #define CC_EXT_LPO_PU 0x200000 | |
| 729 | #define GC_EXT_LPO_PU 0x2 | |
| 730 | #define CC_INT_LPO_PU 0x100000 | |
| 731 | #define GC_INT_LPO_PU 0x1 | |
| 732 | #define EXT_LPO_SEL 0x8 | |
| 733 | #define INT_LPO_SEL 0x4 | |
| 734 | #define ENABLE_FINE_CBUCK_CTRL (1 << 30) | |
| 735 | #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000 | |
| 736 | #define REGCTRL5_PWM_AUTO_CTRL_SHIFT 17 | |
| 737 | #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000 | |
| 738 | #define REGCTRL6_PWM_AUTO_CTRL_SHIFT 16 | |
| 739 | #define CC_BP_IND_ACCESS_START_SHIFT 9 | |
| 740 | #define CC_BP_IND_ACCESS_START_MASK (1 << CC_BP_IND_ACCESS_START_SHIFT) | |
| 741 | #define CC_BP_IND_ACCESS_RDWR_SHIFT 8 | |
| 742 | #define CC_BP_IND_ACCESS_RDWR_MASK (1 << CC_BP_IND_ACCESS_RDWR_SHIFT) | |
| 743 | #define CC_BP_IND_ACCESS_ERROR_SHIFT 10 | |
| 744 | #define CC_BP_IND_ACCESS_ERROR_MASK (1 << CC_BP_IND_ACCESS_ERROR_SHIFT) | |
| 745 | #define GC_BT_CTRL_UARTPADS_OVRD_EN (1u << 1) | |
| 746 | ||
| 747 | #define LPO_SEL_TIMEOUT 1000 | |
| 748 | ||
| 749 | #define LPO_FINAL_SEL_SHIFT 18 | |
| 750 | ||
| 751 | #define LHL_LPO1_SEL 0 | |
| 752 | #define LHL_LPO2_SEL 0x1 | |
| 753 | #define LHL_32k_SEL 0x2 | |
| 754 | #define LHL_EXT_SEL 0x3 | |
| 755 | ||
| 756 | #define EXTLPO_BUF_PD 0x40 | |
| 757 | #define LPO1_PD_EN 0x1 | |
| 758 | #define LPO1_PD_SEL 0x6 | |
| 759 | #define LPO1_PD_SEL_VAL 0x4 | |
| 760 | #define LPO2_PD_EN 0x8 | |
| 761 | #define LPO2_PD_SEL 0x30 | |
| 762 | #define LPO2_PD_SEL_VAL 0x20 | |
| 763 | #define OSC_32k_PD 0x80 | |
| 764 | ||
| 765 | #define LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL 0x3 | |
| 766 | ||
| 767 | #define LHL_LPO_AUTO 0x0 | |
| 768 | #define LHL_LPO1_ENAB 0x1 | |
| 769 | #define LHL_LPO2_ENAB 0x2 | |
| 770 | #define LHL_OSC_32k_ENAB 0x3 | |
| 771 | #define LHL_EXT_LPO_ENAB 0x4 | |
| 772 | #define RADIO_LPO_ENAB 0x5 | |
| 773 | ||
| 774 | #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN 0x4 | |
| 775 | #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR 0x8 | |
| 776 | #define LHL_CLK_DET_CNT 0xF0 | |
| 777 | #define LHL_CLK_DET_CNT_SHIFT 4 | |
| 778 | #define LPO_SEL_SHIFT 9 | |
| 779 | ||
| 780 | #define LHL_MAIN_CTL_ADR_FINAL_CLK_SEL 0x3C0000 | |
| 781 | #define LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL 0x600 | |
| 782 | ||
| 783 | #define CLK_DET_CNT_THRESH 8 | |
| 784 | ||
| 785 | #ifdef SR_DEBUG | |
| 786 | #define SUBCORE_POWER_ON 0x0001 | |
| 787 | #define PHY_POWER_ON 0x0010 | |
| 788 | #define VDDM_POWER_ON 0x0100 | |
| 789 | #define MEMLPLDO_POWER_ON 0x1000 | |
| 790 | #define SUBCORE_POWER_ON_CHK 0x00040000 | |
| 791 | #define PHY_POWER_ON_CHK 0x00080000 | |
| 792 | #define VDDM_POWER_ON_CHK 0x00100000 | |
| 793 | #define MEMLPLDO_POWER_ON_CHK 0x00200000 | |
| 794 | #endif /* SR_DEBUG */ | |
| 795 | ||
| 796 | #ifdef CCNFLASH_SUPPORT | |
| 797 | /* NAND flash support */ | |
| 798 | #define CC_NAND_REVISION 0xC00 | |
| 799 | #define CC_NAND_CMD_START 0xC04 | |
| 800 | #define CC_NAND_CMD_ADDR 0xC0C | |
| 801 | #define CC_NAND_SPARE_RD_0 0xC20 | |
| 802 | #define CC_NAND_SPARE_RD_4 0xC24 | |
| 803 | #define CC_NAND_SPARE_RD_8 0xC28 | |
| 804 | #define CC_NAND_SPARE_RD_C 0xC2C | |
| 805 | #define CC_NAND_CONFIG 0xC48 | |
| 806 | #define CC_NAND_DEVID 0xC60 | |
| 807 | #define CC_NAND_DEVID_EXT 0xC64 | |
| 808 | #define CC_NAND_INTFC_STATUS 0xC6C | |
| 809 | #endif /* CCNFLASH_SUPPORT */ | |
| 810 | ||
| 811 | /* chipid */ | |
| 812 | #define CID_ID_MASK 0x0000ffff /**< Chip Id mask */ | |
| 813 | #define CID_REV_MASK 0x000f0000 /**< Chip Revision mask */ | |
| 814 | #define CID_REV_SHIFT 16 /**< Chip Revision shift */ | |
| 815 | #define CID_PKG_MASK 0x00f00000 /**< Package Option mask */ | |
| 816 | #define CID_PKG_SHIFT 20 /**< Package Option shift */ | |
| 817 | #define CID_CC_MASK 0x0f000000 /**< CoreCount (corerev >= 4) */ | |
| 818 | #define CID_CC_SHIFT 24 | |
| 819 | #define CID_TYPE_MASK 0xf0000000 /**< Chip Type */ | |
| 820 | #define CID_TYPE_SHIFT 28 | |
| 821 | ||
| 822 | /* capabilities */ | |
| 823 | #define CC_CAP_UARTS_MASK 0x00000003u /**< Number of UARTs */ | |
| 824 | #define CC_CAP_MIPSEB 0x00000004u /**< MIPS is in big-endian mode */ | |
| 825 | #define CC_CAP_UCLKSEL 0x00000018u /**< UARTs clock select */ | |
| 826 | #define CC_CAP_UINTCLK 0x00000008u /**< UARTs are driven by internal divided clock */ | |
| 827 | #define CC_CAP_UARTGPIO 0x00000020u /**< UARTs own GPIOs 15:12 */ | |
| 828 | #define CC_CAP_EXTBUS_MASK 0x000000c0u /**< External bus mask */ | |
| 829 | #define CC_CAP_EXTBUS_NONE 0x00000000u /**< No ExtBus present */ | |
| 830 | #define CC_CAP_EXTBUS_FULL 0x00000040u /**< ExtBus: PCMCIA, IDE & Prog */ | |
| 831 | #define CC_CAP_EXTBUS_PROG 0x00000080u /**< ExtBus: ProgIf only */ | |
| 832 | #define CC_CAP_FLASH_MASK 0x00000700u /**< Type of flash */ | |
| 833 | #define CC_CAP_PLL_MASK 0x00038000u /**< Type of PLL */ | |
| 834 | #define CC_CAP_PWR_CTL 0x00040000u /**< Power control */ | |
| 835 | #define CC_CAP_OTPSIZE 0x00380000u /**< OTP Size (0 = none) */ | |
| 836 | #define CC_CAP_OTPSIZE_SHIFT 19 /**< OTP Size shift */ | |
| 837 | #define CC_CAP_OTPSIZE_BASE 5 /**< OTP Size base */ | |
| 838 | #define CC_CAP_JTAGP 0x00400000u /**< JTAG Master Present */ | |
| 839 | #define CC_CAP_ROM 0x00800000u /**< Internal boot rom active */ | |
| 840 | #define CC_CAP_BKPLN64 0x08000000u /**< 64-bit backplane */ | |
| 841 | #define CC_CAP_PMU 0x10000000u /**< PMU Present, rev >= 20 */ | |
| 842 | #define CC_CAP_ECI 0x20000000u /**< ECI Present, rev >= 21 */ | |
| 843 | #define CC_CAP_SROM 0x40000000u /**< Srom Present, rev >= 32 */ | |
| 844 | #define CC_CAP_NFLASH 0x80000000u /**< Nand flash present, rev >= 35 */ | |
| 845 | ||
| 846 | #define CC_CAP2_SECI 0x00000001u /**< SECI Present, rev >= 36 */ | |
| 847 | #define CC_CAP2_GSIO 0x00000002u /**< GSIO (spi/i2c) present, rev >= 37 */ | |
| 848 | ||
| 849 | /* capabilities extension */ | |
| 850 | #define CC_CAP_EXT_SECI_PRESENT 0x00000001u /**< SECI present */ | |
| 851 | #define CC_CAP_EXT_GSIO_PRESENT 0x00000002u /**< GSIO present */ | |
| 852 | #define CC_CAP_EXT_GCI_PRESENT 0x00000004u /**< GCI present */ | |
| 853 | #define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008u /**< UART present */ | |
| 854 | #define CC_CAP_EXT_AOB_PRESENT 0x00000040u /**< AOB present */ | |
| 855 | #define CC_CAP_EXT_SWD_PRESENT 0x00000400u /**< SWD present */ | |
| 856 | #define CC_CAP_SR_AON_PRESENT 0x0001E000u /**< SWD present */ | |
| 857 | #define CC_CAP_EXT1_DVFS_PRESENT 0x00001000u /**< DVFS present */ | |
| 858 | ||
| 859 | /* SpmCtrl (Chipcommon Offset 0x690) | |
| 860 | * Bits 27:16 AlpDiv | |
| 861 | * Clock divider control for dividing ALP or TCK clock | |
| 862 | * (bit 8 determines ALP vs TCK) | |
| 863 | * Bits 8 UseDivTck | |
| 864 | * See UseDivAlp (bit 1) for more details | |
| 865 | * Bits 7:6 DebugMuxSel | |
| 866 | * Controls the debug mux for SpmDebug register | |
| 867 | * Bits 5 IntPending | |
| 868 | * This field is set to 1 when any of the bits in IntHiStatus or IntLoStatus | |
| 869 | * is set. It is automatically cleared after reading and clearing the | |
| 870 | * IntHiStatus and IntLoStatus registers. This bit is Read only. | |
| 871 | * Bits 4 SpmIdle | |
| 872 | * Indicates whether the spm controller is running (SpmIdle=0) or in idle | |
| 873 | * state (SpmIdle=1); Note that after setting Spmen=1 (or 0), it takes a | |
| 874 | * few clock cycles (ILP or divided ALP) for SpmIdle to go to 0 (or 1). | |
| 875 | * This bit is Read only. | |
| 876 | * Bits 3 RoDisOutput | |
| 877 | * Debug register - gate off all the SPM ring oscillator clock outputs | |
| 878 | * Bits 2 RstSpm | |
| 879 | * Reset spm controller. | |
| 880 | * Put spm in reset before changing UseDivAlp and AlpDiv | |
| 881 | * Bits 1 UseDivAlp | |
| 882 | * This field, along with UseDivTck, selects the clock as the reference clock | |
| 883 | * Bits [UseDivTck,UseDivAlp]: | |
| 884 | * 00 - Use ILP clock as reference clock | |
| 885 | * 01 - Use divided ALP clock | |
| 886 | * 10 - Use divided jtag TCK | |
| 887 | * Bits 0 Spmen | |
| 888 | * 0 - SPM disabled | |
| 889 | * 1 - SPM enabled | |
| 890 | * Program all the SPM controls before enabling spm. For one-shot operation, | |
| 891 | * SpmIdle indicates when the one-shot run has completed. After one-shot | |
| 892 | * completion, spmen needs to be disabled first before enabling again. | |
| 893 | */ | |
| 894 | #define SPMCTRL_ALPDIV_FUNC 0x1ffu | |
| 895 | #define SPMCTRL_ALPDIV_RO 0xfffu | |
| 896 | #define SPMCTRL_ALPDIV_SHIFT 16u | |
| 897 | #define SPMCTRL_ALPDIV_MASK (0xfffu << SPMCTRL_ALPDIV_SHIFT) | |
| 898 | #define SPMCTRL_RSTSPM 0x1u | |
| 899 | #define SPMCTRL_RSTSPM_SHIFT 2u | |
| 900 | #define SPMCTRL_RSTSPM_MASK (0x1u << SPMCTRL_RSTSPM_SHIFT) | |
| 901 | #define SPMCTRL_USEDIVALP 0x1u | |
| 902 | #define SPMCTRL_USEDIVALP_SHIFT 1u | |
| 903 | #define SPMCTRL_USEDIVALP_MASK (0x1u << SPMCTRL_USEDIVALP_SHIFT) | |
| 904 | #define SPMCTRL_SPMEN 0x1u | |
| 905 | #define SPMCTRL_SPMEN_SHIFT 0u | |
| 906 | #define SPMCTRL_SPMEN_MASK (0x1u << SPMCTRL_SPMEN_SHIFT) | |
| 907 | ||
| 908 | /* SpmClkCtrl (Chipcommon Offset 0x698) | |
| 909 | * Bits 31 OneShot | |
| 910 | * 0 means Take periodic measurements based on IntervalValue | |
| 911 | * 1 means Take a one shot measurement | |
| 912 | * when OneShot=1 IntervalValue determines the amount of time to wait before | |
| 913 | * taking the measurement | |
| 914 | * Bits 30:28 ROClkprediv1 | |
| 915 | * ROClkprediv1 and ROClkprediv2 controls the clock dividers of the RO clk | |
| 916 | * before it goes to the monitor | |
| 917 | * The RO clk goes through prediv1, followed by prediv2 | |
| 918 | * prediv1: | |
| 919 | * 0 - no divide | |
| 920 | * 1 - divide by 2 | |
| 921 | * 2 - divide by 4 | |
| 922 | * 3 - divide by 8 | |
| 923 | * 4 - divide by 16 | |
| 924 | * 5 - divide by 32 | |
| 925 | * prediv2: | |
| 926 | * 0 - no divide | |
| 927 | * 1 to 15 - divide by (prediv2+1) | |
| 928 | */ | |
| 929 | #define SPMCLKCTRL_SAMPLETIME 0x2u | |
| 930 | #define SPMCLKCTRL_SAMPLETIME_SHIFT 24u | |
| 931 | #define SPMCLKCTRL_SAMPLETIME_MASK (0xfu << SPMCLKCTRL_SAMPLETIME_SHIFT) | |
| 932 | #define SPMCLKCTRL_ONESHOT 0x1u | |
| 933 | #define SPMCLKCTRL_ONESHOT_SHIFT 31u | |
| 934 | #define SPMCLKCTRL_ONESHOT_MASK (0x1u << SPMCLKCTRL_ONESHOT_SHIFT) | |
| 935 | ||
| 936 | /* MonCtrlN (Chipcommon Offset 0x6a8) | |
| 937 | * Bits 15:8 TargetRo | |
| 938 | * The target ring oscillator to observe | |
| 939 | * Bits 7:6 TargetRoExt | |
| 940 | * Extended select option to choose the target clock to monitor; | |
| 941 | * 00 - selects ring oscillator clock; | |
| 942 | * 10 - selects functional clock; | |
| 943 | * 11 - selects DFT clocks; | |
| 944 | * Bits 15:8 (TargetRO) is used to select the specific RO or functional or | |
| 945 | * DFT clock | |
| 946 | * Bits 3 intHiEn | |
| 947 | * Interrupt hi enable (MonEn should be 1) | |
| 948 | * Bits 2 intLoEn | |
| 949 | * Interrupt hi enable (MonEn should be 1) | |
| 950 | * Bits 1 HwEnable | |
| 951 | * TBD | |
| 952 | * Bits 0 MonEn | |
| 953 | * Enable monitor, interrupt and watermark functions | |
| 954 | */ | |
| 955 | #define MONCTRLN_TARGETRO_PMU_ALP_CLK 0u | |
| 956 | #define MONCTRLN_TARGETRO_PCIE_ALP_CLK 1u | |
| 957 | #define MONCTRLN_TARGETRO_CB_BP_CLK 2u | |
| 958 | #define MONCTRLN_TARGETRO_ARMCR4_CLK_4387B0 3u | |
| 959 | #define MONCTRLN_TARGETRO_ARMCR4_CLK_4387C0 20u | |
| 960 | #define MONCTRLN_TARGETRO_SHIFT 8u | |
| 961 | #define MONCTRLN_TARGETRO_MASK (0xffu << MONCTRLN_TARGETRO_SHIFT) | |
| 962 | #define MONCTRLN_TARGETROMAX 64u | |
| 963 | #define MONCTRLN_TARGETROHI 32u | |
| 964 | #define MONCTRLN_TARGETROEXT_RO 0x0u | |
| 965 | #define MONCTRLN_TARGETROEXT_FUNC 0x2u | |
| 966 | #define MONCTRLN_TARGETROEXT_DFT 0x3u | |
| 967 | #define MONCTRLN_TARGETROEXT_SHIFT 6u | |
| 968 | #define MONCTRLN_TARGETROEXT_MASK (0x3u << MONCTRLN_TARGETROEXT_SHIFT) | |
| 969 | #define MONCTRLN_MONEN 0x1u | |
| 970 | #define MONCTRLN_MONEN_SHIFT 0u | |
| 971 | #define MONCTRLN_MONEN_MASK (0x1u << MONCTRLN_MONENEXT_SHIFT) | |
| 972 | ||
| 973 | /* DvfsCoreCtrlN | |
| 974 | * Bits 10 Request_override_PDn | |
| 975 | * When set, the dvfs_request logic for this core is overridden with the | |
| 976 | * content in Request_val_PDn. This field is ignored when | |
| 977 | * DVFSCtrl1.dvfs_req_override is set. | |
| 978 | * Bits 9:8 Request_val_PDn | |
| 979 | * see Request_override_PDn description | |
| 980 | * Bits 4:0 DVFS_RsrcTrig_PDn | |
| 981 | * Specifies the pmu resource that is used to trigger the DVFS request for | |
| 982 | * this core request. Current plan is to use the appropriate PWRSW_* pmu | |
| 983 | * resource each power domain / cores | |
| 984 | */ | |
| 985 | #define CTRLN_REQUEST_OVERRIDE_SHIFT 10u | |
| 986 | #define CTRLN_REQUEST_OVERRIDE_MASK (0x1u << CTRLN_REQUEST_OVERRIDE_SHIFT) | |
| 987 | #define CTRLN_REQUEST_VAL_SHIFT 8u | |
| 988 | #define CTRLN_REQUEST_VAL_MASK (0x3u << CTRLN_REQUEST_VAL_SHIFT) | |
| 989 | #define CTRLN_RSRC_TRIG_SHIFT 0u | |
| 990 | #define CTRLN_RSRC_TRIG_MASK (0x1Fu << CTRLN_RSRC_TRIG_SHIFT) | |
| 991 | #define CTRLN_RSRC_TRIG_CHIPC 0x1Au | |
| 992 | #define CTRLN_RSRC_TRIG_PCIE 0x1Au | |
| 993 | #define CTRLN_RSRC_TRIG_ARM 0x8u | |
| 994 | #define CTRLN_RSRC_TRIG_D11_MAIN 0xEu | |
| 995 | #define CTRLN_RSRC_TRIG_D11_AUX 0xBu | |
| 996 | #define CTRLN_RSRC_TRIG_D11_SCAN 0xCu | |
| 997 | #define CTRLN_RSRC_TRIG_BT_MAIN 0x9u | |
| 998 | #define CTRLN_RSRC_TRIG_BT_SCAN 0xAu | |
| 999 | ||
| 1000 | #define DVFS_CORE_CHIPC 0u | |
| 1001 | #define DVFS_CORE_PCIE 1u | |
| 1002 | #define DVFS_CORE_ARM 2u | |
| 1003 | #define DVFS_CORE_D11_MAIN 3u | |
| 1004 | #define DVFS_CORE_D11_AUX 4u | |
| 1005 | #define DVFS_CORE_D11_SCAN 5u | |
| 1006 | #define DVFS_CORE_BT_MAIN 6u | |
| 1007 | #define DVFS_CORE_BT_SCAN 7u | |
| 1008 | #define DVFS_CORE_MASK 7u | |
| 1009 | ||
| 1010 | /* DVFS_Ctrl2 (PMU_BASE + 0x814) | |
| 1011 | * Bits 31:28 Voltage ramp down step | |
| 1012 | * Voltage increment amount during ramp down (10mv units) | |
| 1013 | * Bits 27:24 Voltage ramp up step | |
| 1014 | * Voltage increment amount during ramp up (10mv units) | |
| 1015 | * Bits 23:16 Voltage ramp down interval | |
| 1016 | * Number of clocks to wait during each voltage decrement | |
| 1017 | * Bits 15:8 Voltage ramp up interval | |
| 1018 | * Number of clocks to wait during each voltage increment | |
| 1019 | * Bits 7:0 Clock stable time | |
| 1020 | * Number of clocks to wait after dvfs_clk_sel is asserted | |
| 1021 | */ | |
| 1022 | #define DVFS_VOLTAGE_RAMP_DOWN_STEP 1u | |
| 1023 | #define DVFS_VOLTAGE_RAMP_DOWN_STEP_SHIFT 28u | |
| 1024 | #define DVFS_VOLTAGE_RAMP_DOWN_STEP_MASK (0xFu << DVFS_VOLTAGE_RAMP_DOWN_STEP_SHIFT) | |
| 1025 | #define DVFS_VOLTAGE_RAMP_UP_STEP 1u | |
| 1026 | #define DVFS_VOLTAGE_RAMP_UP_STEP_SHIFT 24u | |
| 1027 | #define DVFS_VOLTAGE_RAMP_UP_STEP_MASK (0xFu << DVFS_VOLTAGE_RAMP_UP_STEP_SHIFT) | |
| 1028 | #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL 1u | |
| 1029 | #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_SHIFT 16u | |
| 1030 | #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_MASK (0xFFu << DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_SHIFT) | |
| 1031 | #define DVFS_VOLTAGE_RAMP_UP_INTERVAL 1u | |
| 1032 | #define DVFS_VOLTAGE_RAMP_UP_INTERVAL_SHIFT 8u | |
| 1033 | #define DVFS_VOLTAGE_RAMP_UP_INTERVAL_MASK (0xFFu << DVFS_VOLTAGE_RAMP_UP_INTERVAL_SHIFT) | |
| 1034 | #define DVFS_CLOCK_STABLE_TIME 3u | |
| 1035 | #define DVFS_CLOCK_STABLE_TIME_SHIFT 0 | |
| 1036 | #define DVFS_CLOCK_STABLE_TIME_MASK (0xFFu << DVFS_CLOCK_STABLE_TIME_SHIFT) | |
| 1037 | ||
| 1038 | /* DVFS_Voltage (PMU_BASE + 0x818) | |
| 1039 | * Bits 22:16 HDV Voltage | |
| 1040 | * Specifies the target HDV voltage in 10mv units | |
| 1041 | * Bits 14:8 NDV Voltage | |
| 1042 | * Specifies the target NDV voltage in 10mv units | |
| 1043 | * Bits 6:0 LDV Voltage | |
| 1044 | * Specifies the target LDV voltage in 10mv units | |
| 1045 | */ | |
| 1046 | #define DVFS_VOLTAGE_XDV 0u /* Reserved */ | |
| 1047 | #define DVFS_VOLTAGE_HDV 72u /* 0.72V */ | |
| 1048 | #define DVFS_VOLTAGE_HDV_PWR_OPT 68u /* 0.68V */ | |
| 1049 | #define DVFS_VOLTAGE_HDV_SHIFT 16u | |
| 1050 | #define DVFS_VOLTAGE_HDV_MASK (0x7Fu << DVFS_VOLTAGE_HDV_SHIFT) | |
| 1051 | #define DVFS_VOLTAGE_NDV 72u /* 0.72V */ | |
| 1052 | #define DVFS_VOLTAGE_NDV_PWR_OPT 68u /* 0.68V */ | |
| 1053 | #define DVFS_VOLTAGE_NDV_SHIFT 8u | |
| 1054 | #define DVFS_VOLTAGE_NDV_MASK (0x7Fu << DVFS_VOLTAGE_NDV_SHIFT) | |
| 1055 | #define DVFS_VOLTAGE_LDV 65u /* 0.65V */ | |
| 1056 | #define DVFS_VOLTAGE_LDV_PWR_OPT 65u /* 0.65V */ | |
| 1057 | #define DVFS_VOLTAGE_LDV_SHIFT 0u | |
| 1058 | #define DVFS_VOLTAGE_LDV_MASK (0x7Fu << DVFS_VOLTAGE_LDV_SHIFT) | |
| 1059 | ||
| 1060 | /* DVFS_Status (PMU_BASE + 0x81C) | |
| 1061 | * Bits 27:26 Raw_Core_Reqn | |
| 1062 | * Bits 25:24 Active_Core_Reqn | |
| 1063 | * Bits 12:11 Core_dvfs_status | |
| 1064 | * Bits 9:8 Dvfs_clk_sel | |
| 1065 | * 00 - LDV | |
| 1066 | * 01 - NDV | |
| 1067 | * Bits 6:0 Dvfs Voltage | |
| 1068 | * The real time voltage that is being output from the dvfs controller | |
| 1069 | */ | |
| 1070 | #define DVFS_RAW_CORE_REQ_SHIFT 26u | |
| 1071 | #define DVFS_RAW_CORE_REQ_MASK (0x3u << DVFS_RAW_CORE_REQ_SHIFT) | |
| 1072 | #define DVFS_ACT_CORE_REQ_SHIFT 24u | |
| 1073 | #define DVFS_ACT_CORE_REQ_MASK (0x3u << DVFS_ACT_CORE_REQ_SHIFT) | |
| 1074 | #define DVFS_CORE_STATUS_SHIFT 11u | |
| 1075 | #define DVFS_CORE_STATUS_MASK (0x3u << DVFS_CORE_STATUS_SHIFT) | |
| 1076 | #define DVFS_CLK_SEL_SHIFT 8u | |
| 1077 | #define DVFS_CLK_SEL_MASK (0x3u << DVFS_CLK_SEL_SHIFT) | |
| 1078 | #define DVFS_VOLTAGE_SHIFT 0u | |
| 1079 | #define DVFS_VOLTAGE_MASK (0x7Fu << DVFS_VOLTAGE_SHIFT) | |
| 1080 | ||
| 1081 | /* DVFS_Ctrl1 (PMU_BASE + 0x810) | |
| 1082 | * Bits 0 Enable DVFS | |
| 1083 | * This bit will enable DVFS operation. When cleared, the complete DVFS | |
| 1084 | * controller is bypassed and DVFS_voltage output will be the contents of | |
| 1085 | * NDV voltage register | |
| 1086 | */ | |
| 1087 | #define DVFS_DISABLE_DVFS 0u | |
| 1088 | #define DVFS_ENABLE_DVFS 1u | |
| 1089 | #define DVFS_ENABLE_DVFS_SHIFT 0u | |
| 1090 | #define DVFS_ENABLE_DVFS_MASK (1u << DVFS_ENABLE_DVFS_SHIFT) | |
| 1091 | ||
| 1092 | #define DVFS_LPO_DELAY 40u /* usec (1 LPO clock + margin) */ | |
| 1093 | #define DVFS_FASTLPO_DELAY 2u /* usec (1 FAST_LPO clock + margin) */ | |
| 1094 | #define DVFS_NDV_LPO_DELAY 1500u | |
| 1095 | #define DVFS_NDV_FASTLPO_DELAY 50u | |
| 1096 | ||
| 1097 | #if defined(BCM_FASTLPO) && !defined(BCM_FASTLPO_DISABLED) | |
| 1098 | #define DVFS_DELAY DVFS_FASTLPO_DELAY | |
| 1099 | #define DVFS_NDV_DELAY DVFS_NDV_FASTLPO_DELAY | |
| 1100 | #else | |
| 1101 | #define DVFS_DELAY DVFS_LPO_DELAY | |
| 1102 | #define DVFS_NDV_DELAY DVFS_NDV_LPO_DELAY | |
| 1103 | #endif /* BCM_FASTLPO && !BCM_FASTLPO_DISABLED */ | |
| 1104 | ||
| 1105 | #define DVFS_LDV 0u | |
| 1106 | #define DVFS_NDV 1u | |
| 1107 | #define DVFS_HDV 2u | |
| 1108 | ||
| 1109 | /* PowerControl2 (Core Offset 0x1EC) | |
| 1110 | * Bits 17:16 DVFSStatus | |
| 1111 | * This 2-bit field is the DVFS voltage status mapped as | |
| 1112 | * 00 - LDV | |
| 1113 | * 01 - NDV | |
| 1114 | * 10 - HDV | |
| 1115 | * Bits 1:0 DVFSRequest | |
| 1116 | * This 2-bit field is used to request DVFS voltage mapped as shown above | |
| 1117 | */ | |
| 1118 | #define DVFS_REQ_LDV DVFS_LDV | |
| 1119 | #define DVFS_REQ_NDV DVFS_NDV | |
| 1120 | #define DVFS_REQ_HDV DVFS_HDV | |
| 1121 | #define DVFS_REQ_SHIFT 0u | |
| 1122 | #define DVFS_REQ_MASK (0x3u << DVFS_REQ_SHIFT) | |
| 1123 | #define DVFS_STATUS_SHIFT 16u | |
| 1124 | #define DVFS_STATUS_MASK (0x3u << DVFS_STATUS_SHIFT) | |
| 1125 | ||
| 1126 | /* GCI Chip Control 16 Register | |
| 1127 | * Bits 0 CB Clock sel | |
| 1128 | * 0 - 160MHz | |
| 1129 | * 1 - 80Mhz - BT can force CB backplane clock to 80Mhz when wl is down | |
| 1130 | */ | |
| 1131 | #define GCI_CC16_CB_CLOCK_SEL_160 0u | |
| 1132 | #define GCI_CC16_CB_CLOCK_SEL_80 1u | |
| 1133 | #define GCI_CC16_CB_CLOCK_SEL_SHIFT 0u | |
| 1134 | #define GCI_CC16_CB_CLOCK_SEL_MASK (0x1u << GCI_CC16_CB_CLOCK_SEL_SHIFT) | |
| 1135 | ||
| 1136 | /* WL Channel Info to BT via GCI - bits 40 - 47 */ | |
| 1137 | #define GCI_WL_CHN_INFO_MASK (0xFF00) | |
| 1138 | /* WL indication of MCHAN enabled/disabled to BT - bit 36 */ | |
| 1139 | #define GCI_WL_MCHAN_BIT_MASK (0x0010) | |
| 1140 | ||
| 1141 | #ifdef WLC_SW_DIVERSITY | |
| 1142 | /* WL indication of SWDIV enabled/disabled to BT - bit 33 */ | |
| 1143 | #define GCI_WL_SWDIV_ANT_VALID_BIT_MASK (0x0002) | |
| 1144 | #define GCI_SWDIV_ANT_VALID_SHIFT 0x1 | |
| 1145 | #define GCI_SWDIV_ANT_VALID_DISABLE 0x0 | |
| 1146 | #endif | |
| 1147 | ||
| 1148 | /* Indicate to BT that WL is scheduling ACL based ble scan grant */ | |
| 1149 | #define GCI_WL2BT_ACL_BSD_BLE_SCAN_GRNT_MASK 0x8000000 | |
| 1150 | /* WLAN is awake Indicate to BT */ | |
| 1151 | #define GCI_WL2BT_2G_AWAKE_MASK (1u << 27u) | |
| 1152 | ||
| 1153 | /* WL inidcation of Aux Core 2G hibernate status - bit 50 */ | |
| 1154 | #define GCI_WL2BT_2G_HIB_STATE_MASK (0x0040000u) | |
| 1155 | ||
| 1156 | /* WL Strobe to BT */ | |
| 1157 | #define GCI_WL_STROBE_BIT_MASK (0x0020) | |
| 1158 | /* bits [51:48] - reserved for wlan TX pwr index */ | |
| 1159 | /* bits [55:52] btc mode indication */ | |
| 1160 | #define GCI_WL_BTC_MODE_SHIFT (20) | |
| 1161 | #define GCI_WL_BTC_MODE_MASK (0xF << GCI_WL_BTC_MODE_SHIFT) | |
| 1162 | #define GCI_WL_ANT_BIT_MASK (0x00c0) | |
| 1163 | #define GCI_WL_ANT_SHIFT_BITS (6) | |
| 1164 | /* PLL type */ | |
| 1165 | #define PLL_NONE 0x00000000 | |
| 1166 | #define PLL_TYPE1 0x00010000 /**< 48MHz base, 3 dividers */ | |
| 1167 | #define PLL_TYPE2 0x00020000 /**< 48MHz, 4 dividers */ | |
| 1168 | #define PLL_TYPE3 0x00030000 /**< 25MHz, 2 dividers */ | |
| 1169 | #define PLL_TYPE4 0x00008000 /**< 48MHz, 4 dividers */ | |
| 1170 | #define PLL_TYPE5 0x00018000 /**< 25MHz, 4 dividers */ | |
| 1171 | #define PLL_TYPE6 0x00028000 /**< 100/200 or 120/240 only */ | |
| 1172 | #define PLL_TYPE7 0x00038000 /**< 25MHz, 4 dividers */ | |
| 1173 | ||
| 1174 | /* ILP clock */ | |
| 1175 | #define ILP_CLOCK 32000 | |
| 1176 | ||
| 1177 | /* ALP clock on pre-PMU chips */ | |
| 1178 | #define ALP_CLOCK 20000000 | |
| 1179 | ||
| 1180 | #ifdef CFG_SIM | |
| 1181 | #define NS_ALP_CLOCK 84922 | |
| 1182 | #define NS_SLOW_ALP_CLOCK 84922 | |
| 1183 | #define NS_CPU_CLOCK 534500 | |
| 1184 | #define NS_SLOW_CPU_CLOCK 534500 | |
| 1185 | #define NS_SI_CLOCK 271750 | |
| 1186 | #define NS_SLOW_SI_CLOCK 271750 | |
| 1187 | #define NS_FAST_MEM_CLOCK 271750 | |
| 1188 | #define NS_MEM_CLOCK 271750 | |
| 1189 | #define NS_SLOW_MEM_CLOCK 271750 | |
| 1190 | #else | |
| 1191 | #define NS_ALP_CLOCK 125000000 | |
| 1192 | #define NS_SLOW_ALP_CLOCK 100000000 | |
| 1193 | #define NS_CPU_CLOCK 1000000000 | |
| 1194 | #define NS_SLOW_CPU_CLOCK 800000000 | |
| 1195 | #define NS_SI_CLOCK 250000000 | |
| 1196 | #define NS_SLOW_SI_CLOCK 200000000 | |
| 1197 | #define NS_FAST_MEM_CLOCK 800000000 | |
| 1198 | #define NS_MEM_CLOCK 533000000 | |
| 1199 | #define NS_SLOW_MEM_CLOCK 400000000 | |
| 1200 | #endif /* CFG_SIM */ | |
| 1201 | ||
| 1202 | /* HT clock */ | |
| 1203 | #define HT_CLOCK 80000000 | |
| 1204 | ||
| 1205 | /* corecontrol */ | |
| 1206 | #define CC_UARTCLKO 0x00000001 /**< Drive UART with internal clock */ | |
| 1207 | #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */ | |
| 1208 | #define CC_ASYNCGPIO 0x00000004 /**< 1=generate GPIO interrupt without backplane clock */ | |
| 1209 | #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */ | |
| 1210 | #define CC_RBG_RESET 0x00000040 /**< Reset RBG block (corerev > = 65 */ | |
| 1211 | ||
| 1212 | /* retention_ctl */ | |
| 1213 | #define RCTL_MEM_RET_SLEEP_LOG_SHIFT 29 | |
| 1214 | #define RCTL_MEM_RET_SLEEP_LOG_MASK (1 << RCTL_MEM_RET_SLEEP_LOG_SHIFT) | |
| 1215 | ||
| 1216 | /* 4321 chipcontrol */ | |
| 1217 | #define CHIPCTRL_4321_PLL_DOWN 0x800000 /**< serdes PLL down override */ | |
| 1218 | ||
| 1219 | /* Fields in the otpstatus register in rev >= 21 */ | |
| 1220 | #define OTPS_OL_MASK 0x000000ff | |
| 1221 | #define OTPS_OL_MFG 0x00000001 /**< manuf row is locked */ | |
| 1222 | #define OTPS_OL_OR1 0x00000002 /**< otp redundancy row 1 is locked */ | |
| 1223 | #define OTPS_OL_OR2 0x00000004 /**< otp redundancy row 2 is locked */ | |
| 1224 | #define OTPS_OL_GU 0x00000008 /**< general use region is locked */ | |
| 1225 | #define OTPS_GUP_MASK 0x00000f00 | |
| 1226 | #define OTPS_GUP_SHIFT 8 | |
| 1227 | #define OTPS_GUP_HW 0x00000100 /**< h/w subregion is programmed */ | |
| 1228 | #define OTPS_GUP_SW 0x00000200 /**< s/w subregion is programmed */ | |
| 1229 | #define OTPS_GUP_CI 0x00000400 /**< chipid/pkgopt subregion is programmed */ | |
| 1230 | #define OTPS_GUP_FUSE 0x00000800 /**< fuse subregion is programmed */ | |
| 1231 | #define OTPS_READY 0x00001000 | |
| 1232 | #define OTPS_RV(x) (1 << (16 + (x))) /**< redundancy entry valid */ | |
| 1233 | #define OTPS_RV_MASK 0x0fff0000 | |
| 1234 | #define OTPS_PROGOK 0x40000000 | |
| 1235 | ||
| 1236 | /* Fields in the otpcontrol register in rev >= 21 */ | |
| 1237 | #define OTPC_PROGSEL 0x00000001 | |
| 1238 | #define OTPC_PCOUNT_MASK 0x0000000e | |
| 1239 | #define OTPC_PCOUNT_SHIFT 1 | |
| 1240 | #define OTPC_VSEL_MASK 0x000000f0 | |
| 1241 | #define OTPC_VSEL_SHIFT 4 | |
| 1242 | #define OTPC_TMM_MASK 0x00000700 | |
| 1243 | #define OTPC_TMM_SHIFT 8 | |
| 1244 | #define OTPC_ODM 0x00000800 | |
| 1245 | #define OTPC_PROGEN 0x80000000 | |
| 1246 | ||
| 1247 | /* Fields in the 40nm otpcontrol register in rev >= 40 */ | |
| 1248 | #define OTPC_40NM_PROGSEL_SHIFT 0 | |
| 1249 | #define OTPC_40NM_PCOUNT_SHIFT 1 | |
| 1250 | #define OTPC_40NM_PCOUNT_WR 0xA | |
| 1251 | #define OTPC_40NM_PCOUNT_V1X 0xB | |
| 1252 | #define OTPC_40NM_REGCSEL_SHIFT 5 | |
| 1253 | #define OTPC_40NM_REGCSEL_DEF 0x4 | |
| 1254 | #define OTPC_40NM_PROGIN_SHIFT 8 | |
| 1255 | #define OTPC_40NM_R2X_SHIFT 10 | |
| 1256 | #define OTPC_40NM_ODM_SHIFT 11 | |
| 1257 | #define OTPC_40NM_DF_SHIFT 15 | |
| 1258 | #define OTPC_40NM_VSEL_SHIFT 16 | |
| 1259 | #define OTPC_40NM_VSEL_WR 0xA | |
| 1260 | #define OTPC_40NM_VSEL_V1X 0xA | |
| 1261 | #define OTPC_40NM_VSEL_R1X 0x5 | |
| 1262 | #define OTPC_40NM_COFAIL_SHIFT 30 | |
| 1263 | ||
| 1264 | #define OTPC1_CPCSEL_SHIFT 0 | |
| 1265 | #define OTPC1_CPCSEL_DEF 6 | |
| 1266 | #define OTPC1_TM_SHIFT 8 | |
| 1267 | #define OTPC1_TM_WR 0x84 | |
| 1268 | #define OTPC1_TM_V1X 0x84 | |
| 1269 | #define OTPC1_TM_R1X 0x4 | |
| 1270 | #define OTPC1_CLK_EN_MASK 0x00020000 | |
| 1271 | #define OTPC1_CLK_DIV_MASK 0x00FC0000 | |
| 1272 | ||
| 1273 | /* Fields in otpprog in rev >= 21 and HND OTP */ | |
| 1274 | #define OTPP_COL_MASK 0x000000ff | |
| 1275 | #define OTPP_COL_SHIFT 0 | |
| 1276 | #define OTPP_ROW_MASK 0x0000ff00 | |
| 1277 | #define OTPP_ROW_MASK9 0x0001ff00 /* for ccrev >= 49 */ | |
| 1278 | #define OTPP_ROW_SHIFT 8 | |
| 1279 | #define OTPP_OC_MASK 0x0f000000 | |
| 1280 | #define OTPP_OC_SHIFT 24 | |
| 1281 | #define OTPP_READERR 0x10000000 | |
| 1282 | #define OTPP_VALUE_MASK 0x20000000 | |
| 1283 | #define OTPP_VALUE_SHIFT 29 | |
| 1284 | #define OTPP_START_BUSY 0x80000000 | |
| 1285 | #define OTPP_READ 0x40000000 /* HND OTP */ | |
| 1286 | ||
| 1287 | /* Fields in otplayout register */ | |
| 1288 | #define OTPL_HWRGN_OFF_MASK 0x00000FFF | |
| 1289 | #define OTPL_HWRGN_OFF_SHIFT 0 | |
| 1290 | #define OTPL_WRAP_REVID_MASK 0x00F80000 | |
| 1291 | #define OTPL_WRAP_REVID_SHIFT 19 | |
| 1292 | #define OTPL_WRAP_TYPE_MASK 0x00070000 | |
| 1293 | #define OTPL_WRAP_TYPE_SHIFT 16 | |
| 1294 | #define OTPL_WRAP_TYPE_65NM 0 | |
| 1295 | #define OTPL_WRAP_TYPE_40NM 1 | |
| 1296 | #define OTPL_WRAP_TYPE_28NM 2 | |
| 1297 | #define OTPL_WRAP_TYPE_16NM 3 | |
| 1298 | #define OTPL_ROW_SIZE_MASK 0x0000F000 | |
| 1299 | #define OTPL_ROW_SIZE_SHIFT 12 | |
| 1300 | ||
| 1301 | /* otplayout reg corerev >= 36 */ | |
| 1302 | #define OTP_CISFORMAT_NEW 0x80000000 | |
| 1303 | ||
| 1304 | /* Opcodes for OTPP_OC field */ | |
| 1305 | #define OTPPOC_READ 0 | |
| 1306 | #define OTPPOC_BIT_PROG 1 | |
| 1307 | #define OTPPOC_VERIFY 3 | |
| 1308 | #define OTPPOC_INIT 4 | |
| 1309 | #define OTPPOC_SET 5 | |
| 1310 | #define OTPPOC_RESET 6 | |
| 1311 | #define OTPPOC_OCST 7 | |
| 1312 | #define OTPPOC_ROW_LOCK 8 | |
| 1313 | #define OTPPOC_PRESCN_TEST 9 | |
| 1314 | ||
| 1315 | /* Opcodes for OTPP_OC field (40NM) */ | |
| 1316 | #define OTPPOC_READ_40NM 0 | |
| 1317 | #define OTPPOC_PROG_ENABLE_40NM 1 | |
| 1318 | #define OTPPOC_PROG_DISABLE_40NM 2 | |
| 1319 | #define OTPPOC_VERIFY_40NM 3 | |
| 1320 | #define OTPPOC_WORD_VERIFY_1_40NM 4 | |
| 1321 | #define OTPPOC_ROW_LOCK_40NM 5 | |
| 1322 | #define OTPPOC_STBY_40NM 6 | |
| 1323 | #define OTPPOC_WAKEUP_40NM 7 | |
| 1324 | #define OTPPOC_WORD_VERIFY_0_40NM 8 | |
| 1325 | #define OTPPOC_PRESCN_TEST_40NM 9 | |
| 1326 | #define OTPPOC_BIT_PROG_40NM 10 | |
| 1327 | #define OTPPOC_WORDPROG_40NM 11 | |
| 1328 | #define OTPPOC_BURNIN_40NM 12 | |
| 1329 | #define OTPPOC_AUTORELOAD_40NM 13 | |
| 1330 | #define OTPPOC_OVST_READ_40NM 14 | |
| 1331 | #define OTPPOC_OVST_PROG_40NM 15 | |
| 1332 | ||
| 1333 | /* Opcodes for OTPP_OC field (28NM) */ | |
| 1334 | #define OTPPOC_READ_28NM 0 | |
| 1335 | #define OTPPOC_READBURST_28NM 1 | |
| 1336 | #define OTPPOC_PROG_ENABLE_28NM 2 | |
| 1337 | #define OTPPOC_PROG_DISABLE_28NM 3 | |
| 1338 | #define OTPPOC_PRESCREEN_28NM 4 | |
| 1339 | #define OTPPOC_PRESCREEN_RP_28NM 5 | |
| 1340 | #define OTPPOC_FLUSH_28NM 6 | |
| 1341 | #define OTPPOC_NOP_28NM 7 | |
| 1342 | #define OTPPOC_PROG_ECC_28NM 8 | |
| 1343 | #define OTPPOC_PROG_ECC_READ_28NM 9 | |
| 1344 | #define OTPPOC_PROG_28NM 10 | |
| 1345 | #define OTPPOC_PROGRAM_RP_28NM 11 | |
| 1346 | #define OTPPOC_PROGRAM_OVST_28NM 12 | |
| 1347 | #define OTPPOC_RELOAD_28NM 13 | |
| 1348 | #define OTPPOC_ERASE_28NM 14 | |
| 1349 | #define OTPPOC_LOAD_RF_28NM 15 | |
| 1350 | #define OTPPOC_CTRL_WR_28NM 16 | |
| 1351 | #define OTPPOC_CTRL_RD_28NM 17 | |
| 1352 | #define OTPPOC_READ_HP_28NM 18 | |
| 1353 | #define OTPPOC_READ_OVST_28NM 19 | |
| 1354 | #define OTPPOC_READ_VERIFY0_28NM 20 | |
| 1355 | #define OTPPOC_READ_VERIFY1_28NM 21 | |
| 1356 | #define OTPPOC_READ_FORCE0_28NM 22 | |
| 1357 | #define OTPPOC_READ_FORCE1_28NM 23 | |
| 1358 | #define OTPPOC_BURNIN_28NM 24 | |
| 1359 | #define OTPPOC_PROGRAM_LOCK_28NM 25 | |
| 1360 | #define OTPPOC_PROGRAM_TESTCOL_28NM 26 | |
| 1361 | #define OTPPOC_READ_TESTCOL_28NM 27 | |
| 1362 | #define OTPPOC_READ_FOUT_28NM 28 | |
| 1363 | #define OTPPOC_SFT_RESET_28NM 29 | |
| 1364 | ||
| 1365 | #define OTPP_OC_MASK_28NM 0x0f800000 | |
| 1366 | #define OTPP_OC_SHIFT_28NM 23 | |
| 1367 | #define OTPC_PROGEN_28NM 0x8 | |
| 1368 | #define OTPC_DBLERRCLR 0x20 | |
| 1369 | #define OTPC_CLK_EN_MASK 0x00000040 | |
| 1370 | #define OTPC_CLK_DIV_MASK 0x00000F80 | |
| 1371 | ||
| 1372 | /* Fields in otplayoutextension */ | |
| 1373 | #define OTPLAYOUTEXT_FUSE_MASK 0x3FF | |
| 1374 | ||
| 1375 | /* Jtagm characteristics that appeared at a given corerev */ | |
| 1376 | #define JTAGM_CREV_OLD 10 /**< Old command set, 16bit max IR */ | |
| 1377 | #define JTAGM_CREV_IRP 22 /**< Able to do pause-ir */ | |
| 1378 | #define JTAGM_CREV_RTI 28 /**< Able to do return-to-idle */ | |
| 1379 | ||
| 1380 | /* jtagcmd */ | |
| 1381 | #define JCMD_START 0x80000000 | |
| 1382 | #define JCMD_BUSY 0x80000000 | |
| 1383 | #define JCMD_STATE_MASK 0x60000000 | |
| 1384 | #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */ | |
| 1385 | #define JCMD_STATE_PIR 0x20000000 /**< Pause IR */ | |
| 1386 | #define JCMD_STATE_PDR 0x40000000 /**< Pause DR */ | |
| 1387 | #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */ | |
| 1388 | #define JCMD0_ACC_MASK 0x0000f000 | |
| 1389 | #define JCMD0_ACC_IRDR 0x00000000 | |
| 1390 | #define JCMD0_ACC_DR 0x00001000 | |
| 1391 | #define JCMD0_ACC_IR 0x00002000 | |
| 1392 | #define JCMD0_ACC_RESET 0x00003000 | |
| 1393 | #define JCMD0_ACC_IRPDR 0x00004000 | |
| 1394 | #define JCMD0_ACC_PDR 0x00005000 | |
| 1395 | #define JCMD0_IRW_MASK 0x00000f00 | |
| 1396 | #define JCMD_ACC_MASK 0x000f0000 /**< Changes for corerev 11 */ | |
| 1397 | #define JCMD_ACC_IRDR 0x00000000 | |
| 1398 | #define JCMD_ACC_DR 0x00010000 | |
| 1399 | #define JCMD_ACC_IR 0x00020000 | |
| 1400 | #define JCMD_ACC_RESET 0x00030000 | |
| 1401 | #define JCMD_ACC_IRPDR 0x00040000 | |
| 1402 | #define JCMD_ACC_PDR 0x00050000 | |
| 1403 | #define JCMD_ACC_PIR 0x00060000 | |
| 1404 | #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */ | |
| 1405 | #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */ | |
| 1406 | #define JCMD_IRW_MASK 0x00001f00 | |
| 1407 | #define JCMD_IRW_SHIFT 8 | |
| 1408 | #define JCMD_DRW_MASK 0x0000003f | |
| 1409 | ||
| 1410 | /* jtagctrl */ | |
| 1411 | #define JCTRL_FORCE_CLK 4 /**< Force clock */ | |
| 1412 | #define JCTRL_EXT_EN 2 /**< Enable external targets */ | |
| 1413 | #define JCTRL_EN 1 /**< Enable Jtag master */ | |
| 1414 | #define JCTRL_TAPSEL_BIT 0x00000008 /**< JtagMasterCtrl tap_sel bit */ | |
| 1415 | ||
| 1416 | /* swdmasterctrl */ | |
| 1417 | #define SWDCTRL_INT_EN 8 /**< Enable internal targets */ | |
| 1418 | #define SWDCTRL_FORCE_CLK 4 /**< Force clock */ | |
| 1419 | #define SWDCTRL_OVJTAG 2 /**< Enable shared SWD/JTAG pins */ | |
| 1420 | #define SWDCTRL_EN 1 /**< Enable Jtag master */ | |
| 1421 | ||
| 1422 | /* Fields in clkdiv */ | |
| 1423 | #define CLKD_SFLASH 0x1f000000 | |
| 1424 | #define CLKD_SFLASH_SHIFT 24 | |
| 1425 | #define CLKD_OTP 0x000f0000 | |
| 1426 | #define CLKD_OTP_SHIFT 16 | |
| 1427 | #define CLKD_JTAG 0x00000f00 | |
| 1428 | #define CLKD_JTAG_SHIFT 8 | |
| 1429 | #define CLKD_UART 0x000000ff | |
| 1430 | ||
| 1431 | #define CLKD2_SROM 0x00000007 | |
| 1432 | #define CLKD2_SROMDIV_32 0 | |
| 1433 | #define CLKD2_SROMDIV_64 1 | |
| 1434 | #define CLKD2_SROMDIV_96 2 | |
| 1435 | #define CLKD2_SROMDIV_128 3 | |
| 1436 | #define CLKD2_SROMDIV_192 4 | |
| 1437 | #define CLKD2_SROMDIV_256 5 | |
| 1438 | #define CLKD2_SROMDIV_384 6 | |
| 1439 | #define CLKD2_SROMDIV_512 7 | |
| 1440 | #define CLKD2_SWD 0xf8000000 | |
| 1441 | #define CLKD2_SWD_SHIFT 27 | |
| 1442 | ||
| 1443 | /* intstatus/intmask */ | |
| 1444 | #define CI_GPIO 0x00000001 /**< gpio intr */ | |
| 1445 | #define CI_EI 0x00000002 /**< extif intr (corerev >= 3) */ | |
| 1446 | #define CI_TEMP 0x00000004 /**< temp. ctrl intr (corerev >= 15) */ | |
| 1447 | #define CI_SIRQ 0x00000008 /**< serial IRQ intr (corerev >= 15) */ | |
| 1448 | #define CI_ECI 0x00000010 /**< eci intr (corerev >= 21) */ | |
| 1449 | #define CI_PMU 0x00000020 /**< pmu intr (corerev >= 21) */ | |
| 1450 | #define CI_UART 0x00000040 /**< uart intr (corerev >= 21) */ | |
| 1451 | #define CI_WECI 0x00000080 /* eci wakeup intr (corerev >= 21) */ | |
| 1452 | #define CI_SPMI 0x00100000 /* SPMI (corerev >= 65) */ | |
| 1453 | #define CI_RNG 0x00200000 /**< rng intr (corerev >= 65) */ | |
| 1454 | #define CI_SSRESET_F0 0x10000000 /**< ss reset occurred */ | |
| 1455 | #define CI_SSRESET_F1 0x20000000 /**< ss reset occurred */ | |
| 1456 | #define CI_SSRESET_F2 0x40000000 /**< ss reset occurred */ | |
| 1457 | #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */ | |
| 1458 | ||
| 1459 | /* slow_clk_ctl */ | |
| 1460 | #define SCC_SS_MASK 0x00000007 /**< slow clock source mask */ | |
| 1461 | #define SCC_SS_LPO 0x00000000 /**< source of slow clock is LPO */ | |
| 1462 | #define SCC_SS_XTAL 0x00000001 /**< source of slow clock is crystal */ | |
| 1463 | #define SCC_SS_PCI 0x00000002 /**< source of slow clock is PCI */ | |
| 1464 | #define SCC_LF 0x00000200 /**< LPOFreqSel, 1: 160Khz, 0: 32KHz */ | |
| 1465 | #define SCC_LP 0x00000400 /**< LPOPowerDown, 1: LPO is disabled, | |
| 1466 | * 0: LPO is enabled | |
| 1467 | */ | |
| 1468 | #define SCC_FS 0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock, | |
| 1469 | * 0: power logic control | |
| 1470 | */ | |
| 1471 | #define SCC_IP 0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors | |
| 1472 | * PLL clock disable requests from core | |
| 1473 | */ | |
| 1474 | #define SCC_XC 0x00002000 /**< XtalControlEn, 1/0: power logic does/doesn't | |
| 1475 | * disable crystal when appropriate | |
| 1476 | */ | |
| 1477 | #define SCC_XP 0x00004000 /**< XtalPU (RO), 1/0: crystal running/disabled */ | |
| 1478 | #define SCC_CD_MASK 0xffff0000 /**< ClockDivider (SlowClk = 1/(4+divisor)) */ | |
| 1479 | #define SCC_CD_SHIFT 16 | |
| 1480 | ||
| 1481 | /* system_clk_ctl */ | |
| 1482 | #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */ | |
| 1483 | #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */ | |
| 1484 | #define SYCC_FP 0x00000004 /**< ForcePLLOn */ | |
| 1485 | #define SYCC_AR 0x00000008 /**< Force ALP (or HT if ALPen is not set */ | |
| 1486 | #define SYCC_HR 0x00000010 /**< Force HT */ | |
| 1487 | #define SYCC_CD_MASK 0xffff0000 /**< ClkDiv (ILP = 1/(4 * (divisor + 1)) */ | |
| 1488 | #define SYCC_CD_SHIFT 16 | |
| 1489 | ||
| 1490 | /* watchdogcounter */ | |
| 1491 | /* WL sub-system reset */ | |
| 1492 | #define WD_SSRESET_PCIE_F0_EN 0x10000000 | |
| 1493 | /* BT sub-system reset */ | |
| 1494 | #define WD_SSRESET_PCIE_F1_EN 0x20000000 | |
| 1495 | #define WD_SSRESET_PCIE_F2_EN 0x40000000 | |
| 1496 | /* Both WL and BT sub-system reset */ | |
| 1497 | #define WD_SSRESET_PCIE_ALL_FN_EN 0x80000000 | |
| 1498 | #define WD_COUNTER_MASK 0x0fffffff | |
| 1499 | #define WD_ENABLE_MASK \ | |
| 1500 | (WD_SSRESET_PCIE_F0_EN | WD_SSRESET_PCIE_F1_EN | \ | |
| 1501 | WD_SSRESET_PCIE_F2_EN | WD_SSRESET_PCIE_ALL_FN_EN) | |
| 1502 | ||
| 1503 | /* Indirect backplane access */ | |
| 1504 | #define BPIA_BYTEEN 0x0000000f | |
| 1505 | #define BPIA_SZ1 0x00000001 | |
| 1506 | #define BPIA_SZ2 0x00000003 | |
| 1507 | #define BPIA_SZ4 0x00000007 | |
| 1508 | #define BPIA_SZ8 0x0000000f | |
| 1509 | #define BPIA_WRITE 0x00000100 | |
| 1510 | #define BPIA_START 0x00000200 | |
| 1511 | #define BPIA_BUSY 0x00000200 | |
| 1512 | #define BPIA_ERROR 0x00000400 | |
| 1513 | ||
| 1514 | /* pcmcia/prog/flash_config */ | |
| 1515 | #define CF_EN 0x00000001 /**< enable */ | |
| 1516 | #define CF_EM_MASK 0x0000000e /**< mode */ | |
| 1517 | #define CF_EM_SHIFT 1 | |
| 1518 | #define CF_EM_FLASH 0 /**< flash/asynchronous mode */ | |
| 1519 | #define CF_EM_SYNC 2 /**< synchronous mode */ | |
| 1520 | #define CF_EM_PCMCIA 4 /**< pcmcia mode */ | |
| 1521 | #define CF_DS 0x00000010 /**< destsize: 0=8bit, 1=16bit */ | |
| 1522 | #define CF_BS 0x00000020 /**< byteswap */ | |
| 1523 | #define CF_CD_MASK 0x000000c0 /**< clock divider */ | |
| 1524 | #define CF_CD_SHIFT 6 | |
| 1525 | #define CF_CD_DIV2 0x00000000 /**< backplane/2 */ | |
| 1526 | #define CF_CD_DIV3 0x00000040 /**< backplane/3 */ | |
| 1527 | #define CF_CD_DIV4 0x00000080 /**< backplane/4 */ | |
| 1528 | #define CF_CE 0x00000100 /**< clock enable */ | |
| 1529 | #define CF_SB 0x00000200 /**< size/bytestrobe (synch only) */ | |
| 1530 | ||
| 1531 | /* pcmcia_memwait */ | |
| 1532 | #define PM_W0_MASK 0x0000003f /**< waitcount0 */ | |
| 1533 | #define PM_W1_MASK 0x00001f00 /**< waitcount1 */ | |
| 1534 | #define PM_W1_SHIFT 8 | |
| 1535 | #define PM_W2_MASK 0x001f0000 /**< waitcount2 */ | |
| 1536 | #define PM_W2_SHIFT 16 | |
| 1537 | #define PM_W3_MASK 0x1f000000 /**< waitcount3 */ | |
| 1538 | #define PM_W3_SHIFT 24 | |
| 1539 | ||
| 1540 | /* pcmcia_attrwait */ | |
| 1541 | #define PA_W0_MASK 0x0000003f /**< waitcount0 */ | |
| 1542 | #define PA_W1_MASK 0x00001f00 /**< waitcount1 */ | |
| 1543 | #define PA_W1_SHIFT 8 | |
| 1544 | #define PA_W2_MASK 0x001f0000 /**< waitcount2 */ | |
| 1545 | #define PA_W2_SHIFT 16 | |
| 1546 | #define PA_W3_MASK 0x1f000000 /**< waitcount3 */ | |
| 1547 | #define PA_W3_SHIFT 24 | |
| 1548 | ||
| 1549 | /* pcmcia_iowait */ | |
| 1550 | #define PI_W0_MASK 0x0000003f /**< waitcount0 */ | |
| 1551 | #define PI_W1_MASK 0x00001f00 /**< waitcount1 */ | |
| 1552 | #define PI_W1_SHIFT 8 | |
| 1553 | #define PI_W2_MASK 0x001f0000 /**< waitcount2 */ | |
| 1554 | #define PI_W2_SHIFT 16 | |
| 1555 | #define PI_W3_MASK 0x1f000000 /**< waitcount3 */ | |
| 1556 | #define PI_W3_SHIFT 24 | |
| 1557 | ||
| 1558 | /* prog_waitcount */ | |
| 1559 | #define PW_W0_MASK 0x0000001f /**< waitcount0 */ | |
| 1560 | #define PW_W1_MASK 0x00001f00 /**< waitcount1 */ | |
| 1561 | #define PW_W1_SHIFT 8 | |
| 1562 | #define PW_W2_MASK 0x001f0000 /**< waitcount2 */ | |
| 1563 | #define PW_W2_SHIFT 16 | |
| 1564 | #define PW_W3_MASK 0x1f000000 /**< waitcount3 */ | |
| 1565 | #define PW_W3_SHIFT 24 | |
| 1566 | ||
| 1567 | #define PW_W0 0x0000000c | |
| 1568 | #define PW_W1 0x00000a00 | |
| 1569 | #define PW_W2 0x00020000 | |
| 1570 | #define PW_W3 0x01000000 | |
| 1571 | ||
| 1572 | /* flash_waitcount */ | |
| 1573 | #define FW_W0_MASK 0x0000003f /**< waitcount0 */ | |
| 1574 | #define FW_W1_MASK 0x00001f00 /**< waitcount1 */ | |
| 1575 | #define FW_W1_SHIFT 8 | |
| 1576 | #define FW_W2_MASK 0x001f0000 /**< waitcount2 */ | |
| 1577 | #define FW_W2_SHIFT 16 | |
| 1578 | #define FW_W3_MASK 0x1f000000 /**< waitcount3 */ | |
| 1579 | #define FW_W3_SHIFT 24 | |
| 1580 | ||
| 1581 | /* When Srom support present, fields in sromcontrol */ | |
| 1582 | #define SRC_START 0x80000000 | |
| 1583 | #define SRC_BUSY 0x80000000 | |
| 1584 | #define SRC_OPCODE 0x60000000 | |
| 1585 | #define SRC_OP_READ 0x00000000 | |
| 1586 | #define SRC_OP_WRITE 0x20000000 | |
| 1587 | #define SRC_OP_WRDIS 0x40000000 | |
| 1588 | #define SRC_OP_WREN 0x60000000 | |
| 1589 | #define SRC_OTPSEL 0x00000010 | |
| 1590 | #define SRC_OTPPRESENT 0x00000020 | |
| 1591 | #define SRC_LOCK 0x00000008 | |
| 1592 | #define SRC_SIZE_MASK 0x00000006 | |
| 1593 | #define SRC_SIZE_1K 0x00000000 | |
| 1594 | #define SRC_SIZE_4K 0x00000002 | |
| 1595 | #define SRC_SIZE_16K 0x00000004 | |
| 1596 | #define SRC_SIZE_SHIFT 1 | |
| 1597 | #define SRC_PRESENT 0x00000001 | |
| 1598 | ||
| 1599 | /* Fields in pmucontrol */ | |
| 1600 | #define PCTL_ILP_DIV_MASK 0xffff0000 | |
| 1601 | #define PCTL_ILP_DIV_SHIFT 16 | |
| 1602 | #define PCTL_LQ_REQ_EN 0x00008000 | |
| 1603 | #define PCTL_PLL_PLLCTL_UPD 0x00000400 /**< rev 2 */ | |
| 1604 | #define PCTL_NOILP_ON_WAIT 0x00000200 /**< rev 1 */ | |
| 1605 | #define PCTL_HT_REQ_EN 0x00000100 | |
| 1606 | #define PCTL_ALP_REQ_EN 0x00000080 | |
| 1607 | #define PCTL_XTALFREQ_MASK 0x0000007c | |
| 1608 | #define PCTL_XTALFREQ_SHIFT 2 | |
| 1609 | #define PCTL_ILP_DIV_EN 0x00000002 | |
| 1610 | #define PCTL_LPO_SEL 0x00000001 | |
| 1611 | ||
| 1612 | /* Fields in pmucontrol_ext */ | |
| 1613 | #define PCTL_EXT_FAST_TRANS_ENAB 0x00000001u | |
| 1614 | #define PCTL_EXT_USE_LHL_TIMER 0x00000010u | |
| 1615 | #define PCTL_EXT_FASTLPO_ENAB 0x00000080u | |
| 1616 | #define PCTL_EXT_FASTLPO_SWENAB 0x00000200u | |
| 1617 | #define PCTL_EXT_FASTSEQ_ENAB 0x00001000u | |
| 1618 | #define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000u /**< rev33 for FLL1M */ | |
| 1619 | #define PCTL_EXT_FASTLPO_SB_SWENAB 0x00008000u /**< rev36 for FLL1M */ | |
| 1620 | #define PCTL_EXT_REQ_MIRROR_ENAB 0x00010000u /**< rev36 for ReqMirrorEn */ | |
| 1621 | ||
| 1622 | #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77 | |
| 1623 | ||
| 1624 | /* Retention Control */ | |
| 1625 | #define PMU_RCTL_CLK_DIV_SHIFT 0 | |
| 1626 | #define PMU_RCTL_CHAIN_LEN_SHIFT 12 | |
| 1627 | #define PMU_RCTL_MACPHY_DISABLE_SHIFT 26 | |
| 1628 | #define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) | |
| 1629 | #define PMU_RCTL_LOGIC_DISABLE_SHIFT 27 | |
| 1630 | #define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) | |
| 1631 | #define PMU_RCTL_MEMSLP_LOG_SHIFT 28 | |
| 1632 | #define PMU_RCTL_MEMSLP_LOG_MASK (1 << 28) | |
| 1633 | #define PMU_RCTL_MEMRETSLP_LOG_SHIFT 29 | |
| 1634 | #define PMU_RCTL_MEMRETSLP_LOG_MASK (1 << 29) | |
| 1635 | ||
| 1636 | /* Retention Group Control */ | |
| 1637 | #define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0 | |
| 1638 | #define PMU_RCTLGRP_RMODE_ENABLE_SHIFT 14 | |
| 1639 | #define PMU_RCTLGRP_RMODE_ENABLE_MASK (1 << 14) | |
| 1640 | #define PMU_RCTLGRP_DFT_ENABLE_SHIFT 15 | |
| 1641 | #define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15) | |
| 1642 | #define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16 | |
| 1643 | #define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16) | |
| 1644 | ||
| 1645 | /* Fields in clkstretch */ | |
| 1646 | #define CSTRETCH_HT 0xffff0000 | |
| 1647 | #define CSTRETCH_ALP 0x0000ffff | |
| 1648 | #define CSTRETCH_REDUCE_8 0x00080008 | |
| 1649 | ||
| 1650 | /* gpiotimerval */ | |
| 1651 | #define GPIO_ONTIME_SHIFT 16 | |
| 1652 | ||
| 1653 | /* clockcontrol_n */ | |
| 1654 | /* Some pll types use less than the number of bits in some of these (n or m) masks */ | |
| 1655 | #define CN_N1_MASK 0x3f /**< n1 control */ | |
| 1656 | #define CN_N2_MASK 0x3f00 /**< n2 control */ | |
| 1657 | #define CN_N2_SHIFT 8 | |
| 1658 | #define CN_PLLC_MASK 0xf0000 /**< pll control */ | |
| 1659 | #define CN_PLLC_SHIFT 16 | |
| 1660 | ||
| 1661 | /* clockcontrol_sb/pci/uart */ | |
| 1662 | #define CC_M1_MASK 0x3f /**< m1 control */ | |
| 1663 | #define CC_M2_MASK 0x3f00 /**< m2 control */ | |
| 1664 | #define CC_M2_SHIFT 8 | |
| 1665 | #define CC_M3_MASK 0x3f0000 /**< m3 control */ | |
| 1666 | #define CC_M3_SHIFT 16 | |
| 1667 | #define CC_MC_MASK 0x1f000000 /**< mux control */ | |
| 1668 | #define CC_MC_SHIFT 24 | |
| 1669 | ||
| 1670 | /* N3M Clock control magic field values */ | |
| 1671 | #define CC_F6_2 0x02 /**< A factor of 2 in */ | |
| 1672 | #define CC_F6_3 0x03 /**< 6-bit fields like */ | |
| 1673 | #define CC_F6_4 0x05 /**< N1, M1 or M3 */ | |
| 1674 | #define CC_F6_5 0x09 | |
| 1675 | #define CC_F6_6 0x11 | |
| 1676 | #define CC_F6_7 0x21 | |
| 1677 | ||
| 1678 | #define CC_F5_BIAS 5 /**< 5-bit fields get this added */ | |
| 1679 | ||
| 1680 | #define CC_MC_BYPASS 0x08 | |
| 1681 | #define CC_MC_M1 0x04 | |
| 1682 | #define CC_MC_M1M2 0x02 | |
| 1683 | #define CC_MC_M1M2M3 0x01 | |
| 1684 | #define CC_MC_M1M3 0x11 | |
| 1685 | ||
| 1686 | /* Type 2 Clock control magic field values */ | |
| 1687 | #define CC_T2_BIAS 2 /**< n1, n2, m1 & m3 bias */ | |
| 1688 | #define CC_T2M2_BIAS 3 /**< m2 bias */ | |
| 1689 | ||
| 1690 | #define CC_T2MC_M1BYP 1 | |
| 1691 | #define CC_T2MC_M2BYP 2 | |
| 1692 | #define CC_T2MC_M3BYP 4 | |
| 1693 | ||
| 1694 | /* Type 6 Clock control magic field values */ | |
| 1695 | #define CC_T6_MMASK 1 /**< bits of interest in m */ | |
| 1696 | #define CC_T6_M0 120000000 /**< sb clock for m = 0 */ | |
| 1697 | #define CC_T6_M1 100000000 /**< sb clock for m = 1 */ | |
| 1698 | #define SB2MIPS_T6(sb) (2 * (sb)) | |
| 1699 | ||
| 1700 | /* Common clock base */ | |
| 1701 | #define CC_CLOCK_BASE1 24000000 /**< Half the clock freq */ | |
| 1702 | #define CC_CLOCK_BASE2 12500000 /**< Alternate crystal on some PLLs */ | |
| 1703 | ||
| 1704 | /* Flash types in the chipcommon capabilities register */ | |
| 1705 | #define FLASH_NONE 0x000 /**< No flash */ | |
| 1706 | #define SFLASH_ST 0x100 /**< ST serial flash */ | |
| 1707 | #define SFLASH_AT 0x200 /**< Atmel serial flash */ | |
| 1708 | #define NFLASH 0x300 /**< NAND flash */ | |
| 1709 | #define PFLASH 0x700 /**< Parallel flash */ | |
| 1710 | #define QSPIFLASH_ST 0x800 | |
| 1711 | #define QSPIFLASH_AT 0x900 | |
| 1712 | ||
| 1713 | /* Bits in the ExtBus config registers */ | |
| 1714 | #define CC_CFG_EN 0x0001 /**< Enable */ | |
| 1715 | #define CC_CFG_EM_MASK 0x000e /**< Extif Mode */ | |
| 1716 | #define CC_CFG_EM_ASYNC 0x0000 /**< Async/Parallel flash */ | |
| 1717 | #define CC_CFG_EM_SYNC 0x0002 /**< Synchronous */ | |
| 1718 | #define CC_CFG_EM_PCMCIA 0x0004 /**< PCMCIA */ | |
| 1719 | #define CC_CFG_EM_IDE 0x0006 /**< IDE */ | |
| 1720 | #define CC_CFG_DS 0x0010 /**< Data size, 0=8bit, 1=16bit */ | |
| 1721 | #define CC_CFG_CD_MASK 0x00e0 /**< Sync: Clock divisor, rev >= 20 */ | |
| 1722 | #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */ | |
| 1723 | #define CC_CFG_SB 0x0200 /**< Sync: Size/Bytestrobe, rev >= 20 */ | |
| 1724 | #define CC_CFG_IS 0x0400 /**< Extif Sync Clk Select, rev >= 20 */ | |
| 1725 | ||
| 1726 | /* ExtBus address space */ | |
| 1727 | #define CC_EB_BASE 0x1a000000 /**< Chipc ExtBus base address */ | |
| 1728 | #define CC_EB_PCMCIA_MEM 0x1a000000 /**< PCMCIA 0 memory base address */ | |
| 1729 | #define CC_EB_PCMCIA_IO 0x1a200000 /**< PCMCIA 0 I/O base address */ | |
| 1730 | #define CC_EB_PCMCIA_CFG 0x1a400000 /**< PCMCIA 0 config base address */ | |
| 1731 | #define CC_EB_IDE 0x1a800000 /**< IDE memory base */ | |
| 1732 | #define CC_EB_PCMCIA1_MEM 0x1a800000 /**< PCMCIA 1 memory base address */ | |
| 1733 | #define CC_EB_PCMCIA1_IO 0x1aa00000 /**< PCMCIA 1 I/O base address */ | |
| 1734 | #define CC_EB_PCMCIA1_CFG 0x1ac00000 /**< PCMCIA 1 config base address */ | |
| 1735 | #define CC_EB_PROGIF 0x1b000000 /**< ProgIF Async/Sync base address */ | |
| 1736 | ||
| 1737 | /* Start/busy bit in flashcontrol */ | |
| 1738 | #define SFLASH_OPCODE 0x000000ff | |
| 1739 | #define SFLASH_ACTION 0x00000700 | |
| 1740 | #define SFLASH_CS_ACTIVE 0x00001000 /**< Chip Select Active, rev >= 20 */ | |
| 1741 | #define SFLASH_START 0x80000000 | |
| 1742 | #define SFLASH_BUSY SFLASH_START | |
| 1743 | ||
| 1744 | /* flashcontrol action codes */ | |
| 1745 | #define SFLASH_ACT_OPONLY 0x0000 /**< Issue opcode only */ | |
| 1746 | #define SFLASH_ACT_OP1D 0x0100 /**< opcode + 1 data byte */ | |
| 1747 | #define SFLASH_ACT_OP3A 0x0200 /**< opcode + 3 addr bytes */ | |
| 1748 | #define SFLASH_ACT_OP3A1D 0x0300 /**< opcode + 3 addr & 1 data bytes */ | |
| 1749 | #define SFLASH_ACT_OP3A4D 0x0400 /**< opcode + 3 addr & 4 data bytes */ | |
| 1750 | #define SFLASH_ACT_OP3A4X4D 0x0500 /**< opcode + 3 addr, 4 don't care & 4 data bytes */ | |
| 1751 | #define SFLASH_ACT_OP3A1X4D 0x0700 /**< opcode + 3 addr, 1 don't care & 4 data bytes */ | |
| 1752 | ||
| 1753 | /* flashcontrol action+opcodes for ST flashes */ | |
| 1754 | #define SFLASH_ST_WREN 0x0006 /**< Write Enable */ | |
| 1755 | #define SFLASH_ST_WRDIS 0x0004 /**< Write Disable */ | |
| 1756 | #define SFLASH_ST_RDSR 0x0105 /**< Read Status Register */ | |
| 1757 | #define SFLASH_ST_WRSR 0x0101 /**< Write Status Register */ | |
| 1758 | #define SFLASH_ST_READ 0x0303 /**< Read Data Bytes */ | |
| 1759 | #define SFLASH_ST_PP 0x0302 /**< Page Program */ | |
| 1760 | #define SFLASH_ST_SE 0x02d8 /**< Sector Erase */ | |
| 1761 | #define SFLASH_ST_BE 0x00c7 /**< Bulk Erase */ | |
| 1762 | #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */ | |
| 1763 | #define SFLASH_ST_RES 0x03ab /**< Read Electronic Signature */ | |
| 1764 | #define SFLASH_ST_CSA 0x1000 /**< Keep chip select asserted */ | |
| 1765 | #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */ | |
| 1766 | ||
| 1767 | #define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */ | |
| 1768 | #define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */ | |
| 1769 | #define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */ | |
| 1770 | #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */ | |
| 1771 | ||
| 1772 | #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */ | |
| 1773 | #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */ | |
| 1774 | ||
| 1775 | #define SFLASH_WINBOND_RDID 0x0390 /* Read Manufacture ID */ | |
| 1776 | #define SFLASH_WINBOND_MFID 0xef /* Winbond Manufacture ID */ | |
| 1777 | ||
| 1778 | /* Status register bits for ST flashes */ | |
| 1779 | #define SFLASH_ST_WIP 0x01 /**< Write In Progress */ | |
| 1780 | #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */ | |
| 1781 | #define SFLASH_ST_BP_MASK 0x1c /**< Block Protect */ | |
| 1782 | #define SFLASH_ST_BP_SHIFT 2 | |
| 1783 | #define SFLASH_ST_SRWD 0x80 /**< Status Register Write Disable */ | |
| 1784 | ||
| 1785 | /* flashcontrol action+opcodes for Atmel flashes */ | |
| 1786 | #define SFLASH_AT_READ 0x07e8 | |
| 1787 | #define SFLASH_AT_PAGE_READ 0x07d2 | |
| 1788 | /* PR9631: impossible to specify Atmel Buffer Read command */ | |
| 1789 | #define SFLASH_AT_BUF1_READ | |
| 1790 | #define SFLASH_AT_BUF2_READ | |
| 1791 | #define SFLASH_AT_STATUS 0x01d7 | |
| 1792 | #define SFLASH_AT_BUF1_WRITE 0x0384 | |
| 1793 | #define SFLASH_AT_BUF2_WRITE 0x0387 | |
| 1794 | #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 | |
| 1795 | #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 | |
| 1796 | #define SFLASH_AT_BUF1_PROGRAM 0x0288 | |
| 1797 | #define SFLASH_AT_BUF2_PROGRAM 0x0289 | |
| 1798 | #define SFLASH_AT_PAGE_ERASE 0x0281 | |
| 1799 | #define SFLASH_AT_BLOCK_ERASE 0x0250 | |
| 1800 | #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 | |
| 1801 | #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 | |
| 1802 | #define SFLASH_AT_BUF1_LOAD 0x0253 | |
| 1803 | #define SFLASH_AT_BUF2_LOAD 0x0255 | |
| 1804 | #define SFLASH_AT_BUF1_COMPARE 0x0260 | |
| 1805 | #define SFLASH_AT_BUF2_COMPARE 0x0261 | |
| 1806 | #define SFLASH_AT_BUF1_REPROGRAM 0x0258 | |
| 1807 | #define SFLASH_AT_BUF2_REPROGRAM 0x0259 | |
| 1808 | ||
| 1809 | /* Status register bits for Atmel flashes */ | |
| 1810 | #define SFLASH_AT_READY 0x80 | |
| 1811 | #define SFLASH_AT_MISMATCH 0x40 | |
| 1812 | #define SFLASH_AT_ID_MASK 0x38 | |
| 1813 | #define SFLASH_AT_ID_SHIFT 3 | |
| 1814 | ||
| 1815 | /* SPI register bits, corerev >= 37 */ | |
| 1816 | #define GSIO_START 0x80000000u | |
| 1817 | #define GSIO_BUSY GSIO_START | |
| 1818 | ||
| 1819 | /* UART Function sel related */ | |
| 1820 | #define MUXENAB_DEF_UART_MASK 0x0000000fu | |
| 1821 | #define MUXENAB_DEF_UART_SHIFT 0 | |
| 1822 | ||
| 1823 | /* HOST_WAKE Function sel related */ | |
| 1824 | #define MUXENAB_DEF_HOSTWAKE_MASK 0x000000f0u /**< configure GPIO for host_wake */ | |
| 1825 | #define MUXENAB_DEF_HOSTWAKE_SHIFT 4u | |
| 1826 | ||
| 1827 | /* GCI UART Function sel related */ | |
| 1828 | #define MUXENAB_GCI_UART_MASK 0x00000f00u | |
| 1829 | #define MUXENAB_GCI_UART_SHIFT 8u | |
| 1830 | #define MUXENAB_GCI_UART_FNSEL_MASK 0x00003000u | |
| 1831 | #define MUXENAB_GCI_UART_FNSEL_SHIFT 12u | |
| 1832 | ||
| 1833 | /* Mask used to decide whether MUX to be performed or not */ | |
| 1834 | #define MUXENAB_DEF_GETIX(val, name) \ | |
| 1835 | ((((val) & MUXENAB_DEF_ ## name ## _MASK) >> MUXENAB_DEF_ ## name ## _SHIFT) - 1) | |
| 1836 | ||
| 1837 | /* | |
| 1838 | * These are the UART port assignments, expressed as offsets from the base | |
| 1839 | * register. These assignments should hold for any serial port based on | |
| 1840 | * a 8250, 16450, or 16550(A). | |
| 1841 | */ | |
| 1842 | ||
| 1843 | #define UART_RX 0 /**< In: Receive buffer (DLAB=0) */ | |
| 1844 | #define UART_TX 0 /**< Out: Transmit buffer (DLAB=0) */ | |
| 1845 | #define UART_DLL 0 /**< Out: Divisor Latch Low (DLAB=1) */ | |
| 1846 | #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */ | |
| 1847 | #define UART_DLM 1 /**< Out: Divisor Latch High (DLAB=1) */ | |
| 1848 | #define UART_IIR 2 /**< In: Interrupt Identity Register */ | |
| 1849 | #define UART_FCR 2 /**< Out: FIFO Control Register */ | |
| 1850 | #define UART_LCR 3 /**< Out: Line Control Register */ | |
| 1851 | #define UART_MCR 4 /**< Out: Modem Control Register */ | |
| 1852 | #define UART_LSR 5 /**< In: Line Status Register */ | |
| 1853 | #define UART_MSR 6 /**< In: Modem Status Register */ | |
| 1854 | #define UART_SCR 7 /**< I/O: Scratch Register */ | |
| 1855 | #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ | |
| 1856 | #define UART_LCR_WLEN8 0x03 /**< Word length: 8 bits */ | |
| 1857 | #define UART_MCR_OUT2 0x08 /**< MCR GPIO out 2 */ | |
| 1858 | #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ | |
| 1859 | #define UART_LSR_RX_FIFO 0x80 /**< Receive FIFO error */ | |
| 1860 | #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */ | |
| 1861 | #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ | |
| 1862 | #define UART_LSR_BREAK 0x10 /**< Break interrupt */ | |
| 1863 | #define UART_LSR_FRAMING 0x08 /**< Framing error */ | |
| 1864 | #define UART_LSR_PARITY 0x04 /**< Parity error */ | |
| 1865 | #define UART_LSR_OVERRUN 0x02 /**< Overrun error */ | |
| 1866 | #define UART_LSR_RXRDY 0x01 /**< Receiver ready */ | |
| 1867 | #define UART_FCR_FIFO_ENABLE 1 /**< FIFO control register bit controlling FIFO enable/disable */ | |
| 1868 | ||
| 1869 | /* Interrupt Identity Register (IIR) bits */ | |
| 1870 | #define UART_IIR_FIFO_MASK 0xc0 /**< IIR FIFO disable/enabled mask */ | |
| 1871 | #define UART_IIR_INT_MASK 0xf /**< IIR interrupt ID source */ | |
| 1872 | #define UART_IIR_MDM_CHG 0x0 /**< Modem status changed */ | |
| 1873 | #define UART_IIR_NOINT 0x1 /**< No interrupt pending */ | |
| 1874 | #define UART_IIR_THRE 0x2 /**< THR empty */ | |
| 1875 | #define UART_IIR_RCVD_DATA 0x4 /**< Received data available */ | |
| 1876 | #define UART_IIR_RCVR_STATUS 0x6 /**< Receiver status */ | |
| 1877 | #define UART_IIR_CHAR_TIME 0xc /**< Character time */ | |
| 1878 | ||
| 1879 | /* Interrupt Enable Register (IER) bits */ | |
| 1880 | #define UART_IER_PTIME 128 /**< Programmable THRE Interrupt Mode Enable */ | |
| 1881 | #define UART_IER_EDSSI 8 /**< enable modem status interrupt */ | |
| 1882 | #define UART_IER_ELSI 4 /**< enable receiver line status interrupt */ | |
| 1883 | #define UART_IER_ETBEI 2 /**< enable transmitter holding register empty interrupt */ | |
| 1884 | #define UART_IER_ERBFI 1 /**< enable data available interrupt */ | |
| 1885 | ||
| 1886 | /* pmustatus */ | |
| 1887 | #define PST_SLOW_WR_PENDING 0x0400 | |
| 1888 | #define PST_EXTLPOAVAIL 0x0100 | |
| 1889 | #define PST_WDRESET 0x0080 | |
| 1890 | #define PST_INTPEND 0x0040 | |
| 1891 | #define PST_SBCLKST 0x0030 | |
| 1892 | #define PST_SBCLKST_ILP 0x0010 | |
| 1893 | #define PST_SBCLKST_ALP 0x0020 | |
| 1894 | #define PST_SBCLKST_HT 0x0030 | |
| 1895 | #define PST_ALPAVAIL 0x0008 | |
| 1896 | #define PST_HTAVAIL 0x0004 | |
| 1897 | #define PST_RESINIT 0x0003 | |
| 1898 | #define PST_ILPFASTLPO 0x00010000 | |
| 1899 | ||
| 1900 | /* pmucapabilities */ | |
| 1901 | #define PCAP_REV_MASK 0x000000ff | |
| 1902 | #define PCAP_RC_MASK 0x00001f00 | |
| 1903 | #define PCAP_RC_SHIFT 8 | |
| 1904 | #define PCAP_TC_MASK 0x0001e000 | |
| 1905 | #define PCAP_TC_SHIFT 13 | |
| 1906 | #define PCAP_PC_MASK 0x001e0000 | |
| 1907 | #define PCAP_PC_SHIFT 17 | |
| 1908 | #define PCAP_VC_MASK 0x01e00000 | |
| 1909 | #define PCAP_VC_SHIFT 21 | |
| 1910 | #define PCAP_CC_MASK 0x1e000000 | |
| 1911 | #define PCAP_CC_SHIFT 25 | |
| 1912 | #define PCAP5_PC_MASK 0x003e0000 /**< PMU corerev >= 5 */ | |
| 1913 | #define PCAP5_PC_SHIFT 17 | |
| 1914 | #define PCAP5_VC_MASK 0x07c00000 | |
| 1915 | #define PCAP5_VC_SHIFT 22 | |
| 1916 | #define PCAP5_CC_MASK 0xf8000000 | |
| 1917 | #define PCAP5_CC_SHIFT 27 | |
| 1918 | ||
| 1919 | /* pmucapabilities ext */ | |
| 1920 | #define PCAP_EXT_ST_NUM_SHIFT (8) /* stat timer number */ | |
| 1921 | #define PCAP_EXT_ST_NUM_MASK (0xf << PCAP_EXT_ST_NUM_SHIFT) | |
| 1922 | #define PCAP_EXT_ST_SRC_NUM_SHIFT (12) /* stat timer source number */ | |
| 1923 | #define PCAP_EXT_ST_SRC_NUM_MASK (0xf << PCAP_EXT_ST_SRC_NUM_SHIFT) | |
| 1924 | #define PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_SHIFT (20u) /* # of MAC rsrc req timers */ | |
| 1925 | #define PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_MASK (7u << PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_SHIFT) | |
| 1926 | #define PCAP_EXT_PMU_INTR_RCVR_CNT_SHIFT (23u) /* pmu int rcvr cnt */ | |
| 1927 | #define PCAP_EXT_PMU_INTR_RCVR_CNT_MASK (7u << PCAP_EXT_PMU_INTR_RCVR_CNT_SHIFT) | |
| 1928 | ||
| 1929 | /* pmustattimer ctrl */ | |
| 1930 | #define PMU_ST_SRC_SHIFT (0) /* stat timer source number */ | |
| 1931 | #define PMU_ST_SRC_MASK (0xff << PMU_ST_SRC_SHIFT) | |
| 1932 | #define PMU_ST_CNT_MODE_SHIFT (10) /* stat timer count mode */ | |
| 1933 | #define PMU_ST_CNT_MODE_MASK (0x3 << PMU_ST_CNT_MODE_SHIFT) | |
| 1934 | #define PMU_ST_EN_SHIFT (8) /* stat timer enable */ | |
| 1935 | #define PMU_ST_EN_MASK (0x1 << PMU_ST_EN_SHIFT) | |
| 1936 | #define PMU_ST_ENAB 1 | |
| 1937 | #define PMU_ST_DISAB 0 | |
| 1938 | #define PMU_ST_INT_EN_SHIFT (9) /* stat timer enable */ | |
| 1939 | #define PMU_ST_INT_EN_MASK (0x1 << PMU_ST_INT_EN_SHIFT) | |
| 1940 | #define PMU_ST_INT_ENAB 1 | |
| 1941 | #define PMU_ST_INT_DISAB 0 | |
| 1942 | ||
| 1943 | /* CoreCapabilitiesExtension */ | |
| 1944 | #define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000 | |
| 1945 | ||
| 1946 | /* PMU Resource Request Timer registers */ | |
| 1947 | /* This is based on PmuRev0 */ | |
| 1948 | #define PRRT_TIME_MASK 0x03ff | |
| 1949 | #define PRRT_INTEN 0x0400 | |
| 1950 | /* ReqActive 25 | |
| 1951 | * The hardware sets this field to 1 when the timer expires. | |
| 1952 | * Software writes this field to 1 to make immediate resource requests. | |
| 1953 | */ | |
| 1954 | #define PRRT_REQ_ACTIVE 0x0800 /* To check h/w status */ | |
| 1955 | #define PRRT_IMMEDIATE_RES_REQ 0x0800 /* macro for sw immediate res req */ | |
| 1956 | #define PRRT_ALP_REQ 0x1000 | |
| 1957 | #define PRRT_HT_REQ 0x2000 | |
| 1958 | #define PRRT_HQ_REQ 0x4000 | |
| 1959 | ||
| 1960 | /* PMU Int Control register bits */ | |
| 1961 | #define PMU_INTC_ALP_REQ 0x1 | |
| 1962 | #define PMU_INTC_HT_REQ 0x2 | |
| 1963 | #define PMU_INTC_HQ_REQ 0x4 | |
| 1964 | ||
| 1965 | /* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */ | |
| 1966 | #define RSRC_INTR_MASK_TIMER_INT_0 1 | |
| 1967 | #define PMU_INTR_MASK_EXTWAKE_REQ_ACTIVE_0 (1 << 20) | |
| 1968 | ||
| 1969 | #define PMU_INT_STAT_RSRC_EVENT_INT0_SHIFT (8u) | |
| 1970 | #define PMU_INT_STAT_RSRC_EVENT_INT0_MASK (1u << PMU_INT_STAT_RSRC_EVENT_INT0_SHIFT) | |
| 1971 | ||
| 1972 | /* bit 16 of the PMU interrupt vector - Stats Timer Interrupt */ | |
| 1973 | #define PMU_INT_STAT_TIMER_INT_SHIFT (16u) | |
| 1974 | #define PMU_INT_STAT_TIMER_INT_MASK (1u << PMU_INT_STAT_TIMER_INT_SHIFT) | |
| 1975 | ||
| 1976 | /* | |
| 1977 | * bit 18 of the PMU interrupt vector - S/R self test fails | |
| 1978 | */ | |
| 1979 | #define PMU_INT_STAT_SR_ERR_SHIFT (18u) | |
| 1980 | #define PMU_INT_STAT_SR_ERR_MASK (1u << PMU_INT_STAT_SR_ERR_SHIFT) | |
| 1981 | ||
| 1982 | /* PMU resource bit position */ | |
| 1983 | #define PMURES_BIT(bit) (1 << (bit)) | |
| 1984 | ||
| 1985 | /* PMU resource number limit */ | |
| 1986 | #define PMURES_MAX_RESNUM 30 | |
| 1987 | ||
| 1988 | /* PMU chip control0 register */ | |
| 1989 | #define PMU_CHIPCTL0 0 | |
| 1990 | ||
| 1991 | #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) | |
| 1992 | #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) | |
| 1993 | #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0xF << 6) | |
| 1994 | #define PMU_CC0_4369B0_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6) | |
| 1995 | #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) | |
| 1996 | #define PMU_CC0_4369_XTAL_RES_BYPASS_START_VAL (0 << 12) | |
| 1997 | #define PMU_CC0_4369_XTAL_RES_BYPASS_START_MASK (0x7 << 12) | |
| 1998 | #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_VAL (0x1 << 15) | |
| 1999 | #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) | |
| 2000 | ||
| 2001 | // This is not used. so retains reset value | |
| 2002 | #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20u << 0u) | |
| 2003 | ||
| 2004 | #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3Fu << 0u) | |
| 2005 | #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1Au << 6u) | |
| 2006 | #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3Fu << 6u) | |
| 2007 | #define PMU_CC0_4362_XTAL_RES_BYPASS_START_VAL (0x00u << 12u) | |
| 2008 | #define PMU_CC0_4362_XTAL_RES_BYPASS_START_MASK (0x07u << 12u) | |
| 2009 | #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_VAL (0x02u << 15u) | |
| 2010 | #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_MASK (0x07u << 15u) | |
| 2011 | ||
| 2012 | #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) | |
| 2013 | #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) | |
| 2014 | #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6) | |
| 2015 | #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) | |
| 2016 | #define PMU_CC0_4378_XTAL_RES_BYPASS_START_VAL (0 << 12) | |
| 2017 | #define PMU_CC0_4378_XTAL_RES_BYPASS_START_MASK (0x7 << 12) | |
| 2018 | #define PMU_CC0_4378_XTAL_RES_BYPASS_NORMAL_VAL (0x2 << 15) | |
| 2019 | #define PMU_CC0_4378_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) | |
| 2020 | ||
| 2021 | #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) | |
| 2022 | #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) | |
| 2023 | #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6) | |
| 2024 | #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) | |
| 2025 | #define PMU_CC0_4387_XTAL_RES_BYPASS_START_VAL (0 << 12) | |
| 2026 | #define PMU_CC0_4387_XTAL_RES_BYPASS_START_MASK (0x7 << 12) | |
| 2027 | #define PMU_CC0_4387_XTAL_RES_BYPASS_NORMAL_VAL (0x2 << 15) | |
| 2028 | #define PMU_CC0_4387_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) | |
| 2029 | #define PMU_CC0_4387_BT_PU_WAKE_MASK (0x3u << 30u) | |
| 2030 | ||
| 2031 | /* clock req types */ | |
| 2032 | #define PMU_CC1_CLKREQ_TYPE_SHIFT 19 | |
| 2033 | #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT) | |
| 2034 | ||
| 2035 | #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0 | |
| 2036 | #define CLKREQ_TYPE_CONFIG_PUSHPULL 1 | |
| 2037 | ||
| 2038 | /* Power Control */ | |
| 2039 | #define PWRCTL_ENAB_MEM_CLK_GATE_SHIFT 5 | |
| 2040 | #define PWRCTL_FORCE_HW_PWR_REQ_OFF_SHIFT 6 | |
| 2041 | #define PWRCTL_AUTO_MEM_STBYRET 28 | |
| 2042 | ||
| 2043 | /* PMU chip control1 register */ | |
| 2044 | #define PMU_CHIPCTL1 1 | |
| 2045 | #define PMU_CC1_RXC_DLL_BYPASS 0x00010000 | |
| 2046 | #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010 | |
| 2047 | ||
| 2048 | #define PMU_CC1_IF_TYPE_MASK 0x00000030 | |
| 2049 | #define PMU_CC1_IF_TYPE_RMII 0x00000000 | |
| 2050 | #define PMU_CC1_IF_TYPE_MII 0x00000010 | |
| 2051 | #define PMU_CC1_IF_TYPE_RGMII 0x00000020 | |
| 2052 | ||
| 2053 | #define PMU_CC1_SW_TYPE_MASK 0x000000c0 | |
| 2054 | #define PMU_CC1_SW_TYPE_EPHY 0x00000000 | |
| 2055 | #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 | |
| 2056 | #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 | |
| 2057 | #define PMU_CC1_SW_TYPE_RGMII 0x000000c0 | |
| 2058 | ||
| 2059 | #define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080 | |
| 2060 | #define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000 | |
| 2061 | ||
| 2062 | #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK 0x00003F00u | |
| 2063 | #ifdef BCM_FASTLPO_PMU | |
| 2064 | #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00002000u | |
| 2065 | #else | |
| 2066 | #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00000400u | |
| 2067 | #endif /* BCM_FASTLPO_PMU */ | |
| 2068 | ||
| 2069 | /* PMU chip control2 register */ | |
| 2070 | #define PMU_CC2_CB2WL_INTR_PWRREQ_EN (1u << 13u) | |
| 2071 | #define PMU_CC2_RFLDO3P3_PU_FORCE_ON (1u << 15u) | |
| 2072 | #define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000u | |
| 2073 | ||
| 2074 | #define PMU_CC2_WL2CDIG_I_PMU_SLEEP (1u << 16u) | |
| 2075 | #define PMU_CHIPCTL2 2u | |
| 2076 | #define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1u << 18u) | |
| 2077 | #define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1u << 19u) | |
| 2078 | #define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1u << 20u) | |
| 2079 | #define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1u << 21u) | |
| 2080 | #define PMU_CC2_MASK_WL_DEV_WAKE (1u << 22u) | |
| 2081 | #define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE (1u << 25u) | |
| 2082 | #define PMU_CC2_GCI2_WAKE (1u << 31u) | |
| 2083 | ||
| 2084 | #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) | |
| 2085 | #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) | |
| 2086 | #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) | |
| 2087 | #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) | |
| 2088 | ||
| 2089 | #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) | |
| 2090 | #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) | |
| 2091 | #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) | |
| 2092 | #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) | |
| 2093 | ||
| 2094 | #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) | |
| 2095 | #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) | |
| 2096 | #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) | |
| 2097 | #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) | |
| 2098 | ||
| 2099 | #define PMU_CC2_4368_SR_RET_ENABLE (0x7u << 14u) | |
| 2100 | #define PMU_CC2_4368_WLAN2CB_INT_PWR_MASK (1u << 13u) | |
| 2101 | #define PMU_CC2_4368_WLAN2CB_INT_PWR_SHIFT 13u | |
| 2102 | ||
| 2103 | #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) | |
| 2104 | #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) | |
| 2105 | #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) | |
| 2106 | #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) | |
| 2107 | ||
| 2108 | /* PMU chip control3 register */ | |
| 2109 | #define PMU_CHIPCTL3 3u | |
| 2110 | #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19u | |
| 2111 | #define PMU_CC3_ENABLE_RF_SHIFT 22u | |
| 2112 | #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23u | |
| 2113 | ||
| 2114 | #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u) | |
| 2115 | #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u) | |
| 2116 | #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u) | |
| 2117 | #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u) | |
| 2118 | #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u) | |
| 2119 | #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u) | |
| 2120 | #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21) | |
| 2121 | #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21) | |
| 2122 | #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2u << 12u) | |
| 2123 | #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7u << 12u) | |
| 2124 | #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x2u << 27u) | |
| 2125 | #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7u << 27u) | |
| 2126 | ||
| 2127 | #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u) | |
| 2128 | #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u) | |
| 2129 | #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u) | |
| 2130 | #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u) | |
| 2131 | #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u) | |
| 2132 | #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u) | |
| 2133 | #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21u) | |
| 2134 | #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21u) | |
| 2135 | #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_VAL (0x02u << 12u) | |
| 2136 | #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_MASK (0x07u << 12u) | |
| 2137 | /* Changed from 6 to 4 for wlan PHN and to 2 for BT PER issues */ | |
| 2138 | #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_VAL (0x02u << 27u) | |
| 2139 | #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_MASK (0x07u << 27u) | |
| 2140 | ||
| 2141 | #define PMU_CC3_4378_XTALCORESIZE_PMOS_START_VAL (0x3F << 0) | |
| 2142 | #define PMU_CC3_4378_XTALCORESIZE_PMOS_START_MASK (0x3F << 0) | |
| 2143 | #define PMU_CC3_4378_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15) | |
| 2144 | #define PMU_CC3_4378_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15) | |
| 2145 | #define PMU_CC3_4378_XTALCORESIZE_NMOS_START_VAL (0x3F << 6) | |
| 2146 | #define PMU_CC3_4378_XTALCORESIZE_NMOS_START_MASK (0x3F << 6) | |
| 2147 | #define PMU_CC3_4378_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21) | |
| 2148 | #define PMU_CC3_4378_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21) | |
| 2149 | #define PMU_CC3_4378_XTALSEL_BIAS_RES_START_VAL (0x2 << 12) | |
| 2150 | #define PMU_CC3_4378_XTALSEL_BIAS_RES_START_MASK (0x7 << 12) | |
| 2151 | #define PMU_CC3_4378_XTALSEL_BIAS_RES_NORMAL_VAL (0x2 << 27) | |
| 2152 | #define PMU_CC3_4378_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27) | |
| 2153 | ||
| 2154 | #define PMU_CC3_4387_XTALCORESIZE_PMOS_START_VAL (0x3F << 0) | |
| 2155 | #define PMU_CC3_4387_XTALCORESIZE_PMOS_START_MASK (0x3F << 0) | |
| 2156 | #define PMU_CC3_4387_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15) | |
| 2157 | #define PMU_CC3_4387_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15) | |
| 2158 | #define PMU_CC3_4387_XTALCORESIZE_NMOS_START_VAL (0x3F << 6) | |
| 2159 | #define PMU_CC3_4387_XTALCORESIZE_NMOS_START_MASK (0x3F << 6) | |
| 2160 | #define PMU_CC3_4387_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21) | |
| 2161 | #define PMU_CC3_4387_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21) | |
| 2162 | #define PMU_CC3_4387_XTALSEL_BIAS_RES_START_VAL (0x2 << 12) | |
| 2163 | #define PMU_CC3_4387_XTALSEL_BIAS_RES_START_MASK (0x7 << 12) | |
| 2164 | #define PMU_CC3_4387_XTALSEL_BIAS_RES_NORMAL_VAL (0x5 << 27) | |
| 2165 | #define PMU_CC3_4387_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27) | |
| 2166 | ||
| 2167 | /* PMU chip control4 register */ | |
| 2168 | #define PMU_CHIPCTL4 4 | |
| 2169 | ||
| 2170 | /* 53537 series moved switch_type and gmac_if_type to CC4 [15:14] and [13:12] */ | |
| 2171 | #define PMU_CC4_IF_TYPE_MASK 0x00003000 | |
| 2172 | #define PMU_CC4_IF_TYPE_RMII 0x00000000 | |
| 2173 | #define PMU_CC4_IF_TYPE_MII 0x00001000 | |
| 2174 | #define PMU_CC4_IF_TYPE_RGMII 0x00002000 | |
| 2175 | ||
| 2176 | #define PMU_CC4_SW_TYPE_MASK 0x0000c000 | |
| 2177 | #define PMU_CC4_SW_TYPE_EPHY 0x00000000 | |
| 2178 | #define PMU_CC4_SW_TYPE_EPHYMII 0x00004000 | |
| 2179 | #define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000 | |
| 2180 | #define PMU_CC4_SW_TYPE_RGMII 0x0000c000 | |
| 2181 | #define PMU_CC4_DISABLE_LQ_AVAIL (1<<27) | |
| 2182 | ||
| 2183 | #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) | |
| 2184 | #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) | |
| 2185 | #define PMU_CC4_4369_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) | |
| 2186 | #define PMU_CC4_4369_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) | |
| 2187 | ||
| 2188 | #define PMU_CC4_4369_AUX_PD_CBUCK2VDDB_ON (1u << 21u) | |
| 2189 | #define PMU_CC4_4369_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) | |
| 2190 | #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) | |
| 2191 | #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) | |
| 2192 | ||
| 2193 | #define PMU_CC4_4362_PD_CBUCK2VDDB_ON (1u << 15u) | |
| 2194 | #define PMU_CC4_4362_PD_CBUCK2VDDRET_ON (1u << 16u) | |
| 2195 | #define PMU_CC4_4362_PD_MEMLPLDO2VDDB_ON (1u << 17u) | |
| 2196 | #define PMU_CC4_4362_PD_MEMLPDLO2VDDRET_ON (1u << 18u) | |
| 2197 | ||
| 2198 | #define PMU_CC4_4378_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) | |
| 2199 | #define PMU_CC4_4378_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) | |
| 2200 | #define PMU_CC4_4378_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) | |
| 2201 | #define PMU_CC4_4378_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) | |
| 2202 | ||
| 2203 | #define PMU_CC4_4378_AUX_PD_CBUCK2VDDB_ON (1u << 21u) | |
| 2204 | #define PMU_CC4_4378_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) | |
| 2205 | #define PMU_CC4_4378_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) | |
| 2206 | #define PMU_CC4_4378_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) | |
| 2207 | ||
| 2208 | #define PMU_CC4_4387_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) | |
| 2209 | #define PMU_CC4_4387_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) | |
| 2210 | #define PMU_CC4_4387_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) | |
| 2211 | #define PMU_CC4_4387_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) | |
| 2212 | ||
| 2213 | #define PMU_CC4_4387_AUX_PD_CBUCK2VDDB_ON (1u << 21u) | |
| 2214 | #define PMU_CC4_4387_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) | |
| 2215 | #define PMU_CC4_4387_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) | |
| 2216 | #define PMU_CC4_4387_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) | |
| 2217 | ||
| 2218 | /* PMU chip control5 register */ | |
| 2219 | #define PMU_CHIPCTL5 5 | |
| 2220 | ||
| 2221 | #define PMU_CC5_4369_SUBCORE_CBUCK2VDDB_ON (1u << 9u) | |
| 2222 | #define PMU_CC5_4369_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) | |
| 2223 | #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) | |
| 2224 | #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) | |
| 2225 | ||
| 2226 | #define PMU_CC5_4362_SUBCORE_CBUCK2VDDB_ON (1u << 9u) | |
| 2227 | #define PMU_CC5_4362_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) | |
| 2228 | #define PMU_CC5_4362_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) | |
| 2229 | #define PMU_CC5_4362_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) | |
| 2230 | ||
| 2231 | #define PMU_CC5_4378_SUBCORE_CBUCK2VDDB_ON (1u << 9u) | |
| 2232 | #define PMU_CC5_4378_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) | |
| 2233 | #define PMU_CC5_4378_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) | |
| 2234 | #define PMU_CC5_4378_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) | |
| 2235 | ||
| 2236 | #define PMU_CC5_4387_SUBCORE_CBUCK2VDDB_ON (1u << 9u) | |
| 2237 | #define PMU_CC5_4387_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) | |
| 2238 | #define PMU_CC5_4387_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) | |
| 2239 | #define PMU_CC5_4387_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) | |
| 2240 | ||
| 2241 | #define PMU_CC5_4389_SUBCORE_SDTCCLK0_ON (1u << 3u) | |
| 2242 | #define PMU_CC5_4389_SUBCORE_SDTCCLK1_ON (1u << 4u) | |
| 2243 | ||
| 2244 | /* PMU chip control6 register */ | |
| 2245 | #define PMU_CHIPCTL6 6 | |
| 2246 | #define PMU_CC6_RX4_CLK_SEQ_SELECT_MASK BCM_MASK32(1u, 0u) | |
| 2247 | #define PMU_CC6_ENABLE_DMN1_WAKEUP (1 << 3) | |
| 2248 | #define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4) | |
| 2249 | #define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6) | |
| 2250 | #define PMU_CC6_ENABLE_PCIE_RETENTION (1 << 12) | |
| 2251 | #define PMU_CC6_ENABLE_PMU_EXT_PERST (1 << 13) | |
| 2252 | #define PMU_CC6_ENABLE_PMU_WAKEUP_PERST (1 << 14) | |
| 2253 | #define PMU_CC6_ENABLE_LEGACY_WAKEUP (1 << 16) | |
| 2254 | ||
| 2255 | /* PMU chip control7 register */ | |
| 2256 | #define PMU_CHIPCTL7 7 | |
| 2257 | #define PMU_CC7_ENABLE_L2REFCLKPAD_PWRDWN (1 << 25) | |
| 2258 | #define PMU_CC7_ENABLE_MDIO_RESET_WAR (1 << 27) | |
| 2259 | /* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */ | |
| 2260 | #define PMU_CC7_IF_TYPE_MASK 0x000000c0 | |
| 2261 | #define PMU_CC7_IF_TYPE_RMII 0x00000000 | |
| 2262 | #define PMU_CC7_IF_TYPE_MII 0x00000040 | |
| 2263 | #define PMU_CC7_IF_TYPE_RGMII 0x00000080 | |
| 2264 | ||
| 2265 | #define PMU_CHIPCTL8 8 | |
| 2266 | #define PMU_CHIPCTL9 9 | |
| 2267 | ||
| 2268 | #define PMU_CHIPCTL10 10 | |
| 2269 | #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_SHIFT 0 | |
| 2270 | #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_MASK 0x000000ff | |
| 2271 | #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_SHIFT 8 | |
| 2272 | #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_MASK 0x0000ff00 | |
| 2273 | #define PMU_CC10_PCIE_PWRSW_UP_DLY_SHIFT 16 | |
| 2274 | #define PMU_CC10_PCIE_PWRSW_UP_DLY_MASK 0x000f0000 | |
| 2275 | #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_SHIFT 20 | |
| 2276 | #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_MASK 0x00f00000 | |
| 2277 | #define PMU_CC10_FORCE_PCIE_ON (1 << 24) | |
| 2278 | #define PMU_CC10_FORCE_PCIE_SW_ON (1 << 25) | |
| 2279 | #define PMU_CC10_FORCE_PCIE_RETNT_ON (1 << 26) | |
| 2280 | ||
| 2281 | #define PMU_CC10_4368_FORCE_PCIE_RETNT_ON (1 << 25) | |
| 2282 | ||
| 2283 | #define PMU_CC10_PCIE_PWRSW_RESET_CNT_4US 1 | |
| 2284 | #define PMU_CC10_PCIE_PWRSW_RESET_CNT_8US 2 | |
| 2285 | ||
| 2286 | #define PMU_CC10_PCIE_PWRSW_UP_DLY_0US 0 | |
| 2287 | ||
| 2288 | #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_4US 1 | |
| 2289 | #define PMU_CC10_PCIE_RESET0_CNT_SLOW_MASK (0xFu << 4u) | |
| 2290 | #define PMU_CC10_PCIE_RESET1_CNT_SLOW_MASK (0xFu << 12u) | |
| 2291 | ||
| 2292 | #define PMU_CHIPCTL11 11 | |
| 2293 | ||
| 2294 | /* PMU chip control12 register */ | |
| 2295 | #define PMU_CHIPCTL12 12 | |
| 2296 | #define PMU_CC12_DISABLE_LQ_CLK_ON (1u << 31u) /* HW4387-254 */ | |
| 2297 | ||
| 2298 | /* PMU chip control13 register */ | |
| 2299 | #define PMU_CHIPCTL13 13 | |
| 2300 | ||
| 2301 | #define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u) | |
| 2302 | #define PMU_CC13_SUBCORE_CBUCK2VDDRET_OFF (1u << 1u) | |
| 2303 | #define PMU_CC13_SUBCORE_MEMLPLDO2VDDB_OFF (1u << 2u) | |
| 2304 | #define PMU_CC13_SUBCORE_MEMLPLDO2VDDRET_OFF (1u << 3u) | |
| 2305 | ||
| 2306 | #define PMU_CC13_MAIN_CBUCK2VDDB_OFF (1u << 4u) | |
| 2307 | #define PMU_CC13_MAIN_CBUCK2VDDRET_OFF (1u << 5u) | |
| 2308 | #define PMU_CC13_MAIN_MEMLPLDO2VDDB_OFF (1u << 6u) | |
| 2309 | #define PMU_CC13_MAIN_MEMLPLDO2VDDRET_OFF (1u << 7u) | |
| 2310 | ||
| 2311 | #define PMU_CC13_AUX_CBUCK2VDDB_OFF (1u << 8u) | |
| 2312 | #define PMU_CC13_AUX_MEMLPLDO2VDDB_OFF (1u << 10u) | |
| 2313 | #define PMU_CC13_AUX_MEMLPLDO2VDDRET_OFF (1u << 11u) | |
| 2314 | #define PMU_CC13_AUX_CBUCK2VDDRET_OFF (1u << 12u) | |
| 2315 | #define PMU_CC13_CMN_MEMLPLDO2VDDRET_ON (1u << 18u) | |
| 2316 | ||
| 2317 | /* HW4368-331 */ | |
| 2318 | #define PMU_CC13_MAIN_ALWAYS_USE_COHERENT_IF0 (1u << 13u) | |
| 2319 | #define PMU_CC13_MAIN_ALWAYS_USE_COHERENT_IF1 (1u << 14u) | |
| 2320 | #define PMU_CC13_AUX_ALWAYS_USE_COHERENT_IF0 (1u << 15u) | |
| 2321 | #define PMU_CC13_AUX_ALWAYS_USE_COHERENT_IF1 (1u << 19u) | |
| 2322 | ||
| 2323 | #define PMU_CC13_LHL_TIMER_SELECT (1u << 23u) | |
| 2324 | ||
| 2325 | #define PMU_CC13_4369_LHL_TIMER_SELECT (1u << 23u) | |
| 2326 | #define PMU_CC13_4378_LHL_TIMER_SELECT (1u << 23u) | |
| 2327 | ||
| 2328 | #define PMU_CC13_4387_ENAB_RADIO_REG_CLK (1u << 9u) | |
| 2329 | #define PMU_CC13_4387_LHL_TIMER_SELECT (1u << 23u) | |
| 2330 | ||
| 2331 | #define PMU_CHIPCTL14 14 | |
| 2332 | #define PMU_CHIPCTL15 15 | |
| 2333 | #define PMU_CHIPCTL16 16 | |
| 2334 | #define PMU_CC16_CLK4M_DIS (1 << 4) | |
| 2335 | #define PMU_CC16_FF_ZERO_ADJ (4 << 5) | |
| 2336 | ||
| 2337 | /* PMU chip control17 register */ | |
| 2338 | #define PMU_CHIPCTL17 17u | |
| 2339 | ||
| 2340 | #define PMU_CC17_SCAN_CBUCK2VDDB_OFF (1u << 8u) | |
| 2341 | #define PMU_CC17_SCAN_MEMLPLDO2VDDB_OFF (1u << 10u) | |
| 2342 | #define PMU_CC17_SCAN_MEMLPLDO2VDDRET_OFF (1u << 11u) | |
| 2343 | #define PMU_CC17_SCAN_CBUCK2VDDB_ON (1u << 24u) | |
| 2344 | #define PMU_CC17_SCAN_MEMLPLDO2VDDB_ON (1u << 26u) | |
| 2345 | #define PMU_CC17_SCAN_MEMLPLDO2VDDRET_ON (1u << 27u) | |
| 2346 | ||
| 2347 | #define PMU_CHIPCTL23 23 | |
| 2348 | #define PMU_CC23_MACPHYCLK_MASK (1 << 31) | |
| 2349 | ||
| 2350 | #define PMU_CC23_AT_CLK0_ON (1u << 14u) | |
| 2351 | #define PMU_CC23_AT_CLK1_ON (1u << 15u) | |
| 2352 | ||
| 2353 | /* PMU chip control14 register */ | |
| 2354 | #define PMU_CC14_MAIN_VDDB2VDDRET_UP_DLY_MASK (0xF) | |
| 2355 | #define PMU_CC14_MAIN_VDDB2VDD_UP_DLY_MASK (0xF << 4) | |
| 2356 | #define PMU_CC14_AUX_VDDB2VDDRET_UP_DLY_MASK (0xF << 8) | |
| 2357 | #define PMU_CC14_AUX_VDDB2VDD_UP_DLY_MASK (0xF << 12) | |
| 2358 | #define PMU_CC14_PCIE_VDDB2VDDRET_UP_DLY_MASK (0xF << 16) | |
| 2359 | #define PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK (0xF << 20) | |
| 2360 | ||
| 2361 | /* PMU chip control15 register */ | |
| 2362 | #define PMU_CC15_PCIE_VDDB_CURRENT_LIMIT_DELAY_MASK (0xFu << 4u) | |
| 2363 | #define PMU_CC15_PCIE_VDDB_FORCE_RPS_PWROK_DELAY_MASK (0xFu << 8u) | |
| 2364 | ||
| 2365 | /* PMU corerev and chip specific PLL controls. | |
| 2366 | * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number | |
| 2367 | * to differentiate different PLLs controlled by the same PMU rev. | |
| 2368 | */ | |
| 2369 | /* pllcontrol registers */ | |
| 2370 | /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ | |
| 2371 | #define PMU0_PLL0_PLLCTL0 0 | |
| 2372 | #define PMU0_PLL0_PC0_PDIV_MASK 1 | |
| 2373 | #define PMU0_PLL0_PC0_PDIV_FREQ 25000 | |
| 2374 | #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 | |
| 2375 | #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 | |
| 2376 | #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 | |
| 2377 | ||
| 2378 | /* PC0_DIV_ARM for PLLOUT_ARM */ | |
| 2379 | #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 | |
| 2380 | #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 | |
| 2381 | #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 | |
| 2382 | #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ | |
| 2383 | #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 | |
| 2384 | #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 | |
| 2385 | #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 | |
| 2386 | #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 | |
| 2387 | ||
| 2388 | /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ | |
| 2389 | #define PMU0_PLL0_PLLCTL1 1 | |
| 2390 | #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 | |
| 2391 | #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 | |
| 2392 | #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 | |
| 2393 | #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 | |
| 2394 | #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 | |
| 2395 | ||
| 2396 | /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ | |
| 2397 | #define PMU0_PLL0_PLLCTL2 2 | |
| 2398 | #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf | |
| 2399 | #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 | |
| 2400 | ||
| 2401 | /* pllcontrol registers */ | |
| 2402 | /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ | |
| 2403 | #define PMU1_PLL0_PLLCTL0 0 | |
| 2404 | #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 | |
| 2405 | #define PMU1_PLL0_PC0_P1DIV_SHIFT 20 | |
| 2406 | #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 | |
| 2407 | #define PMU1_PLL0_PC0_P2DIV_SHIFT 24 | |
| 2408 | ||
| 2409 | /* m<x>div */ | |
| 2410 | #define PMU1_PLL0_PLLCTL1 1 | |
| 2411 | #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff | |
| 2412 | #define PMU1_PLL0_PC1_M1DIV_SHIFT 0 | |
| 2413 | #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 | |
| 2414 | #define PMU1_PLL0_PC1_M2DIV_SHIFT 8 | |
| 2415 | #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 | |
| 2416 | #define PMU1_PLL0_PC1_M3DIV_SHIFT 16 | |
| 2417 | #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 | |
| 2418 | #define PMU1_PLL0_PC1_M4DIV_SHIFT 24 | |
| 2419 | #define PMU1_PLL0_PC1_M4DIV_BY_9 9 | |
| 2420 | #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12 | |
| 2421 | #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24 | |
| 2422 | #define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C | |
| 2423 | #define PMU1_PLL0_PC1_M2_M4DIV_MASK 0xff00ff00 | |
| 2424 | #define PMU1_PLL0_PC1_HOLD_LOAD_CH 0x28 | |
| 2425 | ||
| 2426 | #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 | |
| 2427 | #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) | |
| 2428 | #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) | |
| 2429 | ||
| 2430 | /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ | |
| 2431 | #define PMU1_PLL0_PLLCTL2 2 | |
| 2432 | #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff | |
| 2433 | #define PMU1_PLL0_PC2_M5DIV_SHIFT 0 | |
| 2434 | #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc | |
| 2435 | #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12 | |
| 2436 | #define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f | |
| 2437 | #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24 | |
| 2438 | #define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a | |
| 2439 | #define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c | |
| 2440 | #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 | |
| 2441 | #define PMU1_PLL0_PC2_M6DIV_SHIFT 8 | |
| 2442 | #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12 | |
| 2443 | #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24 | |
| 2444 | #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 | |
| 2445 | #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 | |
| 2446 | #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 | |
| 2447 | #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 | |
| 2448 | #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 | |
| 2449 | #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 | |
| 2450 | ||
| 2451 | /* ndiv_frac */ | |
| 2452 | #define PMU1_PLL0_PLLCTL3 3 | |
| 2453 | #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff | |
| 2454 | #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 | |
| 2455 | ||
| 2456 | /* pll_ctrl */ | |
| 2457 | #define PMU1_PLL0_PLLCTL4 4 | |
| 2458 | ||
| 2459 | /* pll_ctrl, vco_rng, clkdrive_ch<x> */ | |
| 2460 | #define PMU1_PLL0_PLLCTL5 5 | |
| 2461 | #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 | |
| 2462 | #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 | |
| 2463 | #define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000 | |
| 2464 | #define PMU1_PLL0_PC5_ASSERT_CH_SHIFT 24 | |
| 2465 | #define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000 | |
| 2466 | ||
| 2467 | #define PMU1_PLL0_PLLCTL6 6 | |
| 2468 | #define PMU1_PLL0_PLLCTL7 7 | |
| 2469 | #define PMU1_PLL0_PLLCTL8 8 | |
| 2470 | ||
| 2471 | #define PMU1_PLLCTL8_OPENLOOP_MASK (1 << 1) | |
| 2472 | ||
| 2473 | #define PMU1_PLL0_PLLCTL9 9 | |
| 2474 | ||
| 2475 | #define PMU1_PLL0_PLLCTL10 10 | |
| 2476 | ||
| 2477 | /* PMU rev 2 control words */ | |
| 2478 | #define PMU2_PHY_PLL_PLLCTL 4 | |
| 2479 | #define PMU2_SI_PLL_PLLCTL 10 | |
| 2480 | ||
| 2481 | /* PMU rev 2 */ | |
| 2482 | /* pllcontrol registers */ | |
| 2483 | /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ | |
| 2484 | #define PMU2_PLL_PLLCTL0 0 | |
| 2485 | #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 | |
| 2486 | #define PMU2_PLL_PC0_P1DIV_SHIFT 20 | |
| 2487 | #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 | |
| 2488 | #define PMU2_PLL_PC0_P2DIV_SHIFT 24 | |
| 2489 | ||
| 2490 | /* m<x>div */ | |
| 2491 | #define PMU2_PLL_PLLCTL1 1 | |
| 2492 | #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff | |
| 2493 | #define PMU2_PLL_PC1_M1DIV_SHIFT 0 | |
| 2494 | #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 | |
| 2495 | #define PMU2_PLL_PC1_M2DIV_SHIFT 8 | |
| 2496 | #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 | |
| 2497 | #define PMU2_PLL_PC1_M3DIV_SHIFT 16 | |
| 2498 | #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 | |
| 2499 | #define PMU2_PLL_PC1_M4DIV_SHIFT 24 | |
| 2500 | ||
| 2501 | /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ | |
| 2502 | #define PMU2_PLL_PLLCTL2 2 | |
| 2503 | #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff | |
| 2504 | #define PMU2_PLL_PC2_M5DIV_SHIFT 0 | |
| 2505 | #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 | |
| 2506 | #define PMU2_PLL_PC2_M6DIV_SHIFT 8 | |
| 2507 | #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 | |
| 2508 | #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 | |
| 2509 | #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 | |
| 2510 | #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 | |
| 2511 | ||
| 2512 | /* ndiv_frac */ | |
| 2513 | #define PMU2_PLL_PLLCTL3 3 | |
| 2514 | #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff | |
| 2515 | #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 | |
| 2516 | ||
| 2517 | /* pll_ctrl */ | |
| 2518 | #define PMU2_PLL_PLLCTL4 4 | |
| 2519 | ||
| 2520 | /* pll_ctrl, vco_rng, clkdrive_ch<x> */ | |
| 2521 | #define PMU2_PLL_PLLCTL5 5 | |
| 2522 | #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 | |
| 2523 | #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 | |
| 2524 | #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 | |
| 2525 | #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 | |
| 2526 | #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 | |
| 2527 | #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 | |
| 2528 | #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 | |
| 2529 | #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 | |
| 2530 | #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 | |
| 2531 | #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 | |
| 2532 | #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 | |
| 2533 | #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 | |
| 2534 | ||
| 2535 | /* PMU rev 5 (& 6) */ | |
| 2536 | #define PMU5_PLL_P1P2_OFF 0 | |
| 2537 | #define PMU5_PLL_P1_MASK 0x0f000000 | |
| 2538 | #define PMU5_PLL_P1_SHIFT 24 | |
| 2539 | #define PMU5_PLL_P2_MASK 0x00f00000 | |
| 2540 | #define PMU5_PLL_P2_SHIFT 20 | |
| 2541 | #define PMU5_PLL_M14_OFF 1 | |
| 2542 | #define PMU5_PLL_MDIV_MASK 0x000000ff | |
| 2543 | #define PMU5_PLL_MDIV_WIDTH 8 | |
| 2544 | #define PMU5_PLL_NM5_OFF 2 | |
| 2545 | #define PMU5_PLL_NDIV_MASK 0xfff00000 | |
| 2546 | #define PMU5_PLL_NDIV_SHIFT 20 | |
| 2547 | #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 | |
| 2548 | #define PMU5_PLL_NDIV_MODE_SHIFT 17 | |
| 2549 | #define PMU5_PLL_FMAB_OFF 3 | |
| 2550 | #define PMU5_PLL_MRAT_MASK 0xf0000000 | |
| 2551 | #define PMU5_PLL_MRAT_SHIFT 28 | |
| 2552 | #define PMU5_PLL_ABRAT_MASK 0x08000000 | |
| 2553 | #define PMU5_PLL_ABRAT_SHIFT 27 | |
| 2554 | #define PMU5_PLL_FDIV_MASK 0x07ffffff | |
| 2555 | #define PMU5_PLL_PLLCTL_OFF 4 | |
| 2556 | #define PMU5_PLL_PCHI_OFF 5 | |
| 2557 | #define PMU5_PLL_PCHI_MASK 0x0000003f | |
| 2558 | ||
| 2559 | /* pmu XtalFreqRatio */ | |
| 2560 | #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF | |
| 2561 | #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 | |
| 2562 | #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 | |
| 2563 | ||
| 2564 | /* Divider allocation in 5357 */ | |
| 2565 | #define PMU5_MAINPLL_CPU 1 | |
| 2566 | #define PMU5_MAINPLL_MEM 2 | |
| 2567 | #define PMU5_MAINPLL_SI 3 | |
| 2568 | ||
| 2569 | #define PMU7_PLL_PLLCTL7 7 | |
| 2570 | #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000 | |
| 2571 | #define PMU7_PLL_CTL7_M4DIV_SHIFT 24 | |
| 2572 | #define PMU7_PLL_CTL7_M4DIV_BY_6 6 | |
| 2573 | #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc | |
| 2574 | #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18 | |
| 2575 | #define PMU7_PLL_PLLCTL8 8 | |
| 2576 | #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff | |
| 2577 | #define PMU7_PLL_CTL8_M5DIV_SHIFT 0 | |
| 2578 | #define PMU7_PLL_CTL8_M5DIV_BY_8 8 | |
| 2579 | #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc | |
| 2580 | #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18 | |
| 2581 | #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00 | |
| 2582 | #define PMU7_PLL_CTL8_M6DIV_SHIFT 8 | |
| 2583 | #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc | |
| 2584 | #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18 | |
| 2585 | #define PMU7_PLL_PLLCTL11 11 | |
| 2586 | #define PMU7_PLL_PLLCTL11_MASK 0xffffff00 | |
| 2587 | #define PMU7_PLL_PLLCTL11_VAL 0x22222200 | |
| 2588 | ||
| 2589 | /* PMU rev 15 */ | |
| 2590 | #define PMU15_PLL_PLLCTL0 0 | |
| 2591 | #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 | |
| 2592 | #define PMU15_PLL_PC0_CLKSEL_SHIFT 0 | |
| 2593 | #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC | |
| 2594 | #define PMU15_PLL_PC0_FREQTGT_SHIFT 2 | |
| 2595 | #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 | |
| 2596 | #define PMU15_PLL_PC0_PRESCALE_SHIFT 22 | |
| 2597 | #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 | |
| 2598 | #define PMU15_PLL_PC0_KPCTRL_SHIFT 24 | |
| 2599 | #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 | |
| 2600 | #define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 | |
| 2601 | #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 | |
| 2602 | #define PMU15_PLL_PC0_FDCMODE_SHIFT 30 | |
| 2603 | #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 | |
| 2604 | #define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 | |
| 2605 | ||
| 2606 | #define PMU15_PLL_PLLCTL1 1 | |
| 2607 | #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060 | |
| 2608 | #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5 | |
| 2609 | #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040 | |
| 2610 | #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6 | |
| 2611 | #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80 | |
| 2612 | #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7 | |
| 2613 | #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000 | |
| 2614 | #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17 | |
| 2615 | #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000 | |
| 2616 | #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26 | |
| 2617 | #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000 | |
| 2618 | #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28 | |
| 2619 | #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000 | |
| 2620 | #define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30 | |
| 2621 | ||
| 2622 | #define PMU15_PLL_PLLCTL2 2 | |
| 2623 | #define PMU15_PLL_PC2_CTEN_MASK 0x00000001 | |
| 2624 | #define PMU15_PLL_PC2_CTEN_SHIFT 0 | |
| 2625 | ||
| 2626 | #define PMU15_PLL_PLLCTL3 3 | |
| 2627 | #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001 | |
| 2628 | #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0 | |
| 2629 | #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000 | |
| 2630 | #define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25 | |
| 2631 | #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01 | |
| 2632 | #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0 | |
| 2633 | #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02 | |
| 2634 | #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1 | |
| 2635 | #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04 | |
| 2636 | #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2 | |
| 2637 | #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18 | |
| 2638 | #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3 | |
| 2639 | #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60 | |
| 2640 | #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5 | |
| 2641 | #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0 | |
| 2642 | #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1 | |
| 2643 | #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2 | |
| 2644 | #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3 | |
| 2645 | ||
| 2646 | #define PMU15_PLL_PLLCTL4 4 | |
| 2647 | #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007 | |
| 2648 | #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0 | |
| 2649 | #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038 | |
| 2650 | #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3 | |
| 2651 | #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0 | |
| 2652 | #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6 | |
| 2653 | #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00 | |
| 2654 | #define PMU15_PLL_PC4_DBGMODE_SHIFT 9 | |
| 2655 | #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000 | |
| 2656 | #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12 | |
| 2657 | #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000 | |
| 2658 | #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13 | |
| 2659 | #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000 | |
| 2660 | #define PMU15_PLL_PC4_DINPOL_SHIFT 20 | |
| 2661 | #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000 | |
| 2662 | #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21 | |
| 2663 | #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000 | |
| 2664 | #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22 | |
| 2665 | #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000 | |
| 2666 | #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23 | |
| 2667 | #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000 | |
| 2668 | #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24 | |
| 2669 | #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000 | |
| 2670 | #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25 | |
| 2671 | #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000 | |
| 2672 | #define PMU15_PLL_PC4_TEST_EN_SHIFT 26 | |
| 2673 | ||
| 2674 | #define PMU15_PLL_PLLCTL5 5 | |
| 2675 | #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF | |
| 2676 | #define PMU15_PLL_PC5_FREQTGT_SHIFT 0 | |
| 2677 | #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000 | |
| 2678 | #define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20 | |
| 2679 | #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000 | |
| 2680 | #define PMU15_PLL_PC5_PRESCALE_SHIFT 27 | |
| 2681 | ||
| 2682 | #define PMU15_PLL_PLLCTL6 6 | |
| 2683 | #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF | |
| 2684 | #define PMU15_PLL_PC6_FREQTGT_SHIFT 0 | |
| 2685 | #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000 | |
| 2686 | #define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20 | |
| 2687 | #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000 | |
| 2688 | #define PMU15_PLL_PC6_PRESCALE_SHIFT 27 | |
| 2689 | ||
| 2690 | #define PMU15_FREQTGT_480_DEFAULT 0x19AB1 | |
| 2691 | #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5 | |
| 2692 | #define PMU15_ARM_96MHZ 96000000 /**< 96 Mhz */ | |
| 2693 | #define PMU15_ARM_98MHZ 98400000 /**< 98.4 Mhz */ | |
| 2694 | #define PMU15_ARM_97MHZ 97000000 /**< 97 Mhz */ | |
| 2695 | ||
| 2696 | #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070 | |
| 2697 | #define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4 | |
| 2698 | ||
| 2699 | #define PMU17_PLLCTL2_NDIV_MODE_INT 0 | |
| 2700 | #define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1 | |
| 2701 | #define PMU17_PLLCTL2_NDIV_MODE_MASH111 2 | |
| 2702 | #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3 | |
| 2703 | ||
| 2704 | #define PMU17_PLLCTL0_BBPLL_PWRDWN 0 | |
| 2705 | #define PMU17_PLLCTL0_BBPLL_DRST 3 | |
| 2706 | #define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8 | |
| 2707 | ||
| 2708 | /* PLL usage in 4716/47162 */ | |
| 2709 | #define PMU4716_MAINPLL_PLL0 12 | |
| 2710 | ||
| 2711 | /* PLL Usages for 4368 */ | |
| 2712 | #define PMU4368_P1DIV_LO_SHIFT 0 | |
| 2713 | #define PMU4368_P1DIV_HI_SHIFT 2 | |
| 2714 | ||
| 2715 | #define PMU4368_PLL1_PC4_P1DIV_MASK 0xC0000000 | |
| 2716 | #define PMU4368_PLL1_PC4_P1DIV_SHIFT 30 | |
| 2717 | #define PMU4368_PLL1_PC5_P1DIV_MASK 0x00000003 | |
| 2718 | #define PMU4368_PLL1_PC5_P1DIV_SHIFT 0 | |
| 2719 | #define PMU4368_PLL1_PC5_NDIV_INT_MASK 0x00000ffc | |
| 2720 | #define PMU4368_PLL1_PC5_NDIV_INT_SHIFT 2 | |
| 2721 | #define PMU4368_PLL1_PC5_NDIV_FRAC_MASK 0xfffff000 | |
| 2722 | #define PMU4368_PLL1_PC5_NDIV_FRAC_SHIFT 12 | |
| 2723 | #define PMU4368_PLL1_PC7_CH0_MDIV_MASK 0x0000000f | |
| 2724 | #define PMU4368_PLL1_PC7_CH0_MDIV_SHIFT 0 | |
| 2725 | #define PMU4368_PLL1_PC7_CH1_MDIV_MASK 0x000000f0 | |
| 2726 | #define PMU4368_PLL1_PC7_CH1_MDIV_SHIFT 4 | |
| 2727 | ||
| 2728 | /* PLL usage in 4369 */ | |
| 2729 | #define PMU4369_PLL0_PC2_PDIV_MASK 0x000f0000 | |
| 2730 | #define PMU4369_PLL0_PC2_PDIV_SHIFT 16 | |
| 2731 | #define PMU4369_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 | |
| 2732 | #define PMU4369_PLL0_PC2_NDIV_INT_SHIFT 20 | |
| 2733 | #define PMU4369_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff | |
| 2734 | #define PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT 0 | |
| 2735 | #define PMU4369_PLL1_PC5_P1DIV_MASK 0xc0000000 | |
| 2736 | #define PMU4369_PLL1_PC5_P1DIV_SHIFT 30 | |
| 2737 | #define PMU4369_PLL1_PC6_P1DIV_MASK 0x00000003 | |
| 2738 | #define PMU4369_PLL1_PC6_P1DIV_SHIFT 0 | |
| 2739 | #define PMU4369_PLL1_PC6_NDIV_INT_MASK 0x00000ffc | |
| 2740 | #define PMU4369_PLL1_PC6_NDIV_INT_SHIFT 2 | |
| 2741 | #define PMU4369_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000 | |
| 2742 | #define PMU4369_PLL1_PC6_NDIV_FRAC_SHIFT 12 | |
| 2743 | ||
| 2744 | #define PMU4369_P1DIV_LO_SHIFT 0 | |
| 2745 | #define PMU4369_P1DIV_HI_SHIFT 2 | |
| 2746 | ||
| 2747 | #define PMU4369_PLL6VAL_P1DIV 4 | |
| 2748 | #define PMU4369_PLL6VAL_P1DIV_BIT3_2 1 | |
| 2749 | #define PMU4369_PLL6VAL_PRE_SCALE (1 << 17) | |
| 2750 | #define PMU4369_PLL6VAL_POST_SCALE (1 << 3) | |
| 2751 | ||
| 2752 | /* PLL usage in 4378 | |
| 2753 | * Temporay setting, update is needed. | |
| 2754 | */ | |
| 2755 | #define PMU4378_PLL0_PC2_P1DIV_MASK 0x000f0000 | |
| 2756 | #define PMU4378_PLL0_PC2_P1DIV_SHIFT 16 | |
| 2757 | #define PMU4378_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 | |
| 2758 | #define PMU4378_PLL0_PC2_NDIV_INT_SHIFT 20 | |
| 2759 | ||
| 2760 | /* PLL usage in 4387 */ | |
| 2761 | #define PMU4387_PLL0_PC1_ICH2_MDIV_SHIFT 18 | |
| 2762 | #define PMU4387_PLL0_PC1_ICH2_MDIV_MASK 0x07FC0000 | |
| 2763 | #define PMU4387_PLL0_PC2_ICH3_MDIV_MASK 0x000001ff | |
| 2764 | ||
| 2765 | /* PLL usage in 4389 */ | |
| 2766 | #define PMU4389_APLL_NDIV_P 0x154u | |
| 2767 | #define PMU4389_APLL_NDIV_Q 0x1ffu | |
| 2768 | #define PMU4389_APLL_PDIV 0x3u | |
| 2769 | #define PMU4389_ARMPLL_I_NDIV_INT_MASK 0x01ff8000u | |
| 2770 | #define PMU4389_ARMPLL_I_NDIV_INT_SHIFT 15u | |
| 2771 | ||
| 2772 | /* 5357 Chip specific ChipControl register bits */ | |
| 2773 | #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ | |
| 2774 | #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ | |
| 2775 | #define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */ | |
| 2776 | /* 43217 Chip specific ChipControl register bits */ | |
| 2777 | #define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */ | |
| 2778 | #define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */ | |
| 2779 | ||
| 2780 | #define PMU1_PLL0_CHIPCTL0 0 | |
| 2781 | #define PMU1_PLL0_CHIPCTL1 1 | |
| 2782 | #define PMU1_PLL0_CHIPCTL2 2 | |
| 2783 | ||
| 2784 | #define SOCDEVRAM_BP_ADDR 0x1E000000 | |
| 2785 | #define SOCDEVRAM_ARM_ADDR 0x00800000 | |
| 2786 | ||
| 2787 | #define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0 | |
| 2788 | #define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2 | |
| 2789 | #define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3 | |
| 2790 | #define PMU_VREG0_CBUCKFSW_ADJ_SHIFT 7 | |
| 2791 | #define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F | |
| 2792 | #define PMU_VREG0_RAMP_SEL_SHIFT 13 | |
| 2793 | #define PMU_VREG0_RAMP_SEL_MASK 0x7 | |
| 2794 | #define PMU_VREG0_VFB_RSEL_SHIFT 17 | |
| 2795 | #define PMU_VREG0_VFB_RSEL_MASK 3 | |
| 2796 | ||
| 2797 | #define PMU_VREG4_ADDR 4 | |
| 2798 | ||
| 2799 | #define PMU_VREG4_CLDO_PWM_SHIFT 4 | |
| 2800 | #define PMU_VREG4_CLDO_PWM_MASK 0x7 | |
| 2801 | ||
| 2802 | #define PMU_VREG4_LPLDO1_SHIFT 15 | |
| 2803 | #define PMU_VREG4_LPLDO1_MASK 0x7 | |
| 2804 | #define PMU_VREG4_LPLDO1_1p20V 0 | |
| 2805 | #define PMU_VREG4_LPLDO1_1p15V 1 | |
| 2806 | #define PMU_VREG4_LPLDO1_1p10V 2 | |
| 2807 | #define PMU_VREG4_LPLDO1_1p25V 3 | |
| 2808 | #define PMU_VREG4_LPLDO1_1p05V 4 | |
| 2809 | #define PMU_VREG4_LPLDO1_1p00V 5 | |
| 2810 | #define PMU_VREG4_LPLDO1_0p95V 6 | |
| 2811 | #define PMU_VREG4_LPLDO1_0p90V 7 | |
| 2812 | ||
| 2813 | #define PMU_VREG4_LPLDO2_LVM_SHIFT 18 | |
| 2814 | #define PMU_VREG4_LPLDO2_LVM_MASK 0x7 | |
| 2815 | #define PMU_VREG4_LPLDO2_HVM_SHIFT 21 | |
| 2816 | #define PMU_VREG4_LPLDO2_HVM_MASK 0x7 | |
| 2817 | #define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f | |
| 2818 | #define PMU_VREG4_LPLDO2_1p00V 0 | |
| 2819 | #define PMU_VREG4_LPLDO2_1p15V 1 | |
| 2820 | #define PMU_VREG4_LPLDO2_1p20V 2 | |
| 2821 | #define PMU_VREG4_LPLDO2_1p10V 3 | |
| 2822 | #define PMU_VREG4_LPLDO2_0p90V 4 /**< 4 - 7 is 0.90V */ | |
| 2823 | ||
| 2824 | #define PMU_VREG4_HSICLDO_BYPASS_SHIFT 27 | |
| 2825 | #define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1 | |
| 2826 | ||
| 2827 | #define PMU_VREG5_ADDR 5 | |
| 2828 | #define PMU_VREG5_HSICAVDD_PD_SHIFT 6 | |
| 2829 | #define PMU_VREG5_HSICAVDD_PD_MASK 0x1 | |
| 2830 | #define PMU_VREG5_HSICDVDD_PD_SHIFT 11 | |
| 2831 | #define PMU_VREG5_HSICDVDD_PD_MASK 0x1 | |
| 2832 | ||
| 2833 | /* 43228 chipstatus reg bits */ | |
| 2834 | #define CST43228_OTP_PRESENT 0x2 | |
| 2835 | ||
| 2836 | /* 4360 Chip specific ChipControl register bits */ | |
| 2837 | /* 43602 uses these ChipControl definitions as well */ | |
| 2838 | #define CCTRL4360_I2C_MODE (1 << 0) | |
| 2839 | #define CCTRL4360_UART_MODE (1 << 1) | |
| 2840 | #define CCTRL4360_SECI_MODE (1 << 2) | |
| 2841 | #define CCTRL4360_BTSWCTRL_MODE (1 << 3) | |
| 2842 | #define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4) | |
| 2843 | #define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5) | |
| 2844 | #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6) | |
| 2845 | #define CCTRL4360_EXTRA_GPIO_MODE (1 << 7) | |
| 2846 | #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8) | |
| 2847 | #define CCTRL4360_BT_LGCY_MODE (1 << 9) | |
| 2848 | #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21) | |
| 2849 | #define CCTRL4360_SECI_ON_GPIO01 (1 << 24) | |
| 2850 | ||
| 2851 | /* 4360 Chip specific Regulator Control register bits */ | |
| 2852 | #define RCTRL4360_RFLDO_PWR_DOWN (1 << 1) | |
| 2853 | ||
| 2854 | /* 4360 PMU resources and chip status bits */ | |
| 2855 | #define RES4360_REGULATOR 0 | |
| 2856 | #define RES4360_ILP_AVAIL 1 | |
| 2857 | #define RES4360_ILP_REQ 2 | |
| 2858 | #define RES4360_XTAL_LDO_PU 3 | |
| 2859 | #define RES4360_XTAL_PU 4 | |
| 2860 | #define RES4360_ALP_AVAIL 5 | |
| 2861 | #define RES4360_BBPLLPWRSW_PU 6 | |
| 2862 | #define RES4360_HT_AVAIL 7 | |
| 2863 | #define RES4360_OTP_PU 8 | |
| 2864 | #define RES4360_AVB_PLL_PWRSW_PU 9 | |
| 2865 | #define RES4360_PCIE_TL_CLK_AVAIL 10 | |
| 2866 | ||
| 2867 | #define CST4360_XTAL_40MZ 0x00000001 | |
| 2868 | #define CST4360_SFLASH 0x00000002 | |
| 2869 | #define CST4360_SPROM_PRESENT 0x00000004 | |
| 2870 | #define CST4360_SFLASH_TYPE 0x00000004 | |
| 2871 | #define CST4360_OTP_ENABLED 0x00000008 | |
| 2872 | #define CST4360_REMAP_ROM 0x00000010 | |
| 2873 | #define CST4360_RSRC_INIT_MODE_MASK 0x00000060 | |
| 2874 | #define CST4360_RSRC_INIT_MODE_SHIFT 5 | |
| 2875 | #define CST4360_ILP_DIVEN 0x00000080 | |
| 2876 | #define CST4360_MODE_USB 0x00000100 | |
| 2877 | #define CST4360_SPROM_SIZE_MASK 0x00000600 | |
| 2878 | #define CST4360_SPROM_SIZE_SHIFT 9 | |
| 2879 | #define CST4360_BBPLL_LOCK 0x00000800 | |
| 2880 | #define CST4360_AVBBPLL_LOCK 0x00001000 | |
| 2881 | #define CST4360_USBBBPLL_LOCK 0x00002000 | |
| 2882 | #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ | |
| 2883 | CST4360_RSRC_INIT_MODE_SHIFT) | |
| 2884 | ||
| 2885 | #define CCTRL_4360_UART_SEL 0x2 | |
| 2886 | ||
| 2887 | #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ | |
| 2888 | CST4360_RSRC_INIT_MODE_SHIFT) | |
| 2889 | ||
| 2890 | #define PMU4360_CC1_GPIO7_OVRD (1<<23) /* GPIO7 override */ | |
| 2891 | ||
| 2892 | /* 43602 PMU resources based on pmu_params.xls version v0.95 */ | |
| 2893 | #define RES43602_LPLDO_PU 0 | |
| 2894 | #define RES43602_REGULATOR 1 | |
| 2895 | #define RES43602_PMU_SLEEP 2 | |
| 2896 | #define RES43602_RSVD_3 3 | |
| 2897 | #define RES43602_XTALLDO_PU 4 | |
| 2898 | #define RES43602_SERDES_PU 5 | |
| 2899 | #define RES43602_BBPLL_PWRSW_PU 6 | |
| 2900 | #define RES43602_SR_CLK_START 7 | |
| 2901 | #define RES43602_SR_PHY_PWRSW 8 | |
| 2902 | #define RES43602_SR_SUBCORE_PWRSW 9 | |
| 2903 | #define RES43602_XTAL_PU 10 | |
| 2904 | #define RES43602_PERST_OVR 11 | |
| 2905 | #define RES43602_SR_CLK_STABLE 12 | |
| 2906 | #define RES43602_SR_SAVE_RESTORE 13 | |
| 2907 | #define RES43602_SR_SLEEP 14 | |
| 2908 | #define RES43602_LQ_START 15 | |
| 2909 | #define RES43602_LQ_AVAIL 16 | |
| 2910 | #define RES43602_WL_CORE_RDY 17 | |
| 2911 | #define RES43602_ILP_REQ 18 | |
| 2912 | #define RES43602_ALP_AVAIL 19 | |
| 2913 | #define RES43602_RADIO_PU 20 | |
| 2914 | #define RES43602_RFLDO_PU 21 | |
| 2915 | #define RES43602_HT_START 22 | |
| 2916 | #define RES43602_HT_AVAIL 23 | |
| 2917 | #define RES43602_MACPHY_CLKAVAIL 24 | |
| 2918 | #define RES43602_PARLDO_PU 25 | |
| 2919 | #define RES43602_RSVD_26 26 | |
| 2920 | ||
| 2921 | /* 43602 chip status bits */ | |
| 2922 | #define CST43602_SPROM_PRESENT (1<<1) | |
| 2923 | #define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */ | |
| 2924 | #define CST43602_BBPLL_LOCK (1<<11) | |
| 2925 | #define CST43602_RF_LDO_OUT_OK (1<<15) /* RF LDO output OK */ | |
| 2926 | ||
| 2927 | #define PMU43602_CC1_GPIO12_OVRD (1<<28) /* GPIO12 override */ | |
| 2928 | ||
| 2929 | #define PMU43602_CC2_PCIE_CLKREQ_L_WAKE_EN (1<<1) /* creates gated_pcie_wake, pmu_wakeup logic */ | |
| 2930 | #define PMU43602_CC2_PCIE_PERST_L_WAKE_EN (1<<2) /* creates gated_pcie_wake, pmu_wakeup logic */ | |
| 2931 | #define PMU43602_CC2_ENABLE_L2REFCLKPAD_PWRDWN (1<<3) | |
| 2932 | #define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5) /* enable pmu_wakeup to request for ALP_AVAIL */ | |
| 2933 | #define PMU43602_CC2_PERST_L_EXTEND_EN (1<<9) /* extend perst_l until rsc PERST_OVR comes up */ | |
| 2934 | #define PMU43602_CC2_FORCE_EXT_LPO (1<<19) /* 1=ext LPO clock is the final LPO clock */ | |
| 2935 | #define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */ | |
| 2936 | ||
| 2937 | #define CC_SR1_43602_SR_ASM_ADDR (0x0) | |
| 2938 | ||
| 2939 | /* PLL CTL register values for open loop, used during S/R operation */ | |
| 2940 | #define PMU43602_PLL_CTL6_VAL 0x68000528 | |
| 2941 | #define PMU43602_PLL_CTL7_VAL 0x6 | |
| 2942 | ||
| 2943 | #define PMU43602_CC3_ARMCR4_DBG_CLK (1 << 29) | |
| 2944 | ||
| 2945 | #define CC_SR0_43602_SR_ENG_EN_MASK 0x1 | |
| 2946 | #define CC_SR0_43602_SR_ENG_EN_SHIFT 0 | |
| 2947 | ||
| 2948 | /* GCI function sel values */ | |
| 2949 | #define CC_FNSEL_HWDEF (0u) | |
| 2950 | #define CC_FNSEL_SAMEASPIN (1u) | |
| 2951 | #define CC_FNSEL_GPIO0 (2u) | |
| 2952 | #define CC_FNSEL_GPIO1 (3u) | |
| 2953 | #define CC_FNSEL_GCI0 (4u) | |
| 2954 | #define CC_FNSEL_GCI1 (5u) | |
| 2955 | #define CC_FNSEL_UART (6u) | |
| 2956 | #define CC_FNSEL_SFLASH (7u) | |
| 2957 | #define CC_FNSEL_SPROM (8u) | |
| 2958 | #define CC_FNSEL_MISC0 (9u) | |
| 2959 | #define CC_FNSEL_MISC1 (10u) | |
| 2960 | #define CC_FNSEL_MISC2 (11u) | |
| 2961 | #define CC_FNSEL_IND (12u) | |
| 2962 | #define CC_FNSEL_PDN (13u) | |
| 2963 | #define CC_FNSEL_PUP (14u) | |
| 2964 | #define CC_FNSEL_TRI (15u) | |
| 2965 | ||
| 2966 | /* 4387 GCI function sel values */ | |
| 2967 | #define CC4387_FNSEL_FUART (3u) | |
| 2968 | #define CC4387_FNSEL_DBG_UART (6u) | |
| 2969 | #define CC4387_FNSEL_SPI (7u) | |
| 2970 | ||
| 2971 | /* Indices of PMU voltage regulator registers */ | |
| 2972 | #define PMU_VREG_0 (0u) | |
| 2973 | #define PMU_VREG_1 (1u) | |
| 2974 | #define PMU_VREG_2 (2u) | |
| 2975 | #define PMU_VREG_3 (3u) | |
| 2976 | #define PMU_VREG_4 (4u) | |
| 2977 | #define PMU_VREG_5 (5u) | |
| 2978 | #define PMU_VREG_6 (6u) | |
| 2979 | #define PMU_VREG_7 (7u) | |
| 2980 | #define PMU_VREG_8 (8u) | |
| 2981 | #define PMU_VREG_9 (9u) | |
| 2982 | #define PMU_VREG_10 (10u) | |
| 2983 | #define PMU_VREG_11 (11u) | |
| 2984 | #define PMU_VREG_12 (12u) | |
| 2985 | #define PMU_VREG_13 (13u) | |
| 2986 | #define PMU_VREG_14 (14u) | |
| 2987 | #define PMU_VREG_15 (15u) | |
| 2988 | #define PMU_VREG_16 (16u) | |
| 2989 | ||
| 2990 | /* 43012 Chipcommon ChipStatus bits */ | |
| 2991 | #define CST43012_FLL_LOCK (1 << 13) | |
| 2992 | /* 43012 resources - End */ | |
| 2993 | ||
| 2994 | /* 43012 related Cbuck modes */ | |
| 2995 | #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03 | |
| 2996 | #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490 | |
| 2997 | #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03 | |
| 2998 | #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410 | |
| 2999 | ||
| 3000 | /* 43012 related dynamic cbuck mode mask */ | |
| 3001 | #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFC07 | |
| 3002 | #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFFFF | |
| 3003 | ||
| 3004 | /* 4369 related VREG masks */ | |
| 3005 | #define PMU_4369_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u) | |
| 3006 | #define PMU_4369_VREG_5_MISCLDO_POWER_UP_SHIFT 11u | |
| 3007 | #define PMU_4369_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u) | |
| 3008 | #define PMU_4369_VREG_5_LPLDO_POWER_UP_SHIFT 27u | |
| 3009 | #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(23u, 20u) | |
| 3010 | #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_SHIFT 20u | |
| 3011 | #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28) | |
| 3012 | #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT 28u | |
| 3013 | ||
| 3014 | #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u) | |
| 3015 | #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT 3u | |
| 3016 | ||
| 3017 | #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u) | |
| 3018 | #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_SHIFT 27u | |
| 3019 | #define PMU_4369_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u) | |
| 3020 | #define PMU_4369_VREG_7_WL_PMU_LP_MODE_SHIFT 28u | |
| 3021 | #define PMU_4369_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u) | |
| 3022 | #define PMU_4369_VREG_7_WL_PMU_LV_MODE_SHIFT 29u | |
| 3023 | ||
| 3024 | #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0) | |
| 3025 | #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u | |
| 3026 | ||
| 3027 | #define PMU_4369_VREG13_RSRC_EN0_ASR_MASK BCM_MASK32(9, 9) | |
| 3028 | #define PMU_4369_VREG13_RSRC_EN0_ASR_SHIFT 9u | |
| 3029 | #define PMU_4369_VREG13_RSRC_EN1_ASR_MASK BCM_MASK32(10, 10) | |
| 3030 | #define PMU_4369_VREG13_RSRC_EN1_ASR_SHIFT 10u | |
| 3031 | #define PMU_4369_VREG13_RSRC_EN2_ASR_MASK BCM_MASK32(11, 11) | |
| 3032 | #define PMU_4369_VREG13_RSRC_EN2_ASR_SHIFT 11u | |
| 3033 | ||
| 3034 | #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u) | |
| 3035 | #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT 23u | |
| 3036 | ||
| 3037 | #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0) | |
| 3038 | #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u | |
| 3039 | #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15) | |
| 3040 | #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_SHIFT 15u | |
| 3041 | #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18) | |
| 3042 | #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT 18u | |
| 3043 | #define PMU_4369_VREG16_RSRC2_ABUCK_MODE_MASK BCM_MASK32(23, 21) | |
| 3044 | #define PMU_4369_VREG16_RSRC2_ABUCK_MODE_SHIFT 21u | |
| 3045 | ||
| 3046 | /* 4362 related VREG masks */ | |
| 3047 | #define PMU_4362_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u) | |
| 3048 | #define PMU_4362_VREG_5_MISCLDO_POWER_UP_SHIFT (11u) | |
| 3049 | #define PMU_4362_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u) | |
| 3050 | #define PMU_4362_VREG_5_LPLDO_POWER_UP_SHIFT (27u) | |
| 3051 | #define PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28) | |
| 3052 | #define PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT (28u) | |
| 3053 | #define PMU_4362_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u) | |
| 3054 | #define PMU_4362_VREG_6_MEMLPLDO_POWER_UP_SHIFT (3u) | |
| 3055 | ||
| 3056 | #define PMU_4362_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u) | |
| 3057 | #define PMU_4362_VREG_7_PMU_FORCE_HP_MODE_SHIFT (27u) | |
| 3058 | #define PMU_4362_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u) | |
| 3059 | #define PMU_4362_VREG_7_WL_PMU_LP_MODE_SHIFT (28u) | |
| 3060 | #define PMU_4362_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u) | |
| 3061 | #define PMU_4362_VREG_7_WL_PMU_LV_MODE_SHIFT (29u) | |
| 3062 | ||
| 3063 | #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0) | |
| 3064 | #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_SHIFT (0u) | |
| 3065 | ||
| 3066 | #define PMU_4362_VREG8_ASR_OVADJ_PFM_MASK BCM_MASK32(9, 5) | |
| 3067 | #define PMU_4362_VREG8_ASR_OVADJ_PFM_SHIFT (5u) | |
| 3068 | ||
| 3069 | #define PMU_4362_VREG8_ASR_OVADJ_PWM_MASK BCM_MASK32(14, 10) | |
| 3070 | #define PMU_4362_VREG8_ASR_OVADJ_PWM_SHIFT (10u) | |
| 3071 | ||
| 3072 | #define PMU_4362_VREG13_RSRC_EN0_ASR_MASK BCM_MASK32(9, 9) | |
| 3073 | #define PMU_4362_VREG13_RSRC_EN0_ASR_SHIFT 9u | |
| 3074 | #define PMU_4362_VREG13_RSRC_EN1_ASR_MASK BCM_MASK32(10, 10) | |
| 3075 | #define PMU_4362_VREG13_RSRC_EN1_ASR_SHIFT 10u | |
| 3076 | #define PMU_4362_VREG13_RSRC_EN2_ASR_MASK BCM_MASK32(11, 11) | |
| 3077 | #define PMU_4362_VREG13_RSRC_EN2_ASR_SHIFT 11u | |
| 3078 | ||
| 3079 | #define PMU_4362_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u) | |
| 3080 | #define PMU_4362_VREG14_RSRC_EN_CSR_MASK0_SHIFT (23u) | |
| 3081 | ||
| 3082 | #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0) | |
| 3083 | #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_SHIFT (0u) | |
| 3084 | #define PMU_4362_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15) | |
| 3085 | #define PMU_4362_VREG16_RSRC0_ABUCK_MODE_SHIFT (15u) | |
| 3086 | #define PMU_4362_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18) | |
| 3087 | #define PMU_4362_VREG16_RSRC1_ABUCK_MODE_SHIFT (18u) | |
| 3088 | #define PMU_4362_VREG16_RSRC2_ABUCK_MODE_MASK BCM_MASK32(23, 21) | |
| 3089 | #define PMU_4362_VREG16_RSRC2_ABUCK_MODE_SHIFT 21u | |
| 3090 | ||
| 3091 | #define VREG0_4378_CSR_VOLT_ADJ_PWM_MASK 0x00001F00u | |
| 3092 | #define VREG0_4378_CSR_VOLT_ADJ_PWM_SHIFT 8u | |
| 3093 | #define VREG0_4378_CSR_VOLT_ADJ_PFM_MASK 0x0003E000u | |
| 3094 | #define VREG0_4378_CSR_VOLT_ADJ_PFM_SHIFT 13u | |
| 3095 | #define VREG0_4378_CSR_VOLT_ADJ_LP_PFM_MASK 0x007C0000u | |
| 3096 | #define VREG0_4378_CSR_VOLT_ADJ_LP_PFM_SHIFT 18u | |
| 3097 | #define VREG0_4378_CSR_OUT_VOLT_TRIM_ADJ_MASK 0x07800000u | |
| 3098 | #define VREG0_4378_CSR_OUT_VOLT_TRIM_ADJ_SHIFT 23u | |
| 3099 | ||
| 3100 | #define PMU_4387_VREG1_CSR_OVERI_DIS_MASK (1u << 22u) | |
| 3101 | ||
| 3102 | #define PMU_4387_VREG6_WL_PMU_LV_MODE_MASK (0x00000002u) | |
| 3103 | ||
| 3104 | #define PMU_4389_VREG6_WL_PMU_LV_MODE_SHIFT (1u) | |
| 3105 | #define PMU_4389_VREG6_WL_PMU_LV_MODE_MASK (1u << PMU_4389_VREG6_WL_PMU_LV_MODE_SHIFT) | |
| 3106 | #define PMU_4389_VREG6_MEMLDO_PU_SHIFT (3u) | |
| 3107 | #define PMU_4389_VREG6_MEMLDO_PU_MASK (1u << PMU_4389_VREG6_MEMLDO_PU_SHIFT) | |
| 3108 | ||
| 3109 | #define PMU_4387_VREG8_ASR_OVERI_DIS_MASK (1u << 7u) | |
| 3110 | ||
| 3111 | #define PMU_VREG13_ASR_OVADJ_PWM_MASK (0x001F0000u) | |
| 3112 | #define PMU_VREG13_ASR_OVADJ_PWM_SHIFT (16u) | |
| 3113 | ||
| 3114 | #define PMU_VREG14_RSRC_EN_ASR_PWM_PFM_MASK (1u << 18u) | |
| 3115 | #define PMU_VREG14_RSRC_EN_ASR_PWM_PFM_SHIFT (18u) | |
| 3116 | ||
| 3117 | #define CSR_VOLT_ADJ_PWM_4378 (0x17u) | |
| 3118 | #define CSR_VOLT_ADJ_PFM_4378 (0x17u) | |
| 3119 | #define CSR_VOLT_ADJ_LP_PFM_4378 (0x17u) | |
| 3120 | #define CSR_OUT_VOLT_TRIM_ADJ_4378 (0xEu) | |
| 3121 | ||
| 3122 | /* 1.00V */ | |
| 3123 | #define ABUCK_VOLT_SW_DEFAULT_4387 (0x1Fu) | |
| 3124 | ||
| 3125 | /* 0.68V */ | |
| 3126 | #define CBUCK_VOLT_SW_DEFAULT_4387 (0xFu) | |
| 3127 | ||
| 3128 | #define CC_GCI1_REG (0x1) | |
| 3129 | ||
| 3130 | #define FORCE_CLK_ON 1 | |
| 3131 | #define FORCE_CLK_OFF 0 | |
| 3132 | ||
| 3133 | #define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0) | |
| 3134 | #define PMU1_PLL0_SWITCH_MACCLOCK_160MHZ (1) | |
| 3135 | #define PMU1_PLL0_PC1_M2DIV_VALUE_120MHZ 8 | |
| 3136 | #define PMU1_PLL0_PC1_M2DIV_VALUE_160MHZ 6 | |
| 3137 | ||
| 3138 | /* 4369 Related */ | |
| 3139 | ||
| 3140 | /* | |
| 3141 | * PMU VREG Definitions: | |
| 3142 | * http://confluence.broadcom.com/display/WLAN/BCM4369+PMU+Vreg+Control+Register | |
| 3143 | */ | |
| 3144 | /* PMU VREG4 */ | |
| 3145 | #define PMU_28NM_VREG4_WL_LDO_CNTL_EN (0x1 << 10) | |
| 3146 | ||
| 3147 | /* PMU VREG6 */ | |
| 3148 | #define PMU_28NM_VREG6_BTLDO3P3_PU (0x1 << 12) | |
| 3149 | #define PMU_4387_VREG6_BTLDO3P3_PU (0x1 << 8) | |
| 3150 | ||
| 3151 | /* PMU resources */ | |
| 3152 | #define RES4347_XTAL_PU 6 | |
| 3153 | #define RES4347_CORE_RDY_DIG 17 | |
| 3154 | #define RES4347_CORE_RDY_AUX 18 | |
| 3155 | #define RES4347_CORE_RDY_MAIN 22 | |
| 3156 | ||
| 3157 | /* 4369 PMU Resources */ | |
| 3158 | #define RES4369_DUMMY 0 | |
| 3159 | #define RES4369_ABUCK 1 | |
| 3160 | #define RES4369_PMU_SLEEP 2 | |
| 3161 | #define RES4369_MISCLDO 3 | |
| 3162 | #define RES4369_LDO3P3 4 | |
| 3163 | #define RES4369_FAST_LPO_AVAIL 5 | |
| 3164 | #define RES4369_XTAL_PU 6 | |
| 3165 | #define RES4369_XTAL_STABLE 7 | |
| 3166 | #define RES4369_PWRSW_DIG 8 | |
| 3167 | #define RES4369_SR_DIG 9 | |
| 3168 | #define RES4369_SLEEP_DIG 10 | |
| 3169 | #define RES4369_PWRSW_AUX 11 | |
| 3170 | #define RES4369_SR_AUX 12 | |
| 3171 | #define RES4369_SLEEP_AUX 13 | |
| 3172 | #define RES4369_PWRSW_MAIN 14 | |
| 3173 | #define RES4369_SR_MAIN 15 | |
| 3174 | #define RES4369_SLEEP_MAIN 16 | |
| 3175 | #define RES4369_DIG_CORE_RDY 17 | |
| 3176 | #define RES4369_CORE_RDY_AUX 18 | |
| 3177 | #define RES4369_ALP_AVAIL 19 | |
| 3178 | #define RES4369_RADIO_AUX_PU 20 | |
| 3179 | #define RES4369_MINIPMU_AUX_PU 21 | |
| 3180 | #define RES4369_CORE_RDY_MAIN 22 | |
| 3181 | #define RES4369_RADIO_MAIN_PU 23 | |
| 3182 | #define RES4369_MINIPMU_MAIN_PU 24 | |
| 3183 | #define RES4369_PCIE_EP_PU 25 | |
| 3184 | #define RES4369_COLD_START_WAIT 26 | |
| 3185 | #define RES4369_ARMHTAVAIL 27 | |
| 3186 | #define RES4369_HT_AVAIL 28 | |
| 3187 | #define RES4369_MACPHY_AUX_CLK_AVAIL 29 | |
| 3188 | #define RES4369_MACPHY_MAIN_CLK_AVAIL 30 | |
| 3189 | ||
| 3190 | /* | |
| 3191 | * 4378 PMU Resources | |
| 3192 | */ | |
| 3193 | #define RES4378_DUMMY 0 | |
| 3194 | #define RES4378_ABUCK 1 | |
| 3195 | #define RES4378_PMU_SLEEP 2 | |
| 3196 | #define RES4378_MISC_LDO 3 | |
| 3197 | #define RES4378_LDO3P3_PU 4 | |
| 3198 | #define RES4378_FAST_LPO_AVAIL 5 | |
| 3199 | #define RES4378_XTAL_PU 6 | |
| 3200 | #define RES4378_XTAL_STABLE 7 | |
| 3201 | #define RES4378_PWRSW_DIG 8 | |
| 3202 | #define RES4378_SR_DIG 9 | |
| 3203 | #define RES4378_SLEEP_DIG 10 | |
| 3204 | #define RES4378_PWRSW_AUX 11 | |
| 3205 | #define RES4378_SR_AUX 12 | |
| 3206 | #define RES4378_SLEEP_AUX 13 | |
| 3207 | #define RES4378_PWRSW_MAIN 14 | |
| 3208 | #define RES4378_SR_MAIN 15 | |
| 3209 | #define RES4378_SLEEP_MAIN 16 | |
| 3210 | #define RES4378_CORE_RDY_DIG 17 | |
| 3211 | #define RES4378_CORE_RDY_AUX 18 | |
| 3212 | #define RES4378_ALP_AVAIL 19 | |
| 3213 | #define RES4378_RADIO_AUX_PU 20 | |
| 3214 | #define RES4378_MINIPMU_AUX_PU 21 | |
| 3215 | #define RES4378_CORE_RDY_MAIN 22 | |
| 3216 | #define RES4378_RADIO_MAIN_PU 23 | |
| 3217 | #define RES4378_MINIPMU_MAIN_PU 24 | |
| 3218 | #define RES4378_CORE_RDY_CB 25 | |
| 3219 | #define RES4378_PWRSW_CB 26 | |
| 3220 | #define RES4378_ARMHTAVAIL 27 | |
| 3221 | #define RES4378_HT_AVAIL 28 | |
| 3222 | #define RES4378_MACPHY_AUX_CLK_AVAIL 29 | |
| 3223 | #define RES4378_MACPHY_MAIN_CLK_AVAIL 30 | |
| 3224 | #define RES4378_RESERVED_31 31 | |
| 3225 | ||
| 3226 | /* | |
| 3227 | * 4387 PMU Resources | |
| 3228 | */ | |
| 3229 | #define RES4387_DUMMY 0 | |
| 3230 | #define RES4387_RESERVED_1 1 | |
| 3231 | #define RES4387_FAST_LPO_AVAIL 1 /* C0 */ | |
| 3232 | #define RES4387_PMU_SLEEP 2 | |
| 3233 | #define RES4387_PMU_LP 2 /* C0 */ | |
| 3234 | #define RES4387_MISC_LDO 3 | |
| 3235 | #define RES4387_RESERVED_4 4 | |
| 3236 | #define RES4387_SERDES_AFE_RET 4 /* C0 */ | |
| 3237 | #define RES4387_XTAL_HQ 5 | |
| 3238 | #define RES4387_XTAL_PU 6 | |
| 3239 | #define RES4387_XTAL_STABLE 7 | |
| 3240 | #define RES4387_PWRSW_DIG 8 | |
| 3241 | #define RES4387_CORE_RDY_BTMAIN 9 | |
| 3242 | #define RES4387_CORE_RDY_BTSC 10 | |
| 3243 | #define RES4387_PWRSW_AUX 11 | |
| 3244 | #define RES4387_PWRSW_SCAN 12 | |
| 3245 | #define RES4387_CORE_RDY_SCAN 13 | |
| 3246 | #define RES4387_PWRSW_MAIN 14 | |
| 3247 | #define RES4387_RESERVED_15 15 | |
| 3248 | #define RES4387_XTAL_PM_CLK 15 /* C0 */ | |
| 3249 | #define RES4387_RESERVED_16 16 | |
| 3250 | #define RES4387_CORE_RDY_DIG 17 | |
| 3251 | #define RES4387_CORE_RDY_AUX 18 | |
| 3252 | #define RES4387_ALP_AVAIL 19 | |
| 3253 | #define RES4387_RADIO_PU_AUX 20 | |
| 3254 | #define RES4387_RADIO_PU_SCAN 21 | |
| 3255 | #define RES4387_CORE_RDY_MAIN 22 | |
| 3256 | #define RES4387_RADIO_PU_MAIN 23 | |
| 3257 | #define RES4387_MACPHY_CLK_SCAN 24 | |
| 3258 | #define RES4387_CORE_RDY_CB 25 | |
| 3259 | #define RES4387_PWRSW_CB 26 | |
| 3260 | #define RES4387_ARMCLK_AVAIL 27 | |
| 3261 | #define RES4387_HT_AVAIL 28 | |
| 3262 | #define RES4387_MACPHY_CLK_AUX 29 | |
| 3263 | #define RES4387_MACPHY_CLK_MAIN 30 | |
| 3264 | #define RES4387_RESERVED_31 31 | |
| 3265 | ||
| 3266 | /* 4388 PMU Resources */ | |
| 3267 | #define RES4388_DUMMY 0u | |
| 3268 | #define RES4388_FAST_LPO_AVAIL 1u | |
| 3269 | #define RES4388_PMU_LP 2u | |
| 3270 | #define RES4388_MISC_LDO 3u | |
| 3271 | #define RES4388_SERDES_AFE_RET 4u | |
| 3272 | #define RES4388_XTAL_HQ 5u | |
| 3273 | #define RES4388_XTAL_PU 6u | |
| 3274 | #define RES4388_XTAL_STABLE 7u | |
| 3275 | #define RES4388_PWRSW_DIG 8u | |
| 3276 | #define RES4388_BTMC_TOP_RDY 9u | |
| 3277 | #define RES4388_BTSC_TOP_RDY 10u | |
| 3278 | #define RES4388_PWRSW_AUX 11u | |
| 3279 | #define RES4388_PWRSW_SCAN 12u | |
| 3280 | #define RES4388_CORE_RDY_SCAN 13u | |
| 3281 | #define RES4388_PWRSW_MAIN 14u | |
| 3282 | #define RES4388_RESERVED_15 15u | |
| 3283 | #define RES4388_RESERVED_16 16u | |
| 3284 | #define RES4388_CORE_RDY_DIG 17u | |
| 3285 | #define RES4388_CORE_RDY_AUX 18u | |
| 3286 | #define RES4388_ALP_AVAIL 19u | |
| 3287 | #define RES4388_RADIO_PU_AUX 20u | |
| 3288 | #define RES4388_RADIO_PU_SCAN 21u | |
| 3289 | #define RES4388_CORE_RDY_MAIN 22u | |
| 3290 | #define RES4388_RADIO_PU_MAIN 23u | |
| 3291 | #define RES4388_MACPHY_CLK_SCAN 24u | |
| 3292 | #define RES4388_CORE_RDY_CB 25u | |
| 3293 | #define RES4388_PWRSW_CB 26u | |
| 3294 | #define RES4388_ARMCLKAVAIL 27u | |
| 3295 | #define RES4388_HT_AVAIL 28u | |
| 3296 | #define RES4388_MACPHY_CLK_AUX 29u | |
| 3297 | #define RES4388_MACPHY_CLK_MAIN 30u | |
| 3298 | #define RES4388_RESERVED_31 31u | |
| 3299 | ||
| 3300 | /* 4389 PMU Resources */ | |
| 3301 | #define RES4389_DUMMY 0u | |
| 3302 | #define RES4389_FAST_LPO_AVAIL 1u | |
| 3303 | #define RES4389_PMU_LP 2u | |
| 3304 | #define RES4389_MISC_LDO 3u | |
| 3305 | #define RES4389_SERDES_AFE_RET 4u | |
| 3306 | #define RES4389_XTAL_HQ 5u | |
| 3307 | #define RES4389_XTAL_PU 6u | |
| 3308 | #define RES4389_XTAL_STABLE 7u | |
| 3309 | #define RES4389_PWRSW_DIG 8u | |
| 3310 | #define RES4389_BTMC_TOP_RDY 9u | |
| 3311 | #define RES4389_BTSC_TOP_RDY 10u | |
| 3312 | #define RES4389_PWRSW_AUX 11u | |
| 3313 | #define RES4389_PWRSW_SCAN 12u | |
| 3314 | #define RES4389_CORE_RDY_SCAN 13u | |
| 3315 | #define RES4389_PWRSW_MAIN 14u | |
| 3316 | #define RES4389_RESERVED_15 15u | |
| 3317 | #define RES4389_RESERVED_16 16u | |
| 3318 | #define RES4389_CORE_RDY_DIG 17u | |
| 3319 | #define RES4389_CORE_RDY_AUX 18u | |
| 3320 | #define RES4389_ALP_AVAIL 19u | |
| 3321 | #define RES4389_RADIO_PU_AUX 20u | |
| 3322 | #define RES4389_RADIO_PU_SCAN 21u | |
| 3323 | #define RES4389_CORE_RDY_MAIN 22u | |
| 3324 | #define RES4389_RADIO_PU_MAIN 23u | |
| 3325 | #define RES4389_MACPHY_CLK_SCAN 24u | |
| 3326 | #define RES4389_CORE_RDY_CB 25u | |
| 3327 | #define RES4389_PWRSW_CB 26u | |
| 3328 | #define RES4389_ARMCLKAVAIL 27u | |
| 3329 | #define RES4389_HT_AVAIL 28u | |
| 3330 | #define RES4389_MACPHY_CLK_AUX 29u | |
| 3331 | #define RES4389_MACPHY_CLK_MAIN 30u | |
| 3332 | #define RES4389_RESERVED_31 31u | |
| 3333 | ||
| 3334 | /* 4397 PMU Resources */ | |
| 3335 | #define RES4397_DUMMY 0u | |
| 3336 | #define RES4397_FAST_LPO_AVAIL 1u | |
| 3337 | #define RES4397_PMU_LP 2u | |
| 3338 | #define RES4397_MISC_LDO 3u | |
| 3339 | #define RES4397_SERDES_AFE_RET 4u | |
| 3340 | #define RES4397_XTAL_HQ 5u | |
| 3341 | #define RES4397_XTAL_PU 6u | |
| 3342 | #define RES4397_XTAL_STABLE 7u | |
| 3343 | #define RES4397_PWRSW_DIG 8u | |
| 3344 | #define RES4397_BTMC_TOP_RDY 9u | |
| 3345 | #define RES4397_BTSC_TOP_RDY 10u | |
| 3346 | #define RES4397_PWRSW_AUX 11u | |
| 3347 | #define RES4397_PWRSW_SCAN 12u | |
| 3348 | #define RES4397_CORE_RDY_SCAN 13u | |
| 3349 | #define RES4397_PWRSW_MAIN 14u | |
| 3350 | #define RES4397_XTAL_PM_CLK 15u | |
| 3351 | #define RES4397_PWRSW_DRR2 16u | |
| 3352 | #define RES4397_CORE_RDY_DIG 17u | |
| 3353 | #define RES4397_CORE_RDY_AUX 18u | |
| 3354 | #define RES4397_ALP_AVAIL 19u | |
| 3355 | #define RES4397_RADIO_PU_AUX 20u | |
| 3356 | #define RES4397_RADIO_PU_SCAN 21u | |
| 3357 | #define RES4397_CORE_RDY_MAIN 22u | |
| 3358 | #define RES4397_RADIO_PU_MAIN 23u | |
| 3359 | #define RES4397_MACPHY_CLK_SCAN 24u | |
| 3360 | #define RES4397_CORE_RDY_CB 25u | |
| 3361 | #define RES4397_PWRSW_CB 26u | |
| 3362 | #define RES4397_ARMCLKAVAIL 27u | |
| 3363 | #define RES4397_HT_AVAIL 28u | |
| 3364 | #define RES4397_MACPHY_CLK_AUX 29u | |
| 3365 | #define RES4397_MACPHY_CLK_MAIN 30u | |
| 3366 | #define RES4397_RESERVED_31 31u | |
| 3367 | ||
| 3368 | /* 0: BToverPCIe, 1: BToverUART */ | |
| 3369 | #define CST4378_CHIPMODE_BTOU(cs) (((cs) & (1 << 6)) != 0) | |
| 3370 | #define CST4378_CHIPMODE_BTOP(cs) (((cs) & (1 << 6)) == 0) | |
| 3371 | #define CST4378_SPROM_PRESENT 0x00000010 | |
| 3372 | ||
| 3373 | #define CST4368_SFLASH_PRESENT 0x00000010U | |
| 3374 | ||
| 3375 | #define CST4387_CHIPMODE_BTOU(cs) (((cs) & (1 << 6)) != 0) | |
| 3376 | #define CST4387_CHIPMODE_BTOP(cs) (((cs) & (1 << 6)) == 0) | |
| 3377 | #define CST4387_SPROM_PRESENT 0x00000010 | |
| 3378 | ||
| 3379 | /* GCI chip status */ | |
| 3380 | #define GCI_CS_4369_FLL1MHZ_LOCK_MASK (1 << 1) | |
| 3381 | #define GCI_CS_4387_FLL1MHZ_LOCK_MASK (1 << 1) | |
| 3382 | ||
| 3383 | /* GCI chip control registers */ | |
| 3384 | #define GCI_CC7_AAON_BYPASS_PWRSW_SEL 13 | |
| 3385 | #define GCI_CC7_AAON_BYPASS_PWRSW_SEQ_ON 14 | |
| 3386 | ||
| 3387 | /* 4368 GCI chip control registers */ | |
| 3388 | #define GCI_CC7_PRISEL_MASK (1 << 8 | 1 << 9) | |
| 3389 | #define GCI_CC12_PRISEL_MASK (1 << 0 | 1 << 1) | |
| 3390 | #define GCI_CC12_PRISEL_SHIFT 0 | |
| 3391 | #define GCI_CC12_DMASK_MASK (0x3ff << 10) | |
| 3392 | #define GCI_CC16_ANT_SHARE_MASK (1 << 16 | 1 << 17) | |
| 3393 | ||
| 3394 | #define CC2_4362_SDIO_AOS_WAKEUP_MASK (1u << 24u) | |
| 3395 | #define CC2_4362_SDIO_AOS_WAKEUP_SHIFT 24u | |
| 3396 | ||
| 3397 | #define CC2_4378_MAIN_MEMLPLDO_VDDB_OFF_MASK (1 << 12) | |
| 3398 | #define CC2_4378_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12 | |
| 3399 | #define CC2_4378_AUX_MEMLPLDO_VDDB_OFF_MASK (1 << 13) | |
| 3400 | #define CC2_4378_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13 | |
| 3401 | #define CC2_4378_MAIN_VDDRET_ON_MASK (1 << 15) | |
| 3402 | #define CC2_4378_MAIN_VDDRET_ON_SHIFT 15 | |
| 3403 | #define CC2_4378_AUX_VDDRET_ON_MASK (1 << 16) | |
| 3404 | #define CC2_4378_AUX_VDDRET_ON_SHIFT 16 | |
| 3405 | #define CC2_4378_GCI2WAKE_MASK (1 << 31) | |
| 3406 | #define CC2_4378_GCI2WAKE_SHIFT 31 | |
| 3407 | #define CC2_4378_SDIO_AOS_WAKEUP_MASK (1 << 24) | |
| 3408 | #define CC2_4378_SDIO_AOS_WAKEUP_SHIFT 24 | |
| 3409 | #define CC4_4378_LHL_TIMER_SELECT (1 << 0) | |
| 3410 | #define CC6_4378_PWROK_WDT_EN_IN_MASK (1 << 6) | |
| 3411 | #define CC6_4378_PWROK_WDT_EN_IN_SHIFT 6 | |
| 3412 | #define CC6_4378_SDIO_AOS_CHIP_WAKEUP_MASK (1 << 24) | |
| 3413 | #define CC6_4378_SDIO_AOS_CHIP_WAKEUP_SHIFT 24 | |
| 3414 | ||
| 3415 | #define CC2_4378_USE_WLAN_BP_CLK_ON_REQ_MASK (1 << 15) | |
| 3416 | #define CC2_4378_USE_WLAN_BP_CLK_ON_REQ_SHIFT 15 | |
| 3417 | #define CC2_4378_USE_CMN_BP_CLK_ON_REQ_MASK (1 << 16) | |
| 3418 | #define CC2_4378_USE_CMN_BP_CLK_ON_REQ_SHIFT 16 | |
| 3419 | ||
| 3420 | #define CC2_4387_MAIN_MEMLPLDO_VDDB_OFF_MASK (1 << 12) | |
| 3421 | #define CC2_4387_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12 | |
| 3422 | #define CC2_4387_AUX_MEMLPLDO_VDDB_OFF_MASK (1 << 13) | |
| 3423 | #define CC2_4387_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13 | |
| 3424 | #define CC2_4387_MAIN_VDDRET_ON_MASK (1 << 15) | |
| 3425 | #define CC2_4387_MAIN_VDDRET_ON_SHIFT 15 | |
| 3426 | #define CC2_4387_AUX_VDDRET_ON_MASK (1 << 16) | |
| 3427 | #define CC2_4387_AUX_VDDRET_ON_SHIFT 16 | |
| 3428 | #define CC2_4387_GCI2WAKE_MASK (1 << 31) | |
| 3429 | #define CC2_4387_GCI2WAKE_SHIFT 31 | |
| 3430 | #define CC2_4387_SDIO_AOS_WAKEUP_MASK (1 << 24) | |
| 3431 | #define CC2_4387_SDIO_AOS_WAKEUP_SHIFT 24 | |
| 3432 | #define CC4_4387_LHL_TIMER_SELECT (1 << 0) | |
| 3433 | #define CC6_4387_PWROK_WDT_EN_IN_MASK (1 << 6) | |
| 3434 | #define CC6_4387_PWROK_WDT_EN_IN_SHIFT 6 | |
| 3435 | #define CC6_4387_SDIO_AOS_CHIP_WAKEUP_MASK (1 << 24) | |
| 3436 | #define CC6_4387_SDIO_AOS_CHIP_WAKEUP_SHIFT 24 | |
| 3437 | ||
| 3438 | #define CC2_4387_USE_WLAN_BP_CLK_ON_REQ_MASK (1 << 15) | |
| 3439 | #define CC2_4387_USE_WLAN_BP_CLK_ON_REQ_SHIFT 15 | |
| 3440 | #define CC2_4387_USE_CMN_BP_CLK_ON_REQ_MASK (1 << 16) | |
| 3441 | #define CC2_4387_USE_CMN_BP_CLK_ON_REQ_SHIFT 16 | |
| 3442 | ||
| 3443 | #define CC2_4389_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u) | |
| 3444 | #define CC2_4389_MAIN_MEMLPLDO_VDDB_OFF_SHIFT (12u) | |
| 3445 | #define CC2_4389_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u) | |
| 3446 | #define CC2_4389_AUX_MEMLPLDO_VDDB_OFF_SHIFT (13u) | |
| 3447 | #define CC2_4389_MAIN_VDDRET_ON_MASK (1u << 15u) | |
| 3448 | #define CC2_4389_MAIN_VDDRET_ON_SHIFT (15u) | |
| 3449 | #define CC2_4389_AUX_VDDRET_ON_MASK (1u << 16u) | |
| 3450 | #define CC2_4389_AUX_VDDRET_ON_SHIFT (16u) | |
| 3451 | #define CC2_4389_GCI2WAKE_MASK (1u << 31u) | |
| 3452 | #define CC2_4389_GCI2WAKE_SHIFT (31u) | |
| 3453 | #define CC2_4389_SDIO_AOS_WAKEUP_MASK (1u << 24u) | |
| 3454 | #define CC2_4389_SDIO_AOS_WAKEUP_SHIFT (24u) | |
| 3455 | #define CC4_4389_LHL_TIMER_SELECT (1u << 0u) | |
| 3456 | #define CC6_4389_PWROK_WDT_EN_IN_MASK (1u << 6u) | |
| 3457 | #define CC6_4389_PWROK_WDT_EN_IN_SHIFT (6u) | |
| 3458 | #define CC6_4389_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u) | |
| 3459 | #define CC6_4389_SDIO_AOS_CHIP_WAKEUP_SHIFT (24u) | |
| 3460 | ||
| 3461 | #define CC2_4389_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u) | |
| 3462 | #define CC2_4389_USE_WLAN_BP_CLK_ON_REQ_SHIFT (15u) | |
| 3463 | #define CC2_4389_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u) | |
| 3464 | #define CC2_4389_USE_CMN_BP_CLK_ON_REQ_SHIFT (16u) | |
| 3465 | ||
| 3466 | #define PCIE_GPIO1_GPIO_PIN CC_GCI_GPIO_0 | |
| 3467 | #define PCIE_PERST_GPIO_PIN CC_GCI_GPIO_1 | |
| 3468 | #define PCIE_CLKREQ_GPIO_PIN CC_GCI_GPIO_2 | |
| 3469 | ||
| 3470 | #define VREG5_4378_MEMLPLDO_ADJ_MASK 0xF0000000 | |
| 3471 | #define VREG5_4378_MEMLPLDO_ADJ_SHIFT 28 | |
| 3472 | #define VREG5_4378_LPLDO_ADJ_MASK 0x00F00000 | |
| 3473 | #define VREG5_4378_LPLDO_ADJ_SHIFT 20 | |
| 3474 | ||
| 3475 | #define VREG5_4387_MISCLDO_PU_MASK (0x00000800u) | |
| 3476 | #define VREG5_4387_MISCLDO_PU_SHIFT (11u) | |
| 3477 | ||
| 3478 | #define VREG5_4387_MEMLPLDO_ADJ_MASK 0xF0000000 | |
| 3479 | #define VREG5_4387_MEMLPLDO_ADJ_SHIFT 28 | |
| 3480 | #define VREG5_4387_LPLDO_ADJ_MASK 0x00F00000 | |
| 3481 | #define VREG5_4387_LPLDO_ADJ_SHIFT 20 | |
| 3482 | ||
| 3483 | /* lpldo/memlpldo voltage */ | |
| 3484 | #define PMU_VREG5_LPLDO_VOLT_0_88 0xf /* 0.88v */ | |
| 3485 | #define PMU_VREG5_LPLDO_VOLT_0_86 0xe /* 0.86v */ | |
| 3486 | #define PMU_VREG5_LPLDO_VOLT_0_84 0xd /* 0.84v */ | |
| 3487 | #define PMU_VREG5_LPLDO_VOLT_0_82 0xc /* 0.82v */ | |
| 3488 | #define PMU_VREG5_LPLDO_VOLT_0_80 0xb /* 0.80v */ | |
| 3489 | #define PMU_VREG5_LPLDO_VOLT_0_78 0xa /* 0.78v */ | |
| 3490 | #define PMU_VREG5_LPLDO_VOLT_0_76 0x9 /* 0.76v */ | |
| 3491 | #define PMU_VREG5_LPLDO_VOLT_0_74 0x8 /* 0.74v */ | |
| 3492 | #define PMU_VREG5_LPLDO_VOLT_0_72 0x7 /* 0.72v */ | |
| 3493 | #define PMU_VREG5_LPLDO_VOLT_1_10 0x6 /* 1.10v */ | |
| 3494 | #define PMU_VREG5_LPLDO_VOLT_1_00 0x5 /* 1.00v */ | |
| 3495 | #define PMU_VREG5_LPLDO_VOLT_0_98 0x4 /* 0.98v */ | |
| 3496 | #define PMU_VREG5_LPLDO_VOLT_0_96 0x3 /* 0.96v */ | |
| 3497 | #define PMU_VREG5_LPLDO_VOLT_0_94 0x2 /* 0.94v */ | |
| 3498 | #define PMU_VREG5_LPLDO_VOLT_0_92 0x1 /* 0.92v */ | |
| 3499 | #define PMU_VREG5_LPLDO_VOLT_0_90 0x0 /* 0.90v */ | |
| 3500 | ||
| 3501 | /* Save/Restore engine */ | |
| 3502 | ||
| 3503 | /* 512 bytes block */ | |
| 3504 | #define SR_ASM_ADDR_BLK_SIZE_SHIFT (9u) | |
| 3505 | ||
| 3506 | #define BM_ADDR_TO_SR_ADDR(bmaddr) ((bmaddr) >> SR_ASM_ADDR_BLK_SIZE_SHIFT) | |
| 3507 | #define SR_ADDR_TO_BM_ADDR(sraddr) ((sraddr) << SR_ASM_ADDR_BLK_SIZE_SHIFT) | |
| 3508 | ||
| 3509 | /* Txfifo is 512KB for main core and 128KB for aux core | |
| 3510 | * We use first 12kB (0x3000) in BMC buffer for template in main core and | |
| 3511 | * 6.5kB (0x1A00) in aux core, followed by ASM code | |
| 3512 | */ | |
| 3513 | #define SR_ASM_ADDR_MAIN_4369 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3514 | #define SR_ASM_ADDR_AUX_4369 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3515 | #define SR_ASM_ADDR_DIG_4369 (0x0) | |
| 3516 | ||
| 3517 | #define SR_ASM_ADDR_MAIN_4362 BM_ADDR_TO_SR_ADDR(0xc00u) | |
| 3518 | #define SR_ASM_ADDR_DIG_4362 (0x0u) | |
| 3519 | ||
| 3520 | #define SR_ASM_ADDR_MAIN_4378 (0x18) | |
| 3521 | #define SR_ASM_ADDR_AUX_4378 (0xd) | |
| 3522 | /* backplane address, use last 16k of BTCM for s/r */ | |
| 3523 | #define SR_ASM_ADDR_DIG_4378A0 (0x51c000) | |
| 3524 | ||
| 3525 | /* backplane address, use last 32k of BTCM for s/r */ | |
| 3526 | #define SR_ASM_ADDR_DIG_4378B0 (0x518000) | |
| 3527 | ||
| 3528 | #define SR_ASM_ADDR_MAIN_4368 (0x40) | |
| 3529 | #define SR_ASM_ADDR_AUX_4368 (0x48) | |
| 3530 | #define SR_ASM_ADDR_DIG_4368 (0x18520000) | |
| 3531 | #define SR_ASM_SIZE_DIG_4368 (6114u * 8u) | |
| 3532 | ||
| 3533 | #define SR_ASM_ADDR_MAIN_4387 (0x18) | |
| 3534 | #define SR_ASM_ADDR_AUX_4387 (0xd) | |
| 3535 | #define SR_ASM_ADDR_SCAN_4387 (0) | |
| 3536 | /* backplane address */ | |
| 3537 | #define SR_ASM_ADDR_DIG_4387 (0x800000) | |
| 3538 | ||
| 3539 | #define SR_ASM_ADDR_MAIN_4387C0 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3540 | #define SR_ASM_ADDR_AUX_4387C0 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3541 | #define SR_ASM_ADDR_DIG_4387C0 (0x931000) | |
| 3542 | #define SR_ASM_ADDR_DIG_4387_C0 (0x931000) | |
| 3543 | ||
| 3544 | #define SR_ASM_ADDR_MAIN_4388 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3545 | #define SR_ASM_ADDR_AUX_4388 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3546 | #define SR_ASM_ADDR_SCAN_4388 BM_ADDR_TO_SR_ADDR(0) | |
| 3547 | #define SR_ASM_ADDR_DIG_4388 (0x18520000) | |
| 3548 | #define SR_ASM_SIZE_DIG_4388 (65536u) | |
| 3549 | ||
| 3550 | #define SR_ASM_ADDR_MAIN_4389C0 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3551 | #define SR_ASM_ADDR_AUX_4389C0 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3552 | #define SR_ASM_ADDR_SCAN_4389C0 BM_ADDR_TO_SR_ADDR(0x000) | |
| 3553 | #define SR_ASM_ADDR_DIG_4389C0 (0x18520000) | |
| 3554 | #define SR_ASM_SIZE_DIG_4389C0 (8192u * 8u) | |
| 3555 | ||
| 3556 | #define SR_ASM_ADDR_MAIN_4389 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3557 | #define SR_ASM_ADDR_AUX_4389 BM_ADDR_TO_SR_ADDR(0xC00) | |
| 3558 | #define SR_ASM_ADDR_SCAN_4389 BM_ADDR_TO_SR_ADDR(0x000) | |
| 3559 | #define SR_ASM_ADDR_DIG_4389 (0x18520000) | |
| 3560 | #define SR_ASM_SIZE_DIG_4389 (8192u * 8u) | |
| 3561 | #define FIS_CMN_SUBCORE_ADDR_4389 (0x1640u) | |
| 3562 | ||
| 3563 | #define SR_ASM_ADDR_DIG_4397 (0x18520000) | |
| 3564 | ||
| 3565 | /* SR Control0 bits */ | |
| 3566 | #define SR0_SR_ENG_EN_MASK 0x1 | |
| 3567 | #define SR0_SR_ENG_EN_SHIFT 0 | |
| 3568 | #define SR0_SR_ENG_CLK_EN (1 << 1) | |
| 3569 | #define SR0_RSRC_TRIGGER (0xC << 2) | |
| 3570 | #define SR0_WD_MEM_MIN_DIV (0x3 << 6) | |
| 3571 | #define SR0_INVERT_SR_CLK (1 << 11) | |
| 3572 | #define SR0_MEM_STBY_ALLOW (1 << 16) | |
| 3573 | #define SR0_ENABLE_SR_ILP (1 << 17) | |
| 3574 | #define SR0_ENABLE_SR_ALP (1 << 18) | |
| 3575 | #define SR0_ENABLE_SR_HT (1 << 19) | |
| 3576 | #define SR0_ALLOW_PIC (3 << 20) | |
| 3577 | #define SR0_ENB_PMU_MEM_DISABLE (1 << 30) | |
| 3578 | ||
| 3579 | /* SR Control0 bits for 4369 */ | |
| 3580 | #define SR0_4369_SR_ENG_EN_MASK 0x1 | |
| 3581 | #define SR0_4369_SR_ENG_EN_SHIFT 0 | |
| 3582 | #define SR0_4369_SR_ENG_CLK_EN (1 << 1) | |
| 3583 | #define SR0_4369_RSRC_TRIGGER (0xC << 2) | |
| 3584 | #define SR0_4369_WD_MEM_MIN_DIV (0x2 << 6) | |
| 3585 | #define SR0_4369_INVERT_SR_CLK (1 << 11) | |
| 3586 | #define SR0_4369_MEM_STBY_ALLOW (1 << 16) | |
| 3587 | #define SR0_4369_ENABLE_SR_ILP (1 << 17) | |
| 3588 | #define SR0_4369_ENABLE_SR_ALP (1 << 18) | |
| 3589 | #define SR0_4369_ENABLE_SR_HT (1 << 19) | |
| 3590 | #define SR0_4369_ALLOW_PIC (3 << 20) | |
| 3591 | #define SR0_4369_ENB_PMU_MEM_DISABLE (1 << 30) | |
| 3592 | ||
| 3593 | /* SR Control0 bits for 4378 */ | |
| 3594 | #define SR0_4378_SR_ENG_EN_MASK 0x1 | |
| 3595 | #define SR0_4378_SR_ENG_EN_SHIFT 0 | |
| 3596 | #define SR0_4378_SR_ENG_CLK_EN (1 << 1) | |
| 3597 | #define SR0_4378_RSRC_TRIGGER (0xC << 2) | |
| 3598 | #define SR0_4378_WD_MEM_MIN_DIV (0x2 << 6) | |
| 3599 | #define SR0_4378_INVERT_SR_CLK (1 << 11) | |
| 3600 | #define SR0_4378_MEM_STBY_ALLOW (1 << 16) | |
| 3601 | #define SR0_4378_ENABLE_SR_ILP (1 << 17) | |
| 3602 | #define SR0_4378_ENABLE_SR_ALP (1 << 18) | |
| 3603 | #define SR0_4378_ENABLE_SR_HT (1 << 19) | |
| 3604 | #define SR0_4378_ALLOW_PIC (3 << 20) | |
| 3605 | #define SR0_4378_ENB_PMU_MEM_DISABLE (1 << 30) | |
| 3606 | ||
| 3607 | /* SR Control0 bits for 4368 */ | |
| 3608 | #define SR0_4368_SR_ENG_EN_MASK 0x1 | |
| 3609 | #define SR0_4368_SR_ENG_EN_SHIFT 0 | |
| 3610 | #define SR0_4368_SR_ENG_CLK_EN (1 << 1) | |
| 3611 | #define SR0_4368_RSRC_TRIGGER (0xC << 2) | |
| 3612 | #define SR0_4368_WD_MEM_MIN_DIV (0x2 << 6) | |
| 3613 | #define SR0_4368_INVERT_SR_CLK (1 << 11) | |
| 3614 | #define SR0_4368_MEM_STBY_ALLOW (1 << 16) | |
| 3615 | #define SR0_4368_ENABLE_SR_ILP (1 << 17) | |
| 3616 | #define SR0_4368_ENABLE_SR_ALP (1 << 18) | |
| 3617 | #define SR0_4368_ENABLE_SR_HT (1 << 19) | |
| 3618 | #define SR0_4368_ALLOW_PIC (3 << 20) | |
| 3619 | #define SR0_4368_ENB_PMU_MEM_DISABLE (1 << 30) | |
| 3620 | ||
| 3621 | /* SR Control0 bits for 4387 */ | |
| 3622 | #define SR0_4387_SR_ENG_EN_MASK 0x1 | |
| 3623 | #define SR0_4387_SR_ENG_EN_SHIFT 0 | |
| 3624 | #define SR0_4387_SR_ENG_CLK_EN (1 << 1) | |
| 3625 | #define SR0_4387_RSRC_TRIGGER (0xC << 2) | |
| 3626 | #define SR0_4387_WD_MEM_MIN_DIV (0x2 << 6) | |
| 3627 | #define SR0_4387_WD_MEM_MIN_DIV_AUX (0x4 << 6) | |
| 3628 | #define SR0_4387_INVERT_SR_CLK (1 << 11) | |
| 3629 | #define SR0_4387_MEM_STBY_ALLOW (1 << 16) | |
| 3630 | #define SR0_4387_ENABLE_SR_ILP (1 << 17) | |
| 3631 | #define SR0_4387_ENABLE_SR_ALP (1 << 18) | |
| 3632 | #define SR0_4387_ENABLE_SR_HT (1 << 19) | |
| 3633 | #define SR0_4387_ALLOW_PIC (3 << 20) | |
| 3634 | #define SR0_4387_ENB_PMU_MEM_DISABLE (1 << 30) | |
| 3635 | ||
| 3636 | /* SR Control0 bits for 4388 */ | |
| 3637 | #define SR0_4388_SR_ENG_EN_MASK 0x1u | |
| 3638 | #define SR0_4388_SR_ENG_EN_SHIFT 0 | |
| 3639 | #define SR0_4388_SR_ENG_CLK_EN (1u << 1u) | |
| 3640 | #define SR0_4388_RSRC_TRIGGER (0xCu << 2u) | |
| 3641 | #define SR0_4388_WD_MEM_MIN_DIV (0x2u << 6u) | |
| 3642 | #define SR0_4388_INVERT_SR_CLK (1u << 11u) | |
| 3643 | #define SR0_4388_MEM_STBY_ALLOW (1u << 16u) | |
| 3644 | #define SR0_4388_ENABLE_SR_ILP (1u << 17u) | |
| 3645 | #define SR0_4388_ENABLE_SR_ALP (1u << 18u) | |
| 3646 | #define SR0_4388_ENABLE_SR_HT (1u << 19u) | |
| 3647 | #define SR0_4388_ALLOW_PIC (3u << 20u) | |
| 3648 | #define SR0_4388_ENB_PMU_MEM_DISABLE (1u << 30u) | |
| 3649 | ||
| 3650 | /* SR Control0 bits for 4389 */ | |
| 3651 | #define SR0_4389_SR_ENG_EN_MASK 0x1 | |
| 3652 | #define SR0_4389_SR_ENG_EN_SHIFT 0 | |
| 3653 | #define SR0_4389_SR_ENG_CLK_EN (1 << 1) | |
| 3654 | #define SR0_4389_RSRC_TRIGGER (0xC << 2) | |
| 3655 | #define SR0_4389_WD_MEM_MIN_DIV (0x2 << 6) | |
| 3656 | #define SR0_4389_INVERT_SR_CLK (1 << 11) | |
| 3657 | #define SR0_4389_MEM_STBY_ALLOW (1 << 16) | |
| 3658 | #define SR0_4389_ENABLE_SR_ILP (1 << 17) | |
| 3659 | #define SR0_4389_ENABLE_SR_ALP (1 << 18) | |
| 3660 | #define SR0_4389_ENABLE_SR_HT (1 << 19) | |
| 3661 | #define SR0_4389_ALLOW_PIC (3 << 20) | |
| 3662 | #define SR0_4389_ENB_PMU_MEM_DISABLE (1 << 30) | |
| 3663 | ||
| 3664 | /* SR Control1 bits */ | |
| 3665 | #define SR1_INIT_ADDR_MASK (0x000003FFu) | |
| 3666 | #define SR1_SELFTEST_ENB_MASK (0x00004000u) | |
| 3667 | #define SR1_SELFTEST_ERR_INJCT_ENB_MASK (0x00008000u) | |
| 3668 | #define SR1_SELFTEST_ERR_INJCT_PRD_MASK (0xFFFF0000u) | |
| 3669 | #define SR1_SELFTEST_ERR_INJCT_PRD_SHIFT (16u) | |
| 3670 | ||
| 3671 | /* SR Control2 bits */ | |
| 3672 | #define SR2_INIT_ADDR_LONG_MASK (0x00003FFFu) | |
| 3673 | ||
| 3674 | #define SR_SELFTEST_ERR_INJCT_PRD (0x10u) | |
| 3675 | ||
| 3676 | /* SR Status1 bits */ | |
| 3677 | #define SR_STS1_SR_ERR_MASK (0x00000001u) | |
| 3678 | ||
| 3679 | /* =========== LHL regs =========== */ | |
| 3680 | /* 4369 LHL register settings */ | |
| 3681 | #define LHL4369_UP_CNT 0 | |
| 3682 | #define LHL4369_DN_CNT 2 | |
| 3683 | #define LHL4369_PWRSW_EN_DWN_CNT (LHL4369_DN_CNT + 2) | |
| 3684 | #define LHL4369_ISO_EN_DWN_CNT (LHL4369_PWRSW_EN_DWN_CNT + 3) | |
| 3685 | #define LHL4369_SLB_EN_DWN_CNT (LHL4369_ISO_EN_DWN_CNT + 1) | |
| 3686 | #define LHL4369_ASR_CLK4M_DIS_DWN_CNT (LHL4369_DN_CNT) | |
| 3687 | #define LHL4369_ASR_LPPFM_MODE_DWN_CNT (LHL4369_DN_CNT) | |
| 3688 | #define LHL4369_ASR_MODE_SEL_DWN_CNT (LHL4369_DN_CNT) | |
| 3689 | #define LHL4369_ASR_MANUAL_MODE_DWN_CNT (LHL4369_DN_CNT) | |
| 3690 | #define LHL4369_ASR_ADJ_DWN_CNT (LHL4369_DN_CNT) | |
| 3691 | #define LHL4369_ASR_OVERI_DIS_DWN_CNT (LHL4369_DN_CNT) | |
| 3692 | #define LHL4369_ASR_TRIM_ADJ_DWN_CNT (LHL4369_DN_CNT) | |
| 3693 | #define LHL4369_VDDC_SW_DIS_DWN_CNT (LHL4369_SLB_EN_DWN_CNT + 1) | |
| 3694 | #define LHL4369_VMUX_ASR_SEL_DWN_CNT (LHL4369_VDDC_SW_DIS_DWN_CNT + 1) | |
| 3695 | #define LHL4369_CSR_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3696 | #define LHL4369_CSR_MODE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3697 | #define LHL4369_CSR_OVERI_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3698 | #define LHL4369_HPBG_CHOP_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3699 | #define LHL4369_SRBG_REF_SEL_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3700 | #define LHL4369_PFM_PWR_SLICE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3701 | #define LHL4369_CSR_TRIM_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3702 | #define LHL4369_CSR_VOLTAGE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3703 | #define LHL4369_HPBG_PU_EN_DWN_CNT (LHL4369_CSR_MODE_DWN_CNT + 1) | |
| 3704 | ||
| 3705 | #define LHL4369_HPBG_PU_EN_UP_CNT (LHL4369_UP_CNT + 1) | |
| 3706 | #define LHL4369_CSR_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3707 | #define LHL4369_CSR_MODE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3708 | #define LHL4369_CSR_OVERI_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3709 | #define LHL4369_HPBG_CHOP_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3710 | #define LHL4369_SRBG_REF_SEL_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3711 | #define LHL4369_PFM_PWR_SLICE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3712 | #define LHL4369_CSR_TRIM_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3713 | #define LHL4369_CSR_VOLTAGE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) | |
| 3714 | #define LHL4369_VMUX_ASR_SEL_UP_CNT (LHL4369_CSR_MODE_UP_CNT + 1) | |
| 3715 | #define LHL4369_VDDC_SW_DIS_UP_CNT (LHL4369_VMUX_ASR_SEL_UP_CNT + 1) | |
| 3716 | #define LHL4369_SLB_EN_UP_CNT (LHL4369_VDDC_SW_DIS_UP_CNT + 8) | |
| 3717 | #define LHL4369_ISO_EN_UP_CNT (LHL4369_SLB_EN_UP_CNT + 1) | |
| 3718 | #define LHL4369_PWRSW_EN_UP_CNT (LHL4369_ISO_EN_UP_CNT + 3) | |
| 3719 | #define LHL4369_ASR_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3720 | #define LHL4369_ASR_CLK4M_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3721 | #define LHL4369_ASR_LPPFM_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3722 | #define LHL4369_ASR_MODE_SEL_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3723 | #define LHL4369_ASR_MANUAL_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3724 | #define LHL4369_ASR_OVERI_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3725 | #define LHL4369_ASR_TRIM_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) | |
| 3726 | ||
| 3727 | /* 4362 LHL register settings */ | |
| 3728 | #define LHL4362_UP_CNT (0u) | |
| 3729 | #define LHL4362_DN_CNT (2u) | |
| 3730 | #define LHL4362_PWRSW_EN_DWN_CNT (LHL4362_DN_CNT + 2) | |
| 3731 | #define LHL4362_ISO_EN_DWN_CNT (LHL4362_PWRSW_EN_DWN_CNT + 3) | |
| 3732 | #define LHL4362_SLB_EN_DWN_CNT (LHL4362_ISO_EN_DWN_CNT + 1) | |
| 3733 | #define LHL4362_ASR_CLK4M_DIS_DWN_CNT (LHL4362_DN_CNT) | |
| 3734 | #define LHL4362_ASR_LPPFM_MODE_DWN_CNT (LHL4362_DN_CNT) | |
| 3735 | #define LHL4362_ASR_MODE_SEL_DWN_CNT (LHL4362_DN_CNT) | |
| 3736 | #define LHL4362_ASR_MANUAL_MODE_DWN_CNT (LHL4362_DN_CNT) | |
| 3737 | #define LHL4362_ASR_ADJ_DWN_CNT (LHL4362_DN_CNT) | |
| 3738 | #define LHL4362_ASR_OVERI_DIS_DWN_CNT (LHL4362_DN_CNT) | |
| 3739 | #define LHL4362_ASR_TRIM_ADJ_DWN_CNT (LHL4362_DN_CNT) | |
| 3740 | #define LHL4362_VDDC_SW_DIS_DWN_CNT (LHL4362_SLB_EN_DWN_CNT + 1) | |
| 3741 | #define LHL4362_VMUX_ASR_SEL_DWN_CNT (LHL4362_VDDC_SW_DIS_DWN_CNT + 1) | |
| 3742 | #define LHL4362_CSR_ADJ_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3743 | #define LHL4362_CSR_MODE_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3744 | #define LHL4362_CSR_OVERI_DIS_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3745 | #define LHL4362_HPBG_CHOP_DIS_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3746 | #define LHL4362_SRBG_REF_SEL_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3747 | #define LHL4362_PFM_PWR_SLICE_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3748 | #define LHL4362_CSR_TRIM_ADJ_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3749 | #define LHL4362_CSR_VOLTAGE_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) | |
| 3750 | #define LHL4362_HPBG_PU_EN_DWN_CNT (LHL4362_CSR_MODE_DWN_CNT + 1) | |
| 3751 | ||
| 3752 | #define LHL4362_HPBG_PU_EN_UP_CNT (LHL4362_UP_CNT + 1) | |
| 3753 | #define LHL4362_CSR_ADJ_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3754 | #define LHL4362_CSR_MODE_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3755 | #define LHL4362_CSR_OVERI_DIS_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3756 | #define LHL4362_HPBG_CHOP_DIS_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3757 | #define LHL4362_SRBG_REF_SEL_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3758 | #define LHL4362_PFM_PWR_SLICE_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3759 | #define LHL4362_CSR_TRIM_ADJ_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3760 | #define LHL4362_CSR_VOLTAGE_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) | |
| 3761 | #define LHL4362_VMUX_ASR_SEL_UP_CNT (LHL4362_CSR_MODE_UP_CNT + 1) | |
| 3762 | #define LHL4362_VDDC_SW_DIS_UP_CNT (LHL4362_VMUX_ASR_SEL_UP_CNT + 1) | |
| 3763 | #define LHL4362_SLB_EN_UP_CNT (LHL4362_VDDC_SW_DIS_UP_CNT + 8) | |
| 3764 | #define LHL4362_ISO_EN_UP_CNT (LHL4362_SLB_EN_UP_CNT + 1) | |
| 3765 | #define LHL4362_PWRSW_EN_UP_CNT (LHL4362_ISO_EN_UP_CNT + 3) | |
| 3766 | #define LHL4362_ASR_ADJ_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3767 | #define LHL4362_ASR_CLK4M_DIS_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3768 | #define LHL4362_ASR_LPPFM_MODE_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3769 | #define LHL4362_ASR_MODE_SEL_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3770 | #define LHL4362_ASR_MANUAL_MODE_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3771 | #define LHL4362_ASR_OVERI_DIS_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3772 | #define LHL4362_ASR_TRIM_ADJ_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) | |
| 3773 | ||
| 3774 | /* 4378 LHL register settings */ | |
| 3775 | #define LHL4378_CSR_OVERI_DIS_DWN_CNT 5u | |
| 3776 | #define LHL4378_CSR_MODE_DWN_CNT 5u | |
| 3777 | #define LHL4378_CSR_ADJ_DWN_CNT 5u | |
| 3778 | ||
| 3779 | #define LHL4378_CSR_OVERI_DIS_UP_CNT 1u | |
| 3780 | #define LHL4378_CSR_MODE_UP_CNT 1u | |
| 3781 | #define LHL4378_CSR_ADJ_UP_CNT 1u | |
| 3782 | ||
| 3783 | #define LHL4378_VDDC_SW_DIS_DWN_CNT 3u | |
| 3784 | #define LHL4378_ASR_ADJ_DWN_CNT 3u | |
| 3785 | #define LHL4378_HPBG_CHOP_DIS_DWN_CNT 0 | |
| 3786 | ||
| 3787 | #define LHL4378_VDDC_SW_DIS_UP_CNT 3u | |
| 3788 | #define LHL4378_ASR_ADJ_UP_CNT 1u | |
| 3789 | #define LHL4378_HPBG_CHOP_DIS_UP_CNT 0 | |
| 3790 | ||
| 3791 | #define LHL4378_ASR_MANUAL_MODE_DWN_CNT 5u | |
| 3792 | #define LHL4378_ASR_MODE_SEL_DWN_CNT 5u | |
| 3793 | #define LHL4378_ASR_LPPFM_MODE_DWN_CNT 5u | |
| 3794 | #define LHL4378_ASR_CLK4M_DIS_DWN_CNT 0 | |
| 3795 | ||
| 3796 | #define LHL4378_ASR_MANUAL_MODE_UP_CNT 1u | |
| 3797 | #define LHL4378_ASR_MODE_SEL_UP_CNT 1u | |
| 3798 | #define LHL4378_ASR_LPPFM_MODE_UP_CNT 1u | |
| 3799 | #define LHL4378_ASR_CLK4M_DIS_UP_CNT 0 | |
| 3800 | ||
| 3801 | #define LHL4378_PFM_PWR_SLICE_DWN_CNT 5u | |
| 3802 | #define LHL4378_ASR_OVERI_DIS_DWN_CNT 5u | |
| 3803 | #define LHL4378_SRBG_REF_SEL_DWN_CNT 5u | |
| 3804 | #define LHL4378_HPBG_PU_EN_DWN_CNT 6u | |
| 3805 | ||
| 3806 | #define LHL4378_PFM_PWR_SLICE_UP_CNT 1u | |
| 3807 | #define LHL4378_ASR_OVERI_DIS_UP_CNT 1u | |
| 3808 | #define LHL4378_SRBG_REF_SEL_UP_CNT 1u | |
| 3809 | #define LHL4378_HPBG_PU_EN_UP_CNT 0 | |
| 3810 | ||
| 3811 | #define LHL4378_CSR_TRIM_ADJ_CNT_SHIFT (16u) | |
| 3812 | #define LHL4378_CSR_TRIM_ADJ_CNT_MASK (0x3Fu << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT) | |
| 3813 | #define LHL4378_CSR_TRIM_ADJ_DWN_CNT 0 | |
| 3814 | #define LHL4378_CSR_TRIM_ADJ_UP_CNT 0 | |
| 3815 | ||
| 3816 | #define LHL4378_ASR_TRIM_ADJ_CNT_SHIFT (0u) | |
| 3817 | #define LHL4378_ASR_TRIM_ADJ_CNT_MASK (0x3Fu << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT) | |
| 3818 | #define LHL4378_ASR_TRIM_ADJ_UP_CNT 0 | |
| 3819 | #define LHL4378_ASR_TRIM_ADJ_DWN_CNT 0 | |
| 3820 | ||
| 3821 | #define LHL4378_PWRSW_EN_DWN_CNT 0 | |
| 3822 | #define LHL4378_SLB_EN_DWN_CNT 2u | |
| 3823 | #define LHL4378_ISO_EN_DWN_CNT 1u | |
| 3824 | ||
| 3825 | #define LHL4378_VMUX_ASR_SEL_DWN_CNT 4u | |
| 3826 | ||
| 3827 | #define LHL4378_PWRSW_EN_UP_CNT 6u | |
| 3828 | #define LHL4378_SLB_EN_UP_CNT 4u | |
| 3829 | #define LHL4378_ISO_EN_UP_CNT 5u | |
| 3830 | ||
| 3831 | #define LHL4378_VMUX_ASR_SEL_UP_CNT 2u | |
| 3832 | ||
| 3833 | #define LHL4387_VMUX_ASR_SEL_DWN_CNT (8u) | |
| 3834 | #define LHL4387_VMUX_ASR_SEL_UP_CNT (0x14u) | |
| 3835 | ||
| 3836 | /* MacResourceReqTimer0/1 */ | |
| 3837 | #define MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT 24 | |
| 3838 | #define MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT 26 | |
| 3839 | #define MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT 27 | |
| 3840 | #define MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT 28 | |
| 3841 | #define MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT 29 | |
| 3842 | ||
| 3843 | /* for pmu rev32 and higher */ | |
| 3844 | #define PMU32_MAC_MAIN_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ | |
| 3845 | (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ | |
| 3846 | (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ | |
| 3847 | (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ | |
| 3848 | (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) | |
| 3849 | ||
| 3850 | #define PMU32_MAC_AUX_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ | |
| 3851 | (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ | |
| 3852 | (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ | |
| 3853 | (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ | |
| 3854 | (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) | |
| 3855 | ||
| 3856 | /* for pmu rev38 and higher */ | |
| 3857 | #define PMU32_MAC_SCAN_RSRC_REQ_TIMER ((1u << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ | |
| 3858 | (1u << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ | |
| 3859 | (1u << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ | |
| 3860 | (1u << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ | |
| 3861 | (0u << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) | |
| 3862 | ||
| 3863 | /* 4369 related: 4369 parameters | |
| 3864 | * http://www.sj.broadcom.com/projects/BCM4369/gallery_backend.RC6.0/design/backplane/pmu_params.xls | |
| 3865 | */ | |
| 3866 | #define RES4369_DUMMY 0 | |
| 3867 | #define RES4369_ABUCK 1 | |
| 3868 | #define RES4369_PMU_SLEEP 2 | |
| 3869 | #define RES4369_MISCLDO_PU 3 | |
| 3870 | #define RES4369_LDO3P3_PU 4 | |
| 3871 | #define RES4369_FAST_LPO_AVAIL 5 | |
| 3872 | #define RES4369_XTAL_PU 6 | |
| 3873 | #define RES4369_XTAL_STABLE 7 | |
| 3874 | #define RES4369_PWRSW_DIG 8 | |
| 3875 | #define RES4369_SR_DIG 9 | |
| 3876 | #define RES4369_SLEEP_DIG 10 | |
| 3877 | #define RES4369_PWRSW_AUX 11 | |
| 3878 | #define RES4369_SR_AUX 12 | |
| 3879 | #define RES4369_SLEEP_AUX 13 | |
| 3880 | #define RES4369_PWRSW_MAIN 14 | |
| 3881 | #define RES4369_SR_MAIN 15 | |
| 3882 | #define RES4369_SLEEP_MAIN 16 | |
| 3883 | #define RES4369_DIG_CORE_RDY 17 | |
| 3884 | #define RES4369_CORE_RDY_AUX 18 | |
| 3885 | #define RES4369_ALP_AVAIL 19 | |
| 3886 | #define RES4369_RADIO_AUX_PU 20 | |
| 3887 | #define RES4369_MINIPMU_AUX_PU 21 | |
| 3888 | #define RES4369_CORE_RDY_MAIN 22 | |
| 3889 | #define RES4369_RADIO_MAIN_PU 23 | |
| 3890 | #define RES4369_MINIPMU_MAIN_PU 24 | |
| 3891 | #define RES4369_PCIE_EP_PU 25 | |
| 3892 | #define RES4369_COLD_START_WAIT 26 | |
| 3893 | #define RES4369_ARMHTAVAIL 27 | |
| 3894 | #define RES4369_HT_AVAIL 28 | |
| 3895 | #define RES4369_MACPHY_AUX_CLK_AVAIL 29 | |
| 3896 | #define RES4369_MACPHY_MAIN_CLK_AVAIL 30 | |
| 3897 | #define RES4369_RESERVED_31 31 | |
| 3898 | ||
| 3899 | #define CST4369_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ | |
| 3900 | #define CST4369_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ | |
| 3901 | #define CST4369_SPROM_PRESENT 0x00000010 | |
| 3902 | ||
| 3903 | #define PMU_4369_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF | |
| 3904 | #define PMU_4369_MACCORE_1_RES_REQ_MASK 0x7FFB3647 | |
| 3905 | ||
| 3906 | /* 4362 related */ | |
| 3907 | /* 4362 resource_table | |
| 3908 | * http://www.sj.broadcom.com/projects/BCM4362/gallery_backend.RC1.mar_15_2017/design/backplane/ | |
| 3909 | * pmu_params.xls | |
| 3910 | */ | |
| 3911 | #define RES4362_DUMMY (0u) | |
| 3912 | #define RES4362_ABUCK (1u) | |
| 3913 | #define RES4362_PMU_SLEEP (2u) | |
| 3914 | #define RES4362_MISCLDO_PU (3u) | |
| 3915 | #define RES4362_LDO3P3_PU (4u) | |
| 3916 | #define RES4362_FAST_LPO_AVAIL (5u) | |
| 3917 | #define RES4362_XTAL_PU (6u) | |
| 3918 | #define RES4362_XTAL_STABLE (7u) | |
| 3919 | #define RES4362_PWRSW_DIG (8u) | |
| 3920 | #define RES4362_SR_DIG (9u) | |
| 3921 | #define RES4362_SLEEP_DIG (10u) | |
| 3922 | #define RES4362_PWRSW_AUX (11u) | |
| 3923 | #define RES4362_SR_AUX (12u) | |
| 3924 | #define RES4362_SLEEP_AUX (13u) | |
| 3925 | #define RES4362_PWRSW_MAIN (14u) | |
| 3926 | #define RES4362_SR_MAIN (15u) | |
| 3927 | #define RES4362_SLEEP_MAIN (16u) | |
| 3928 | #define RES4362_DIG_CORE_RDY (17u) | |
| 3929 | #define RES4362_CORE_RDY_AUX (18u) | |
| 3930 | #define RES4362_ALP_AVAIL (19u) | |
| 3931 | #define RES4362_RADIO_AUX_PU (20u) | |
| 3932 | #define RES4362_MINIPMU_AUX_PU (21u) | |
| 3933 | #define RES4362_CORE_RDY_MAIN (22u) | |
| 3934 | #define RES4362_RADIO_MAIN_PU (23u) | |
| 3935 | #define RES4362_MINIPMU_MAIN_PU (24u) | |
| 3936 | #define RES4362_PCIE_EP_PU (25u) | |
| 3937 | #define RES4362_COLD_START_WAIT (26u) | |
| 3938 | #define RES4362_ARMHTAVAIL (27u) | |
| 3939 | #define RES4362_HT_AVAIL (28u) | |
| 3940 | #define RES4362_MACPHY_AUX_CLK_AVAIL (29u) | |
| 3941 | #define RES4362_MACPHY_MAIN_CLK_AVAIL (30u) | |
| 3942 | #define RES4362_RESERVED_31 (31u) | |
| 3943 | ||
| 3944 | #define CST4362_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ | |
| 3945 | #define CST4362_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ | |
| 3946 | #define CST4362_SPROM_PRESENT (0x00000010u) | |
| 3947 | ||
| 3948 | #define PMU_4362_MACCORE_0_RES_REQ_MASK (0x3FCBF7FFu) | |
| 3949 | #define PMU_4362_MACCORE_1_RES_REQ_MASK (0x7FFB3647u) | |
| 3950 | ||
| 3951 | /* 4368 related */ | |
| 3952 | #define RES4368_ABUCK 0 | |
| 3953 | #define RES4368_CBUCK 1 | |
| 3954 | #define RES4368_MISCLDO_PU 2 | |
| 3955 | #define RES4368_VBOOST 3 | |
| 3956 | #define RES4368_LDO3P3_PU 4 | |
| 3957 | #define RES4368_FAST_LPO_AVAIL 5 | |
| 3958 | #define RES4368_XTAL_PU 6 | |
| 3959 | #define RES4368_XTAL_STABLE 7 | |
| 3960 | #define RES4368_PWRSW_DIG 8 | |
| 3961 | #define RES4368_SR_DIG 9 | |
| 3962 | #define RES4368_SPARE10 10 | |
| 3963 | #define RES4368_PWRSW_AUX 11 | |
| 3964 | #define RES4368_SR_AUX 12 | |
| 3965 | #define RES4368_SPARE2 13 | |
| 3966 | #define RES4368_PWRSW_MAIN 14 | |
| 3967 | #define RES4368_SR_MAIN 15 | |
| 3968 | #define RES4368_ARMPLL_PWRUP 16 | |
| 3969 | #define RES4368_CORE_RDY_DIG 17 | |
| 3970 | #define RES4368_CORE_RDY_AUX 18 | |
| 3971 | #define RES4368_ALP_AVAIL 19 | |
| 3972 | #define RES4368_RADIO_AUX_PU 20 | |
| 3973 | #define RES4368_MINIPMU_AUX_PU 21 | |
| 3974 | #define RES4368_CORE_RDY_MAIN 22 | |
| 3975 | #define RES4368_RADIO_MAIN_PU 23 | |
| 3976 | #define RES4368_MINIPMU_MAIN_PU 24 | |
| 3977 | #define RES4368_PWRSW_CB 25 | |
| 3978 | #define RES4368_CORE_RDY_CB 26 | |
| 3979 | #define RES4368_ARMHTAVAIL 27 | |
| 3980 | #define RES4368_HT_AVAIL 28 | |
| 3981 | #define RES4368_MACPHY_AUX_CLK_AVAIL 29 | |
| 3982 | #define RES4368_MACPHY_MAIN_CLK_AVAIL 30 | |
| 3983 | #define RES4368_RESERVED_31 31 | |
| 3984 | ||
| 3985 | #define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000 | |
| 3986 | #define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F | |
| 3987 | ||
| 3988 | #define PMU43012_MAC_RES_REQ_TIMER 0x1D000000 | |
| 3989 | #define PMU43012_MAC_RES_REQ_MASK 0x3FBBF7FF | |
| 3990 | ||
| 3991 | #define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000 | |
| 3992 | #define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F | |
| 3993 | ||
| 3994 | /* defines to detect active host interface in use */ | |
| 3995 | #define CHIP_HOSTIF_PCIEMODE 0x1 | |
| 3996 | #define CHIP_HOSTIF_USBMODE 0x2 | |
| 3997 | #define CHIP_HOSTIF_SDIOMODE 0x4 | |
| 3998 | #define CHIP_HOSTIF_PCIE(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE) | |
| 3999 | #define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE) | |
| 4000 | #define CHIP_HOSTIF_SDIO(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE) | |
| 4001 | ||
| 4002 | #define PATCHTBL_SIZE (0x800) | |
| 4003 | #define CR4_4335_RAM_BASE (0x180000) | |
| 4004 | #define CR4_4345_LT_C0_RAM_BASE (0x1b0000) | |
| 4005 | #define CR4_4345_GE_C0_RAM_BASE (0x198000) | |
| 4006 | #define CR4_4349_RAM_BASE (0x180000) | |
| 4007 | #define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000) | |
| 4008 | #define CR4_4350_RAM_BASE (0x180000) | |
| 4009 | #define CR4_4360_RAM_BASE (0x0) | |
| 4010 | #define CR4_43602_RAM_BASE (0x180000) | |
| 4011 | ||
| 4012 | #define CR4_4347_RAM_BASE (0x170000) | |
| 4013 | #define CR4_4362_RAM_BASE (0x170000) | |
| 4014 | #define CR4_4364_RAM_BASE (0x160000) | |
| 4015 | #define CR4_4369_RAM_BASE (0x170000) | |
| 4016 | #define CR4_4377_RAM_BASE (0x170000) | |
| 4017 | #define CR4_43751_RAM_BASE (0x170000) | |
| 4018 | #define CR4_43752_RAM_BASE (0x170000) | |
| 4019 | #define CR4_4376_RAM_BASE (0x352000) | |
| 4020 | #define CR4_4378_RAM_BASE (0x352000) | |
| 4021 | #define CR4_4387_RAM_BASE (0x740000) | |
| 4022 | #define CR4_4385_RAM_BASE (0x740000) | |
| 4023 | #define CA7_4368_RAM_BASE (0x200000) | |
| 4024 | #define CA7_4389_RAM_BASE (0x200000) | |
| 4025 | #define CA7_4385_RAM_BASE (0x200000) | |
| 4026 | ||
| 4027 | /* 43012 PMU resources based on pmu_params.xls - Start */ | |
| 4028 | #define RES43012_MEMLPLDO_PU 0 | |
| 4029 | #define RES43012_PMU_SLEEP 1 | |
| 4030 | #define RES43012_FAST_LPO 2 | |
| 4031 | #define RES43012_BTLPO_3P3 3 | |
| 4032 | #define RES43012_SR_POK 4 | |
| 4033 | #define RES43012_DUMMY_PWRSW 5 | |
| 4034 | #define RES43012_DUMMY_LDO3P3 6 | |
| 4035 | #define RES43012_DUMMY_BT_LDO3P3 7 | |
| 4036 | #define RES43012_DUMMY_RADIO 8 | |
| 4037 | #define RES43012_VDDB_VDDRET 9 | |
| 4038 | #define RES43012_HV_LDO3P3 10 | |
| 4039 | #define RES43012_OTP_PU 11 | |
| 4040 | #define RES43012_XTAL_PU 12 | |
| 4041 | #define RES43012_SR_CLK_START 13 | |
| 4042 | #define RES43012_XTAL_STABLE 14 | |
| 4043 | #define RES43012_FCBS 15 | |
| 4044 | #define RES43012_CBUCK_MODE 16 | |
| 4045 | #define RES43012_CORE_READY 17 | |
| 4046 | #define RES43012_ILP_REQ 18 | |
| 4047 | #define RES43012_ALP_AVAIL 19 | |
| 4048 | #define RES43012_RADIOLDO_1P8 20 | |
| 4049 | #define RES43012_MINI_PMU 21 | |
| 4050 | #define RES43012_UNUSED 22 | |
| 4051 | #define RES43012_SR_SAVE_RESTORE 23 | |
| 4052 | #define RES43012_PHY_PWRSW 24 | |
| 4053 | #define RES43012_VDDB_CLDO 25 | |
| 4054 | #define RES43012_SUBCORE_PWRSW 26 | |
| 4055 | #define RES43012_SR_SLEEP 27 | |
| 4056 | #define RES43012_HT_START 28 | |
| 4057 | #define RES43012_HT_AVAIL 29 | |
| 4058 | #define RES43012_MACPHY_CLK_AVAIL 30 | |
| 4059 | #define CST43012_SPROM_PRESENT 0x00000010 | |
| 4060 | ||
| 4061 | /* SR Control0 bits */ | |
| 4062 | #define SR0_43012_SR_ENG_EN_MASK 0x1 | |
| 4063 | #define SR0_43012_SR_ENG_EN_SHIFT 0 | |
| 4064 | #define SR0_43012_SR_ENG_CLK_EN (1 << 1) | |
| 4065 | #define SR0_43012_SR_RSRC_TRIGGER (0xC << 2) | |
| 4066 | #define SR0_43012_SR_WD_MEM_MIN_DIV (0x3 << 6) | |
| 4067 | #define SR0_43012_SR_MEM_STBY_ALLOW_MSK (1 << 16) | |
| 4068 | #define SR0_43012_SR_MEM_STBY_ALLOW_SHIFT 16 | |
| 4069 | #define SR0_43012_SR_ENABLE_ILP (1 << 17) | |
| 4070 | #define SR0_43012_SR_ENABLE_ALP (1 << 18) | |
| 4071 | #define SR0_43012_SR_ENABLE_HT (1 << 19) | |
| 4072 | #define SR0_43012_SR_ALLOW_PIC (3 << 20) | |
| 4073 | #define SR0_43012_SR_PMU_MEM_DISABLE (1 << 30) | |
| 4074 | #define CC_43012_VDDM_PWRSW_EN_MASK (1 << 20) | |
| 4075 | #define CC_43012_VDDM_PWRSW_EN_SHIFT (20) | |
| 4076 | #define CC_43012_SDIO_AOS_WAKEUP_MASK (1 << 24) | |
| 4077 | #define CC_43012_SDIO_AOS_WAKEUP_SHIFT (24) | |
| 4078 | ||
| 4079 | /* 43012 - offset at 5K */ | |
| 4080 | #define SR1_43012_SR_INIT_ADDR_MASK 0x3ff | |
| 4081 | #define SR1_43012_SR_ASM_ADDR 0xA | |
| 4082 | ||
| 4083 | /* PLL usage in 43012 */ | |
| 4084 | #define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003f | |
| 4085 | #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0 | |
| 4086 | #define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00 | |
| 4087 | #define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT 10 | |
| 4088 | #define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00 | |
| 4089 | #define PMU43012_PLL0_PC3_PDIV_SHIFT 10 | |
| 4090 | #define PMU43012_PLL_NDIV_FRAC_BITS 20 | |
| 4091 | #define PMU43012_PLL_P_DIV_SCALE_BITS 10 | |
| 4092 | ||
| 4093 | #define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003 | |
| 4094 | #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0 | |
| 4095 | #define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000c | |
| 4096 | #define CCTL_43012_ARM_ONCOUNT_SHIFT 2 | |
| 4097 | ||
| 4098 | /* PMU Rev >= 30 */ | |
| 4099 | #define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000 | |
| 4100 | ||
| 4101 | /* 43012 PMU Chip Control Registers */ | |
| 4102 | #define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010 | |
| 4103 | #define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040 | |
| 4104 | #define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800 | |
| 4105 | #define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000 | |
| 4106 | #define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000 | |
| 4107 | #define PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF (1 << 12) | |
| 4108 | ||
| 4109 | #define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000 | |
| 4110 | #define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000 | |
| 4111 | #define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000 | |
| 4112 | #define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000 | |
| 4113 | #define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000 | |
| 4114 | #define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000 | |
| 4115 | #define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000 | |
| 4116 | #define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000 | |
| 4117 | #define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000 | |
| 4118 | #define PMUCCTL04_43012_USE_LOCK 0x20000000 | |
| 4119 | #define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000 | |
| 4120 | #define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000 | |
| 4121 | #define PMUCCTL05_43012_DISABLE_SPM_CLK (1 << 8) | |
| 4122 | #define PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN (1 << 14) | |
| 4123 | #define PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB (1 << 31) | |
| 4124 | #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0 | |
| 4125 | #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT 6 | |
| 4126 | #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000 | |
| 4127 | #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT 18 | |
| 4128 | #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000 | |
| 4129 | #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 24 | |
| 4130 | #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000 | |
| 4131 | #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 12 | |
| 4132 | #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038 | |
| 4133 | #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT 3 | |
| 4134 | ||
| 4135 | #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_MASK 0x00000FC0 | |
| 4136 | #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_SHIFT 6 | |
| 4137 | /* during normal operation normal value is reduced for optimized power */ | |
| 4138 | #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_VAL 0x1F | |
| 4139 | ||
| 4140 | #define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400 | |
| 4141 | ||
| 4142 | #define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001 | |
| 4143 | #define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020 | |
| 4144 | #define PMUCCTL14_43012_DOT11MAC_PHY_CLK_EN_INITVAL 0x00000080 | |
| 4145 | #define PMUCCTL14_43012_DOT11MAC_PHY_CNTL_EN_INITVAL 0x00000200 | |
| 4146 | #define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400 | |
| 4147 | #define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000 | |
| 4148 | #define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000 | |
| 4149 | #define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000 | |
| 4150 | #define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000 | |
| 4151 | ||
| 4152 | #define VREG6_43012_MEMLPLDO_ADJ_MASK 0x0000F000 | |
| 4153 | #define VREG6_43012_MEMLPLDO_ADJ_SHIFT 12 | |
| 4154 | ||
| 4155 | #define VREG6_43012_LPLDO_ADJ_MASK 0x000000F0 | |
| 4156 | #define VREG6_43012_LPLDO_ADJ_SHIFT 4 | |
| 4157 | ||
| 4158 | #define VREG7_43012_PWRSW_1P8_PU_MASK 0x00400000 | |
| 4159 | #define VREG7_43012_PWRSW_1P8_PU_SHIFT 22 | |
| 4160 | ||
| 4161 | /* 4378 PMU Chip Control Registers */ | |
| 4162 | #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000 | |
| 4163 | #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_SHIFT 15 | |
| 4164 | #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F | |
| 4165 | ||
| 4166 | #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000 | |
| 4167 | #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_SHIFT 21 | |
| 4168 | #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F | |
| 4169 | ||
| 4170 | #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000 | |
| 4171 | #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 27 | |
| 4172 | #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0 | |
| 4173 | ||
| 4174 | #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0 | |
| 4175 | #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 6 | |
| 4176 | #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5 | |
| 4177 | ||
| 4178 | #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000 | |
| 4179 | #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_SHIFT 15 | |
| 4180 | #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_VAL 0x7 | |
| 4181 | ||
| 4182 | /* 4387 PMU Chip Control Registers */ | |
| 4183 | #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000 | |
| 4184 | #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_SHIFT 15 | |
| 4185 | #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F | |
| 4186 | ||
| 4187 | #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000 | |
| 4188 | #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_SHIFT 21 | |
| 4189 | #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F | |
| 4190 | ||
| 4191 | #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000 | |
| 4192 | #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 27 | |
| 4193 | #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0 | |
| 4194 | ||
| 4195 | #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0 | |
| 4196 | #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 6 | |
| 4197 | #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5 | |
| 4198 | ||
| 4199 | #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000 | |
| 4200 | #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_SHIFT 15 | |
| 4201 | #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_VAL 0x7 | |
| 4202 | ||
| 4203 | /* GPIO pins */ | |
| 4204 | #define CC_PIN_GPIO_00 (0u) | |
| 4205 | #define CC_PIN_GPIO_01 (1u) | |
| 4206 | #define CC_PIN_GPIO_02 (2u) | |
| 4207 | #define CC_PIN_GPIO_03 (3u) | |
| 4208 | #define CC_PIN_GPIO_04 (4u) | |
| 4209 | #define CC_PIN_GPIO_05 (5u) | |
| 4210 | #define CC_PIN_GPIO_06 (6u) | |
| 4211 | #define CC_PIN_GPIO_07 (7u) | |
| 4212 | #define CC_PIN_GPIO_08 (8u) | |
| 4213 | #define CC_PIN_GPIO_09 (9u) | |
| 4214 | #define CC_PIN_GPIO_10 (10u) | |
| 4215 | #define CC_PIN_GPIO_11 (11u) | |
| 4216 | #define CC_PIN_GPIO_12 (12u) | |
| 4217 | #define CC_PIN_GPIO_13 (13u) | |
| 4218 | #define CC_PIN_GPIO_14 (14u) | |
| 4219 | #define CC_PIN_GPIO_15 (15u) | |
| 4220 | #define CC_PIN_GPIO_16 (16u) | |
| 4221 | #define CC_PIN_GPIO_17 (17u) | |
| 4222 | #define CC_PIN_GPIO_18 (18u) | |
| 4223 | #define CC_PIN_GPIO_19 (19u) | |
| 4224 | ||
| 4225 | /* Last GPIO Pad */ | |
| 4226 | #define CC_PIN_GPIO_LAST (31u) | |
| 4227 | ||
| 4228 | /* GCI chipcontrol register indices */ | |
| 4229 | #define CC_GCI_CHIPCTRL_00 (0) | |
| 4230 | #define CC_GCI_CHIPCTRL_01 (1) | |
| 4231 | #define CC_GCI_CHIPCTRL_02 (2) | |
| 4232 | #define CC_GCI_CHIPCTRL_03 (3) | |
| 4233 | #define CC_GCI_CHIPCTRL_04 (4) | |
| 4234 | #define CC_GCI_CHIPCTRL_05 (5) | |
| 4235 | #define CC_GCI_CHIPCTRL_06 (6) | |
| 4236 | #define CC_GCI_CHIPCTRL_07 (7) | |
| 4237 | #define CC_GCI_CHIPCTRL_08 (8) | |
| 4238 | #define CC_GCI_CHIPCTRL_09 (9) | |
| 4239 | #define CC_GCI_CHIPCTRL_10 (10) | |
| 4240 | #define CC_GCI_CHIPCTRL_10 (10) | |
| 4241 | #define CC_GCI_CHIPCTRL_11 (11) | |
| 4242 | #define CC_GCI_CHIPCTRL_12 (12) | |
| 4243 | #define CC_GCI_CHIPCTRL_13 (13) | |
| 4244 | #define CC_GCI_CHIPCTRL_14 (14) | |
| 4245 | #define CC_GCI_CHIPCTRL_15 (15) | |
| 4246 | #define CC_GCI_CHIPCTRL_16 (16) | |
| 4247 | #define CC_GCI_CHIPCTRL_17 (17) | |
| 4248 | #define CC_GCI_CHIPCTRL_18 (18) | |
| 4249 | #define CC_GCI_CHIPCTRL_19 (19) | |
| 4250 | #define CC_GCI_CHIPCTRL_20 (20) | |
| 4251 | #define CC_GCI_CHIPCTRL_21 (21) | |
| 4252 | #define CC_GCI_CHIPCTRL_22 (22) | |
| 4253 | #define CC_GCI_CHIPCTRL_23 (23) | |
| 4254 | #define CC_GCI_CHIPCTRL_24 (24) | |
| 4255 | #define CC_GCI_CHIPCTRL_25 (25) | |
| 4256 | #define CC_GCI_CHIPCTRL_26 (26) | |
| 4257 | #define CC_GCI_CHIPCTRL_27 (27) | |
| 4258 | #define CC_GCI_CHIPCTRL_28 (28) | |
| 4259 | ||
| 4260 | /* GCI chip ctrl SDTC Soft reset */ | |
| 4261 | #define GCI_CHIP_CTRL_SDTC_SOFT_RESET (1 << 31) | |
| 4262 | ||
| 4263 | #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12) | |
| 4264 | ||
| 4265 | #define CC_GCI_04_SDIO_DRVSTR_SHIFT 15 | |
| 4266 | #define CC_GCI_04_SDIO_DRVSTR_MASK (0x0f << CC_GCI_04_SDIO_DRVSTR_SHIFT) /* 0x00078000 */ | |
| 4267 | #define CC_GCI_04_SDIO_DRVSTR_OVERRIDE_BIT (1 << 18) | |
| 4268 | #define CC_GCI_04_SDIO_DRVSTR_DEFAULT_MA 14 | |
| 4269 | #define CC_GCI_04_SDIO_DRVSTR_MIN_MA 2 | |
| 4270 | #define CC_GCI_04_SDIO_DRVSTR_MAX_MA 16 | |
| 4271 | ||
| 4272 | #define CC_GCI_04_4387C0_XTAL_PM_CLK (1u << 20u) | |
| 4273 | ||
| 4274 | #define CC_GCI_CHIPCTRL_07_BTDEFLO_ANT0_NBIT 2u | |
| 4275 | #define CC_GCI_CHIPCTRL_07_BTDEFLO_ANT0_MASK 0xFu | |
| 4276 | #define CC_GCI_CHIPCTRL_07_BTDEFHI_ANT0_NBIT 11u | |
| 4277 | #define CC_GCI_CHIPCTRL_07_BTDEFHI_ANT0_MASK 1u | |
| 4278 | ||
| 4279 | #define CC_GCI_CHIPCTRL_18_BTDEF_ANT0_NBIT 10u | |
| 4280 | #define CC_GCI_CHIPCTRL_18_BTDEF_ANT0_MASK 0x1Fu | |
| 4281 | #define CC_GCI_CHIPCTRL_18_BTDEFLO_ANT1_NBIT 15u | |
| 4282 | #define CC_GCI_CHIPCTRL_18_BTDEFLO_ANT1_MASK 1u | |
| 4283 | #define CC_GCI_CHIPCTRL_18_BTDEFHI_ANT1_NBIT 26u | |
| 4284 | #define CC_GCI_CHIPCTRL_18_BTDEFHI_ANT1_MASK 0x3Fu | |
| 4285 | ||
| 4286 | #define CC_GCI_CHIPCTRL_19_BTDEF_ANT1_NBIT 10u | |
| 4287 | #define CC_GCI_CHIPCTRL_19_BTDEF_ANT1_MASK 0x7u | |
| 4288 | ||
| 4289 | #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_NBIT 16u | |
| 4290 | #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_NBIT 17u | |
| 4291 | #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_NBIT 18u | |
| 4292 | #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_NBIT 19u | |
| 4293 | #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_NBIT 20u | |
| 4294 | #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_NBIT 21u | |
| 4295 | #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_NBIT 22u | |
| 4296 | #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_NBIT 23u | |
| 4297 | #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_NBIT 24u | |
| 4298 | #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_NBIT 25u | |
| 4299 | ||
| 4300 | #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_MASK (1u <<\ | |
| 4301 | CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_NBIT) | |
| 4302 | #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_MASK (1u <<\ | |
| 4303 | CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_NBIT) | |
| 4304 | #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_MASK (1u <<\ | |
| 4305 | CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_NBIT) | |
| 4306 | #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_MASK (1u <<\ | |
| 4307 | CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_NBIT) | |
| 4308 | #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_MASK (1u <<\ | |
| 4309 | CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_NBIT) | |
| 4310 | #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_MASK (1u <<\ | |
| 4311 | CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_NBIT) | |
| 4312 | #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_MASK (1u <<\ | |
| 4313 | CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_NBIT) | |
| 4314 | #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_MASK (1u <<\ | |
| 4315 | CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_NBIT) | |
| 4316 | #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_MASK (1u <<\ | |
| 4317 | CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_NBIT) | |
| 4318 | #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_MASK (1u <<\ | |
| 4319 | CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_NBIT) | |
| 4320 | ||
| 4321 | /* 2G core0/core1 Pulse width register (offset : 0x47C) | |
| 4322 | * wl_rx_long_pulse_width_2g_core0 [4:0]; | |
| 4323 | * wl_rx_short_pulse_width_2g_core0 [9:5]; | |
| 4324 | * wl_rx_long_pulse_width_2g_core1 [20:16]; | |
| 4325 | * wl_rx_short_pulse_width_2g_core1 [25:21]; | |
| 4326 | */ | |
| 4327 | #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_NBIT (16u) | |
| 4328 | #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu) | |
| 4329 | #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\ | |
| 4330 | CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_NBIT) | |
| 4331 | ||
| 4332 | #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_NBIT (5u) | |
| 4333 | #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_NBIT (16u) | |
| 4334 | #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_NBIT (21u) | |
| 4335 | ||
| 4336 | #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu) | |
| 4337 | #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\ | |
| 4338 | CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_NBIT) | |
| 4339 | #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu <<\ | |
| 4340 | CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_NBIT) | |
| 4341 | #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\ | |
| 4342 | CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_NBIT) | |
| 4343 | ||
| 4344 | /* 5G core0/Core1 (offset : 0x480) | |
| 4345 | * wl_rx_long_pulse_width_5g[4:0]; | |
| 4346 | * wl_rx_short_pulse_width_5g[9:5] | |
| 4347 | */ | |
| 4348 | ||
| 4349 | #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_NBIT (5u) | |
| 4350 | ||
| 4351 | #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_5G_MASK (0x1Fu) | |
| 4352 | #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_MASK (0x1Fu <<\ | |
| 4353 | CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_NBIT) | |
| 4354 | ||
| 4355 | #define CC_GCI_CNCB_GLITCH_FILTER_WIDTH_MASK (0xFFu) | |
| 4356 | ||
| 4357 | #define CC_GCI_06_JTAG_SEL_SHIFT 4 | |
| 4358 | #define CC_GCI_06_JTAG_SEL_MASK (1 << 4) | |
| 4359 | ||
| 4360 | #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8) | |
| 4361 | ||
| 4362 | #define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFF << 8) | |
| 4363 | #define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCC << 8) | |
| 4364 | ||
| 4365 | #define CC_GCI_13_INSUFF_TREFUP_FIX_SHIFT 31 | |
| 4366 | /* Note: For 4368 B0 onwards, the shift offset remains the same, | |
| 4367 | * but the Chip Common Ctrl GCI register is 16 | |
| 4368 | */ | |
| 4369 | #define CC_GCI_16_INSUFF_TREFUP_FIX_SHIFT 31u | |
| 4370 | ||
| 4371 | #define GPIO_CTRL_REG_DISABLE_INTERRUPT (3 << 9) | |
| 4372 | #define GPIO_CTRL_REG_COUNT 40 | |
| 4373 | ||
| 4374 | #define XTAL_HQ_SETTING_4387 (0xFFF94D30u) | |
| 4375 | #define XTAL_LQ_SETTING_4387 (0xFFF94380u) | |
| 4376 | ||
| 4377 | #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_1_MASK (0x00000200u) | |
| 4378 | #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_1_SHIFT (9u) | |
| 4379 | #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_24_3_MASK (0xFFFFFC00u) | |
| 4380 | #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_24_3_SHIFT (10u) | |
| 4381 | ||
| 4382 | #define CC_GCI_17_BBPLL_CH_CTRL_GRP_PD_TRIG_30_25_MASK (0x0000FC00u) | |
| 4383 | #define CC_GCI_17_BBPLL_CH_CTRL_GRP_PD_TRIG_30_25_SHIFT (10u) | |
| 4384 | #define CC_GCI_17_BBPLL_CH_CTRL_EN_MASK (0x04000000u) | |
| 4385 | ||
| 4386 | #define CC_GCI_20_BBPLL_CH_CTRL_GRP_MASK (0xFC000000u) | |
| 4387 | #define CC_GCI_20_BBPLL_CH_CTRL_GRP_SHIFT (26u) | |
| 4388 | ||
| 4389 | /* GCI Chip Ctrl Regs */ | |
| 4390 | #define GCI_CC28_IHRP_SEL_MASK (7 << 24) | |
| 4391 | #define GCI_CC28_IHRP_SEL_SHIFT (24u) | |
| 4392 | ||
| 4393 | /* 30=MACPHY_CLK_MAIN, 29=MACPHY_CLK_AUX, 23=RADIO_PU_MAIN, 22=CORE_RDY_MAIN | |
| 4394 | * 20=RADIO_PU_AUX, 18=CORE_RDY_AUX, 14=PWRSW_MAIN, 11=PWRSW_AUX | |
| 4395 | */ | |
| 4396 | #define GRP_PD_TRIGGER_MASK_4387 (0x60d44800u) | |
| 4397 | ||
| 4398 | /* power down ch0=MAIN/AUX PHY_clk, ch2=MAIN/AUX MAC_clk, ch5=RFFE_clk */ | |
| 4399 | #define GRP_PD_MASK_4387 (0x25u) | |
| 4400 | ||
| 4401 | #define CC_GCI_CHIPCTRL_11_2x2_ANT_MASK 0x03 | |
| 4402 | #define CC_GCI_CHIPCTRL_11_SHIFT_ANT_MASK 26 | |
| 4403 | ||
| 4404 | /* GCI chipstatus register indices */ | |
| 4405 | #define GCI_CHIPSTATUS_00 (0) | |
| 4406 | #define GCI_CHIPSTATUS_01 (1) | |
| 4407 | #define GCI_CHIPSTATUS_02 (2) | |
| 4408 | #define GCI_CHIPSTATUS_03 (3) | |
| 4409 | #define GCI_CHIPSTATUS_04 (4) | |
| 4410 | #define GCI_CHIPSTATUS_05 (5) | |
| 4411 | #define GCI_CHIPSTATUS_06 (6) | |
| 4412 | #define GCI_CHIPSTATUS_07 (7) | |
| 4413 | #define GCI_CHIPSTATUS_08 (8) | |
| 4414 | #define GCI_CHIPSTATUS_09 (9) | |
| 4415 | #define GCI_CHIPSTATUS_10 (10) | |
| 4416 | #define GCI_CHIPSTATUS_11 (11) | |
| 4417 | #define GCI_CHIPSTATUS_12 (12) | |
| 4418 | #define GCI_CHIPSTATUS_13 (13) | |
| 4419 | #define GCI_CHIPSTATUS_15 (15) | |
| 4420 | ||
| 4421 | /* 43021 GCI chipstatus registers */ | |
| 4422 | #define GCI43012_CHIPSTATUS_07_BBPLL_LOCK_MASK (1 << 3) | |
| 4423 | ||
| 4424 | /* GCI Core Control Reg */ | |
| 4425 | #define GCI_CORECTRL_SR_MASK (1 << 0) /**< SECI block Reset */ | |
| 4426 | #define GCI_CORECTRL_RSL_MASK (1 << 1) /**< ResetSECILogic */ | |
| 4427 | #define GCI_CORECTRL_ES_MASK (1 << 2) /**< EnableSECI */ | |
| 4428 | #define GCI_CORECTRL_FSL_MASK (1 << 3) /**< Force SECI Out Low */ | |
| 4429 | #define GCI_CORECTRL_SOM_MASK (7 << 4) /**< SECI Op Mode */ | |
| 4430 | #define GCI_CORECTRL_US_MASK (1 << 7) /**< Update SECI */ | |
| 4431 | #define GCI_CORECTRL_BOS_MASK (1 << 8) /**< Break On Sleep */ | |
| 4432 | #define GCI_CORECTRL_FORCEREGCLK_MASK (1 << 18) /* ForceRegClk */ | |
| 4433 | ||
| 4434 | /* 4378 & 4387 GCI AVS function */ | |
| 4435 | #define GCI6_AVS_ENAB 1u | |
| 4436 | #define GCI6_AVS_ENAB_SHIFT 31u | |
| 4437 | #define GCI6_AVS_ENAB_MASK (1u << GCI6_AVS_ENAB_SHIFT) | |
| 4438 | #define GCI6_AVS_CBUCK_VOLT_SHIFT 25u | |
| 4439 | #define GCI6_AVS_CBUCK_VOLT_MASK (0x1Fu << GCI6_AVS_CBUCK_VOLT_SHIFT) | |
| 4440 | ||
| 4441 | /* GCI GPIO for function sel GCI-0/GCI-1 */ | |
| 4442 | #define CC_GCI_GPIO_0 (0) | |
| 4443 | #define CC_GCI_GPIO_1 (1) | |
| 4444 | #define CC_GCI_GPIO_2 (2) | |
| 4445 | #define CC_GCI_GPIO_3 (3) | |
| 4446 | #define CC_GCI_GPIO_4 (4) | |
| 4447 | #define CC_GCI_GPIO_5 (5) | |
| 4448 | #define CC_GCI_GPIO_6 (6) | |
| 4449 | #define CC_GCI_GPIO_7 (7) | |
| 4450 | #define CC_GCI_GPIO_8 (8) | |
| 4451 | #define CC_GCI_GPIO_9 (9) | |
| 4452 | #define CC_GCI_GPIO_10 (10) | |
| 4453 | #define CC_GCI_GPIO_11 (11) | |
| 4454 | #define CC_GCI_GPIO_12 (12) | |
| 4455 | #define CC_GCI_GPIO_13 (13) | |
| 4456 | #define CC_GCI_GPIO_14 (14) | |
| 4457 | #define CC_GCI_GPIO_15 (15) | |
| 4458 | ||
| 4459 | /* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */ | |
| 4460 | #define CC_GCI_GPIO_INVALID 0xFF | |
| 4461 | ||
| 4462 | /* 4378 LHL GPIO configuration */ | |
| 4463 | #define LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_SHIFT (3u) | |
| 4464 | #define LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_MASK (1u << LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_SHIFT) | |
| 4465 | ||
| 4466 | /* 4378 LHL SPMI bit definitions */ | |
| 4467 | #define LHL_LP_CTL5_SPMI_DATA_SEL_SHIFT (8u) | |
| 4468 | #define LHL_LP_CTL5_SPMI_DATA_SEL_MASK (0x3u << LHL_LP_CTL5_SPMI_CLK_DATA_SHIFT) | |
| 4469 | #define LHL_LP_CTL5_SPMI_CLK_SEL_SHIFT (6u) | |
| 4470 | #define LHL_LP_CTL5_SPMI_CLK_SEL_MASK (0x3u << LHL_LP_CTL5_SPMI_CLK_SEL_SHIFT) | |
| 4471 | #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO0 (0u) | |
| 4472 | #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO1 (1u) | |
| 4473 | #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO2 (2u) | |
| 4474 | ||
| 4475 | /* Plese do not these following defines */ | |
| 4476 | /* find the 4 bit mask given the bit position */ | |
| 4477 | #define GCIMASK(pos) (((uint32)0xF) << pos) | |
| 4478 | /* get the value which can be used to directly OR with chipcontrol reg */ | |
| 4479 | #define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos)) | |
| 4480 | /* Extract nibble from a given position */ | |
| 4481 | #define GCIGETNBL(val, pos) ((val >> pos) & 0xF) | |
| 4482 | ||
| 4483 | /* find the 8 bit mask given the bit position */ | |
| 4484 | #define GCIMASK_8B(pos) (((uint32)0xFF) << pos) | |
| 4485 | /* get the value which can be used to directly OR with chipcontrol reg */ | |
| 4486 | #define GCIPOSVAL_8B(val, pos) ((((uint32)val) << pos) & GCIMASK_8B(pos)) | |
| 4487 | /* Extract nibble from a given position */ | |
| 4488 | #define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF) | |
| 4489 | ||
| 4490 | /* find the 4 bit mask given the bit position */ | |
| 4491 | #define GCIMASK_4B(pos) (((uint32)0xF) << pos) | |
| 4492 | /* get the value which can be used to directly OR with chipcontrol reg */ | |
| 4493 | #define GCIPOSVAL_4B(val, pos) ((((uint32)val) << pos) & GCIMASK_4B(pos)) | |
| 4494 | /* Extract nibble from a given position */ | |
| 4495 | #define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF) | |
| 4496 | ||
| 4497 | /* GCI Intstatus(Mask)/WakeMask Register bits. */ | |
| 4498 | #define GCI_INTSTATUS_RBI (1 << 0) /**< Rx Break Interrupt */ | |
| 4499 | #define GCI_INTSTATUS_UB (1 << 1) /**< UART Break Interrupt */ | |
| 4500 | #define GCI_INTSTATUS_SPE (1 << 2) /**< SECI Parity Error Interrupt */ | |
| 4501 | #define GCI_INTSTATUS_SFE (1 << 3) /**< SECI Framing Error Interrupt */ | |
| 4502 | #define GCI_INTSTATUS_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ | |
| 4503 | #define GCI_INTSTATUS_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ | |
| 4504 | #define GCI_INTSTATUS_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ | |
| 4505 | #define GCI_INTSTATUS_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ | |
| 4506 | #define GCI_INTSTATUS_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ | |
| 4507 | #define GCI_INTSTATUS_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ | |
| 4508 | #define GCI_INTSTATUS_EVENT (1 << 21) /* GCI Event Interrupt */ | |
| 4509 | #define GCI_INTSTATUS_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ | |
| 4510 | #define GCI_INTSTATUS_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ | |
| 4511 | #define GCI_INTSTATUS_GPIOINT (1 << 25) /**< GCIGpioInt */ | |
| 4512 | #define GCI_INTSTATUS_GPIOWAKE (1 << 26) /**< GCIGpioWake */ | |
| 4513 | #define GCI_INTSTATUS_LHLWLWAKE (1 << 30) /* LHL WL wake */ | |
| 4514 | ||
| 4515 | /* GCI IntMask Register bits. */ | |
| 4516 | #define GCI_INTMASK_RBI (1 << 0) /**< Rx Break Interrupt */ | |
| 4517 | #define GCI_INTMASK_UB (1 << 1) /**< UART Break Interrupt */ | |
| 4518 | #define GCI_INTMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ | |
| 4519 | #define GCI_INTMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ | |
| 4520 | #define GCI_INTMASK_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ | |
| 4521 | #define GCI_INTMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ | |
| 4522 | #define GCI_INTMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ | |
| 4523 | #define GCI_INTMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ | |
| 4524 | #define GCI_INTMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ | |
| 4525 | #define GCI_INTMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ | |
| 4526 | #define GCI_INTMASK_EVENT (1 << 21) /* GCI Event Interrupt */ | |
| 4527 | #define GCI_INTMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ | |
| 4528 | #define GCI_INTMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ | |
| 4529 | #define GCI_INTMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ | |
| 4530 | #define GCI_INTMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ | |
| 4531 | #define GCI_INTMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */ | |
| 4532 | ||
| 4533 | /* GCI WakeMask Register bits. */ | |
| 4534 | #define GCI_WAKEMASK_RBI (1 << 0) /**< Rx Break Interrupt */ | |
| 4535 | #define GCI_WAKEMASK_UB (1 << 1) /**< UART Break Interrupt */ | |
| 4536 | #define GCI_WAKEMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ | |
| 4537 | #define GCI_WAKEMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ | |
| 4538 | #define GCI_WAKE_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ | |
| 4539 | #define GCI_WAKEMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ | |
| 4540 | #define GCI_WAKEMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ | |
| 4541 | #define GCI_WAKEMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ | |
| 4542 | #define GCI_WAKEMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ | |
| 4543 | #define GCI_WAKEMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ | |
| 4544 | #define GCI_WAKEMASK_EVENT (1 << 21) /* GCI Event Interrupt */ | |
| 4545 | #define GCI_WAKEMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ | |
| 4546 | #define GCI_WAKEMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ | |
| 4547 | #define GCI_WAKEMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ | |
| 4548 | #define GCI_WAKEMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ | |
| 4549 | #define GCI_WAKEMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */ | |
| 4550 | ||
| 4551 | #define GCI_WAKE_ON_GCI_GPIO1 1 | |
| 4552 | #define GCI_WAKE_ON_GCI_GPIO2 2 | |
| 4553 | #define GCI_WAKE_ON_GCI_GPIO3 3 | |
| 4554 | #define GCI_WAKE_ON_GCI_GPIO4 4 | |
| 4555 | #define GCI_WAKE_ON_GCI_GPIO5 5 | |
| 4556 | #define GCI_WAKE_ON_GCI_GPIO6 6 | |
| 4557 | #define GCI_WAKE_ON_GCI_GPIO7 7 | |
| 4558 | #define GCI_WAKE_ON_GCI_GPIO8 8 | |
| 4559 | #define GCI_WAKE_ON_GCI_SECI_IN 9 | |
| 4560 | ||
| 4561 | #define PMU_EXT_WAKE_MASK_0_SDIO (1u << 2u) | |
| 4562 | #define PMU_EXT_WAKE_MASK_0_PCIE_PERST (1u << 5u) | |
| 4563 | ||
| 4564 | #define PMU_4362_EXT_WAKE_MASK_0_SDIO (1u << 1u | 1u << 2u) | |
| 4565 | ||
| 4566 | /* =========== LHL regs =========== */ | |
| 4567 | #define LHL_PWRSEQCTL_SLEEP_EN (1 << 0) | |
| 4568 | #define LHL_PWRSEQCTL_PMU_SLEEP_MODE (1 << 1) | |
| 4569 | #define LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN (1 << 2) | |
| 4570 | #define LHL_PWRSEQCTL_PMU_TOP_ISO_EN (1 << 3) | |
| 4571 | #define LHL_PWRSEQCTL_PMU_TOP_SLB_EN (1 << 4) | |
| 4572 | #define LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN (1 << 5) | |
| 4573 | #define LHL_PWRSEQCTL_PMU_CLDO_PD (1 << 6) | |
| 4574 | #define LHL_PWRSEQCTL_PMU_LPLDO_PD (1 << 7) | |
| 4575 | #define LHL_PWRSEQCTL_PMU_RSRC6_EN (1 << 8) | |
| 4576 | ||
| 4577 | #define PMU_SLEEP_MODE_0 (LHL_PWRSEQCTL_SLEEP_EN |\ | |
| 4578 | LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN) | |
| 4579 | ||
| 4580 | #define PMU_SLEEP_MODE_1 (LHL_PWRSEQCTL_SLEEP_EN |\ | |
| 4581 | LHL_PWRSEQCTL_PMU_SLEEP_MODE |\ | |
| 4582 | LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN |\ | |
| 4583 | LHL_PWRSEQCTL_PMU_TOP_ISO_EN |\ | |
| 4584 | LHL_PWRSEQCTL_PMU_TOP_SLB_EN |\ | |
| 4585 | LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN |\ | |
| 4586 | LHL_PWRSEQCTL_PMU_CLDO_PD |\ | |
| 4587 | LHL_PWRSEQCTL_PMU_RSRC6_EN) | |
| 4588 | ||
| 4589 | #define PMU_SLEEP_MODE_2 (LHL_PWRSEQCTL_SLEEP_EN |\ | |
| 4590 | LHL_PWRSEQCTL_PMU_SLEEP_MODE |\ | |
| 4591 | LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN |\ | |
| 4592 | LHL_PWRSEQCTL_PMU_TOP_ISO_EN |\ | |
| 4593 | LHL_PWRSEQCTL_PMU_TOP_SLB_EN |\ | |
| 4594 | LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN |\ | |
| 4595 | LHL_PWRSEQCTL_PMU_CLDO_PD |\ | |
| 4596 | LHL_PWRSEQCTL_PMU_LPLDO_PD |\ | |
| 4597 | LHL_PWRSEQCTL_PMU_RSRC6_EN) | |
| 4598 | ||
| 4599 | #define LHL_PWRSEQ_CTL (0x000000ff) | |
| 4600 | ||
| 4601 | /* LHL Top Level Power Up Control Register (lhl_top_pwrup_ctl_adr, Offset 0xE78) | |
| 4602 | * Top Level Counter values for isolation, retention, Power Switch control | |
| 4603 | */ | |
| 4604 | #define LHL_PWRUP_ISOLATION_CNT (0x6 << 8) | |
| 4605 | #define LHL_PWRUP_RETENTION_CNT (0x5 << 16) | |
| 4606 | #define LHL_PWRUP_PWRSW_CNT (0x7 << 24) | |
| 4607 | /* Mask is taken only for isolation 8:13 , Retention 16:21 , | |
| 4608 | * Power Switch control 24:29 | |
| 4609 | */ | |
| 4610 | #define LHL_PWRUP_CTL_MASK (0x3F3F3F00) | |
| 4611 | #define LHL_PWRUP_CTL (LHL_PWRUP_ISOLATION_CNT |\ | |
| 4612 | LHL_PWRUP_RETENTION_CNT |\ | |
| 4613 | LHL_PWRUP_PWRSW_CNT) | |
| 4614 | ||
| 4615 | #define LHL_PWRUP2_CLDO_DN_CNT (0x0) | |
| 4616 | #define LHL_PWRUP2_LPLDO_DN_CNT (0x0 << 8) | |
| 4617 | #define LHL_PWRUP2_RSRC6_DN_CN (0x4 << 16) | |
| 4618 | #define LHL_PWRUP2_RSRC7_DN_CN (0x0 << 24) | |
| 4619 | #define LHL_PWRUP2_CTL_MASK (0x3F3F3F3F) | |
| 4620 | #define LHL_PWRUP2_CTL (LHL_PWRUP2_CLDO_DN_CNT |\ | |
| 4621 | LHL_PWRUP2_LPLDO_DN_CNT |\ | |
| 4622 | LHL_PWRUP2_RSRC6_DN_CN |\ | |
| 4623 | LHL_PWRUP2_RSRC7_DN_CN) | |
| 4624 | ||
| 4625 | /* LHL Top Level Power Down Control Register (lhl_top_pwrdn_ctl_adr, Offset 0xE74) */ | |
| 4626 | #define LHL_PWRDN_SLEEP_CNT (0x4) | |
| 4627 | #define LHL_PWRDN_CTL_MASK (0x3F) | |
| 4628 | ||
| 4629 | /* LHL Top Level Power Down Control 2 Register (lhl_top_pwrdn2_ctl_adr, Offset 0xE80) */ | |
| 4630 | #define LHL_PWRDN2_CLDO_DN_CNT (0x4) | |
| 4631 | #define LHL_PWRDN2_LPLDO_DN_CNT (0x4 << 8) | |
| 4632 | #define LHL_PWRDN2_RSRC6_DN_CN (0x3 << 16) | |
| 4633 | #define LHL_PWRDN2_RSRC7_DN_CN (0x0 << 24) | |
| 4634 | #define LHL_PWRDN2_CTL (LHL_PWRDN2_CLDO_DN_CNT |\ | |
| 4635 | LHL_PWRDN2_LPLDO_DN_CNT |\ | |
| 4636 | LHL_PWRDN2_RSRC6_DN_CN |\ | |
| 4637 | LHL_PWRDN2_RSRC7_DN_CN) | |
| 4638 | #define LHL_PWRDN2_CTL_MASK (0x3F3F3F3F) | |
| 4639 | ||
| 4640 | #define LHL_FAST_WRITE_EN (1 << 14) | |
| 4641 | ||
| 4642 | #define LHL_WL_MACTIMER_MASK 0xFFFFFFFF | |
| 4643 | ||
| 4644 | /* WL ARM Timer0 Interrupt Mask (lhl_wl_armtim0_intrp_adr) */ | |
| 4645 | #define LHL_WL_ARMTIM0_INTRP_EN 0x00000001 | |
| 4646 | #define LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER 0x00000002 | |
| 4647 | ||
| 4648 | /* WL ARM Timer0 Interrupt Status (lhl_wl_armtim0_st_adr) */ | |
| 4649 | #define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001 | |
| 4650 | ||
| 4651 | /* WL MAC TimerX Interrupt Mask (lhl_wl_mactimX_intrp_adr) */ | |
| 4652 | #define LHL_WL_MACTIM_INTRP_EN 0x00000001 | |
| 4653 | #define LHL_WL_MACTIM_INTRP_EDGE_TRIGGER 0x00000002 | |
| 4654 | ||
| 4655 | /* WL MAC TimerX Interrupt Status (lhl_wl_mactimX_st_adr) */ | |
| 4656 | #define LHL_WL_MACTIM_ST_WL_MACTIM_INT_ST 0x00000001 | |
| 4657 | ||
| 4658 | /* LHL Wakeup Status (lhl_wkup_status_adr) */ | |
| 4659 | #define LHL_WKUP_STATUS_WR_PENDING_ARMTIM0 0x00100000 | |
| 4660 | ||
| 4661 | #define LHL_PS_MODE_0 0 | |
| 4662 | #define LHL_PS_MODE_1 1 | |
| 4663 | ||
| 4664 | /* GCI EventIntMask Register SW bits */ | |
| 4665 | #define GCI_MAILBOXDATA_TOWLAN (1 << 0) | |
| 4666 | #define GCI_MAILBOXDATA_TOBT (1 << 1) | |
| 4667 | #define GCI_MAILBOXDATA_TONFC (1 << 2) | |
| 4668 | #define GCI_MAILBOXDATA_TOGPS (1 << 3) | |
| 4669 | #define GCI_MAILBOXDATA_TOLTE (1 << 4) | |
| 4670 | #define GCI_MAILBOXACK_TOWLAN (1 << 8) | |
| 4671 | #define GCI_MAILBOXACK_TOBT (1 << 9) | |
| 4672 | #define GCI_MAILBOXACK_TONFC (1 << 10) | |
| 4673 | #define GCI_MAILBOXACK_TOGPS (1 << 11) | |
| 4674 | #define GCI_MAILBOXACK_TOLTE (1 << 12) | |
| 4675 | #define GCI_WAKE_TOWLAN (1 << 16) | |
| 4676 | #define GCI_WAKE_TOBT (1 << 17) | |
| 4677 | #define GCI_WAKE_TONFC (1 << 18) | |
| 4678 | #define GCI_WAKE_TOGPS (1 << 19) | |
| 4679 | #define GCI_WAKE_TOLTE (1 << 20) | |
| 4680 | #define GCI_SWREADY (1 << 24) | |
| 4681 | ||
| 4682 | /* GCI SECI_OUT TX Status Regiser bits */ | |
| 4683 | #define GCI_SECIOUT_TXSTATUS_TXHALT (1 << 0) | |
| 4684 | #define GCI_SECIOUT_TXSTATUS_TI (1 << 16) | |
| 4685 | ||
| 4686 | /* 43012 MUX options */ | |
| 4687 | #define MUXENAB43012_HOSTWAKE_MASK (0x00000001) | |
| 4688 | #define MUXENAB43012_GETIX(val, name) (val - 1) | |
| 4689 | ||
| 4690 | /* | |
| 4691 | * Maximum delay for the PMU state transition in us. | |
| 4692 | * This is an upper bound intended for spinwaits etc. | |
| 4693 | */ | |
| 4694 | #define PMU_MAX_TRANSITION_DLY 15000 | |
| 4695 | ||
| 4696 | /* PMU resource up transition time in ILP cycles */ | |
| 4697 | #define PMURES_UP_TRANSITION 2 | |
| 4698 | ||
| 4699 | /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */ | |
| 4700 | #define SECI_STAT_BI (1 << 0) /* Break Interrupt */ | |
| 4701 | #define SECI_STAT_SPE (1 << 1) /* Parity Error */ | |
| 4702 | #define SECI_STAT_SFE (1 << 2) /* Parity Error */ | |
| 4703 | #define SECI_STAT_SDU (1 << 3) /* Data Updated */ | |
| 4704 | #define SECI_STAT_SADU (1 << 4) /* Auxiliary Data Updated */ | |
| 4705 | #define SECI_STAT_SAS (1 << 6) /* AUX State */ | |
| 4706 | #define SECI_STAT_SAS2 (1 << 7) /* AUX2 State */ | |
| 4707 | #define SECI_STAT_SRITI (1 << 8) /* Idle Timer Interrupt */ | |
| 4708 | #define SECI_STAT_STFF (1 << 9) /* Tx FIFO Full */ | |
| 4709 | #define SECI_STAT_STFAE (1 << 10) /* Tx FIFO Almost Empty */ | |
| 4710 | #define SECI_STAT_SRFE (1 << 11) /* Rx FIFO Empty */ | |
| 4711 | #define SECI_STAT_SRFAF (1 << 12) /* Rx FIFO Almost Full */ | |
| 4712 | #define SECI_STAT_SFCE (1 << 13) /* Flow Control Event */ | |
| 4713 | ||
| 4714 | /* SECI configuration */ | |
| 4715 | #define SECI_MODE_UART 0x0 | |
| 4716 | #define SECI_MODE_SECI 0x1 | |
| 4717 | #define SECI_MODE_LEGACY_3WIRE_BT 0x2 | |
| 4718 | #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3 | |
| 4719 | #define SECI_MODE_HALF_SECI 0x4 | |
| 4720 | ||
| 4721 | #define SECI_RESET (1 << 0) | |
| 4722 | #define SECI_RESET_BAR_UART (1 << 1) | |
| 4723 | #define SECI_ENAB_SECI_ECI (1 << 2) | |
| 4724 | #define SECI_ENAB_SECIOUT_DIS (1 << 3) | |
| 4725 | #define SECI_MODE_MASK 0x7 | |
| 4726 | #define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */ | |
| 4727 | #define SECI_UPD_SECI (1 << 7) | |
| 4728 | ||
| 4729 | #define SECI_AUX_TX_START (1 << 31) | |
| 4730 | #define SECI_SLIP_ESC_CHAR 0xDB | |
| 4731 | #define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR | |
| 4732 | #define SECI_SIGNOFF_1 0 | |
| 4733 | #define SECI_REFRESH_REQ 0xDA | |
| 4734 | ||
| 4735 | /* seci clk_ctl_st bits */ | |
| 4736 | #define CLKCTL_STS_HT_AVAIL_REQ (1 << 4) | |
| 4737 | #define CLKCTL_STS_SECI_CLK_REQ (1 << 8) | |
| 4738 | #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24) | |
| 4739 | ||
| 4740 | #define SECI_UART_MSR_CTS_STATE (1 << 0) | |
| 4741 | #define SECI_UART_MSR_RTS_STATE (1 << 1) | |
| 4742 | #define SECI_UART_SECI_IN_STATE (1 << 2) | |
| 4743 | #define SECI_UART_SECI_IN2_STATE (1 << 3) | |
| 4744 | ||
| 4745 | /* GCI RX FIFO Control Register */ | |
| 4746 | #define GCI_RXF_LVL_MASK (0xFF << 0) | |
| 4747 | #define GCI_RXF_TIMEOUT_MASK (0xFF << 8) | |
| 4748 | ||
| 4749 | /* GCI UART Registers' Bit definitions */ | |
| 4750 | /* Seci Fifo Level Register */ | |
| 4751 | #define SECI_TXF_LVL_MASK (0x3F << 8) | |
| 4752 | #define TXF_AE_LVL_DEFAULT 0x4 | |
| 4753 | #define SECI_RXF_LVL_FC_MASK (0x3F << 16) | |
| 4754 | ||
| 4755 | /* SeciUARTFCR Bit definitions */ | |
| 4756 | #define SECI_UART_FCR_RFR (1 << 0) | |
| 4757 | #define SECI_UART_FCR_TFR (1 << 1) | |
| 4758 | #define SECI_UART_FCR_SR (1 << 2) | |
| 4759 | #define SECI_UART_FCR_THP (1 << 3) | |
| 4760 | #define SECI_UART_FCR_AB (1 << 4) | |
| 4761 | #define SECI_UART_FCR_ATOE (1 << 5) | |
| 4762 | #define SECI_UART_FCR_ARTSOE (1 << 6) | |
| 4763 | #define SECI_UART_FCR_ABV (1 << 7) | |
| 4764 | #define SECI_UART_FCR_ALM (1 << 8) | |
| 4765 | ||
| 4766 | /* SECI UART LCR register bits */ | |
| 4767 | #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */ | |
| 4768 | #define SECI_UART_LCR_PARITY_EN (1 << 1) | |
| 4769 | #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */ | |
| 4770 | #define SECI_UART_LCR_RX_EN (1 << 3) | |
| 4771 | #define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */ | |
| 4772 | #define SECI_UART_LCR_TXO_EN (1 << 5) | |
| 4773 | #define SECI_UART_LCR_RTSO_EN (1 << 6) | |
| 4774 | #define SECI_UART_LCR_SLIPMODE_EN (1 << 7) | |
| 4775 | #define SECI_UART_LCR_RXCRC_CHK (1 << 8) | |
| 4776 | #define SECI_UART_LCR_TXCRC_INV (1 << 9) | |
| 4777 | #define SECI_UART_LCR_TXCRC_LSBF (1 << 10) | |
| 4778 | #define SECI_UART_LCR_TXCRC_EN (1 << 11) | |
| 4779 | #define SECI_UART_LCR_RXSYNC_EN (1 << 12) | |
| 4780 | ||
| 4781 | #define SECI_UART_MCR_TX_EN (1 << 0) | |
| 4782 | #define SECI_UART_MCR_PRTS (1 << 1) | |
| 4783 | #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2) | |
| 4784 | #define SECI_UART_MCR_HIGHRATE_EN (1 << 3) | |
| 4785 | #define SECI_UART_MCR_LOOPBK_EN (1 << 4) | |
| 4786 | #define SECI_UART_MCR_AUTO_RTS (1 << 5) | |
| 4787 | #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6) | |
| 4788 | #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7) | |
| 4789 | #define SECI_UART_MCR_XONOFF_RPT (1 << 9) | |
| 4790 | ||
| 4791 | /* SeciUARTLSR Bit Mask */ | |
| 4792 | #define SECI_UART_LSR_RXOVR_MASK (1 << 0) | |
| 4793 | #define SECI_UART_LSR_RFF_MASK (1 << 1) | |
| 4794 | #define SECI_UART_LSR_TFNE_MASK (1 << 2) | |
| 4795 | #define SECI_UART_LSR_TI_MASK (1 << 3) | |
| 4796 | #define SECI_UART_LSR_TPR_MASK (1 << 4) | |
| 4797 | #define SECI_UART_LSR_TXHALT_MASK (1 << 5) | |
| 4798 | ||
| 4799 | /* SeciUARTMSR Bit Mask */ | |
| 4800 | #define SECI_UART_MSR_CTSS_MASK (1 << 0) | |
| 4801 | #define SECI_UART_MSR_RTSS_MASK (1 << 1) | |
| 4802 | #define SECI_UART_MSR_SIS_MASK (1 << 2) | |
| 4803 | #define SECI_UART_MSR_SIS2_MASK (1 << 3) | |
| 4804 | ||
| 4805 | /* SeciUARTData Bits */ | |
| 4806 | #define SECI_UART_DATA_RF_NOT_EMPTY_BIT (1 << 12) | |
| 4807 | #define SECI_UART_DATA_RF_FULL_BIT (1 << 13) | |
| 4808 | #define SECI_UART_DATA_RF_OVRFLOW_BIT (1 << 14) | |
| 4809 | #define SECI_UART_DATA_FIFO_PTR_MASK 0xFF | |
| 4810 | #define SECI_UART_DATA_RF_RD_PTR_SHIFT 16 | |
| 4811 | #define SECI_UART_DATA_RF_WR_PTR_SHIFT 24 | |
| 4812 | ||
| 4813 | /* LTECX: ltecxmux */ | |
| 4814 | #define LTECX_EXTRACT_MUX(val, idx) (getbit4(&(val), (idx))) | |
| 4815 | ||
| 4816 | /* LTECX: ltecxmux MODE */ | |
| 4817 | #define LTECX_MUX_MODE_IDX 0 | |
| 4818 | #define LTECX_MUX_MODE_WCI2 0x0 | |
| 4819 | #define LTECX_MUX_MODE_GPIO 0x1 | |
| 4820 | ||
| 4821 | /* LTECX GPIO Information Index */ | |
| 4822 | #define LTECX_NVRAM_FSYNC_IDX 0 | |
| 4823 | #define LTECX_NVRAM_LTERX_IDX 1 | |
| 4824 | #define LTECX_NVRAM_LTETX_IDX 2 | |
| 4825 | #define LTECX_NVRAM_WLPRIO_IDX 3 | |
| 4826 | ||
| 4827 | /* LTECX WCI2 Information Index */ | |
| 4828 | #define LTECX_NVRAM_WCI2IN_IDX 0 | |
| 4829 | #define LTECX_NVRAM_WCI2OUT_IDX 1 | |
| 4830 | ||
| 4831 | /* LTECX: Macros to get GPIO/FNSEL/GCIGPIO */ | |
| 4832 | #define LTECX_EXTRACT_PADNUM(val, idx) (getbit8(&(val), (idx))) | |
| 4833 | #define LTECX_EXTRACT_FNSEL(val, idx) (getbit4(&(val), (idx))) | |
| 4834 | #define LTECX_EXTRACT_GCIGPIO(val, idx) (getbit4(&(val), (idx))) | |
| 4835 | ||
| 4836 | /* WLAN channel numbers - used from wifi.h */ | |
| 4837 | ||
| 4838 | /* WLAN BW */ | |
| 4839 | #define ECI_BW_20 0x0 | |
| 4840 | #define ECI_BW_25 0x1 | |
| 4841 | #define ECI_BW_30 0x2 | |
| 4842 | #define ECI_BW_35 0x3 | |
| 4843 | #define ECI_BW_40 0x4 | |
| 4844 | #define ECI_BW_45 0x5 | |
| 4845 | #define ECI_BW_50 0x6 | |
| 4846 | #define ECI_BW_ALL 0x7 | |
| 4847 | ||
| 4848 | /* WLAN - number of antenna */ | |
| 4849 | #define WLAN_NUM_ANT1 TXANT_0 | |
| 4850 | #define WLAN_NUM_ANT2 TXANT_1 | |
| 4851 | ||
| 4852 | /* otpctrl1 0xF4 */ | |
| 4853 | #define OTPC_FORCE_PWR_OFF 0x02000000 | |
| 4854 | /* chipcommon s/r registers introduced with cc rev >= 48 */ | |
| 4855 | #define CC_SR_CTL0_ENABLE_MASK 0x1 | |
| 4856 | #define CC_SR_CTL0_ENABLE_SHIFT 0 | |
| 4857 | #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */ | |
| 4858 | #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */ | |
| 4859 | #define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk in sr_engine */ | |
| 4860 | #define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16 /* Allow Subcore mem StandBy? */ | |
| 4861 | #define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18 | |
| 4862 | #define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19 | |
| 4863 | #define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power domains */ | |
| 4864 | #define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25 | |
| 4865 | #define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30 | |
| 4866 | ||
| 4867 | #define CC_SR_CTL1_SR_INIT_MASK 0x3FF | |
| 4868 | #define CC_SR_CTL1_SR_INIT_SHIFT 0 | |
| 4869 | ||
| 4870 | #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ | |
| 4871 | #define ECI_INLO_PKTDUR_SHIFT 4 | |
| 4872 | ||
| 4873 | /* gci chip control bits */ | |
| 4874 | #define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0 | |
| 4875 | #define GCI_GPIO_CHIPCTRL_ENAB_OP_BIT 1 | |
| 4876 | #define GCI_GPIO_CHIPCTRL_INVERT_BIT 2 | |
| 4877 | #define GCI_GPIO_CHIPCTRL_PULLUP_BIT 3 | |
| 4878 | #define GCI_GPIO_CHIPCTRL_PULLDN_BIT 4 | |
| 4879 | #define GCI_GPIO_CHIPCTRL_ENAB_BTSIG_BIT 5 | |
| 4880 | #define GCI_GPIO_CHIPCTRL_ENAB_OD_OP_BIT 6 | |
| 4881 | #define GCI_GPIO_CHIPCTRL_ENAB_EXT_GPIO_BIT 7 | |
| 4882 | ||
| 4883 | /* gci GPIO input status bits */ | |
| 4884 | #define GCI_GPIO_STS_VALUE_BIT 0 | |
| 4885 | #define GCI_GPIO_STS_POS_EDGE_BIT 1 | |
| 4886 | #define GCI_GPIO_STS_NEG_EDGE_BIT 2 | |
| 4887 | #define GCI_GPIO_STS_FAST_EDGE_BIT 3 | |
| 4888 | #define GCI_GPIO_STS_CLEAR 0xF | |
| 4889 | ||
| 4890 | #define GCI_GPIO_STS_EDGE_TRIG_BIT 0 | |
| 4891 | #define GCI_GPIO_STS_NEG_EDGE_TRIG_BIT 1 | |
| 4892 | #define GCI_GPIO_STS_DUAL_EDGE_TRIG_BIT 2 | |
| 4893 | #define GCI_GPIO_STS_WL_DIN_SELECT 6 | |
| 4894 | ||
| 4895 | #define GCI_GPIO_STS_VALUE (1 << GCI_GPIO_STS_VALUE_BIT) | |
| 4896 | ||
| 4897 | /* SR Power Control */ | |
| 4898 | #define SRPWR_DMN0_PCIE (0) /* PCIE */ | |
| 4899 | #define SRPWR_DMN0_PCIE_SHIFT (SRPWR_DMN0_PCIE) /* PCIE */ | |
| 4900 | #define SRPWR_DMN0_PCIE_MASK (1 << SRPWR_DMN0_PCIE_SHIFT) /* PCIE */ | |
| 4901 | #define SRPWR_DMN1_ARMBPSD (1) /* ARM/BP/SDIO */ | |
| 4902 | #define SRPWR_DMN1_ARMBPSD_SHIFT (SRPWR_DMN1_ARMBPSD) /* ARM/BP/SDIO */ | |
| 4903 | #define SRPWR_DMN1_ARMBPSD_MASK (1 << SRPWR_DMN1_ARMBPSD_SHIFT) /* ARM/BP/SDIO */ | |
| 4904 | #define SRPWR_DMN2_MACAUX (2) /* MAC/Phy Aux */ | |
| 4905 | #define SRPWR_DMN2_MACAUX_SHIFT (SRPWR_DMN2_MACAUX) /* MAC/Phy Aux */ | |
| 4906 | #define SRPWR_DMN2_MACAUX_MASK (1 << SRPWR_DMN2_MACAUX_SHIFT) /* MAC/Phy Aux */ | |
| 4907 | #define SRPWR_DMN3_MACMAIN (3) /* MAC/Phy Main */ | |
| 4908 | #define SRPWR_DMN3_MACMAIN_SHIFT (SRPWR_DMN3_MACMAIN) /* MAC/Phy Main */ | |
| 4909 | #define SRPWR_DMN3_MACMAIN_MASK (1 << SRPWR_DMN3_MACMAIN_SHIFT) /* MAC/Phy Main */ | |
| 4910 | ||
| 4911 | #define SRPWR_DMN4_MACSCAN (4) /* MAC/Phy Scan */ | |
| 4912 | #define SRPWR_DMN4_MACSCAN_SHIFT (SRPWR_DMN4_MACSCAN) /* MAC/Phy Scan */ | |
| 4913 | #define SRPWR_DMN4_MACSCAN_MASK (1 << SRPWR_DMN4_MACSCAN_SHIFT) /* MAC/Phy Scan */ | |
| 4914 | ||
| 4915 | #define SRPWR_DMN_MAX (5) | |
| 4916 | /* all power domain mask */ | |
| 4917 | #define SRPWR_DMN_ALL_MASK(sih) si_srpwr_domain_all_mask(sih) | |
| 4918 | ||
| 4919 | #define SRPWR_REQON_SHIFT (8) /* PowerOnRequest[11:8] */ | |
| 4920 | #define SRPWR_REQON_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_REQON_SHIFT) | |
| 4921 | ||
| 4922 | #define SRPWR_STATUS_SHIFT (16) /* ExtPwrStatus[19:16], RO */ | |
| 4923 | #define SRPWR_STATUS_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_STATUS_SHIFT) | |
| 4924 | ||
| 4925 | #define SRPWR_BT_STATUS_SHIFT (20) /* PowerDomain[20:21], RO */ | |
| 4926 | #define SRPWR_BT_STATUS_MASK (0x3) | |
| 4927 | ||
| 4928 | #define SRPWR_DMN_ID_SHIFT (28) /* PowerDomain[31:28], RO */ | |
| 4929 | #define SRPWR_DMN_ID_MASK (0xF) | |
| 4930 | ||
| 4931 | #define SRPWR_UP_DOWN_DELAY 100 /* more than 3 ILP clocks */ | |
| 4932 | ||
| 4933 | /* PMU Precision Usec Timer */ | |
| 4934 | #define PMU_PREC_USEC_TIMER_ENABLE 0x1 | |
| 4935 | ||
| 4936 | /* Random Number/Bit Generator defines */ | |
| 4937 | #define MASK_1BIT(offset) (0x1u << offset) | |
| 4938 | ||
| 4939 | #define CC_RNG_CTRL_0_RBG_EN_SHIFT (0u) | |
| 4940 | #define CC_RNG_CTRL_0_RBG_EN_MASK (0x1FFFu << CC_RNG_CTRL_0_RBG_EN_SHIFT) | |
| 4941 | #define CC_RNG_CTRL_0_RBG_EN (0x1FFFu) | |
| 4942 | #define CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT (12u) | |
| 4943 | #define CC_RNG_CTRL_0_RBG_DEV_CTRL_MASK (0x3u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) | |
| 4944 | #define CC_RNG_CTRL_0_RBG_DEV_CTRL_1MHz (0x3u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) | |
| 4945 | #define CC_RNG_CTRL_0_RBG_DEV_CTRL_2MHz (0x2u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) | |
| 4946 | #define CC_RNG_CTRL_0_RBG_DEV_CTRL_4MHz (0x1u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) | |
| 4947 | #define CC_RNG_CTRL_0_RBG_DEV_CTRL_8MHz (0x0u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) | |
| 4948 | ||
| 4949 | /* RNG_FIFO_COUNT */ | |
| 4950 | /* RFC - RNG FIFO COUNT */ | |
| 4951 | #define CC_RNG_FIFO_COUNT_RFC_SHIFT (0u) | |
| 4952 | #define CC_RNG_FIFO_COUNT_RFC_MASK (0xFFu << CC_RNG_FIFO_COUNT_RFC_SHIFT) | |
| 4953 | ||
| 4954 | /* RNG interrupt */ | |
| 4955 | #define CC_RNG_TOT_BITS_CNT_IRQ_SHIFT (0u) | |
| 4956 | #define CC_RNG_TOT_BITS_CNT_IRQ_MASK (0x1u << CC_RNG_TOT_BITS_CNT_IRQ_SHIFT) | |
| 4957 | #define CC_RNG_TOT_BITS_MAX_IRQ_SHIFT (1u) | |
| 4958 | #define CC_RNG_TOT_BITS_MAX_IRQ_MASK (0x1u << CC_RNG_TOT_BITS_MAX_IRQ_SHIFT) | |
| 4959 | #define CC_RNG_FIFO_FULL_IRQ_SHIFT (2u) | |
| 4960 | #define CC_RNG_FIFO_FULL_IRQ_MASK (0x1u << CC_RNG_FIFO_FULL_IRQ_SHIFT) | |
| 4961 | #define CC_RNG_FIFO_OVER_RUN_IRQ_SHIFT (3u) | |
| 4962 | #define CC_RNG_FIFO_OVER_RUN_IRQ_MASK (0x1u << CC_RNG_FIFO_OVER_RUN_IRQ_SHIFT) | |
| 4963 | #define CC_RNG_FIFO_UNDER_RUN_IRQ_SHIFT (4u) | |
| 4964 | #define CC_RNG_FIFO_UNDER_RUN_IRQ_MASK (0x1u << CC_RNG_FIFO_UNDER_RUN_IRQ_SHIFT) | |
| 4965 | #define CC_RNG_NIST_FAIL_IRQ_SHIFT (5u) | |
| 4966 | #define CC_RNG_NIST_FAIL_IRQ_MASK (0x1u << CC_RNG_NIST_FAIL_IRQ_SHIFT) | |
| 4967 | #define CC_RNG_STARTUP_TRANSITION_MET_IRQ_SHIFT (17u) | |
| 4968 | #define CC_RNG_STARTUP_TRANSITION_MET_IRQ_MASK (0x1u << \ | |
| 4969 | CC_RNG_STARTUP_TRANSITION_MET_IRQ_SHIFT) | |
| 4970 | #define CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_SHIFT (31u) | |
| 4971 | #define CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_MASK (0x1u << \ | |
| 4972 | CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_SHIFT) | |
| 4973 | ||
| 4974 | /* FISCtrlStatus */ | |
| 4975 | #define PMU_CLEAR_FIS_DONE_SHIFT 1u | |
| 4976 | #define PMU_CLEAR_FIS_DONE_MASK (1u << PMU_CLEAR_FIS_DONE_SHIFT) | |
| 4977 | ||
| 4978 | #define PMU_FIS_FORCEON_ALL_SHIFT 4u | |
| 4979 | #define PMU_FIS_FORCEON_ALL_MASK (1u << PMU_FIS_FORCEON_ALL_SHIFT) | |
| 4980 | ||
| 4981 | #define PMU_FIS_DN_TIMER_VAL_SHIFT 16u | |
| 4982 | #define PMU_FIS_DN_TIMER_VAL_MASK 0x7FFF0000u | |
| 4983 | ||
| 4984 | #define PMU_FIS_DN_TIMER_VAL_4378 0x2f80u /* micro second */ | |
| 4985 | #define PMU_FIS_DN_TIMER_VAL_4389 0x3f80u /* micro second */ | |
| 4986 | ||
| 4987 | #define PMU_FIS_PCIE_SAVE_EN_SHIFT 5u | |
| 4988 | #define PMU_FIS_PCIE_SAVE_EN_VALUE (1u << PMU_FIS_PCIE_SAVE_EN_SHIFT) | |
| 4989 | ||
| 4990 | #define PMU_REG6_RFLDO_CTRL 0x000000E0 | |
| 4991 | #define PMU_REG6_RFLDO_CTRL_SHFT 5 | |
| 4992 | ||
| 4993 | #define PMU_REG6_BTLDO_CTRL 0x0000E000 | |
| 4994 | #define PMU_REG6_BTLDO_CTRL_SHFT 13 | |
| 4995 | #endif /* _SBCHIPC_H */ |