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wifi: update bcm driver to 101.10.240 to support android r [1/2]
[GitHub/LineageOS/G12/android_hardware_amlogic_kernel-modules_dhd-driver.git] / bcmdhd.101.10.240.x / include / bcmpcie.h
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1b4a7c03
LJ		 1/*
2 * Broadcom PCIE
3 * Software-specific definitions shared between device and host side
4 * Explains the shared area between host and dongle
5 *
6 * Copyright (C) 2020, Broadcom.
7 *
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
13 *
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
21 *
22 *
23 * <<Broadcom-WL-IPTag/Dual:>>
24 */
25
26#ifndef _bcmpcie_h_
27#define _bcmpcie_h_
28
29#include <typedefs.h>
30
31#define ADDR_64(x) (x.addr)
32#define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr))
33#define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr))
34
35typedef struct {
36 uint32 low_addr;
37 uint32 high_addr;
38} sh_addr_t;
39
40/* May be overridden by 43xxxxx-roml.mk */
41#if !defined(BCMPCIE_MAX_TX_FLOWS)
42#define BCMPCIE_MAX_TX_FLOWS 40
43#endif /* ! BCMPCIE_MAX_TX_FLOWS */
44
45#define PCIE_SHARED_VERSION_7 0x00007
46#define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */
47#define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */
48/**
49 * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that
50 * is located in device memory.
51 */
52#define PCIE_SHARED_VERSION_MASK 0x000FF
53#define PCIE_SHARED_ASSERT_BUILT 0x00100
54#define PCIE_SHARED_ASSERT 0x00200
55#define PCIE_SHARED_TRAP 0x00400
56#define PCIE_SHARED_IN_BRPT 0x00800
57#define PCIE_SHARED_SET_BRPT 0x01000
58#define PCIE_SHARED_PENDING_BRPT 0x02000
59/* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */
60#define PCIE_SHARED_EVT_SEQNUM 0x08000
61#define PCIE_SHARED_DMA_INDEX 0x10000
62
63/**
64 * There are host types where a device interrupt can 'race ahead' of data written by the device into
65 * host memory. The dongle can avoid this condition using a variety of techniques (read barrier,
66 * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately
67 * these techniques have drawbacks on router platforms. For these platforms, it was decided to not
68 * avoid the condition, but to detect the condition instead and act on it.
69 * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM
70 */
71#define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000
72#define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000
73#define PCIE_SHARED_D2H_SYNC_MODE_MASK \
74 (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM)
75#define PCIE_SHARED_IDLE_FLOW_RING 0x80000
76#define PCIE_SHARED_2BYTE_INDICES 0x100000
77
78#define PCIE_SHARED_FAST_DELETE_RING 0x00000020 /* Fast Delete Ring */
79#define PCIE_SHARED_EVENT_BUF_POOL_MAX 0x000000c0 /* event buffer pool max bits */
80#define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS 6 /* event buffer pool max bit position */
81
82/* dongle supports fatal buf log collection */
83#define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000
84
85/* Implicit DMA with corerev 19 and after */
86#define PCIE_SHARED_IDMA 0x400000
87
88/* MSI support */
89#define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000
90
91/* IFRM with corerev 19 and after */
92#define PCIE_SHARED_IFRM 0x1000000
93
94/**
95 * From Rev6 and above, suspend/resume can be done using two handshake methods.
96 * 1. Using ctrl post/ctrl cmpl messages (Default rev6)
97 * 2. Using Mailbox data (old method as used in rev5)
98 * This shared flag indicates whether to overide rev6 default method and use mailbox for
99 * suspend/resume.
100 */
101#define PCIE_SHARED_USE_MAILBOX 0x2000000
102
103/* Firmware compiled for mfgbuild purposes */
104#define PCIE_SHARED_MFGBUILD_FW 0x4000000
105
106/* Firmware could use DB0 value as host timestamp */
107#define PCIE_SHARED_TIMESTAMP_DB0 0x8000000
108/* Firmware could use Hostready (IPC rev7) */
109#define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000
110
111/* When set, Firmwar does not support OOB Device Wake based DS protocol */
112#define PCIE_SHARED_NO_OOB_DW 0x20000000
113
114/* When set, Firmwar supports Inband DS protocol */
115#define PCIE_SHARED_INBAND_DS 0x40000000
116
117/* use DAR registers */
118#define PCIE_SHARED_DAR 0x80000000
119
120/**
121 * Following are the shared2 flags. All bits in flags have been used. A flags2
122 * field got added and the definition for these flags come here:
123 */
124/* WAR: D11 txstatus through unused status field of PCIe completion header */
125#define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */
126#define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002
127#define PCIE_SHARED2_BT_LOGGING 0x00000004 /* BT logging support */
128#define PCIE_SHARED2_SNAPSHOT_UPLOAD 0x00000008 /* BT/WLAN snapshot upload support */
129#define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 /* submission count WAR */
130#define PCIE_SHARED2_FAST_DELETE_RING 0x00000020 /* Fast Delete ring support */
131#define PCIE_SHARED2_EVTBUF_MAX_MASK 0x000000C0 /* 0:32, 1:64, 2:128, 3: 256 */
132
133/* using flags2 to indicate firmware support added to reuse timesync to update PKT txstatus */
134#define PCIE_SHARED2_PKT_TX_STATUS 0x00000100
135#define PCIE_SHARED2_FW_SMALL_MEMDUMP 0x00000200 /* FW small memdump */
136#define PCIE_SHARED2_FW_HC_ON_TRAP 0x00000400
137#define PCIE_SHARED2_HSCB 0x00000800 /* Host SCB support */
138
139#define PCIE_SHARED2_EDL_RING 0x00001000 /* Support Enhanced Debug Lane */
140#define PCIE_SHARED2_DEBUG_BUF_DEST 0x00002000 /* debug buf dest support */
141#define PCIE_SHARED2_PCIE_ENUM_RESET_FLR 0x00004000 /* BT producer index reset WAR */
142#define PCIE_SHARED2_PKT_TIMESTAMP 0x00008000 /* Timestamp in packet */
143
144#define PCIE_SHARED2_HP2P 0x00010000u /* HP2P feature */
145#define PCIE_SHARED2_HWA 0x00020000u /* HWA feature */
146#define PCIE_SHARED2_TRAP_ON_HOST_DB7 0x00040000u /* can take a trap on DB7 from host */
147
148#define PCIE_SHARED2_DURATION_SCALE 0x00100000u
149
150#define PCIE_SHARED2_D2H_D11_TX_STATUS 0x40000000
151#define PCIE_SHARED2_H2D_D11_TX_STATUS 0x80000000
152
153#define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09
154#define PCIE_SHARED_H2D_MAGIC 0x12345678
155
156typedef uint16 pcie_hwa_db_index_t; /* 16 bit HWA index (IPC Rev 7) */
157#define PCIE_HWA_DB_INDEX_SZ (2u) /* 2 bytes sizeof(pcie_hwa_db_index_t) */
158
159/**
160 * Message rings convey messages between host and device. They are unidirectional, and are located
161 * in host memory.
162 *
163 * This is the minimal set of message rings, known as 'common message rings':
164 */
165#define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0
166#define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1
167#define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2
168#define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3
169#define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4
170#define BCMPCIE_COMMON_MSGRING_MAX_ID 4
171
172#define BCMPCIE_H2D_COMMON_MSGRINGS 2
173#define BCMPCIE_D2H_COMMON_MSGRINGS 3
174#define BCMPCIE_COMMON_MSGRINGS 5
175
176#define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \
177 (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows))
178
179/* different ring types */
180#define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1
181#define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2
182#define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3
183#define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4
184#define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5
185#define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT 0x6
186
187#define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1
188#define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2
189#define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3
190#define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4
191#define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5
192#define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL 0x6
193#define BCMPCIE_D2H_RING_TYPE_EDL 0x7
194#define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL 0x8
195#define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL 0x9
196
197/**
198 * H2D and D2H, WR and RD index, are maintained in the following arrays:
199 * - Array of all H2D WR Indices
200 * - Array of all H2D RD Indices
201 * - Array of all D2H WR Indices
202 * - Array of all D2H RD Indices
203 *
204 * The offset of the WR or RD indexes (for common rings) in these arrays are
205 * listed below. Arrays ARE NOT indexed by a ring's id.
206 *
207 * D2H common rings WR and RD index start from 0, even though their ringids
208 * start from BCMPCIE_H2D_COMMON_MSGRINGS
209 */
210
211#define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id)
212
213enum h2dring_idx {
214 /* H2D common rings */
215 BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX =
216 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT),
217 BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX =
218 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT),
219
220 /* First TxPost's WR or RD index starts after all H2D common rings */
221 BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START =
222 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS)
223};
224
225#define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \
226 ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS)
227
228enum d2hring_idx {
229 /* D2H Common Rings */
230 BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX =
231 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE),
232 BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX =
233 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE),
234 BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX =
235 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE)
236};
237
238/**
239 * Macros for managing arrays of RD WR indices:
240 * rw_index_sz:
241 * - in dongle, rw_index_sz is known at compile time
242 * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags
243 *
244 * ring_idx: See h2dring_idx and d2hring_idx
245 */
246
247/** Offset of a RD or WR index in H2D or D2H indices array */
248#define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \
249 ((rw_index_sz) * (ring_idx))
250
251/** Fetch the address of RD or WR index in H2D or D2H indices array */
252#define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \
253 (void *)((uint32)(indices_array_base) + \
254 BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx)))
255
256/** H2D DMA Indices array size: given max flow rings */
257#define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \
258 ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows))
259
260/** D2H DMA Indices array size */
261#define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \
262 ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS)
263
264/* Backwards compatibility for legacy branches. */
265#if !defined(PHYS_ADDR_N)
266 #define PHYS_ADDR_N(name) name
267#endif
268
269/**
270 * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used
271 * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated
272 * both in host as well as device memory.
273 */
274typedef struct ring_mem {
275 uint16 idx; /* ring id */
276 uint8 type;
277 uint8 rsvd;
278 uint16 max_item; /* Max number of items in flow ring */
279 uint16 len_items; /* Items are fixed size. Length in bytes of one item */
280 sh_addr_t base_addr; /* 64 bits address, either in host or device memory */
281} ring_mem_t;
282
283/**
284 * Per flow ring, information is maintained in device memory, eg at what address the ringmem and
285 * ringstate are located. The flow ring itself can be instantiated in either host or device memory.
286 *
287 * Perhaps this type should be renamed to make clear that it resides in device memory only.
288 */
289typedef struct ring_info {
290 uint32 PHYS_ADDR_N(ringmem_ptr); /* ring mem location in dongle memory */
291
292 /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not
293 * by a ringid.
294 */
295
296 /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */
297 uint32 PHYS_ADDR_N(h2d_w_idx_ptr); /* Array of all H2D ring's WR indices */
298 uint32 PHYS_ADDR_N(h2d_r_idx_ptr); /* Array of all H2D ring's RD indices */
299 uint32 PHYS_ADDR_N(d2h_w_idx_ptr); /* Array of all D2H ring's WR indices */
300 uint32 PHYS_ADDR_N(d2h_r_idx_ptr); /* Array of all D2H ring's RD indices */
301
302 /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host.
303 * Host may directly fetch WR and RD indices from these host-side arrays.
304 *
305 * 64bit ptr to arrays of WR or RD indices for all rings in host memory.
306 */
307 sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */
308 sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */
309 sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */
310 sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */
311
312 uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */
313 uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */
314 uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */
315 uint16 max_vdevs; /* max number of virtual interfaces supported */
316
317 sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */
318
319 /* 32bit ptr to arrays of HWA DB indices for all rings in dongle memory */
320 uint32 PHYS_ADDR_N(h2d_hwa_db_idx_ptr); /* Array of all H2D rings HWA DB indices */
321 uint32 PHYS_ADDR_N(d2h_hwa_db_idx_ptr); /* Array of all D2H rings HWA DB indices */
322
323} ring_info_t;
324
325/**
326 * A structure located in TCM that is shared between host and device, primarily used during
327 * initialization.
328 */
329typedef struct {
330 /** shared area version captured at flags 7:0 */
331 uint32 flags;
332
333 uint32 PHYS_ADDR_N(trap_addr);
334 uint32 PHYS_ADDR_N(assert_exp_addr);
335 uint32 PHYS_ADDR_N(assert_file_addr);
336 uint32 assert_line;
337 uint32 PHYS_ADDR_N(console_addr); /**< Address of hnd_cons_t */
338
339 uint32 PHYS_ADDR_N(msgtrace_addr);
340
341 uint32 fwid;
342
343 /* Used for debug/flow control */
344 uint16 total_lfrag_pkt_cnt;
345 uint16 max_host_rxbufs; /* rsvd in spec */
346
347 uint32 dma_rxoffset; /* rsvd in spec */
348
349 /** these will be used for sleep request/ack, d3 req/ack */
350 uint32 PHYS_ADDR_N(h2d_mb_data_ptr);
351 uint32 PHYS_ADDR_N(d2h_mb_data_ptr);
352
353 /* information pertinent to host IPC/msgbuf channels */
354 /** location in the TCM memory which has the ring_info */
355 uint32 PHYS_ADDR_N(rings_info_ptr);
356
357 /** block of host memory for the scratch buffer */
358 uint32 host_dma_scratch_buffer_len;
359 sh_addr_t host_dma_scratch_buffer;
360
361 /* location in host memory for scb host offload structures */
362 sh_addr_t host_scb_addr;
363 uint32 host_scb_size;
364
365 /* anonymous union for overloading fields in structure */
366 union {
367 uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */
368 struct {
369 /* Host provided trap buffer length in words */
370 uint16 device_trap_debug_buffer_len;
371 uint16 rsvd2;
372 };
373 };
374
375 /* rev6 compatible changes */
376 uint32 flags2;
377 uint32 host_cap;
378
379 /* location in the host address space to write trap indication.
380 * At this point for the current rev of the spec, firmware will
381 * support only indications to 32 bit host addresses.
382 * This essentially is device_trap_debug_buffer_addr
383 */
384 sh_addr_t host_trap_addr;
385
386 /* location for host fatal error log buffer start address */
387 uint32 PHYS_ADDR_N(device_fatal_logbuf_start);
388
389 /* location in host memory for offloaded modules */
390 sh_addr_t hoffload_addr;
391 uint32 flags3;
392 uint32 host_cap2;
393 uint32 host_cap3;
394} pciedev_shared_t;
395
396/* Device F/W provides the following access function:
397 * pciedev_shared_t *hnd_get_pciedev_shared(void);
398 */
399
400/* host capabilities */
401#define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF
402#define HOSTCAP_H2D_VALID_PHASE 0x00000100
403#define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200
404#define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400
405#define HOSTCAP_DB0_TIMESTAMP 0x00000800
406#define HOSTCAP_DS_NO_OOB_DW 0x00001000
407#define HOSTCAP_DS_INBAND_DW 0x00002000
408#define HOSTCAP_H2D_IDMA 0x00004000
409#define HOSTCAP_H2D_IFRM 0x00008000
410#define HOSTCAP_H2D_DAR 0x00010000
411#define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000
412#define HOSTCAP_TXSTATUS_METADATA 0x00040000
413#define HOSTCAP_BT_LOGGING 0x00080000
414#define HOSTCAP_SNAPSHOT_UPLOAD 0x00100000
415#define HOSTCAP_FAST_DELETE_RING 0x00200000
416#define HOSTCAP_PKT_TXSTATUS 0x00400000
417#define HOSTCAP_UR_FW_NO_TRAP 0x00800000 /* Don't trap on UR */
418#define HOSTCAP_HSCB 0x02000000
419/* Host support for extended device trap debug buffer */
420#define HOSTCAP_EXT_TRAP_DBGBUF 0x04000000
421/* Host support for enhanced debug lane */
422#define HOSTCAP_EDL_RING 0x10000000
423#define HOSTCAP_PKT_TIMESTAMP 0x20000000
424#define HOSTCAP_PKT_HP2P 0x40000000
425#define HOSTCAP_HWA 0x80000000
426#define HOSTCAP2_DURATION_SCALE_MASK 0x0000003Fu
427
428/* extended trap debug buffer allocation sizes. Note that this buffer can be used for
429 * other trap related purposes also.
430 */
431#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN (64u * 1024u)
432#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN (96u * 1024u)
433#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX (256u * 1024u)
434
435/**
436 * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware
437 * support.
438 */
439
440/* H2D mail box Data */
441#define H2D_HOST_D3_INFORM 0x00000001
442#define H2D_HOST_DS_ACK 0x00000002
443#define H2D_HOST_DS_NAK 0x00000004
444#define H2D_HOST_D0_INFORM_IN_USE 0x00000008
445#define H2D_HOST_D0_INFORM 0x00000010
446#define H2DMB_DS_ACTIVE 0x00000020
447#define H2DMB_DS_DEVICE_WAKE 0x00000040
448#define H2D_HOST_IDMA_INITED 0x00000080
449#define H2D_HOST_ACK_NOINT 0x00010000 /* d2h_ack interrupt ignore */
450#define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */
451#define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */
452#define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM
453#define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK
454#define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK
455#define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE
456#define H2DMB_D0_INFORM H2D_HOST_D0_INFORM
457#define H2DMB_FW_TRAP H2D_FW_TRAP
458#define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT
459#define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE
460#define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE
461
462/* D2H mail box Data */
463#define D2H_DEV_D3_ACK 0x00000001
464#define D2H_DEV_DS_ENTER_REQ 0x00000002
465#define D2H_DEV_DS_EXIT_NOTE 0x00000004
466#define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008
467#define D2H_DEV_IDMA_INITED 0x00000010
468#define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK
469#define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ
470#define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE
471
472#define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \
473 D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED)
474#define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK))
475
476/* trap data codes */
477#define D2H_DEV_FWHALT 0x10000000
478#define D2H_DEV_EXT_TRAP_DATA 0x20000000
479#define D2H_DEV_TRAP_IN_TRAP 0x40000000
480#define D2H_DEV_TRAP_HOSTDB 0x80000000 /* trap as set by host DB */
481#define D2H_DEV_TRAP_DUE_TO_BT 0x01000000
482/* Indicates trap due to HMAP violation */
483#define D2H_DEV_TRAP_DUE_TO_HMAP 0x02000000
484/* Indicates whether HMAP violation was Write */
485#define D2H_DEV_TRAP_HMAP_WRITE 0x04000000
486#define D2H_DEV_TRAP_PING_HOST_FAILURE 0x08000000
487#define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */
488
489#define D2HMB_FWHALT D2H_DEV_FWHALT
490#define D2HMB_TRAP_IN_TRAP D2H_DEV_TRAP_IN_TRAP
491#define D2HMB_EXT_TRAP_DATA D2H_DEV_EXT_TRAP_DATA
492
493/* Size of Extended Trap data Buffer */
494#define BCMPCIE_EXT_TRAP_DATA_MAXLEN 4096
495
496/** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */
497#define PREVTXP(i, d) (((i) == 0) ? ((d) - 1) : ((i) - 1))
498#define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1))
499#define NEXTNTXP(i, n, d) ((((i)+(n)) >= (d)) ? 0 : ((i)+(n)))
500#define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w)))
501#define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1)
502
503/* Function can be used to notify host of FW halt */
504#define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r))
505#define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w))
506#define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1)
507#define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \
508 (uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \
509 (uint32)((d) - (w) - 1) : (uint32)((d) - (w))
510
511#define CHECK_NOWRITE_SPACE(r, w, d) \
512 (((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1))))
513
514/* These should be moved into pciedev.h --- */
515#define WRT_PEND(x) ((x)->wr_pending)
516#define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */
517#define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a))
518
519#define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */
520#define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a))
521
522#define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size)
523
524#define RING_READ_PTR(x) ((x)->ringstate->r_offset)
525#define RING_WRITE_PTR(x) ((x)->ringstate->w_offset)
526#define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr)
527#define RING_MAX_ITEM(x) ((x)->ringmem->max_item)
528#define RING_LEN_ITEMS(x) ((x)->ringmem->len_items)
529#define HOST_RING_BASE(x) ((x)->dma_buf.va)
530#define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \
531 ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x))))
532
533/* Trap types copied in the pciedev_shared.trap_addr */
534#define FW_INITIATED_TRAP_TYPE (0x1 << 7)
535#define HEALTHCHECK_NODS_TRAP_TYPE (0x1 << 6)
536
537#endif /* _bcmpcie_h_ */