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dhd: rename 100.10.315.x to 100.10.545.x
[GitHub/LineageOS/G12/android_hardware_amlogic_kernel-modules_dhd-driver.git] / bcmdhd.100.10.545.x / include / bcmpcispi.h
CommitLineData
d2839953
RC		 1/*
2 * Broadcom PCI-SPI Host Controller Register Definitions
3 *
965f77c4 4 * Copyright (C) 1999-2019, Broadcom.
d2839953
RC		 5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 *
25 * <<Broadcom-WL-IPTag/Open:>>
26 *
27 * $Id: bcmpcispi.h 514727 2014-11-12 03:02:48Z $
28 */
29#ifndef _BCM_PCI_SPI_H
30#define _BCM_PCI_SPI_H
31
32/* cpp contortions to concatenate w/arg prescan */
33#ifndef PAD
34#define _PADLINE(line) pad ## line
35#define _XSTR(line) _PADLINE(line)
36#define PAD _XSTR(__LINE__)
37#endif /* PAD */
38
39typedef volatile struct {
40 uint32 spih_ctrl; /* 0x00 SPI Control Register */
41 uint32 spih_stat; /* 0x04 SPI Status Register */
42 uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
43 uint32 spih_ext; /* 0x0C SPI Extension Register */
44 uint32 PAD[4]; /* 0x10-0x1F PADDING */
45
46 uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
47 uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
48 uint32 PAD[6]; /* 0x28-0x3F PADDING */
49
50 uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
51 uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
52 /* 1=Active High) */
53 uint32 spih_int_mask; /* 0x48 SPI Interrupt Mask */
54 uint32 spih_int_status; /* 0x4C SPI Interrupt Status */
55 uint32 PAD[4]; /* 0x50-0x5F PADDING */
56
57 uint32 spih_hex_disp; /* 0x60 SPI 4-digit hex display value */
58 uint32 spih_current_ma; /* 0x64 SPI SD card current consumption in mA */
59 uint32 PAD[1]; /* 0x68 PADDING */
60 uint32 spih_disp_sel; /* 0x6c SPI 4-digit hex display mode select (1=current) */
61 uint32 PAD[4]; /* 0x70-0x7F PADDING */
62 uint32 PAD[8]; /* 0x80-0x9F PADDING */
63 uint32 PAD[8]; /* 0xA0-0xBF PADDING */
64 uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */
65 uint32 spih_pll_status; /* 0xC4 PLL Status Register */
66 uint32 spih_xtal_freq; /* 0xC8 External Clock Frequency in units of 10000Hz */
67 uint32 spih_clk_count; /* 0xCC External Clock Count Register */
68
69} spih_regs_t;
70
71typedef volatile struct {
72 uint32 cfg_space[0x40]; /* 0x000-0x0FF PCI Configuration Space (Read Only) */
73 uint32 P_IMG_CTRL0; /* 0x100 PCI Image0 Control Register */
74
75 uint32 P_BA0; /* 0x104 32 R/W PCI Image0 Base Address register */
76 uint32 P_AM0; /* 0x108 32 R/W PCI Image0 Address Mask register */
77 uint32 P_TA0; /* 0x10C 32 R/W PCI Image0 Translation Address register */
78 uint32 P_IMG_CTRL1; /* 0x110 32 R/W PCI Image1 Control register */
79 uint32 P_BA1; /* 0x114 32 R/W PCI Image1 Base Address register */
80 uint32 P_AM1; /* 0x118 32 R/W PCI Image1 Address Mask register */
81 uint32 P_TA1; /* 0x11C 32 R/W PCI Image1 Translation Address register */
82 uint32 P_IMG_CTRL2; /* 0x120 32 R/W PCI Image2 Control register */
83 uint32 P_BA2; /* 0x124 32 R/W PCI Image2 Base Address register */
84 uint32 P_AM2; /* 0x128 32 R/W PCI Image2 Address Mask register */
85 uint32 P_TA2; /* 0x12C 32 R/W PCI Image2 Translation Address register */
86 uint32 P_IMG_CTRL3; /* 0x130 32 R/W PCI Image3 Control register */
87 uint32 P_BA3; /* 0x134 32 R/W PCI Image3 Base Address register */
88 uint32 P_AM3; /* 0x138 32 R/W PCI Image3 Address Mask register */
89 uint32 P_TA3; /* 0x13C 32 R/W PCI Image3 Translation Address register */
90 uint32 P_IMG_CTRL4; /* 0x140 32 R/W PCI Image4 Control register */
91 uint32 P_BA4; /* 0x144 32 R/W PCI Image4 Base Address register */
92 uint32 P_AM4; /* 0x148 32 R/W PCI Image4 Address Mask register */
93 uint32 P_TA4; /* 0x14C 32 R/W PCI Image4 Translation Address register */
94 uint32 P_IMG_CTRL5; /* 0x150 32 R/W PCI Image5 Control register */
95 uint32 P_BA5; /* 0x154 32 R/W PCI Image5 Base Address register */
96 uint32 P_AM5; /* 0x158 32 R/W PCI Image5 Address Mask register */
97 uint32 P_TA5; /* 0x15C 32 R/W PCI Image5 Translation Address register */
98 uint32 P_ERR_CS; /* 0x160 32 R/W PCI Error Control and Status register */
99 uint32 P_ERR_ADDR; /* 0x164 32 R PCI Erroneous Address register */
100 uint32 P_ERR_DATA; /* 0x168 32 R PCI Erroneous Data register */
101
102 uint32 PAD[5]; /* 0x16C-0x17F PADDING */
103
104 uint32 WB_CONF_SPC_BAR; /* 0x180 32 R WISHBONE Configuration Space Base Address */
105 uint32 W_IMG_CTRL1; /* 0x184 32 R/W WISHBONE Image1 Control register */
106 uint32 W_BA1; /* 0x188 32 R/W WISHBONE Image1 Base Address register */
107 uint32 W_AM1; /* 0x18C 32 R/W WISHBONE Image1 Address Mask register */
108 uint32 W_TA1; /* 0x190 32 R/W WISHBONE Image1 Translation Address reg */
109 uint32 W_IMG_CTRL2; /* 0x194 32 R/W WISHBONE Image2 Control register */
110 uint32 W_BA2; /* 0x198 32 R/W WISHBONE Image2 Base Address register */
111 uint32 W_AM2; /* 0x19C 32 R/W WISHBONE Image2 Address Mask register */
112 uint32 W_TA2; /* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */
113 uint32 W_IMG_CTRL3; /* 0x1A4 32 R/W WISHBONE Image3 Control register */
114 uint32 W_BA3; /* 0x1A8 32 R/W WISHBONE Image3 Base Address register */
115 uint32 W_AM3; /* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */
116 uint32 W_TA3; /* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */
117 uint32 W_IMG_CTRL4; /* 0x1B4 32 R/W WISHBONE Image4 Control register */
118 uint32 W_BA4; /* 0x1B8 32 R/W WISHBONE Image4 Base Address register */
119 uint32 W_AM4; /* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */
120 uint32 W_TA4; /* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */
121 uint32 W_IMG_CTRL5; /* 0x1C4 32 R/W WISHBONE Image5 Control register */
122 uint32 W_BA5; /* 0x1C8 32 R/W WISHBONE Image5 Base Address register */
123 uint32 W_AM5; /* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */
124 uint32 W_TA5; /* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */
125 uint32 W_ERR_CS; /* 0x1D4 32 R/W WISHBONE Error Control and Status reg */
126 uint32 W_ERR_ADDR; /* 0x1D8 32 R WISHBONE Erroneous Address register */
127 uint32 W_ERR_DATA; /* 0x1DC 32 R WISHBONE Erroneous Data register */
128 uint32 CNF_ADDR; /* 0x1E0 32 R/W Configuration Cycle register */
129 uint32 CNF_DATA; /* 0x1E4 32 R/W Configuration Cycle Generation Data reg */
130
131 uint32 INT_ACK; /* 0x1E8 32 R Interrupt Acknowledge register */
132 uint32 ICR; /* 0x1EC 32 R/W Interrupt Control register */
133 uint32 ISR; /* 0x1F0 32 R/W Interrupt Status register */
134} spih_pciregs_t;
135
136/*
137 * PCI Core interrupt enable and status bit definitions.
138 */
139
140/* PCI Core ICR Register bit definitions */
141#define PCI_INT_PROP_EN (1 << 0) /* Interrupt Propagation Enable */
142#define PCI_WB_ERR_INT_EN (1 << 1) /* Wishbone Error Interrupt Enable */
143#define PCI_PCI_ERR_INT_EN (1 << 2) /* PCI Error Interrupt Enable */
144#define PCI_PAR_ERR_INT_EN (1 << 3) /* Parity Error Interrupt Enable */
145#define PCI_SYS_ERR_INT_EN (1 << 4) /* System Error Interrupt Enable */
146#define PCI_SOFTWARE_RESET (1U << 31) /* Software reset of the PCI Core. */
147
148/* PCI Core ISR Register bit definitions */
149#define PCI_INT_PROP_ST (1 << 0) /* Interrupt Propagation Status */
150#define PCI_WB_ERR_INT_ST (1 << 1) /* Wishbone Error Interrupt Status */
151#define PCI_PCI_ERR_INT_ST (1 << 2) /* PCI Error Interrupt Status */
152#define PCI_PAR_ERR_INT_ST (1 << 3) /* Parity Error Interrupt Status */
153#define PCI_SYS_ERR_INT_ST (1 << 4) /* System Error Interrupt Status */
154
155/* Registers on the Wishbone bus */
156#define SPIH_CTLR_INTR (1 << 0) /* SPI Host Controller Core Interrupt */
157#define SPIH_DEV_INTR (1 << 1) /* SPI Device Interrupt */
158#define SPIH_WFIFO_INTR (1 << 2) /* SPI Tx FIFO Empty Intr (FPGA Rev >= 8) */
159
160/* GPIO Bit definitions */
161#define SPIH_CS (1 << 0) /* SPI Chip Select (active low) */
162#define SPIH_SLOT_POWER (1 << 1) /* SD Card Slot Power Enable */
163#define SPIH_CARD_DETECT (1 << 2) /* SD Card Detect */
164
165/* SPI Status Register Bit definitions */
166#define SPIH_STATE_MASK 0x30 /* SPI Transfer State Machine state mask */
167#define SPIH_STATE_SHIFT 4 /* SPI Transfer State Machine state shift */
168#define SPIH_WFFULL (1 << 3) /* SPI Write FIFO Full */
169#define SPIH_WFEMPTY (1 << 2) /* SPI Write FIFO Empty */
170#define SPIH_RFFULL (1 << 1) /* SPI Read FIFO Full */
171#define SPIH_RFEMPTY (1 << 0) /* SPI Read FIFO Empty */
172
173#define SPIH_EXT_CLK (1U << 31) /* Use External Clock as PLL Clock source. */
174
175#define SPIH_PLL_NO_CLK (1 << 1) /* Set to 1 if the PLL's input clock is lost. */
176#define SPIH_PLL_LOCKED (1 << 3) /* Set to 1 when the PLL is locked. */
177
178/* Spin bit loop bound check */
179#define SPI_SPIN_BOUND 0xf4240 /* 1 million */
180
181#endif /* _BCM_PCI_SPI_H */