projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: gadget: fsl_udc_core: convert to udc_start/udc_stop
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / fsl_udc_core.c
CommitLineData
b504882d 1/*
58c559e6 2 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
ea437f39 3 * All rights reserved.
b504882d
LY		 4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
2ea6698d 10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
b504882d
LY		 11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#undef VERBOSE
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/ioport.h>
25#include <linux/types.h>
26#include <linux/errno.h>
ded017ee 27#include <linux/err.h>
b504882d
LY		 28#include <linux/slab.h>
29#include <linux/init.h>
b504882d
LY		 30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/proc_fs.h>
33#include <linux/mm.h>
34#include <linux/moduleparam.h>
35#include <linux/device.h>
36#include <linux/usb/ch9.h>
9454a57a 37#include <linux/usb/gadget.h>
b504882d
LY		 38#include <linux/usb/otg.h>
39#include <linux/dma-mapping.h>
40#include <linux/platform_device.h>
41#include <linux/fsl_devices.h>
42#include <linux/dmapool.h>
54e4026b 43#include <linux/delay.h>
b504882d
LY		 44
45#include <asm/byteorder.h>
46#include <asm/io.h>
b504882d
LY		 47#include <asm/unaligned.h>
48#include <asm/dma.h>
b504882d
LY		 49
50#include "fsl_usb2_udc.h"
51
52#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
53#define DRIVER_AUTHOR "Li Yang/Jiang Bo"
54#define DRIVER_VERSION "Apr 20, 2007"
55
56#define DMA_ADDR_INVALID (~(dma_addr_t)0)
57
58static const char driver_name[] = "fsl-usb2-udc";
59static const char driver_desc[] = DRIVER_DESC;
60
7483cff8 61static struct usb_dr_device *dr_regs;
58c559e6 62
7483cff8 63static struct usb_sys_interface *usb_sys_regs;
b504882d
LY		 64
65/* it is initialized in probe() */
66static struct fsl_udc *udc_controller = NULL;
67
68static const struct usb_endpoint_descriptor
69fsl_ep0_desc = {
70 .bLength = USB_DT_ENDPOINT_SIZE,
71 .bDescriptorType = USB_DT_ENDPOINT,
72 .bEndpointAddress = 0,
73 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
74 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
75};
76
b504882d
LY		 77static void fsl_ep_fifo_flush(struct usb_ep *_ep);
78
79#ifdef CONFIG_PPC32
09ba0def
AG		 80/*
81 * On some SoCs, the USB controller registers can be big or little endian,
82 * depending on the version of the chip. In order to be able to run the
83 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
84 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
85 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
86 * call through those pointers. Platform code for SoCs that have BE USB
87 * registers should set pdata->big_endian_mmio flag.
88 *
89 * This also applies to controller-to-cpu accessors for the USB descriptors,
90 * since their endianness is also SoC dependant. Platform code for SoCs that
91 * have BE USB descriptors should set pdata->big_endian_desc flag.
92 */
93static u32 _fsl_readl_be(const unsigned __iomem *p)
94{
95 return in_be32(p);
96}
97
98static u32 _fsl_readl_le(const unsigned __iomem *p)
99{
100 return in_le32(p);
101}
102
103static void _fsl_writel_be(u32 v, unsigned __iomem *p)
104{
105 out_be32(p, v);
106}
107
108static void _fsl_writel_le(u32 v, unsigned __iomem *p)
109{
110 out_le32(p, v);
111}
112
113static u32 (*_fsl_readl)(const unsigned __iomem *p);
114static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
115
116#define fsl_readl(p) (*_fsl_readl)((p))
117#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
118
3140d5b2
AG		 119static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
120{
121 if (pdata->big_endian_mmio) {
122 _fsl_readl = _fsl_readl_be;
123 _fsl_writel = _fsl_writel_be;
124 } else {
125 _fsl_readl = _fsl_readl_le;
126 _fsl_writel = _fsl_writel_le;
127 }
128}
129
09ba0def
AG		 130static inline u32 cpu_to_hc32(const u32 x)
131{
132 return udc_controller->pdata->big_endian_desc
133 ? (__force u32)cpu_to_be32(x)
134 : (__force u32)cpu_to_le32(x);
135}
136
137static inline u32 hc32_to_cpu(const u32 x)
138{
139 return udc_controller->pdata->big_endian_desc
140 ? be32_to_cpu((__force __be32)x)
141 : le32_to_cpu((__force __le32)x);
142}
143#else /* !CONFIG_PPC32 */
3140d5b2
AG		 144static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
145
b504882d 146#define fsl_readl(addr) readl(addr)
c93eebbe 147#define fsl_writel(val32, addr) writel(val32, addr)
09ba0def
AG		 148#define cpu_to_hc32(x) cpu_to_le32(x)
149#define hc32_to_cpu(x) le32_to_cpu(x)
150#endif /* CONFIG_PPC32 */
b504882d
LY		 151
152/********************************************************************
153 * Internal Used Function
154********************************************************************/
155/*-----------------------------------------------------------------
156 * done() - retire a request; caller blocked irqs
157 * @status : request status to be set, only works when
158 * request is still in progress.
159 *--------------------------------------------------------------*/
160static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
161{
162 struct fsl_udc *udc = NULL;
163 unsigned char stopped = ep->stopped;
164 struct ep_td_struct *curr_td, *next_td;
165 int j;
166
167 udc = (struct fsl_udc *)ep->udc;
168 /* Removed the req from fsl_ep->queue */
169 list_del_init(&req->queue);
170
171 /* req.status should be set as -EINPROGRESS in ep_queue() */
172 if (req->req.status == -EINPROGRESS)
173 req->req.status = status;
174 else
175 status = req->req.status;
176
177 /* Free dtd for the request */
178 next_td = req->head;
179 for (j = 0; j < req->dtd_count; j++) {
180 curr_td = next_td;
181 if (j != req->dtd_count - 1) {
182 next_td = curr_td->next_td_virt;
183 }
184 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
185 }
186
187 if (req->mapped) {
188 dma_unmap_single(ep->udc->gadget.dev.parent,
189 req->req.dma, req->req.length,
190 ep_is_in(ep)
191 ? DMA_TO_DEVICE
192 : DMA_FROM_DEVICE);
193 req->req.dma = DMA_ADDR_INVALID;
194 req->mapped = 0;
195 } else
196 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
197 req->req.dma, req->req.length,
198 ep_is_in(ep)
199 ? DMA_TO_DEVICE
200 : DMA_FROM_DEVICE);
201
202 if (status && (status != -ESHUTDOWN))
203 VDBG("complete %s req %p stat %d len %u/%u",
204 ep->ep.name, &req->req, status,
205 req->req.actual, req->req.length);
206
207 ep->stopped = 1;
208
209 spin_unlock(&ep->udc->lock);
210 /* complete() is from gadget layer,
211 * eg fsg->bulk_in_complete() */
212 if (req->req.complete)
213 req->req.complete(&ep->ep, &req->req);
214
215 spin_lock(&ep->udc->lock);
216 ep->stopped = stopped;
217}
218
219/*-----------------------------------------------------------------
220 * nuke(): delete all requests related to this ep
221 * called with spinlock held
222 *--------------------------------------------------------------*/
223static void nuke(struct fsl_ep *ep, int status)
224{
225 ep->stopped = 1;
226
227 /* Flush fifo */
228 fsl_ep_fifo_flush(&ep->ep);
229
230 /* Whether this eq has request linked */
231 while (!list_empty(&ep->queue)) {
232 struct fsl_req *req = NULL;
233
234 req = list_entry(ep->queue.next, struct fsl_req, queue);
235 done(ep, req, status);
236 }
237}
238
239/*------------------------------------------------------------------
240 Internal Hardware related function
241 ------------------------------------------------------------------*/
242
243static int dr_controller_setup(struct fsl_udc *udc)
244{
ea437f39
RM		 245 unsigned int tmp, portctrl, ep_num;
246 unsigned int max_no_of_ep;
54e4026b 247 unsigned int ctrl;
b504882d 248 unsigned long timeout;
58c559e6 249
b504882d
LY		 250#define FSL_UDC_RESET_TIMEOUT 1000
251
54e4026b
GL		 252 /* Config PHY interface */
253 portctrl = fsl_readl(&dr_regs->portsc1);
254 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
255 switch (udc->phy_mode) {
256 case FSL_USB2_PHY_ULPI:
58c559e6
RM		 257 if (udc->pdata->have_sysif_regs) {
258 if (udc->pdata->controller_ver) {
259 /* controller version 1.6 or above */
260 ctrl = __raw_readl(&usb_sys_regs->control);
261 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
262 ctrl |= USB_CTRL_USB_EN;
263 __raw_writel(ctrl, &usb_sys_regs->control);
264 }
265 }
54e4026b
GL		 266 portctrl |= PORTSCX_PTS_ULPI;
267 break;
268 case FSL_USB2_PHY_UTMI_WIDE:
269 portctrl |= PORTSCX_PTW_16BIT;
270 /* fall through */
271 case FSL_USB2_PHY_UTMI:
58c559e6
RM		 272 if (udc->pdata->have_sysif_regs) {
273 if (udc->pdata->controller_ver) {
274 /* controller version 1.6 or above */
275 ctrl = __raw_readl(&usb_sys_regs->control);
276 ctrl |= (USB_CTRL_UTMI_PHY_EN |
277 USB_CTRL_USB_EN);
278 __raw_writel(ctrl, &usb_sys_regs->control);
279 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
280 PHY CLK to become stable - 10ms*/
281 }
282 }
54e4026b
GL		 283 portctrl |= PORTSCX_PTS_UTMI;
284 break;
285 case FSL_USB2_PHY_SERIAL:
286 portctrl |= PORTSCX_PTS_FSLS;
287 break;
288 default:
289 return -EINVAL;
290 }
291 fsl_writel(portctrl, &dr_regs->portsc1);
292
b504882d
LY		 293 /* Stop and reset the usb controller */
294 tmp = fsl_readl(&dr_regs->usbcmd);
295 tmp &= ~USB_CMD_RUN_STOP;
296 fsl_writel(tmp, &dr_regs->usbcmd);
297
298 tmp = fsl_readl(&dr_regs->usbcmd);
299 tmp |= USB_CMD_CTRL_RESET;
300 fsl_writel(tmp, &dr_regs->usbcmd);
301
302 /* Wait for reset to complete */
303 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
304 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
305 if (time_after(jiffies, timeout)) {
bf7409a2 306 ERR("udc reset timeout!\n");
b504882d
LY		 307 return -ETIMEDOUT;
308 }
309 cpu_relax();
310 }
311
312 /* Set the controller as device mode */
313 tmp = fsl_readl(&dr_regs->usbmode);
2ea6698d 314 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
b504882d
LY		 315 tmp |= USB_MODE_CTRL_MODE_DEVICE;
316 /* Disable Setup Lockout */
317 tmp |= USB_MODE_SETUP_LOCK_OFF;
2ea6698d
AG		 318 if (udc->pdata->es)
319 tmp |= USB_MODE_ES;
b504882d
LY		 320 fsl_writel(tmp, &dr_regs->usbmode);
321
322 /* Clear the setup status */
323 fsl_writel(0, &dr_regs->usbsts);
324
325 tmp = udc->ep_qh_dma;
326 tmp &= USB_EP_LIST_ADDRESS_MASK;
327 fsl_writel(tmp, &dr_regs->endpointlistaddr);
328
329 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
6ef65a7f 330 udc->ep_qh, (int)tmp,
b504882d
LY		 331 fsl_readl(&dr_regs->endpointlistaddr));
332
ea437f39
RM		 333 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
334 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
335 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
336 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
337 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
338 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
339 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
340 }
b504882d 341 /* Config control enable i/o output, cpu endian register */
54e4026b 342#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 343 if (udc->pdata->have_sysif_regs) {
344 ctrl = __raw_readl(&usb_sys_regs->control);
345 ctrl |= USB_CTRL_IOENB;
346 __raw_writel(ctrl, &usb_sys_regs->control);
347 }
54e4026b 348#endif
b504882d
LY		 349
350#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
351 /* Turn on cache snooping hardware, since some PowerPC platforms
352 * wholly rely on hardware to deal with cache coherent. */
353
2ea6698d
AG		 354 if (udc->pdata->have_sysif_regs) {
355 /* Setup Snooping for all the 4GB space */
356 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
357 __raw_writel(tmp, &usb_sys_regs->snoop1);
358 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
359 __raw_writel(tmp, &usb_sys_regs->snoop2);
360 }
b504882d
LY		 361#endif
362
363 return 0;
364}
365
366/* Enable DR irq and set controller to run state */
367static void dr_controller_run(struct fsl_udc *udc)
368{
369 u32 temp;
370
371 /* Enable DR irq reg */
372 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
373 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
374 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
375
376 fsl_writel(temp, &dr_regs->usbintr);
377
378 /* Clear stopped bit */
379 udc->stopped = 0;
380
381 /* Set the controller as device mode */
382 temp = fsl_readl(&dr_regs->usbmode);
383 temp |= USB_MODE_CTRL_MODE_DEVICE;
384 fsl_writel(temp, &dr_regs->usbmode);
385
386 /* Set controller to Run */
387 temp = fsl_readl(&dr_regs->usbcmd);
388 temp |= USB_CMD_RUN_STOP;
389 fsl_writel(temp, &dr_regs->usbcmd);
b504882d
LY		 390}
391
392static void dr_controller_stop(struct fsl_udc *udc)
393{
394 unsigned int tmp;
395
83722bc9
AG		 396 pr_debug("%s\n", __func__);
397
398 /* if we're in OTG mode, and the Host is currently using the port,
399 * stop now and don't rip the controller out from under the
400 * ehci driver
401 */
402 if (udc->gadget.is_otg) {
403 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
404 pr_debug("udc: Leaving early\n");
405 return;
406 }
407 }
408
b504882d
LY		 409 /* disable all INTR */
410 fsl_writel(0, &dr_regs->usbintr);
411
412 /* Set stopped bit for isr */
413 udc->stopped = 1;
414
415 /* disable IO output */
416/* usb_sys_regs->control = 0; */
417
418 /* set controller to Stop */
419 tmp = fsl_readl(&dr_regs->usbcmd);
420 tmp &= ~USB_CMD_RUN_STOP;
421 fsl_writel(tmp, &dr_regs->usbcmd);
b504882d
LY		 422}
423
9c94155e
WN		 424static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
425 unsigned char ep_type)
b504882d
LY		 426{
427 unsigned int tmp_epctrl = 0;
428
429 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
430 if (dir) {
431 if (ep_num)
432 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
433 tmp_epctrl |= EPCTRL_TX_ENABLE;
ea437f39 434 tmp_epctrl &= ~EPCTRL_TX_TYPE;
b504882d
LY		 435 tmp_epctrl |= ((unsigned int)(ep_type)
436 << EPCTRL_TX_EP_TYPE_SHIFT);
437 } else {
438 if (ep_num)
439 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
440 tmp_epctrl |= EPCTRL_RX_ENABLE;
ea437f39 441 tmp_epctrl &= ~EPCTRL_RX_TYPE;
b504882d
LY		 442 tmp_epctrl |= ((unsigned int)(ep_type)
443 << EPCTRL_RX_EP_TYPE_SHIFT);
444 }
445
446 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
447}
448
449static void
450dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
451{
452 u32 tmp_epctrl = 0;
453
454 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
455
456 if (value) {
457 /* set the stall bit */
458 if (dir)
459 tmp_epctrl |= EPCTRL_TX_EP_STALL;
460 else
461 tmp_epctrl |= EPCTRL_RX_EP_STALL;
462 } else {
463 /* clear the stall bit and reset data toggle */
464 if (dir) {
465 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
466 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
467 } else {
468 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
469 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
470 }
471 }
472 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
473}
474
475/* Get stall status of a specific ep
476 Return: 0: not stalled; 1:stalled */
477static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
478{
479 u32 epctrl;
480
481 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
482 if (dir)
483 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
484 else
485 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
486}
487
488/********************************************************************
489 Internal Structure Build up functions
490********************************************************************/
491
492/*------------------------------------------------------------------
493* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
494 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
495 * @mult: Mult field
496 ------------------------------------------------------------------*/
497static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
498 unsigned char dir, unsigned char ep_type,
499 unsigned int max_pkt_len,
500 unsigned int zlt, unsigned char mult)
501{
502 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
503 unsigned int tmp = 0;
504
505 /* set the Endpoint Capabilites in QH */
506 switch (ep_type) {
507 case USB_ENDPOINT_XFER_CONTROL:
508 /* Interrupt On Setup (IOS). for control ep */
509 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
510 | EP_QUEUE_HEAD_IOS;
511 break;
512 case USB_ENDPOINT_XFER_ISOC:
513 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
514 | (mult << EP_QUEUE_HEAD_MULT_POS);
515 break;
516 case USB_ENDPOINT_XFER_BULK:
517 case USB_ENDPOINT_XFER_INT:
518 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
519 break;
520 default:
521 VDBG("error ep type is %d", ep_type);
522 return;
523 }
524 if (zlt)
525 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
9a6e184c 526
09ba0def 527 p_QH->max_pkt_length = cpu_to_hc32(tmp);
9a6e184c
LY		 528 p_QH->next_dtd_ptr = 1;
529 p_QH->size_ioc_int_sts = 0;
b504882d
LY		 530}
531
532/* Setup qh structure and ep register for ep0. */
533static void ep0_setup(struct fsl_udc *udc)
534{
535 /* the intialization of an ep includes: fields in QH, Regs,
536 * fsl_ep struct */
537 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
538 USB_MAX_CTRL_PAYLOAD, 0, 0);
539 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
540 USB_MAX_CTRL_PAYLOAD, 0, 0);
541 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
542 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
543
544 return;
545
546}
547
548/***********************************************************************
549 Endpoint Management Functions
550***********************************************************************/
551
552/*-------------------------------------------------------------------------
553 * when configurations are set, or when interface settings change
554 * for example the do_set_interface() in gadget layer,
555 * the driver will enable or disable the relevant endpoints
556 * ep0 doesn't use this routine. It is always enabled.
557-------------------------------------------------------------------------*/
558static int fsl_ep_enable(struct usb_ep *_ep,
559 const struct usb_endpoint_descriptor *desc)
560{
561 struct fsl_udc *udc = NULL;
562 struct fsl_ep *ep = NULL;
563 unsigned short max = 0;
564 unsigned char mult = 0, zlt;
565 int retval = -EINVAL;
566 unsigned long flags = 0;
567
568 ep = container_of(_ep, struct fsl_ep, ep);
569
570 /* catch various bogus parameters */
1fa75972 571 if (!_ep || !desc
b504882d
LY		 572 || (desc->bDescriptorType != USB_DT_ENDPOINT))
573 return -EINVAL;
574
575 udc = ep->udc;
576
577 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
578 return -ESHUTDOWN;
579
29cc8897 580 max = usb_endpoint_maxp(desc);
b504882d 581
25985edc 582 /* Disable automatic zlp generation. Driver is responsible to indicate
b504882d
LY		 583 * explicitly through req->req.zero. This is needed to enable multi-td
584 * request. */
585 zlt = 1;
586
587 /* Assume the max packet size from gadget is always correct */
588 switch (desc->bmAttributes & 0x03) {
589 case USB_ENDPOINT_XFER_CONTROL:
590 case USB_ENDPOINT_XFER_BULK:
591 case USB_ENDPOINT_XFER_INT:
592 /* mult = 0. Execute N Transactions as demonstrated by
593 * the USB variable length packet protocol where N is
594 * computed using the Maximum Packet Length (dQH) and
595 * the Total Bytes field (dTD) */
596 mult = 0;
597 break;
598 case USB_ENDPOINT_XFER_ISOC:
599 /* Calculate transactions needed for high bandwidth iso */
600 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
88e3b59b 601 max = max & 0x7ff; /* bit 0~10 */
b504882d
LY		 602 /* 3 transactions at most */
603 if (mult > 3)
604 goto en_done;
605 break;
606 default:
607 goto en_done;
608 }
609
610 spin_lock_irqsave(&udc->lock, flags);
611 ep->ep.maxpacket = max;
79149b8b 612 ep->ep.desc = desc;
b504882d
LY		 613 ep->stopped = 0;
614
615 /* Controller related setup */
616 /* Init EPx Queue Head (Ep Capabilites field in QH
617 * according to max, zlt, mult) */
618 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
619 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
620 ? USB_SEND : USB_RECV),
621 (unsigned char) (desc->bmAttributes
622 & USB_ENDPOINT_XFERTYPE_MASK),
623 max, zlt, mult);
624
625 /* Init endpoint ctrl register */
626 dr_ep_setup((unsigned char) ep_index(ep),
627 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
628 ? USB_SEND : USB_RECV),
629 (unsigned char) (desc->bmAttributes
630 & USB_ENDPOINT_XFERTYPE_MASK));
631
632 spin_unlock_irqrestore(&udc->lock, flags);
633 retval = 0;
634
635 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
79149b8b 636 ep->ep.desc->bEndpointAddress & 0x0f,
b504882d
LY		 637 (desc->bEndpointAddress & USB_DIR_IN)
638 ? "in" : "out", max);
639en_done:
640 return retval;
641}
642
643/*---------------------------------------------------------------------
644 * @ep : the ep being unconfigured. May not be ep0
645 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
646*---------------------------------------------------------------------*/
647static int fsl_ep_disable(struct usb_ep *_ep)
648{
649 struct fsl_udc *udc = NULL;
650 struct fsl_ep *ep = NULL;
651 unsigned long flags = 0;
652 u32 epctrl;
653 int ep_num;
654
655 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 656 if (!_ep || !ep->ep.desc) {
b504882d
LY		 657 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
658 return -EINVAL;
659 }
660
661 /* disable ep on controller */
662 ep_num = ep_index(ep);
663 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
ea437f39
RM		 664 if (ep_is_in(ep)) {
665 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
666 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
667 } else {
668 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
669 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
670 }
b504882d
LY		 671 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
672
673 udc = (struct fsl_udc *)ep->udc;
674 spin_lock_irqsave(&udc->lock, flags);
675
676 /* nuke all pending requests (does flush) */
677 nuke(ep, -ESHUTDOWN);
678
f9c56cdd 679 ep->ep.desc = NULL;
b504882d
LY		 680 ep->stopped = 1;
681 spin_unlock_irqrestore(&udc->lock, flags);
682
683 VDBG("disabled %s OK", _ep->name);
684 return 0;
685}
686
687/*---------------------------------------------------------------------
688 * allocate a request object used by this endpoint
689 * the main operation is to insert the req->queue to the eq->queue
690 * Returns the request, or null if one could not be allocated
691*---------------------------------------------------------------------*/
692static struct usb_request *
693fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
694{
695 struct fsl_req *req = NULL;
696
697 req = kzalloc(sizeof *req, gfp_flags);
698 if (!req)
699 return NULL;
700
701 req->req.dma = DMA_ADDR_INVALID;
702 INIT_LIST_HEAD(&req->queue);
703
704 return &req->req;
705}
706
707static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
708{
709 struct fsl_req *req = NULL;
710
711 req = container_of(_req, struct fsl_req, req);
712
713 if (_req)
714 kfree(req);
715}
716
6414e94c
LY		 717/* Actually add a dTD chain to an empty dQH and let go */
718static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
719{
720 struct ep_queue_head *qh = get_qh_by_ep(ep);
721
722 /* Write dQH next pointer and terminate bit to 0 */
723 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
724 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
725
726 /* Clear active and halt bit */
727 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
728 | EP_QUEUE_HEAD_STATUS_HALT));
729
730 /* Ensure that updates to the QH will occur before priming. */
731 wmb();
732
733 /* Prime endpoint by writing correct bit to ENDPTPRIME */
734 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
735 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
736}
737
738/* Add dTD chain to the dQH of an EP */
224b5039 739static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
b504882d 740{
b504882d 741 u32 temp, bitmask, tmp_stat;
b504882d
LY		 742
743 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
744 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
745
746 bitmask = ep_is_in(ep)
747 ? (1 << (ep_index(ep) + 16))
748 : (1 << (ep_index(ep)));
749
750 /* check if the pipe is empty */
f79a60b8 751 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
b504882d
LY		 752 /* Add td to the end */
753 struct fsl_req *lastreq;
754 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
755 lastreq->tail->next_td_ptr =
09ba0def 756 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
4d0947de
PC		 757 /* Ensure dTD's next dtd pointer to be updated */
758 wmb();
b504882d
LY		 759 /* Read prime bit, if 1 goto done */
760 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
6414e94c 761 return;
b504882d
LY		 762
763 do {
764 /* Set ATDTW bit in USBCMD */
765 temp = fsl_readl(&dr_regs->usbcmd);
766 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
767
768 /* Read correct status bit */
769 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
770
771 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
772
773 /* Write ATDTW bit to 0 */
774 temp = fsl_readl(&dr_regs->usbcmd);
775 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
776
777 if (tmp_stat)
6414e94c 778 return;
b504882d
LY		 779 }
780
6414e94c 781 fsl_prime_ep(ep, req->head);
b504882d
LY		 782}
783
784/* Fill in the dTD structure
785 * @req: request that the transfer belongs to
786 * @length: return actually data length of the dTD
787 * @dma: return dma address of the dTD
788 * @is_last: return flag if it is the last dTD of the request
789 * return: pointer to the built dTD */
790static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
c5cc5ed8 791 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
b504882d
LY		 792{
793 u32 swap_temp;
794 struct ep_td_struct *dtd;
795
796 /* how big will this transfer be? */
797 *length = min(req->req.length - req->req.actual,
798 (unsigned)EP_MAX_LENGTH_TRANSFER);
799
c5cc5ed8 800 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
b504882d
LY		 801 if (dtd == NULL)
802 return dtd;
803
804 dtd->td_dma = *dma;
805 /* Clear reserved field */
09ba0def 806 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
b504882d 807 swap_temp &= ~DTD_RESERVED_FIELDS;
09ba0def 808 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 809
810 /* Init all of buffer page pointers */
811 swap_temp = (u32) (req->req.dma + req->req.actual);
09ba0def
AG		 812 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
813 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
814 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
815 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
816 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
b504882d
LY		 817
818 req->req.actual += *length;
819
820 /* zlp is needed if req->req.zero is set */
821 if (req->req.zero) {
822 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
823 *is_last = 1;
824 else
825 *is_last = 0;
826 } else if (req->req.length == req->req.actual)
827 *is_last = 1;
828 else
829 *is_last = 0;
830
831 if ((*is_last) == 0)
bf7409a2 832 VDBG("multi-dtd request!");
b504882d
LY		 833 /* Fill in the transfer size; set active bit */
834 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
835
836 /* Enable interrupt for the last dtd of a request */
837 if (*is_last && !req->req.no_interrupt)
838 swap_temp |= DTD_IOC;
839
09ba0def 840 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 841
842 mb();
843
844 VDBG("length = %d address= 0x%x", *length, (int)*dma);
845
846 return dtd;
847}
848
849/* Generate dtd chain for a request */
c5cc5ed8 850static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
b504882d
LY		 851{
852 unsigned count;
853 int is_last;
854 int is_first =1;
855 struct ep_td_struct *last_dtd = NULL, *dtd;
856 dma_addr_t dma;
857
858 do {
c5cc5ed8 859 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
b504882d
LY		 860 if (dtd == NULL)
861 return -ENOMEM;
862
863 if (is_first) {
864 is_first = 0;
865 req->head = dtd;
866 } else {
09ba0def 867 last_dtd->next_td_ptr = cpu_to_hc32(dma);
b504882d
LY		 868 last_dtd->next_td_virt = dtd;
869 }
870 last_dtd = dtd;
871
872 req->dtd_count++;
873 } while (!is_last);
874
09ba0def 875 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
b504882d
LY		 876
877 req->tail = dtd;
878
879 return 0;
880}
881
882/* queues (submits) an I/O request to an endpoint */
883static int
884fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
885{
886 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
887 struct fsl_req *req = container_of(_req, struct fsl_req, req);
888 struct fsl_udc *udc;
889 unsigned long flags;
b504882d
LY		 890
891 /* catch various bogus parameters */
892 if (!_req || !req->req.complete || !req->req.buf
893 || !list_empty(&req->queue)) {
bf7409a2 894 VDBG("%s, bad params", __func__);
b504882d
LY		 895 return -EINVAL;
896 }
79149b8b 897 if (unlikely(!_ep || !ep->ep.desc)) {
bf7409a2 898 VDBG("%s, bad ep", __func__);
b504882d
LY		 899 return -EINVAL;
900 }
79149b8b 901 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
b504882d
LY		 902 if (req->req.length > ep->ep.maxpacket)
903 return -EMSGSIZE;
b504882d
LY		 904 }
905
906 udc = ep->udc;
907 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
908 return -ESHUTDOWN;
909
910 req->ep = ep;
911
912 /* map virtual address to hardware */
913 if (req->req.dma == DMA_ADDR_INVALID) {
914 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
915 req->req.buf,
916 req->req.length, ep_is_in(ep)
917 ? DMA_TO_DEVICE
918 : DMA_FROM_DEVICE);
919 req->mapped = 1;
920 } else {
921 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
922 req->req.dma, req->req.length,
923 ep_is_in(ep)
924 ? DMA_TO_DEVICE
925 : DMA_FROM_DEVICE);
926 req->mapped = 0;
927 }
928
929 req->req.status = -EINPROGRESS;
930 req->req.actual = 0;
931 req->dtd_count = 0;
932
b504882d 933 /* build dtds and push them to device queue */
c5cc5ed8
PC		 934 if (!fsl_req_to_dtd(req, gfp_flags)) {
935 spin_lock_irqsave(&udc->lock, flags);
b504882d
LY		 936 fsl_queue_td(ep, req);
937 } else {
b504882d
LY		 938 return -ENOMEM;
939 }
940
b504882d
LY		 941 /* irq handler advances the queue */
942 if (req != NULL)
943 list_add_tail(&req->queue, &ep->queue);
944 spin_unlock_irqrestore(&udc->lock, flags);
945
946 return 0;
947}
948
949/* dequeues (cancels, unlinks) an I/O request from an endpoint */
950static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
951{
952 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
953 struct fsl_req *req;
954 unsigned long flags;
955 int ep_num, stopped, ret = 0;
956 u32 epctrl;
957
958 if (!_ep || !_req)
959 return -EINVAL;
960
961 spin_lock_irqsave(&ep->udc->lock, flags);
962 stopped = ep->stopped;
963
964 /* Stop the ep before we deal with the queue */
965 ep->stopped = 1;
966 ep_num = ep_index(ep);
967 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
968 if (ep_is_in(ep))
969 epctrl &= ~EPCTRL_TX_ENABLE;
970 else
971 epctrl &= ~EPCTRL_RX_ENABLE;
972 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
973
974 /* make sure it's actually queued on this endpoint */
975 list_for_each_entry(req, &ep->queue, queue) {
976 if (&req->req == _req)
977 break;
978 }
979 if (&req->req != _req) {
980 ret = -EINVAL;
981 goto out;
982 }
983
984 /* The request is in progress, or completed but not dequeued */
985 if (ep->queue.next == &req->queue) {
986 _req->status = -ECONNRESET;
987 fsl_ep_fifo_flush(_ep); /* flush current transfer */
988
989 /* The request isn't the last request in this ep queue */
990 if (req->queue.next != &ep->queue) {
b504882d
LY		 991 struct fsl_req *next_req;
992
b504882d
LY		 993 next_req = list_entry(req->queue.next, struct fsl_req,
994 queue);
995
6414e94c
LY		 996 /* prime with dTD of next request */
997 fsl_prime_ep(ep, next_req->head);
b504882d 998 }
6414e94c 999 /* The request hasn't been processed, patch up the TD chain */
b504882d
LY		 1000 } else {
1001 struct fsl_req *prev_req;
1002
1003 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
6414e94c 1004 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
b504882d
LY		 1005 }
1006
1007 done(ep, req, -ECONNRESET);
1008
1009 /* Enable EP */
1010out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1011 if (ep_is_in(ep))
1012 epctrl |= EPCTRL_TX_ENABLE;
1013 else
1014 epctrl |= EPCTRL_RX_ENABLE;
1015 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1016 ep->stopped = stopped;
1017
1018 spin_unlock_irqrestore(&ep->udc->lock, flags);
1019 return ret;
1020}
1021
1022/*-------------------------------------------------------------------------*/
1023
1024/*-----------------------------------------------------------------
1025 * modify the endpoint halt feature
1026 * @ep: the non-isochronous endpoint being stalled
1027 * @value: 1--set halt 0--clear halt
1028 * Returns zero, or a negative error code.
1029*----------------------------------------------------------------*/
1030static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1031{
1032 struct fsl_ep *ep = NULL;
1033 unsigned long flags = 0;
1034 int status = -EOPNOTSUPP; /* operation not supported */
1035 unsigned char ep_dir = 0, ep_num = 0;
1036 struct fsl_udc *udc = NULL;
1037
1038 ep = container_of(_ep, struct fsl_ep, ep);
1039 udc = ep->udc;
79149b8b 1040 if (!_ep || !ep->ep.desc) {
b504882d
LY		 1041 status = -EINVAL;
1042 goto out;
1043 }
1044
79149b8b 1045 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
b504882d
LY		 1046 status = -EOPNOTSUPP;
1047 goto out;
1048 }
1049
1050 /* Attempt to halt IN ep will fail if any transfer requests
1051 * are still queue */
1052 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1053 status = -EAGAIN;
1054 goto out;
1055 }
1056
1057 status = 0;
1058 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1059 ep_num = (unsigned char)(ep_index(ep));
1060 spin_lock_irqsave(&ep->udc->lock, flags);
1061 dr_ep_change_stall(ep_num, ep_dir, value);
1062 spin_unlock_irqrestore(&ep->udc->lock, flags);
1063
1064 if (ep_index(ep) == 0) {
1065 udc->ep0_state = WAIT_FOR_SETUP;
1066 udc->ep0_dir = 0;
1067 }
1068out:
1069 VDBG(" %s %s halt stat %d", ep->ep.name,
1070 value ? "set" : "clear", status);
1071
1072 return status;
1073}
1074
2ea6698d
AG		 1075static int fsl_ep_fifo_status(struct usb_ep *_ep)
1076{
1077 struct fsl_ep *ep;
1078 struct fsl_udc *udc;
1079 int size = 0;
1080 u32 bitmask;
6414e94c 1081 struct ep_queue_head *qh;
2ea6698d
AG		 1082
1083 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 1084 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
2ea6698d
AG		 1085 return -ENODEV;
1086
1087 udc = (struct fsl_udc *)ep->udc;
1088
1089 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1090 return -ESHUTDOWN;
1091
6414e94c 1092 qh = get_qh_by_ep(ep);
2ea6698d
AG		 1093
1094 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1095 (1 << (ep_index(ep)));
1096
1097 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
6414e94c 1098 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
2ea6698d
AG		 1099 >> DTD_LENGTH_BIT_POS;
1100
1101 pr_debug("%s %u\n", __func__, size);
1102 return size;
1103}
1104
b504882d
LY		 1105static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1106{
1107 struct fsl_ep *ep;
1108 int ep_num, ep_dir;
1109 u32 bits;
1110 unsigned long timeout;
1111#define FSL_UDC_FLUSH_TIMEOUT 1000
1112
1113 if (!_ep) {
1114 return;
1115 } else {
1116 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 1117 if (!ep->ep.desc)
b504882d
LY		 1118 return;
1119 }
1120 ep_num = ep_index(ep);
1121 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1122
1123 if (ep_num == 0)
1124 bits = (1 << 16) | 1;
1125 else if (ep_dir == USB_SEND)
1126 bits = 1 << (16 + ep_num);
1127 else
1128 bits = 1 << ep_num;
1129
1130 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1131 do {
1132 fsl_writel(bits, &dr_regs->endptflush);
1133
1134 /* Wait until flush complete */
1135 while (fsl_readl(&dr_regs->endptflush)) {
1136 if (time_after(jiffies, timeout)) {
1137 ERR("ep flush timeout\n");
1138 return;
1139 }
1140 cpu_relax();
1141 }
1142 /* See if we need to flush again */
1143 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1144}
1145
1146static struct usb_ep_ops fsl_ep_ops = {
1147 .enable = fsl_ep_enable,
1148 .disable = fsl_ep_disable,
1149
1150 .alloc_request = fsl_alloc_request,
1151 .free_request = fsl_free_request,
1152
b504882d
LY		 1153 .queue = fsl_ep_queue,
1154 .dequeue = fsl_ep_dequeue,
1155
1156 .set_halt = fsl_ep_set_halt,
2ea6698d 1157 .fifo_status = fsl_ep_fifo_status,
b504882d
LY		 1158 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1159};
1160
1161/*-------------------------------------------------------------------------
1162 Gadget Driver Layer Operations
1163-------------------------------------------------------------------------*/
1164
1165/*----------------------------------------------------------------------
1166 * Get the current frame number (from DR frame_index Reg )
1167 *----------------------------------------------------------------------*/
1168static int fsl_get_frame(struct usb_gadget *gadget)
1169{
1170 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1171}
1172
1173/*-----------------------------------------------------------------------
1174 * Tries to wake up the host connected to this gadget
1175 -----------------------------------------------------------------------*/
1176static int fsl_wakeup(struct usb_gadget *gadget)
1177{
1178 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1179 u32 portsc;
1180
1181 /* Remote wakeup feature not enabled by host */
1182 if (!udc->remote_wakeup)
1183 return -ENOTSUPP;
1184
1185 portsc = fsl_readl(&dr_regs->portsc1);
1186 /* not suspended? */
1187 if (!(portsc & PORTSCX_PORT_SUSPEND))
1188 return 0;
1189 /* trigger force resume */
1190 portsc |= PORTSCX_PORT_FORCE_RESUME;
1191 fsl_writel(portsc, &dr_regs->portsc1);
1192 return 0;
1193}
1194
1195static int can_pullup(struct fsl_udc *udc)
1196{
1197 return udc->driver && udc->softconnect && udc->vbus_active;
1198}
1199
1200/* Notify controller that VBUS is powered, Called by whatever
1201 detects VBUS sessions */
1202static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1203{
1204 struct fsl_udc *udc;
1205 unsigned long flags;
1206
1207 udc = container_of(gadget, struct fsl_udc, gadget);
1208 spin_lock_irqsave(&udc->lock, flags);
bf7409a2 1209 VDBG("VBUS %s", is_active ? "on" : "off");
b504882d
LY		 1210 udc->vbus_active = (is_active != 0);
1211 if (can_pullup(udc))
1212 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1213 &dr_regs->usbcmd);
1214 else
1215 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1216 &dr_regs->usbcmd);
1217 spin_unlock_irqrestore(&udc->lock, flags);
1218 return 0;
1219}
1220
1221/* constrain controller's VBUS power usage
1222 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1223 * reporting how much power the device may consume. For example, this
1224 * could affect how quickly batteries are recharged.
1225 *
1226 * Returns zero on success, else negative errno.
1227 */
1228static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1229{
b504882d
LY		 1230 struct fsl_udc *udc;
1231
1232 udc = container_of(gadget, struct fsl_udc, gadget);
ded017ee 1233 if (!IS_ERR_OR_NULL(udc->transceiver))
b96d3b08 1234 return usb_phy_set_power(udc->transceiver, mA);
b504882d
LY		 1235 return -ENOTSUPP;
1236}
1237
1238/* Change Data+ pullup status
1239 * this func is used by usb_gadget_connect/disconnet
1240 */
1241static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1242{
1243 struct fsl_udc *udc;
1244
1245 udc = container_of(gadget, struct fsl_udc, gadget);
1246 udc->softconnect = (is_on != 0);
1247 if (can_pullup(udc))
1248 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1249 &dr_regs->usbcmd);
1250 else
1251 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1252 &dr_regs->usbcmd);
1253
1254 return 0;
1255}
1256
eb65796e
FB		 1257static int fsl_udc_start(struct usb_gadget *g,
1258 struct usb_gadget_driver *driver);
1259static int fsl_udc_stop(struct usb_gadget *g,
1260 struct usb_gadget_driver *driver);
9454a57a 1261/* defined in gadget.h */
b504882d
LY		 1262static struct usb_gadget_ops fsl_gadget_ops = {
1263 .get_frame = fsl_get_frame,
1264 .wakeup = fsl_wakeup,
1265/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1266 .vbus_session = fsl_vbus_session,
1267 .vbus_draw = fsl_vbus_draw,
1268 .pullup = fsl_pullup,
eb65796e
FB		 1269 .udc_start = fsl_udc_start,
1270 .udc_stop = fsl_udc_stop,
b504882d
LY		 1271};
1272
1273/* Set protocol stall on ep0, protocol stall will automatically be cleared
1274 on new transaction */
1275static void ep0stall(struct fsl_udc *udc)
1276{
1277 u32 tmp;
1278
1279 /* must set tx and rx to stall at the same time */
1280 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1281 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1282 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1283 udc->ep0_state = WAIT_FOR_SETUP;
1284 udc->ep0_dir = 0;
1285}
1286
1287/* Prime a status phase for ep0 */
1288static int ep0_prime_status(struct fsl_udc *udc, int direction)
1289{
1290 struct fsl_req *req = udc->status_req;
1291 struct fsl_ep *ep;
b504882d
LY		 1292
1293 if (direction == EP_DIR_IN)
1294 udc->ep0_dir = USB_DIR_IN;
1295 else
1296 udc->ep0_dir = USB_DIR_OUT;
1297
1298 ep = &udc->eps[0];
f79a60b8
PC		 1299 if (udc->ep0_state != DATA_STATE_XMIT)
1300 udc->ep0_state = WAIT_FOR_OUT_STATUS;
b504882d
LY		 1301
1302 req->ep = ep;
1303 req->req.length = 0;
1304 req->req.status = -EINPROGRESS;
1305 req->req.actual = 0;
1306 req->req.complete = NULL;
1307 req->dtd_count = 0;
1308
3140d5b2
AG		 1309 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1310 req->req.buf, req->req.length,
1311 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1312 req->mapped = 1;
1313
c5cc5ed8 1314 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
224b5039 1315 fsl_queue_td(ep, req);
b504882d
LY		 1316 else
1317 return -ENOMEM;
1318
b504882d
LY		 1319 list_add_tail(&req->queue, &ep->queue);
1320
224b5039 1321 return 0;
b504882d
LY		 1322}
1323
825bee3a 1324static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
b504882d
LY		 1325{
1326 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1327
825bee3a
WN		 1328 if (ep->name)
1329 nuke(ep, -ESHUTDOWN);
b504882d
LY		 1330}
1331
1332/*
1333 * ch9 Set address
1334 */
1335static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1336{
1337 /* Save the new address to device struct */
1338 udc->device_address = (u8) value;
1339 /* Update usb state */
1340 udc->usb_state = USB_STATE_ADDRESS;
1341 /* Status phase */
1342 if (ep0_prime_status(udc, EP_DIR_IN))
1343 ep0stall(udc);
1344}
1345
1346/*
1347 * ch9 Get status
1348 */
1349static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1350 u16 index, u16 length)
1351{
1352 u16 tmp = 0; /* Status, cpu endian */
b504882d
LY		 1353 struct fsl_req *req;
1354 struct fsl_ep *ep;
b504882d
LY		 1355
1356 ep = &udc->eps[0];
1357
1358 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1359 /* Get device status */
1360 tmp = 1 << USB_DEVICE_SELF_POWERED;
1361 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1362 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1363 /* Get interface status */
1364 /* We don't have interface information in udc driver */
1365 tmp = 0;
1366 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1367 /* Get endpoint status */
1368 struct fsl_ep *target_ep;
1369
1370 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1371
1372 /* stall if endpoint doesn't exist */
79149b8b 1373 if (!target_ep->ep.desc)
b504882d
LY		 1374 goto stall;
1375 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1376 << USB_ENDPOINT_HALT;
1377 }
1378
1379 udc->ep0_dir = USB_DIR_IN;
1380 /* Borrow the per device status_req */
1381 req = udc->status_req;
1382 /* Fill in the reqest structure */
1383 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
2ea6698d 1384
b504882d
LY		 1385 req->ep = ep;
1386 req->req.length = 2;
1387 req->req.status = -EINPROGRESS;
1388 req->req.actual = 0;
1389 req->req.complete = NULL;
1390 req->dtd_count = 0;
1391
3140d5b2
AG		 1392 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1393 req->req.buf, req->req.length,
1394 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1395 req->mapped = 1;
1396
b504882d 1397 /* prime the data phase */
c5cc5ed8 1398 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
224b5039 1399 fsl_queue_td(ep, req);
b504882d
LY		 1400 else /* no mem */
1401 goto stall;
1402
b504882d
LY		 1403 list_add_tail(&req->queue, &ep->queue);
1404 udc->ep0_state = DATA_STATE_XMIT;
f79a60b8
PC		 1405 if (ep0_prime_status(udc, EP_DIR_OUT))
1406 ep0stall(udc);
1407
b504882d
LY		 1408 return;
1409stall:
1410 ep0stall(udc);
1411}
1412
1413static void setup_received_irq(struct fsl_udc *udc,
1414 struct usb_ctrlrequest *setup)
1415{
1416 u16 wValue = le16_to_cpu(setup->wValue);
1417 u16 wIndex = le16_to_cpu(setup->wIndex);
1418 u16 wLength = le16_to_cpu(setup->wLength);
1419
1420 udc_reset_ep_queue(udc, 0);
1421
39d1f8c9 1422 /* We process some stardard setup requests here */
b504882d 1423 switch (setup->bRequest) {
b504882d 1424 case USB_REQ_GET_STATUS:
39d1f8c9
LY		 1425 /* Data+Status phase from udc */
1426 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
b504882d
LY		 1427 != (USB_DIR_IN | USB_TYPE_STANDARD))
1428 break;
1429 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
39d1f8c9 1430 return;
b504882d 1431
b504882d 1432 case USB_REQ_SET_ADDRESS:
39d1f8c9 1433 /* Status phase from udc */
b504882d
LY		 1434 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1435 | USB_RECIP_DEVICE))
1436 break;
1437 ch9setaddress(udc, wValue, wIndex, wLength);
39d1f8c9 1438 return;
b504882d 1439
b504882d
LY		 1440 case USB_REQ_CLEAR_FEATURE:
1441 case USB_REQ_SET_FEATURE:
39d1f8c9
LY		 1442 /* Status phase from udc */
1443 {
b504882d 1444 int rc = -EOPNOTSUPP;
2ea6698d 1445 u16 ptc = 0;
b504882d 1446
39d1f8c9
LY		 1447 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1448 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
b504882d
LY		 1449 int pipe = get_pipe_by_windex(wIndex);
1450 struct fsl_ep *ep;
1451
118d63f7 1452 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
b504882d
LY		 1453 break;
1454 ep = get_ep_by_pipe(udc, pipe);
1455
1456 spin_unlock(&udc->lock);
1457 rc = fsl_ep_set_halt(&ep->ep,
1458 (setup->bRequest == USB_REQ_SET_FEATURE)
1459 ? 1 : 0);
1460 spin_lock(&udc->lock);
1461
39d1f8c9
LY		 1462 } else if ((setup->bRequestType & (USB_RECIP_MASK
1463 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1464 | USB_TYPE_STANDARD)) {
b504882d
LY		 1465 /* Note: The driver has not include OTG support yet.
1466 * This will be set when OTG support is added */
2ea6698d
AG		 1467 if (wValue == USB_DEVICE_TEST_MODE)
1468 ptc = wIndex >> 8;
1469 else if (gadget_is_otg(&udc->gadget)) {
1470 if (setup->bRequest ==
1471 USB_DEVICE_B_HNP_ENABLE)
1472 udc->gadget.b_hnp_enable = 1;
1473 else if (setup->bRequest ==
1474 USB_DEVICE_A_HNP_SUPPORT)
1475 udc->gadget.a_hnp_support = 1;
1476 else if (setup->bRequest ==
1477 USB_DEVICE_A_ALT_HNP_SUPPORT)
1478 udc->gadget.a_alt_hnp_support = 1;
1479 }
b504882d 1480 rc = 0;
39d1f8c9
LY		 1481 } else
1482 break;
1483
b504882d
LY		 1484 if (rc == 0) {
1485 if (ep0_prime_status(udc, EP_DIR_IN))
1486 ep0stall(udc);
1487 }
2ea6698d
AG		 1488 if (ptc) {
1489 u32 tmp;
1490
1491 mdelay(10);
1492 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1493 fsl_writel(tmp, &dr_regs->portsc1);
1494 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1495 }
1496
39d1f8c9 1497 return;
b504882d 1498 }
b504882d 1499
39d1f8c9 1500 default:
b504882d
LY		 1501 break;
1502 }
39d1f8c9
LY		 1503
1504 /* Requests handled by gadget */
1505 if (wLength) {
1506 /* Data phase from gadget, status phase from udc */
1507 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1508 ? USB_DIR_IN : USB_DIR_OUT;
1509 spin_unlock(&udc->lock);
1510 if (udc->driver->setup(&udc->gadget,
1511 &udc->local_setup_buff) < 0)
1512 ep0stall(udc);
1513 spin_lock(&udc->lock);
1514 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1515 ? DATA_STATE_XMIT : DATA_STATE_RECV;
f79a60b8
PC		 1516 /*
1517 * If the data stage is IN, send status prime immediately.
1518 * See 2.0 Spec chapter 8.5.3.3 for detail.
1519 */
1520 if (udc->ep0_state == DATA_STATE_XMIT)
1521 if (ep0_prime_status(udc, EP_DIR_OUT))
1522 ep0stall(udc);
1523
39d1f8c9
LY		 1524 } else {
1525 /* No data phase, IN status from gadget */
1526 udc->ep0_dir = USB_DIR_IN;
1527 spin_unlock(&udc->lock);
1528 if (udc->driver->setup(&udc->gadget,
1529 &udc->local_setup_buff) < 0)
1530 ep0stall(udc);
1531 spin_lock(&udc->lock);
1532 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1533 }
b504882d
LY		 1534}
1535
1536/* Process request for Data or Status phase of ep0
1537 * prime status phase if needed */
1538static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1539 struct fsl_req *req)
1540{
1541 if (udc->usb_state == USB_STATE_ADDRESS) {
1542 /* Set the new address */
1543 u32 new_address = (u32) udc->device_address;
1544 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1545 &dr_regs->deviceaddr);
1546 }
1547
1548 done(ep0, req, 0);
1549
1550 switch (udc->ep0_state) {
1551 case DATA_STATE_XMIT:
f79a60b8
PC		 1552 /* already primed at setup_received_irq */
1553 udc->ep0_state = WAIT_FOR_OUT_STATUS;
b504882d
LY		 1554 break;
1555 case DATA_STATE_RECV:
1556 /* send status phase */
1557 if (ep0_prime_status(udc, EP_DIR_IN))
1558 ep0stall(udc);
1559 break;
1560 case WAIT_FOR_OUT_STATUS:
1561 udc->ep0_state = WAIT_FOR_SETUP;
1562 break;
1563 case WAIT_FOR_SETUP:
bf7409a2 1564 ERR("Unexpect ep0 packets\n");
b504882d
LY		 1565 break;
1566 default:
1567 ep0stall(udc);
1568 break;
1569 }
1570}
1571
1572/* Tripwire mechanism to ensure a setup packet payload is extracted without
1573 * being corrupted by another incoming setup packet */
1574static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1575{
1576 u32 temp;
1577 struct ep_queue_head *qh;
09ba0def 1578 struct fsl_usb2_platform_data *pdata = udc->pdata;
b504882d
LY		 1579
1580 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1581
1582 /* Clear bit in ENDPTSETUPSTAT */
1583 temp = fsl_readl(&dr_regs->endptsetupstat);
1584 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1585
1586 /* while a hazard exists when setup package arrives */
1587 do {
1588 /* Set Setup Tripwire */
1589 temp = fsl_readl(&dr_regs->usbcmd);
1590 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1591
1592 /* Copy the setup packet to local buffer */
09ba0def
AG		 1593 if (pdata->le_setup_buf) {
1594 u32 *p = (u32 *)buffer_ptr;
1595 u32 *s = (u32 *)qh->setup_buffer;
1596
1597 /* Convert little endian setup buffer to CPU endian */
1598 *p++ = le32_to_cpu(*s++);
1599 *p = le32_to_cpu(*s);
1600 } else {
1601 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1602 }
b504882d
LY		 1603 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1604
1605 /* Clear Setup Tripwire */
1606 temp = fsl_readl(&dr_regs->usbcmd);
1607 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1608}
1609
1610/* process-ep_req(): free the completed Tds for this req */
1611static int process_ep_req(struct fsl_udc *udc, int pipe,
1612 struct fsl_req *curr_req)
1613{
1614 struct ep_td_struct *curr_td;
1615 int td_complete, actual, remaining_length, j, tmp;
1616 int status = 0;
1617 int errors = 0;
1618 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1619 int direction = pipe % 2;
1620
1621 curr_td = curr_req->head;
1622 td_complete = 0;
1623 actual = curr_req->req.length;
1624
1625 for (j = 0; j < curr_req->dtd_count; j++) {
09ba0def 1626 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1627 & DTD_PACKET_SIZE)
1628 >> DTD_LENGTH_BIT_POS;
1629 actual -= remaining_length;
1630
09ba0def
AG		 1631 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1632 if (errors & DTD_ERROR_MASK) {
b504882d
LY		 1633 if (errors & DTD_STATUS_HALTED) {
1634 ERR("dTD error %08x QH=%d\n", errors, pipe);
1635 /* Clear the errors and Halt condition */
09ba0def 1636 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
b504882d 1637 tmp &= ~errors;
09ba0def 1638 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
b504882d
LY		 1639 status = -EPIPE;
1640 /* FIXME: continue with next queued TD? */
1641
1642 break;
1643 }
1644 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1645 VDBG("Transfer overflow");
1646 status = -EPROTO;
1647 break;
1648 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1649 VDBG("ISO error");
1650 status = -EILSEQ;
1651 break;
1652 } else
25985edc 1653 ERR("Unknown error has occurred (0x%x)!\n",
b504882d
LY		 1654 errors);
1655
09ba0def 1656 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1657 & DTD_STATUS_ACTIVE) {
1658 VDBG("Request not complete");
1659 status = REQ_UNCOMPLETE;
1660 return status;
1661 } else if (remaining_length) {
1662 if (direction) {
1663 VDBG("Transmit dTD remaining length not zero");
1664 status = -EPROTO;
1665 break;
1666 } else {
1667 td_complete++;
1668 break;
1669 }
1670 } else {
1671 td_complete++;
bf7409a2 1672 VDBG("dTD transmitted successful");
b504882d
LY		 1673 }
1674
1675 if (j != curr_req->dtd_count - 1)
1676 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1677 }
1678
1679 if (status)
1680 return status;
1681
1682 curr_req->req.actual = actual;
1683
1684 return 0;
1685}
1686
1687/* Process a DTD completion interrupt */
1688static void dtd_complete_irq(struct fsl_udc *udc)
1689{
1690 u32 bit_pos;
1691 int i, ep_num, direction, bit_mask, status;
1692 struct fsl_ep *curr_ep;
1693 struct fsl_req *curr_req, *temp_req;
1694
1695 /* Clear the bits in the register */
1696 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1697 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1698
1699 if (!bit_pos)
1700 return;
1701
118d63f7 1702 for (i = 0; i < udc->max_ep; i++) {
b504882d
LY		 1703 ep_num = i >> 1;
1704 direction = i % 2;
1705
1706 bit_mask = 1 << (ep_num + 16 * direction);
1707
1708 if (!(bit_pos & bit_mask))
1709 continue;
1710
1711 curr_ep = get_ep_by_pipe(udc, i);
1712
1713 /* If the ep is configured */
1714 if (curr_ep->name == NULL) {
b6c63937 1715 WARNING("Invalid EP?");
b504882d
LY		 1716 continue;
1717 }
1718
1719 /* process the req queue until an uncomplete request */
1720 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1721 queue) {
1722 status = process_ep_req(udc, i, curr_req);
1723
1724 VDBG("status of process_ep_req= %d, ep = %d",
1725 status, ep_num);
1726 if (status == REQ_UNCOMPLETE)
1727 break;
1728 /* write back status to req */
1729 curr_req->req.status = status;
1730
1731 if (ep_num == 0) {
1732 ep0_req_complete(udc, curr_ep, curr_req);
1733 break;
1734 } else
1735 done(curr_ep, curr_req, status);
1736 }
1737 }
1738}
1739
e538dfda
MN		 1740static inline enum usb_device_speed portscx_device_speed(u32 reg)
1741{
0e042be3 1742 switch (reg & PORTSCX_PORT_SPEED_MASK) {
e538dfda
MN		 1743 case PORTSCX_PORT_SPEED_HIGH:
1744 return USB_SPEED_HIGH;
1745 case PORTSCX_PORT_SPEED_FULL:
1746 return USB_SPEED_FULL;
1747 case PORTSCX_PORT_SPEED_LOW:
1748 return USB_SPEED_LOW;
1749 default:
1750 return USB_SPEED_UNKNOWN;
1751 }
1752}
1753
b504882d
LY		 1754/* Process a port change interrupt */
1755static void port_change_irq(struct fsl_udc *udc)
1756{
83722bc9
AG		 1757 if (udc->bus_reset)
1758 udc->bus_reset = 0;
1759
b504882d 1760 /* Bus resetting is finished */
e538dfda 1761 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
b504882d 1762 /* Get the speed */
e538dfda
MN		 1763 udc->gadget.speed =
1764 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
b504882d
LY		 1765
1766 /* Update USB state */
1767 if (!udc->resume_state)
1768 udc->usb_state = USB_STATE_DEFAULT;
1769}
1770
1771/* Process suspend interrupt */
1772static void suspend_irq(struct fsl_udc *udc)
1773{
1774 udc->resume_state = udc->usb_state;
1775 udc->usb_state = USB_STATE_SUSPENDED;
1776
1777 /* report suspend to the driver, serial.c does not support this */
1778 if (udc->driver->suspend)
1779 udc->driver->suspend(&udc->gadget);
1780}
1781
1782static void bus_resume(struct fsl_udc *udc)
1783{
1784 udc->usb_state = udc->resume_state;
1785 udc->resume_state = 0;
1786
1787 /* report resume to the driver, serial.c does not support this */
1788 if (udc->driver->resume)
1789 udc->driver->resume(&udc->gadget);
1790}
1791
1792/* Clear up all ep queues */
1793static int reset_queues(struct fsl_udc *udc)
1794{
1795 u8 pipe;
1796
1797 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1798 udc_reset_ep_queue(udc, pipe);
1799
1800 /* report disconnect; the driver is already quiesced */
185e3dea 1801 spin_unlock(&udc->lock);
b504882d 1802 udc->driver->disconnect(&udc->gadget);
185e3dea 1803 spin_lock(&udc->lock);
b504882d
LY		 1804
1805 return 0;
1806}
1807
1808/* Process reset interrupt */
1809static void reset_irq(struct fsl_udc *udc)
1810{
1811 u32 temp;
1812 unsigned long timeout;
1813
1814 /* Clear the device address */
1815 temp = fsl_readl(&dr_regs->deviceaddr);
1816 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1817
1818 udc->device_address = 0;
1819
1820 /* Clear usb state */
1821 udc->resume_state = 0;
1822 udc->ep0_dir = 0;
1823 udc->ep0_state = WAIT_FOR_SETUP;
1824 udc->remote_wakeup = 0; /* default to 0 on reset */
1825 udc->gadget.b_hnp_enable = 0;
1826 udc->gadget.a_hnp_support = 0;
1827 udc->gadget.a_alt_hnp_support = 0;
1828
1829 /* Clear all the setup token semaphores */
1830 temp = fsl_readl(&dr_regs->endptsetupstat);
1831 fsl_writel(temp, &dr_regs->endptsetupstat);
1832
1833 /* Clear all the endpoint complete status bits */
1834 temp = fsl_readl(&dr_regs->endptcomplete);
1835 fsl_writel(temp, &dr_regs->endptcomplete);
1836
1837 timeout = jiffies + 100;
1838 while (fsl_readl(&dr_regs->endpointprime)) {
1839 /* Wait until all endptprime bits cleared */
1840 if (time_after(jiffies, timeout)) {
1841 ERR("Timeout for reset\n");
1842 break;
1843 }
1844 cpu_relax();
1845 }
1846
1847 /* Write 1s to the flush register */
1848 fsl_writel(0xffffffff, &dr_regs->endptflush);
1849
1850 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1851 VDBG("Bus reset");
83722bc9
AG		 1852 /* Bus is reseting */
1853 udc->bus_reset = 1;
b504882d
LY		 1854 /* Reset all the queues, include XD, dTD, EP queue
1855 * head and TR Queue */
1856 reset_queues(udc);
1857 udc->usb_state = USB_STATE_DEFAULT;
1858 } else {
1859 VDBG("Controller reset");
1860 /* initialize usb hw reg except for regs for EP, not
1861 * touch usbintr reg */
1862 dr_controller_setup(udc);
1863
1864 /* Reset all internal used Queues */
1865 reset_queues(udc);
1866
1867 ep0_setup(udc);
1868
1869 /* Enable DR IRQ reg, Set Run bit, change udc state */
1870 dr_controller_run(udc);
1871 udc->usb_state = USB_STATE_ATTACHED;
1872 }
1873}
1874
1875/*
1876 * USB device controller interrupt handler
1877 */
1878static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1879{
1880 struct fsl_udc *udc = _udc;
1881 u32 irq_src;
1882 irqreturn_t status = IRQ_NONE;
1883 unsigned long flags;
1884
1885 /* Disable ISR for OTG host mode */
1886 if (udc->stopped)
1887 return IRQ_NONE;
1888 spin_lock_irqsave(&udc->lock, flags);
1889 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1890 /* Clear notification bits */
1891 fsl_writel(irq_src, &dr_regs->usbsts);
1892
1893 /* VDBG("irq_src [0x%8x]", irq_src); */
1894
1895 /* Need to resume? */
1896 if (udc->usb_state == USB_STATE_SUSPENDED)
1897 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1898 bus_resume(udc);
1899
1900 /* USB Interrupt */
1901 if (irq_src & USB_STS_INT) {
1902 VDBG("Packet int");
1903 /* Setup package, we only support ep0 as control ep */
1904 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1905 tripwire_handler(udc, 0,
1906 (u8 *) (&udc->local_setup_buff));
1907 setup_received_irq(udc, &udc->local_setup_buff);
1908 status = IRQ_HANDLED;
1909 }
1910
1911 /* completion of dtd */
1912 if (fsl_readl(&dr_regs->endptcomplete)) {
1913 dtd_complete_irq(udc);
1914 status = IRQ_HANDLED;
1915 }
1916 }
1917
1918 /* SOF (for ISO transfer) */
1919 if (irq_src & USB_STS_SOF) {
1920 status = IRQ_HANDLED;
1921 }
1922
1923 /* Port Change */
1924 if (irq_src & USB_STS_PORT_CHANGE) {
1925 port_change_irq(udc);
1926 status = IRQ_HANDLED;
1927 }
1928
1929 /* Reset Received */
1930 if (irq_src & USB_STS_RESET) {
83722bc9 1931 VDBG("reset int");
b504882d
LY		 1932 reset_irq(udc);
1933 status = IRQ_HANDLED;
1934 }
1935
1936 /* Sleep Enable (Suspend) */
1937 if (irq_src & USB_STS_SUSPEND) {
1938 suspend_irq(udc);
1939 status = IRQ_HANDLED;
1940 }
1941
1942 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
bf7409a2 1943 VDBG("Error IRQ %x", irq_src);
b504882d
LY		 1944 }
1945
1946 spin_unlock_irqrestore(&udc->lock, flags);
1947 return status;
1948}
1949
1950/*----------------------------------------------------------------*
1951 * Hook to gadget drivers
1952 * Called by initialization code of gadget drivers
1953*----------------------------------------------------------------*/
eb65796e
FB		 1954static int fsl_udc_start(struct usb_gadget *g,
1955 struct usb_gadget_driver *driver)
b504882d 1956{
eb65796e 1957 int retval = 0;
b504882d
LY		 1958 unsigned long flags = 0;
1959
b504882d
LY		 1960 /* lock is needed but whether should use this lock or another */
1961 spin_lock_irqsave(&udc_controller->lock, flags);
1962
7483cff8 1963 driver->driver.bus = NULL;
b504882d
LY		 1964 /* hook up the driver */
1965 udc_controller->driver = driver;
1966 udc_controller->gadget.dev.driver = &driver->driver;
1967 spin_unlock_irqrestore(&udc_controller->lock, flags);
1968
ded017ee 1969 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 1970 /* Suspend the controller until OTG enable it */
1971 udc_controller->stopped = 1;
1972 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1973
1974 /* connect to bus through transceiver */
ded017ee 1975 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
6e13c650
HK		 1976 retval = otg_set_peripheral(
1977 udc_controller->transceiver->otg,
83722bc9
AG		 1978 &udc_controller->gadget);
1979 if (retval < 0) {
1980 ERR("can't bind to transceiver\n");
1981 driver->unbind(&udc_controller->gadget);
1982 udc_controller->gadget.dev.driver = 0;
1983 udc_controller->driver = 0;
1984 return retval;
1985 }
1986 }
1987 } else {
1988 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1989 dr_controller_run(udc_controller);
1990 udc_controller->usb_state = USB_STATE_ATTACHED;
1991 udc_controller->ep0_state = WAIT_FOR_SETUP;
1992 udc_controller->ep0_dir = 0;
1993 }
b504882d 1994
b504882d
LY		 1995 return retval;
1996}
b504882d
LY		 1997
1998/* Disconnect from gadget driver */
eb65796e
FB		 1999static int fsl_udc_stop(struct usb_gadget *g,
2000 struct usb_gadget_driver *driver)
b504882d
LY		 2001{
2002 struct fsl_ep *loop_ep;
2003 unsigned long flags;
2004
ded017ee 2005 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
6e13c650 2006 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
b504882d
LY		 2007
2008 /* stop DR, disable intr */
2009 dr_controller_stop(udc_controller);
2010
2011 /* in fact, no needed */
2012 udc_controller->usb_state = USB_STATE_ATTACHED;
2013 udc_controller->ep0_state = WAIT_FOR_SETUP;
2014 udc_controller->ep0_dir = 0;
2015
2016 /* stand operation */
2017 spin_lock_irqsave(&udc_controller->lock, flags);
2018 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2019 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2020 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2021 ep.ep_list)
2022 nuke(loop_ep, -ESHUTDOWN);
2023 spin_unlock_irqrestore(&udc_controller->lock, flags);
2024
7483cff8
WN		 2025 udc_controller->gadget.dev.driver = NULL;
2026 udc_controller->driver = NULL;
b504882d 2027
b504882d
LY		 2028 return 0;
2029}
b504882d
LY		 2030
2031/*-------------------------------------------------------------------------
2032 PROC File System Support
2033-------------------------------------------------------------------------*/
2034#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2035
2036#include <linux/seq_file.h>
2037
2038static const char proc_filename[] = "driver/fsl_usb2_udc";
2039
2040static int fsl_proc_read(char *page, char **start, off_t off, int count,
2041 int *eof, void *_dev)
2042{
2043 char *buf = page;
2044 char *next = buf;
2045 unsigned size = count;
2046 unsigned long flags;
2047 int t, i;
2048 u32 tmp_reg;
2049 struct fsl_ep *ep = NULL;
2050 struct fsl_req *req;
2051
2052 struct fsl_udc *udc = udc_controller;
2053 if (off != 0)
2054 return 0;
2055
2056 spin_lock_irqsave(&udc->lock, flags);
2057
dc0d5c1e 2058 /* ------basic driver information ---- */
b504882d
LY		 2059 t = scnprintf(next, size,
2060 DRIVER_DESC "\n"
2061 "%s version: %s\n"
2062 "Gadget driver: %s\n\n",
2063 driver_name, DRIVER_VERSION,
2064 udc->driver ? udc->driver->driver.name : "(none)");
2065 size -= t;
2066 next += t;
2067
2068 /* ------ DR Registers ----- */
2069 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2070 t = scnprintf(next, size,
2071 "USBCMD reg:\n"
2072 "SetupTW: %d\n"
2073 "Run/Stop: %s\n\n",
2074 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2075 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2076 size -= t;
2077 next += t;
2078
2079 tmp_reg = fsl_readl(&dr_regs->usbsts);
2080 t = scnprintf(next, size,
2081 "USB Status Reg:\n"
9d9d88c8 2082 "Dr Suspend: %d Reset Received: %d System Error: %s "
b504882d
LY		 2083 "USB Error Interrupt: %s\n\n",
2084 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2085 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2086 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2087 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2088 size -= t;
2089 next += t;
2090
2091 tmp_reg = fsl_readl(&dr_regs->usbintr);
2092 t = scnprintf(next, size,
984e833c 2093 "USB Interrupt Enable Reg:\n"
9d9d88c8 2094 "Sleep Enable: %d SOF Received Enable: %d "
b504882d 2095 "Reset Enable: %d\n"
9d9d88c8 2096 "System Error Enable: %d "
b504882d 2097 "Port Change Dectected Enable: %d\n"
9d9d88c8 2098 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
b504882d
LY		 2099 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2100 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2101 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2102 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2103 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2104 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2105 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2106 size -= t;
2107 next += t;
2108
2109 tmp_reg = fsl_readl(&dr_regs->frindex);
2110 t = scnprintf(next, size,
9d9d88c8 2111 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
b504882d
LY		 2112 (tmp_reg & USB_FRINDEX_MASKS));
2113 size -= t;
2114 next += t;
2115
2116 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2117 t = scnprintf(next, size,
9d9d88c8 2118 "USB Device Address Reg: Device Addr is 0x%x\n\n",
b504882d
LY		 2119 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2120 size -= t;
2121 next += t;
2122
2123 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2124 t = scnprintf(next, size,
9d9d88c8 2125 "USB Endpoint List Address Reg: "
b504882d
LY		 2126 "Device Addr is 0x%x\n\n",
2127 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2128 size -= t;
2129 next += t;
2130
2131 tmp_reg = fsl_readl(&dr_regs->portsc1);
2132 t = scnprintf(next, size,
2133 "USB Port Status&Control Reg:\n"
9d9d88c8
WN		 2134 "Port Transceiver Type : %s Port Speed: %s\n"
2135 "PHY Low Power Suspend: %s Port Reset: %s "
2136 "Port Suspend Mode: %s\n"
2137 "Over-current Change: %s "
b504882d 2138 "Port Enable/Disable Change: %s\n"
9d9d88c8 2139 "Port Enabled/Disabled: %s "
b504882d
LY		 2140 "Current Connect Status: %s\n\n", ( {
2141 char *s;
2142 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2143 case PORTSCX_PTS_UTMI:
2144 s = "UTMI"; break;
2145 case PORTSCX_PTS_ULPI:
2146 s = "ULPI "; break;
2147 case PORTSCX_PTS_FSLS:
2148 s = "FS/LS Serial"; break;
2149 default:
2150 s = "None"; break;
2151 }
e538dfda
MN		 2152 s;} ),
2153 usb_speed_string(portscx_device_speed(tmp_reg)),
b504882d
LY		 2154 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2155 "Normal PHY mode" : "Low power mode",
2156 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2157 "Not in Reset",
2158 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2159 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2160 "No",
2161 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2162 "Not change",
2163 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2164 "Not correct",
2165 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2166 "Attached" : "Not-Att");
2167 size -= t;
2168 next += t;
2169
2170 tmp_reg = fsl_readl(&dr_regs->usbmode);
2171 t = scnprintf(next, size,
9d9d88c8 2172 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
b504882d
LY		 2173 char *s;
2174 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2175 case USB_MODE_CTRL_MODE_IDLE:
2176 s = "Idle"; break;
2177 case USB_MODE_CTRL_MODE_DEVICE:
2178 s = "Device Controller"; break;
2179 case USB_MODE_CTRL_MODE_HOST:
2180 s = "Host Controller"; break;
2181 default:
2182 s = "None"; break;
2183 }
2184 s;
2185 } ));
2186 size -= t;
2187 next += t;
2188
2189 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2190 t = scnprintf(next, size,
9d9d88c8 2191 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
b504882d
LY		 2192 (tmp_reg & EP_SETUP_STATUS_MASK));
2193 size -= t;
2194 next += t;
2195
2196 for (i = 0; i < udc->max_ep / 2; i++) {
2197 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2198 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2199 i, tmp_reg);
2200 size -= t;
2201 next += t;
2202 }
2203 tmp_reg = fsl_readl(&dr_regs->endpointprime);
9d9d88c8 2204 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
b504882d
LY		 2205 size -= t;
2206 next += t;
2207
54e4026b 2208#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 2209 if (udc->pdata->have_sysif_regs) {
2210 tmp_reg = usb_sys_regs->snoop1;
2211 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2212 size -= t;
2213 next += t;
b504882d 2214
2ea6698d
AG		 2215 tmp_reg = usb_sys_regs->control;
2216 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2217 tmp_reg);
2218 size -= t;
2219 next += t;
2220 }
54e4026b 2221#endif
b504882d
LY		 2222
2223 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2224 ep = &udc->eps[0];
2225 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2226 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2227 size -= t;
2228 next += t;
2229
2230 if (list_empty(&ep->queue)) {
2231 t = scnprintf(next, size, "its req queue is empty\n\n");
2232 size -= t;
2233 next += t;
2234 } else {
2235 list_for_each_entry(req, &ep->queue, queue) {
2236 t = scnprintf(next, size,
9d9d88c8 2237 "req %p actual 0x%x length 0x%x buf %p\n",
b504882d
LY		 2238 &req->req, req->req.actual,
2239 req->req.length, req->req.buf);
2240 size -= t;
2241 next += t;
2242 }
2243 }
2244 /* other gadget->eplist ep */
2245 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
79149b8b 2246 if (ep->ep.desc) {
b504882d
LY		 2247 t = scnprintf(next, size,
2248 "\nFor %s Maxpkt is 0x%x "
2249 "index is 0x%x\n",
2250 ep->ep.name, ep_maxpacket(ep),
2251 ep_index(ep));
2252 size -= t;
2253 next += t;
2254
2255 if (list_empty(&ep->queue)) {
2256 t = scnprintf(next, size,
2257 "its req queue is empty\n\n");
2258 size -= t;
2259 next += t;
2260 } else {
2261 list_for_each_entry(req, &ep->queue, queue) {
2262 t = scnprintf(next, size,
9d9d88c8 2263 "req %p actual 0x%x length "
b504882d
LY		 2264 "0x%x buf %p\n",
2265 &req->req, req->req.actual,
2266 req->req.length, req->req.buf);
2267 size -= t;
2268 next += t;
2269 } /* end for each_entry of ep req */
2270 } /* end for else */
2271 } /* end for if(ep->queue) */
2272 } /* end (ep->desc) */
2273
2274 spin_unlock_irqrestore(&udc->lock, flags);
2275
2276 *eof = 1;
2277 return count - size;
2278}
2279
2280#define create_proc_file() create_proc_read_entry(proc_filename, \
2281 0, NULL, fsl_proc_read, NULL)
2282
2283#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2284
2285#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2286
2287#define create_proc_file() do {} while (0)
2288#define remove_proc_file() do {} while (0)
2289
2290#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2291
2292/*-------------------------------------------------------------------------*/
2293
2294/* Release udc structures */
2295static void fsl_udc_release(struct device *dev)
2296{
2297 complete(udc_controller->done);
37c4fd8c 2298 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
b504882d
LY		 2299 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2300 kfree(udc_controller);
2301}
2302
2303/******************************************************************
2304 Internal structure setup functions
2305*******************************************************************/
2306/*------------------------------------------------------------------
2307 * init resource for globle controller
2308 * Return the udc handle on success or NULL on failure
2309 ------------------------------------------------------------------*/
4365831d
LY		 2310static int __init struct_udc_setup(struct fsl_udc *udc,
2311 struct platform_device *pdev)
b504882d 2312{
b504882d
LY		 2313 struct fsl_usb2_platform_data *pdata;
2314 size_t size;
2315
b504882d
LY		 2316 pdata = pdev->dev.platform_data;
2317 udc->phy_mode = pdata->phy_mode;
b504882d
LY		 2318
2319 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2320 if (!udc->eps) {
2321 ERR("malloc fsl_ep failed\n");
4365831d 2322 return -1;
b504882d
LY		 2323 }
2324
2325 /* initialized QHs, take care of alignment */
2326 size = udc->max_ep * sizeof(struct ep_queue_head);
2327 if (size < QH_ALIGNMENT)
2328 size = QH_ALIGNMENT;
2329 else if ((size % QH_ALIGNMENT) != 0) {
2330 size += QH_ALIGNMENT + 1;
2331 size &= ~(QH_ALIGNMENT - 1);
2332 }
2333 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2334 &udc->ep_qh_dma, GFP_KERNEL);
2335 if (!udc->ep_qh) {
2336 ERR("malloc QHs for udc failed\n");
2337 kfree(udc->eps);
4365831d 2338 return -1;
b504882d
LY		 2339 }
2340
2341 udc->ep_qh_size = size;
2342
2343 /* Initialize ep0 status request structure */
2344 /* FIXME: fsl_alloc_request() ignores ep argument */
2345 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2346 struct fsl_req, req);
2347 /* allocate a small amount of memory to get valid address */
2348 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
b504882d
LY		 2349
2350 udc->resume_state = USB_STATE_NOTATTACHED;
2351 udc->usb_state = USB_STATE_POWERED;
2352 udc->ep0_dir = 0;
2353 udc->remote_wakeup = 0; /* default to 0 on reset */
b504882d 2354
4365831d 2355 return 0;
b504882d
LY		 2356}
2357
2358/*----------------------------------------------------------------
2359 * Setup the fsl_ep struct for eps
2360 * Link fsl_ep->ep to gadget->ep_list
2361 * ep0out is not used so do nothing here
2362 * ep0in should be taken care
2363 *--------------------------------------------------------------*/
2364static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2365 char *name, int link)
2366{
2367 struct fsl_ep *ep = &udc->eps[index];
2368
2369 ep->udc = udc;
2370 strcpy(ep->name, name);
2371 ep->ep.name = ep->name;
2372
2373 ep->ep.ops = &fsl_ep_ops;
2374 ep->stopped = 0;
2375
2376 /* for ep0: maxP defined in desc
2377 * for other eps, maxP is set by epautoconfig() called by gadget layer
2378 */
2379 ep->ep.maxpacket = (unsigned short) ~0;
2380
2381 /* the queue lists any req for this ep */
2382 INIT_LIST_HEAD(&ep->queue);
2383
2384 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2385 if (link)
2386 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2387 ep->gadget = &udc->gadget;
2388 ep->qh = &udc->ep_qh[index];
2389
2390 return 0;
2391}
2392
2393/* Driver probe function
4365831d
LY		 2394 * all intialization operations implemented here except enabling usb_intr reg
2395 * board setup should have been done in the platform code
b504882d
LY		 2396 */
2397static int __init fsl_udc_probe(struct platform_device *pdev)
2398{
09ba0def 2399 struct fsl_usb2_platform_data *pdata;
b504882d
LY		 2400 struct resource *res;
2401 int ret = -ENODEV;
2402 unsigned int i;
4365831d 2403 u32 dccparams;
b504882d
LY		 2404
2405 if (strcmp(pdev->name, driver_name)) {
bf7409a2 2406 VDBG("Wrong device");
b504882d
LY		 2407 return -ENODEV;
2408 }
2409
4365831d
LY		 2410 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2411 if (udc_controller == NULL) {
2412 ERR("malloc udc failed\n");
b504882d
LY		 2413 return -ENOMEM;
2414 }
2415
09ba0def
AG		 2416 pdata = pdev->dev.platform_data;
2417 udc_controller->pdata = pdata;
e06da9a8
WN		 2418 spin_lock_init(&udc_controller->lock);
2419 udc_controller->stopped = 1;
2420
83722bc9
AG		 2421#ifdef CONFIG_USB_OTG
2422 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
662dca54 2423 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee 2424 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 2425 ERR("Can't find OTG driver!\n");
2426 ret = -ENODEV;
2427 goto err_kfree;
2428 }
2429 }
2430#endif
2431
b504882d 2432 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4365831d 2433 if (!res) {
23d7cd04
WN		 2434 ret = -ENXIO;
2435 goto err_kfree;
4365831d 2436 }
b504882d 2437
83722bc9 2438 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
28f65c11 2439 if (!request_mem_region(res->start, resource_size(res),
83722bc9
AG		 2440 driver_name)) {
2441 ERR("request mem region for %s failed\n", pdev->name);
2442 ret = -EBUSY;
2443 goto err_kfree;
2444 }
b504882d
LY		 2445 }
2446
54e4026b 2447 dr_regs = ioremap(res->start, resource_size(res));
b504882d
LY		 2448 if (!dr_regs) {
2449 ret = -ENOMEM;
23d7cd04 2450 goto err_release_mem_region;
b504882d
LY		 2451 }
2452
2ea6698d
AG		 2453 pdata->regs = (void *)dr_regs;
2454
2455 /*
2456 * do platform specific init: check the clock, grab/config pins, etc.
2457 */
2458 if (pdata->init && pdata->init(pdev)) {
2459 ret = -ENODEV;
2460 goto err_iounmap_noclk;
2461 }
2462
2463 /* Set accessors only after pdata->init() ! */
3140d5b2 2464 fsl_set_accessors(pdata);
09ba0def 2465
54e4026b 2466#ifndef CONFIG_ARCH_MXC
2ea6698d 2467 if (pdata->have_sysif_regs)
8981d76a 2468 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
54e4026b
GL		 2469#endif
2470
2471 /* Initialize USB clocks */
2472 ret = fsl_udc_clk_init(pdev);
2473 if (ret < 0)
2474 goto err_iounmap_noclk;
b504882d 2475
4365831d
LY		 2476 /* Read Device Controller Capability Parameters register */
2477 dccparams = fsl_readl(&dr_regs->dccparams);
2478 if (!(dccparams & DCCPARAMS_DC)) {
2479 ERR("This SOC doesn't support device role\n");
2480 ret = -ENODEV;
23d7cd04 2481 goto err_iounmap;
4365831d
LY		 2482 }
2483 /* Get max device endpoints */
2484 /* DEN is bidirectional ep number, max_ep doubles the number */
2485 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2486
b504882d
LY		 2487 udc_controller->irq = platform_get_irq(pdev, 0);
2488 if (!udc_controller->irq) {
2489 ret = -ENODEV;
23d7cd04 2490 goto err_iounmap;
b504882d
LY		 2491 }
2492
37b5453d 2493 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
b504882d
LY		 2494 driver_name, udc_controller);
2495 if (ret != 0) {
bf7409a2 2496 ERR("cannot request irq %d err %d\n",
b504882d 2497 udc_controller->irq, ret);
23d7cd04 2498 goto err_iounmap;
b504882d
LY		 2499 }
2500
4365831d
LY		 2501 /* Initialize the udc structure including QH member and other member */
2502 if (struct_udc_setup(udc_controller, pdev)) {
2503 ERR("Can't initialize udc data structure\n");
2504 ret = -ENOMEM;
23d7cd04 2505 goto err_free_irq;
4365831d
LY		 2506 }
2507
ded017ee 2508 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 2509 /* initialize usb hw reg except for regs for EP,
2510 * leave usbintr reg untouched */
2511 dr_controller_setup(udc_controller);
2512 }
b504882d 2513
54e4026b
GL		 2514 fsl_udc_clk_finalize(pdev);
2515
b504882d
LY		 2516 /* Setup gadget structure */
2517 udc_controller->gadget.ops = &fsl_gadget_ops;
d327ab5b 2518 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
b504882d
LY		 2519 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2520 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2521 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2522 udc_controller->gadget.name = driver_name;
2523
2524 /* Setup gadget.dev and register with kernel */
0031a06e 2525 dev_set_name(&udc_controller->gadget.dev, "gadget");
b504882d
LY		 2526 udc_controller->gadget.dev.release = fsl_udc_release;
2527 udc_controller->gadget.dev.parent = &pdev->dev;
cb4baf10 2528 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
b504882d
LY		 2529 ret = device_register(&udc_controller->gadget.dev);
2530 if (ret < 0)
23d7cd04 2531 goto err_free_irq;
b504882d 2532
ded017ee 2533 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
83722bc9
AG		 2534 udc_controller->gadget.is_otg = 1;
2535
b504882d
LY		 2536 /* setup QH and epctrl for ep0 */
2537 ep0_setup(udc_controller);
2538
2539 /* setup udc->eps[] for ep0 */
2540 struct_ep_setup(udc_controller, 0, "ep0", 0);
2541 /* for ep0: the desc defined here;
2542 * for other eps, gadget layer called ep_enable with defined desc
2543 */
80e91fd5 2544 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
b504882d
LY		 2545 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2546
2547 /* setup the udc->eps[] for non-control endpoints and link
2548 * to gadget.ep_list */
2549 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2550 char name[14];
2551
2552 sprintf(name, "ep%dout", i);
2553 struct_ep_setup(udc_controller, i * 2, name, 1);
2554 sprintf(name, "ep%din", i);
2555 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2556 }
2557
2558 /* use dma_pool for TD management */
2559 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2560 sizeof(struct ep_td_struct),
2561 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2562 if (udc_controller->td_pool == NULL) {
2563 ret = -ENOMEM;
23d7cd04 2564 goto err_unregister;
b504882d 2565 }
0f91349b
SAS		 2566
2567 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2568 if (ret)
2569 goto err_del_udc;
2570
b504882d
LY		 2571 create_proc_file();
2572 return 0;
2573
0f91349b
SAS		 2574err_del_udc:
2575 dma_pool_destroy(udc_controller->td_pool);
23d7cd04 2576err_unregister:
b504882d 2577 device_unregister(&udc_controller->gadget.dev);
23d7cd04 2578err_free_irq:
b504882d 2579 free_irq(udc_controller->irq, udc_controller);
23d7cd04 2580err_iounmap:
2ea6698d
AG		 2581 if (pdata->exit)
2582 pdata->exit(pdev);
54e4026b
GL		 2583 fsl_udc_clk_release();
2584err_iounmap_noclk:
b504882d 2585 iounmap(dr_regs);
23d7cd04 2586err_release_mem_region:
83722bc9 2587 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2588 release_mem_region(res->start, resource_size(res));
23d7cd04 2589err_kfree:
4365831d 2590 kfree(udc_controller);
23d7cd04 2591 udc_controller = NULL;
b504882d
LY		 2592 return ret;
2593}
2594
2595/* Driver removal function
2596 * Free resources and finish pending transactions
2597 */
2598static int __exit fsl_udc_remove(struct platform_device *pdev)
2599{
2600 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2ea6698d 2601 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
b504882d
LY		 2602
2603 DECLARE_COMPLETION(done);
2604
2605 if (!udc_controller)
2606 return -ENODEV;
0f91349b
SAS		 2607
2608 usb_del_gadget_udc(&udc_controller->gadget);
b504882d
LY		 2609 udc_controller->done = &done;
2610
54e4026b
GL		 2611 fsl_udc_clk_release();
2612
b504882d
LY		 2613 /* DR has been stopped in usb_gadget_unregister_driver() */
2614 remove_proc_file();
2615
2616 /* Free allocated memory */
2617 kfree(udc_controller->status_req->req.buf);
2618 kfree(udc_controller->status_req);
2619 kfree(udc_controller->eps);
2620
2621 dma_pool_destroy(udc_controller->td_pool);
2622 free_irq(udc_controller->irq, udc_controller);
2623 iounmap(dr_regs);
83722bc9 2624 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2625 release_mem_region(res->start, resource_size(res));
b504882d
LY		 2626
2627 device_unregister(&udc_controller->gadget.dev);
2628 /* free udc --wait for the release() finished */
2629 wait_for_completion(&done);
2630
2ea6698d
AG		 2631 /*
2632 * do platform specific un-initialization:
2633 * release iomux pins, etc.
2634 */
2635 if (pdata->exit)
2636 pdata->exit(pdev);
2637
b504882d
LY		 2638 return 0;
2639}
2640
2641/*-----------------------------------------------------------------
2642 * Modify Power management attributes
2643 * Used by OTG statemachine to disable gadget temporarily
2644 -----------------------------------------------------------------*/
2645static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2646{
2647 dr_controller_stop(udc_controller);
2648 return 0;
2649}
2650
2651/*-----------------------------------------------------------------
2652 * Invoked on USB resume. May be called in_interrupt.
2653 * Here we start the DR controller and enable the irq
2654 *-----------------------------------------------------------------*/
2655static int fsl_udc_resume(struct platform_device *pdev)
2656{
2657 /* Enable DR irq reg and set controller Run */
2658 if (udc_controller->stopped) {
2659 dr_controller_setup(udc_controller);
2660 dr_controller_run(udc_controller);
2661 }
2662 udc_controller->usb_state = USB_STATE_ATTACHED;
2663 udc_controller->ep0_state = WAIT_FOR_SETUP;
2664 udc_controller->ep0_dir = 0;
2665 return 0;
2666}
2667
83722bc9
AG		 2668static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2669{
2670 struct fsl_udc *udc = udc_controller;
2671 u32 mode, usbcmd;
2672
2673 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2674
2675 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2676
2677 /*
2678 * If the controller is already stopped, then this must be a
2679 * PM suspend. Remember this fact, so that we will leave the
2680 * controller stopped at PM resume time.
2681 */
2682 if (udc->stopped) {
2683 pr_debug("gadget already stopped, leaving early\n");
2684 udc->already_stopped = 1;
2685 return 0;
2686 }
2687
2688 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2689 pr_debug("gadget not in device mode, leaving early\n");
2690 return 0;
2691 }
2692
2693 /* stop the controller */
2694 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2695 fsl_writel(usbcmd, &dr_regs->usbcmd);
2696
2697 udc->stopped = 1;
2698
2699 pr_info("USB Gadget suspended\n");
2700
2701 return 0;
2702}
2703
2704static int fsl_udc_otg_resume(struct device *dev)
2705{
2706 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2707 udc_controller->stopped, udc_controller->already_stopped);
2708
2709 /*
2710 * If the controller was stopped at suspend time, then
2711 * don't resume it now.
2712 */
2713 if (udc_controller->already_stopped) {
2714 udc_controller->already_stopped = 0;
2715 pr_debug("gadget was already stopped, leaving early\n");
2716 return 0;
2717 }
2718
2719 pr_info("USB Gadget resume\n");
2720
2721 return fsl_udc_resume(NULL);
2722}
2723
b504882d
LY		 2724/*-------------------------------------------------------------------------
2725 Register entry point for the peripheral controller driver
2726--------------------------------------------------------------------------*/
2727
2728static struct platform_driver udc_driver = {
2729 .remove = __exit_p(fsl_udc_remove),
2730 /* these suspend and resume are not usb suspend and resume */
2731 .suspend = fsl_udc_suspend,
2732 .resume = fsl_udc_resume,
2733 .driver = {
2734 .name = (char *)driver_name,
2735 .owner = THIS_MODULE,
83722bc9
AG		 2736 /* udc suspend/resume called from OTG driver */
2737 .suspend = fsl_udc_otg_suspend,
2738 .resume = fsl_udc_otg_resume,
b504882d
LY		 2739 },
2740};
2741
2742static int __init udc_init(void)
2743{
2744 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2745 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2746}
2747
2748module_init(udc_init);
2749
2750static void __exit udc_exit(void)
2751{
2752 platform_driver_unregister(&udc_driver);
6f8aa65b 2753 printk(KERN_WARNING "%s unregistered\n", driver_desc);
b504882d
LY		 2754}
2755
2756module_exit(udc_exit);
2757
2758MODULE_DESCRIPTION(DRIVER_DESC);
2759MODULE_AUTHOR(DRIVER_AUTHOR);
2760MODULE_LICENSE("GPL");
f34c32f1 2761MODULE_ALIAS("platform:fsl-usb2-udc");
kernel source for telekom puls (alcatel/mediatek)