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staging:iio:ade7758: Fix NULL pointer deref when enabling buffer
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / iio / meter / ade7758_core.c
CommitLineData
8210cfe9 1/*
fb7f6cca 2 * ADE7758 Poly Phase Multifunction Energy Metering IC driver
8210cfe9 3 *
fb7f6cca 4 * Copyright 2010-2011 Analog Devices Inc.
8210cfe9 5 *
fb7f6cca 6 * Licensed under the GPL-2.
8210cfe9
BS		 7 */
8
9#include <linux/interrupt.h>
10#include <linux/irq.h>
8210cfe9
BS		 11#include <linux/delay.h>
12#include <linux/mutex.h>
13#include <linux/device.h>
14#include <linux/kernel.h>
15#include <linux/spi/spi.h>
16#include <linux/slab.h>
17#include <linux/sysfs.h>
18#include <linux/list.h>
99c97852 19#include <linux/module.h>
8210cfe9 20
06458e27
JC		 21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
8210cfe9
BS		 24#include "meter.h"
25#include "ade7758.h"
26
8a27a023 27int ade7758_spi_write_reg_8(struct device *dev,
8210cfe9
BS		 28 u8 reg_address,
29 u8 val)
30{
31 int ret;
196b59c1 32 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
a3f02370 33 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9
BS		 34
35 mutex_lock(&st->buf_lock);
36 st->tx[0] = ADE7758_WRITE_REG(reg_address);
37 st->tx[1] = val;
38
39 ret = spi_write(st->us, st->tx, 2);
40 mutex_unlock(&st->buf_lock);
41
42 return ret;
43}
44
45static int ade7758_spi_write_reg_16(struct device *dev,
46 u8 reg_address,
47 u16 value)
48{
49 int ret;
196b59c1 50 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
a3f02370 51 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9
BS		 52 struct spi_transfer xfers[] = {
53 {
54 .tx_buf = st->tx,
55 .bits_per_word = 8,
56 .len = 3,
57 }
58 };
59
60 mutex_lock(&st->buf_lock);
61 st->tx[0] = ADE7758_WRITE_REG(reg_address);
62 st->tx[1] = (value >> 8) & 0xFF;
63 st->tx[2] = value & 0xFF;
64
ad6c46b0 65 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
8210cfe9
BS		 66 mutex_unlock(&st->buf_lock);
67
68 return ret;
69}
70
71static int ade7758_spi_write_reg_24(struct device *dev,
72 u8 reg_address,
73 u32 value)
74{
75 int ret;
196b59c1 76 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
a3f02370 77 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9
BS		 78 struct spi_transfer xfers[] = {
79 {
80 .tx_buf = st->tx,
81 .bits_per_word = 8,
82 .len = 4,
83 }
84 };
85
86 mutex_lock(&st->buf_lock);
87 st->tx[0] = ADE7758_WRITE_REG(reg_address);
88 st->tx[1] = (value >> 16) & 0xFF;
89 st->tx[2] = (value >> 8) & 0xFF;
90 st->tx[3] = value & 0xFF;
91
ad6c46b0 92 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
8210cfe9
BS		 93 mutex_unlock(&st->buf_lock);
94
95 return ret;
96}
97
f535e08e 98int ade7758_spi_read_reg_8(struct device *dev,
8210cfe9
BS		 99 u8 reg_address,
100 u8 *val)
101{
196b59c1 102 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
a3f02370 103 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9
BS		 104 int ret;
105 struct spi_transfer xfers[] = {
106 {
107 .tx_buf = st->tx,
f535e08e
MH		 108 .bits_per_word = 8,
109 .len = 1,
110 .delay_usecs = 4,
111 },
112 {
113 .tx_buf = &st->tx[1],
8210cfe9
BS		 114 .rx_buf = st->rx,
115 .bits_per_word = 8,
f535e08e 116 .len = 1,
8210cfe9
BS		 117 },
118 };
119
120 mutex_lock(&st->buf_lock);
121 st->tx[0] = ADE7758_READ_REG(reg_address);
122 st->tx[1] = 0;
123
ad6c46b0 124 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
8210cfe9
BS		 125 if (ret) {
126 dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
127 reg_address);
128 goto error_ret;
129 }
f535e08e 130 *val = st->rx[0];
8210cfe9
BS		 131
132error_ret:
133 mutex_unlock(&st->buf_lock);
134 return ret;
135}
136
137static int ade7758_spi_read_reg_16(struct device *dev,
138 u8 reg_address,
139 u16 *val)
140{
196b59c1 141 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
a3f02370 142 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9
BS		 143 int ret;
144 struct spi_transfer xfers[] = {
145 {
146 .tx_buf = st->tx,
f535e08e
MH		 147 .bits_per_word = 8,
148 .len = 1,
149 .delay_usecs = 4,
150 },
151 {
152 .tx_buf = &st->tx[1],
8210cfe9
BS		 153 .rx_buf = st->rx,
154 .bits_per_word = 8,
f535e08e 155 .len = 2,
8210cfe9
BS		 156 },
157 };
158
f535e08e 159
8210cfe9
BS		 160 mutex_lock(&st->buf_lock);
161 st->tx[0] = ADE7758_READ_REG(reg_address);
162 st->tx[1] = 0;
163 st->tx[2] = 0;
164
ad6c46b0 165 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
8210cfe9
BS		 166 if (ret) {
167 dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
168 reg_address);
169 goto error_ret;
170 }
f535e08e
MH		 171
172 *val = (st->rx[0] << 8) | st->rx[1];
8210cfe9
BS		 173
174error_ret:
175 mutex_unlock(&st->buf_lock);
176 return ret;
177}
178
179static int ade7758_spi_read_reg_24(struct device *dev,
180 u8 reg_address,
181 u32 *val)
182{
196b59c1 183 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
a3f02370 184 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9
BS		 185 int ret;
186 struct spi_transfer xfers[] = {
187 {
188 .tx_buf = st->tx,
f535e08e
MH		 189 .bits_per_word = 8,
190 .len = 1,
191 .delay_usecs = 4,
192 },
193 {
194 .tx_buf = &st->tx[1],
8210cfe9
BS		 195 .rx_buf = st->rx,
196 .bits_per_word = 8,
f535e08e 197 .len = 3,
8210cfe9
BS		 198 },
199 };
200
201 mutex_lock(&st->buf_lock);
202 st->tx[0] = ADE7758_READ_REG(reg_address);
203 st->tx[1] = 0;
204 st->tx[2] = 0;
205 st->tx[3] = 0;
206
ad6c46b0 207 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
8210cfe9
BS		 208 if (ret) {
209 dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
210 reg_address);
211 goto error_ret;
212 }
f535e08e 213 *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
8210cfe9
BS		 214
215error_ret:
216 mutex_unlock(&st->buf_lock);
217 return ret;
218}
219
220static ssize_t ade7758_read_8bit(struct device *dev,
221 struct device_attribute *attr,
222 char *buf)
223{
224 int ret;
225 u8 val = 0;
226 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
227
228 ret = ade7758_spi_read_reg_8(dev, this_attr->address, &val);
229 if (ret)
230 return ret;
231
232 return sprintf(buf, "%u\n", val);
233}
234
235static ssize_t ade7758_read_16bit(struct device *dev,
236 struct device_attribute *attr,
237 char *buf)
238{
239 int ret;
240 u16 val = 0;
241 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
242
243 ret = ade7758_spi_read_reg_16(dev, this_attr->address, &val);
244 if (ret)
245 return ret;
246
247 return sprintf(buf, "%u\n", val);
248}
249
250static ssize_t ade7758_read_24bit(struct device *dev,
251 struct device_attribute *attr,
252 char *buf)
253{
254 int ret;
255 u32 val = 0;
256 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
257
258 ret = ade7758_spi_read_reg_24(dev, this_attr->address, &val);
259 if (ret)
260 return ret;
261
262 return sprintf(buf, "%u\n", val & 0xFFFFFF);
263}
264
265static ssize_t ade7758_write_8bit(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf,
268 size_t len)
269{
270 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
271 int ret;
272 long val;
273
274 ret = strict_strtol(buf, 10, &val);
275 if (ret)
276 goto error_ret;
277 ret = ade7758_spi_write_reg_8(dev, this_attr->address, val);
278
279error_ret:
280 return ret ? ret : len;
281}
282
283static ssize_t ade7758_write_16bit(struct device *dev,
284 struct device_attribute *attr,
285 const char *buf,
286 size_t len)
287{
288 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
289 int ret;
290 long val;
291
292 ret = strict_strtol(buf, 10, &val);
293 if (ret)
294 goto error_ret;
295 ret = ade7758_spi_write_reg_16(dev, this_attr->address, val);
296
297error_ret:
298 return ret ? ret : len;
299}
300
4be6f5da 301static int ade7758_reset(struct device *dev)
8210cfe9
BS		 302{
303 int ret;
304 u8 val;
305 ade7758_spi_read_reg_8(dev,
306 ADE7758_OPMODE,
307 &val);
308 val |= 1 << 6; /* Software Chip Reset */
309 ret = ade7758_spi_write_reg_8(dev,
310 ADE7758_OPMODE,
311 val);
312
313 return ret;
314}
315
316static ssize_t ade7758_write_reset(struct device *dev,
317 struct device_attribute *attr,
318 const char *buf, size_t len)
319{
320 if (len < 1)
321 return -1;
322 switch (buf[0]) {
323 case '1':
324 case 'y':
325 case 'Y':
326 return ade7758_reset(dev);
327 }
fb7f6cca 328 return len;
8210cfe9
BS		 329}
330
331static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO,
332 ade7758_read_8bit,
333 ade7758_write_8bit,
334 ADE7758_VPEAK);
335static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO,
336 ade7758_read_8bit,
337 ade7758_write_8bit,
338 ADE7758_VPEAK);
339static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO,
340 ade7758_read_8bit,
341 ade7758_write_8bit,
342 ADE7758_APHCAL);
343static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO,
344 ade7758_read_8bit,
345 ade7758_write_8bit,
346 ADE7758_BPHCAL);
347static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO,
348 ade7758_read_8bit,
349 ade7758_write_8bit,
350 ADE7758_CPHCAL);
351static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO,
352 ade7758_read_8bit,
353 ade7758_write_8bit,
354 ADE7758_WDIV);
355static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO,
356 ade7758_read_8bit,
357 ade7758_write_8bit,
358 ADE7758_VADIV);
359static IIO_DEV_ATTR_AIRMS(S_IRUGO,
360 ade7758_read_24bit,
361 NULL,
362 ADE7758_AIRMS);
363static IIO_DEV_ATTR_BIRMS(S_IRUGO,
364 ade7758_read_24bit,
365 NULL,
366 ADE7758_BIRMS);
367static IIO_DEV_ATTR_CIRMS(S_IRUGO,
368 ade7758_read_24bit,
369 NULL,
370 ADE7758_CIRMS);
371static IIO_DEV_ATTR_AVRMS(S_IRUGO,
372 ade7758_read_24bit,
373 NULL,
374 ADE7758_AVRMS);
375static IIO_DEV_ATTR_BVRMS(S_IRUGO,
376 ade7758_read_24bit,
377 NULL,
378 ADE7758_BVRMS);
379static IIO_DEV_ATTR_CVRMS(S_IRUGO,
380 ade7758_read_24bit,
381 NULL,
382 ADE7758_CVRMS);
383static IIO_DEV_ATTR_AIRMSOS(S_IWUSR | S_IRUGO,
384 ade7758_read_16bit,
385 ade7758_write_16bit,
386 ADE7758_AIRMSOS);
387static IIO_DEV_ATTR_BIRMSOS(S_IWUSR | S_IRUGO,
388 ade7758_read_16bit,
389 ade7758_write_16bit,
390 ADE7758_BIRMSOS);
391static IIO_DEV_ATTR_CIRMSOS(S_IWUSR | S_IRUGO,
392 ade7758_read_16bit,
393 ade7758_write_16bit,
394 ADE7758_CIRMSOS);
395static IIO_DEV_ATTR_AVRMSOS(S_IWUSR | S_IRUGO,
396 ade7758_read_16bit,
397 ade7758_write_16bit,
398 ADE7758_AVRMSOS);
399static IIO_DEV_ATTR_BVRMSOS(S_IWUSR | S_IRUGO,
400 ade7758_read_16bit,
401 ade7758_write_16bit,
402 ADE7758_BVRMSOS);
403static IIO_DEV_ATTR_CVRMSOS(S_IWUSR | S_IRUGO,
404 ade7758_read_16bit,
405 ade7758_write_16bit,
406 ADE7758_CVRMSOS);
407static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO,
408 ade7758_read_16bit,
409 ade7758_write_16bit,
410 ADE7758_AIGAIN);
411static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO,
412 ade7758_read_16bit,
413 ade7758_write_16bit,
414 ADE7758_BIGAIN);
415static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO,
416 ade7758_read_16bit,
417 ade7758_write_16bit,
418 ADE7758_CIGAIN);
419static IIO_DEV_ATTR_AVRMSGAIN(S_IWUSR | S_IRUGO,
420 ade7758_read_16bit,
421 ade7758_write_16bit,
422 ADE7758_AVRMSGAIN);
423static IIO_DEV_ATTR_BVRMSGAIN(S_IWUSR | S_IRUGO,
424 ade7758_read_16bit,
425 ade7758_write_16bit,
426 ADE7758_BVRMSGAIN);
427static IIO_DEV_ATTR_CVRMSGAIN(S_IWUSR | S_IRUGO,
428 ade7758_read_16bit,
429 ade7758_write_16bit,
430 ADE7758_CVRMSGAIN);
431
432int ade7758_set_irq(struct device *dev, bool enable)
433{
434 int ret;
435 u32 irqen;
436 ret = ade7758_spi_read_reg_24(dev, ADE7758_MASK, &irqen);
437 if (ret)
438 goto error_ret;
439
440 if (enable)
441 irqen |= 1 << 16; /* Enables an interrupt when a data is
442 present in the waveform register */
443 else
444 irqen &= ~(1 << 16);
445
446 ret = ade7758_spi_write_reg_24(dev, ADE7758_MASK, irqen);
447 if (ret)
448 goto error_ret;
449
450error_ret:
451 return ret;
452}
453
454/* Power down the device */
455static int ade7758_stop_device(struct device *dev)
456{
457 int ret;
458 u8 val;
459 ade7758_spi_read_reg_8(dev,
460 ADE7758_OPMODE,
461 &val);
462 val |= 7 << 3; /* ADE7758 powered down */
463 ret = ade7758_spi_write_reg_8(dev,
464 ADE7758_OPMODE,
465 val);
466
467 return ret;
468}
469
a3f02370 470static int ade7758_initial_setup(struct iio_dev *indio_dev)
8210cfe9 471{
a3f02370
MH		 472 struct ade7758_state *st = iio_priv(indio_dev);
473 struct device *dev = &indio_dev->dev;
8210cfe9 474 int ret;
8210cfe9
BS		 475
476 /* use low spi speed for init */
8a27a023 477 st->us->mode = SPI_MODE_1;
8210cfe9
BS		 478 spi_setup(st->us);
479
480 /* Disable IRQ */
481 ret = ade7758_set_irq(dev, false);
482 if (ret) {
483 dev_err(dev, "disable irq failed");
484 goto err_ret;
485 }
486
487 ade7758_reset(dev);
488 msleep(ADE7758_STARTUP_DELAY);
489
490err_ret:
491 return ret;
492}
493
494static ssize_t ade7758_read_frequency(struct device *dev,
495 struct device_attribute *attr,
496 char *buf)
497{
498 int ret, len = 0;
499 u8 t;
500 int sps;
501 ret = ade7758_spi_read_reg_8(dev,
502 ADE7758_WAVMODE,
503 &t);
504 if (ret)
505 return ret;
506
507 t = (t >> 5) & 0x3;
508 sps = 26040 / (1 << t);
509
510 len = sprintf(buf, "%d SPS\n", sps);
511 return len;
512}
513
514static ssize_t ade7758_write_frequency(struct device *dev,
515 struct device_attribute *attr,
516 const char *buf,
517 size_t len)
518{
196b59c1 519 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
8210cfe9
BS		 520 unsigned long val;
521 int ret;
522 u8 reg, t;
523
524 ret = strict_strtol(buf, 10, &val);
525 if (ret)
526 return ret;
527
528 mutex_lock(&indio_dev->mlock);
529
9308bc9a
MH		 530 switch (val) {
531 case 26040:
532 t = 0;
533 break;
534 case 13020:
535 t = 1;
536 break;
537 case 6510:
538 t = 2;
539 break;
540 case 3255:
541 t = 3;
542 break;
543 default:
544 ret = -EINVAL;
545 goto out;
546 }
8210cfe9
BS		 547
548 ret = ade7758_spi_read_reg_8(dev,
549 ADE7758_WAVMODE,
550 &reg);
551 if (ret)
552 goto out;
553
554 reg &= ~(5 << 3);
555 reg |= t << 5;
556
557 ret = ade7758_spi_write_reg_8(dev,
558 ADE7758_WAVMODE,
559 reg);
560
561out:
562 mutex_unlock(&indio_dev->mlock);
563
564 return ret ? ret : len;
565}
566
8210cfe9 567static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit);
322c9563
JC		 568static IIO_CONST_ATTR(in_temp_offset, "129 C");
569static IIO_CONST_ATTR(in_temp_scale, "4 C");
8210cfe9
BS		 570
571static IIO_DEV_ATTR_AWATTHR(ade7758_read_16bit,
572 ADE7758_AWATTHR);
573static IIO_DEV_ATTR_BWATTHR(ade7758_read_16bit,
574 ADE7758_BWATTHR);
575static IIO_DEV_ATTR_CWATTHR(ade7758_read_16bit,
576 ADE7758_CWATTHR);
577static IIO_DEV_ATTR_AVARHR(ade7758_read_16bit,
578 ADE7758_AVARHR);
579static IIO_DEV_ATTR_BVARHR(ade7758_read_16bit,
580 ADE7758_BVARHR);
581static IIO_DEV_ATTR_CVARHR(ade7758_read_16bit,
582 ADE7758_CVARHR);
583static IIO_DEV_ATTR_AVAHR(ade7758_read_16bit,
584 ADE7758_AVAHR);
585static IIO_DEV_ATTR_BVAHR(ade7758_read_16bit,
586 ADE7758_BVAHR);
587static IIO_DEV_ATTR_CVAHR(ade7758_read_16bit,
588 ADE7758_CVAHR);
589
590static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
591 ade7758_read_frequency,
592 ade7758_write_frequency);
593
8210cfe9
BS		 594static IIO_DEV_ATTR_RESET(ade7758_write_reset);
595
9308bc9a 596static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255");
8210cfe9 597
8210cfe9 598static struct attribute *ade7758_attributes[] = {
322c9563
JC		 599 &iio_dev_attr_in_temp_raw.dev_attr.attr,
600 &iio_const_attr_in_temp_offset.dev_attr.attr,
601 &iio_const_attr_in_temp_scale.dev_attr.attr,
8210cfe9 602 &iio_dev_attr_sampling_frequency.dev_attr.attr,
8210cfe9
BS		 603 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
604 &iio_dev_attr_reset.dev_attr.attr,
8210cfe9
BS		 605 &iio_dev_attr_awatthr.dev_attr.attr,
606 &iio_dev_attr_bwatthr.dev_attr.attr,
607 &iio_dev_attr_cwatthr.dev_attr.attr,
608 &iio_dev_attr_avarhr.dev_attr.attr,
609 &iio_dev_attr_bvarhr.dev_attr.attr,
610 &iio_dev_attr_cvarhr.dev_attr.attr,
611 &iio_dev_attr_avahr.dev_attr.attr,
612 &iio_dev_attr_bvahr.dev_attr.attr,
613 &iio_dev_attr_cvahr.dev_attr.attr,
614 &iio_dev_attr_vpeak.dev_attr.attr,
615 &iio_dev_attr_ipeak.dev_attr.attr,
616 &iio_dev_attr_aphcal.dev_attr.attr,
617 &iio_dev_attr_bphcal.dev_attr.attr,
618 &iio_dev_attr_cphcal.dev_attr.attr,
619 &iio_dev_attr_wdiv.dev_attr.attr,
620 &iio_dev_attr_vadiv.dev_attr.attr,
621 &iio_dev_attr_airms.dev_attr.attr,
622 &iio_dev_attr_birms.dev_attr.attr,
623 &iio_dev_attr_cirms.dev_attr.attr,
624 &iio_dev_attr_avrms.dev_attr.attr,
625 &iio_dev_attr_bvrms.dev_attr.attr,
626 &iio_dev_attr_cvrms.dev_attr.attr,
627 &iio_dev_attr_aigain.dev_attr.attr,
628 &iio_dev_attr_bigain.dev_attr.attr,
629 &iio_dev_attr_cigain.dev_attr.attr,
630 &iio_dev_attr_avrmsgain.dev_attr.attr,
631 &iio_dev_attr_bvrmsgain.dev_attr.attr,
632 &iio_dev_attr_cvrmsgain.dev_attr.attr,
633 &iio_dev_attr_airmsos.dev_attr.attr,
634 &iio_dev_attr_birmsos.dev_attr.attr,
635 &iio_dev_attr_cirmsos.dev_attr.attr,
636 &iio_dev_attr_avrmsos.dev_attr.attr,
637 &iio_dev_attr_bvrmsos.dev_attr.attr,
638 &iio_dev_attr_cvrmsos.dev_attr.attr,
639 NULL,
640};
641
642static const struct attribute_group ade7758_attribute_group = {
643 .attrs = ade7758_attributes,
644};
645
f4e4b955 646static const struct iio_chan_spec ade7758_channels[] = {
926c0452
JC		 647 {
648 .type = IIO_VOLTAGE,
649 .indexed = 1,
650 .channel = 0,
651 .extend_name = "raw",
926c0452
JC		 652 .address = AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE),
653 .scan_index = 0,
654 .scan_type = {
655 .sign = 's',
656 .realbits = 24,
657 .storagebits = 32,
658 },
659 }, {
660 .type = IIO_CURRENT,
661 .indexed = 1,
662 .channel = 0,
663 .extend_name = "raw",
926c0452
JC		 664 .address = AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT),
665 .scan_index = 1,
666 .scan_type = {
667 .sign = 's',
668 .realbits = 24,
669 .storagebits = 32,
670 },
671 }, {
672 .type = IIO_POWER,
673 .indexed = 1,
674 .channel = 0,
675 .extend_name = "apparent_raw",
926c0452
JC		 676 .address = AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR),
677 .scan_index = 2,
678 .scan_type = {
679 .sign = 's',
680 .realbits = 24,
681 .storagebits = 32,
682 },
683 }, {
684 .type = IIO_POWER,
685 .indexed = 1,
686 .channel = 0,
687 .extend_name = "active_raw",
926c0452
JC		 688 .address = AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR),
689 .scan_index = 3,
690 .scan_type = {
691 .sign = 's',
692 .realbits = 24,
693 .storagebits = 32,
694 },
695 }, {
696 .type = IIO_POWER,
697 .indexed = 1,
698 .channel = 0,
699 .extend_name = "reactive_raw",
926c0452
JC		 700 .address = AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR),
701 .scan_index = 4,
702 .scan_type = {
703 .sign = 's',
704 .realbits = 24,
705 .storagebits = 32,
706 },
707 }, {
708 .type = IIO_VOLTAGE,
709 .indexed = 1,
710 .channel = 1,
711 .extend_name = "raw",
926c0452
JC		 712 .address = AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE),
713 .scan_index = 5,
714 .scan_type = {
715 .sign = 's',
716 .realbits = 24,
717 .storagebits = 32,
718 },
719 }, {
720 .type = IIO_CURRENT,
721 .indexed = 1,
722 .channel = 1,
723 .extend_name = "raw",
926c0452
JC		 724 .address = AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT),
725 .scan_index = 6,
726 .scan_type = {
727 .sign = 's',
728 .realbits = 24,
729 .storagebits = 32,
730 },
731 }, {
732 .type = IIO_POWER,
733 .indexed = 1,
734 .channel = 1,
735 .extend_name = "apparent_raw",
926c0452
JC		 736 .address = AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR),
737 .scan_index = 7,
738 .scan_type = {
739 .sign = 's',
740 .realbits = 24,
741 .storagebits = 32,
742 },
743 }, {
744 .type = IIO_POWER,
745 .indexed = 1,
746 .channel = 1,
747 .extend_name = "active_raw",
926c0452
JC		 748 .address = AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR),
749 .scan_index = 8,
750 .scan_type = {
751 .sign = 's',
752 .realbits = 24,
753 .storagebits = 32,
754 },
755 }, {
756 .type = IIO_POWER,
757 .indexed = 1,
758 .channel = 1,
759 .extend_name = "reactive_raw",
926c0452
JC		 760 .address = AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR),
761 .scan_index = 9,
762 .scan_type = {
763 .sign = 's',
764 .realbits = 24,
765 .storagebits = 32,
766 },
767 }, {
768 .type = IIO_VOLTAGE,
769 .indexed = 1,
770 .channel = 2,
771 .extend_name = "raw",
926c0452
JC		 772 .address = AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE),
773 .scan_index = 10,
774 .scan_type = {
775 .sign = 's',
776 .realbits = 24,
777 .storagebits = 32,
778 },
779 }, {
780 .type = IIO_CURRENT,
781 .indexed = 1,
782 .channel = 2,
783 .extend_name = "raw",
926c0452
JC		 784 .address = AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT),
785 .scan_index = 11,
786 .scan_type = {
787 .sign = 's',
788 .realbits = 24,
789 .storagebits = 32,
790 },
791 }, {
792 .type = IIO_POWER,
793 .indexed = 1,
794 .channel = 2,
795 .extend_name = "apparent_raw",
926c0452
JC		 796 .address = AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR),
797 .scan_index = 12,
798 .scan_type = {
799 .sign = 's',
800 .realbits = 24,
801 .storagebits = 32,
802 },
803 }, {
804 .type = IIO_POWER,
805 .indexed = 1,
806 .channel = 2,
807 .extend_name = "active_raw",
926c0452
JC		 808 .address = AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR),
809 .scan_index = 13,
810 .scan_type = {
811 .sign = 's',
812 .realbits = 24,
813 .storagebits = 32,
814 },
815 }, {
816 .type = IIO_POWER,
817 .indexed = 1,
818 .channel = 2,
819 .extend_name = "reactive_raw",
926c0452
JC		 820 .address = AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR),
821 .scan_index = 14,
822 .scan_type = {
823 .sign = 's',
824 .realbits = 24,
825 .storagebits = 32,
826 },
827 },
8a27a023
MH		 828 IIO_CHAN_SOFT_TIMESTAMP(15),
829};
8210cfe9 830
6fe8135f
JC		 831static const struct iio_info ade7758_info = {
832 .attrs = &ade7758_attribute_group,
833 .driver_module = THIS_MODULE,
834};
835
4ae1c61f 836static int ade7758_probe(struct spi_device *spi)
8210cfe9 837{
ee0312a0 838 int ret;
a3f02370 839 struct ade7758_state *st;
7cbb7537 840 struct iio_dev *indio_dev = iio_device_alloc(sizeof(*st));
a3f02370
MH		 841
842 if (indio_dev == NULL) {
843 ret = -ENOMEM;
8210cfe9
BS		 844 goto error_ret;
845 }
a3f02370
MH		 846
847 st = iio_priv(indio_dev);
8210cfe9 848 /* this is only used for removal purposes */
a3f02370 849 spi_set_drvdata(spi, indio_dev);
8210cfe9
BS		 850
851 /* Allocate the comms buffers */
d83fb184 852 st->rx = kcalloc(ADE7758_MAX_RX, sizeof(*st->rx), GFP_KERNEL);
8210cfe9
BS		 853 if (st->rx == NULL) {
854 ret = -ENOMEM;
a3f02370 855 goto error_free_dev;
8210cfe9 856 }
d83fb184 857 st->tx = kcalloc(ADE7758_MAX_TX, sizeof(*st->tx), GFP_KERNEL);
8210cfe9
BS		 858 if (st->tx == NULL) {
859 ret = -ENOMEM;
860 goto error_free_rx;
861 }
862 st->us = spi;
863 mutex_init(&st->buf_lock);
8210cfe9 864
a3f02370
MH		 865 indio_dev->name = spi->dev.driver->name;
866 indio_dev->dev.parent = &spi->dev;
6fe8135f 867 indio_dev->info = &ade7758_info;
a3f02370 868 indio_dev->modes = INDIO_DIRECT_MODE;
035bc79c
LPC		 869 indio_dev->channels = ade7758_channels;
870 indio_dev->num_channels = ARRAY_SIZE(ade7758_channels);
8210cfe9 871
a3f02370 872 ret = ade7758_configure_ring(indio_dev);
8210cfe9 873 if (ret)
a3f02370 874 goto error_free_tx;
8210cfe9 875
14555b14
JC		 876 ret = iio_buffer_register(indio_dev,
877 &ade7758_channels[0],
878 ARRAY_SIZE(ade7758_channels));
8210cfe9 879 if (ret) {
8a27a023 880 dev_err(&spi->dev, "failed to initialize the ring\n");
8210cfe9
BS		 881 goto error_unreg_ring_funcs;
882 }
883
8a27a023 884 /* Get the device into a sane initial state */
a3f02370 885 ret = ade7758_initial_setup(indio_dev);
8a27a023
MH		 886 if (ret)
887 goto error_uninitialize_ring;
888
8210cfe9 889 if (spi->irq) {
a3f02370 890 ret = ade7758_probe_trigger(indio_dev);
8210cfe9 891 if (ret)
26d25ae3 892 goto error_uninitialize_ring;
8210cfe9
BS		 893 }
894
26d25ae3
JC		 895 ret = iio_device_register(indio_dev);
896 if (ret)
897 goto error_remove_trigger;
898
8210cfe9
BS		 899 return 0;
900
901error_remove_trigger:
487db485 902 if (spi->irq)
a3f02370 903 ade7758_remove_trigger(indio_dev);
8210cfe9 904error_uninitialize_ring:
1aa04278 905 ade7758_uninitialize_ring(indio_dev);
8210cfe9 906error_unreg_ring_funcs:
a3f02370 907 ade7758_unconfigure_ring(indio_dev);
8210cfe9
BS		 908error_free_tx:
909 kfree(st->tx);
910error_free_rx:
911 kfree(st->rx);
a3f02370 912error_free_dev:
7cbb7537 913 iio_device_free(indio_dev);
8210cfe9
BS		 914error_ret:
915 return ret;
916}
917
447d4f29 918static int ade7758_remove(struct spi_device *spi)
8210cfe9 919{
a3f02370
MH		 920 struct iio_dev *indio_dev = spi_get_drvdata(spi);
921 struct ade7758_state *st = iio_priv(indio_dev);
8210cfe9 922
d2fffd6c 923 iio_device_unregister(indio_dev);
4922fd69 924 ade7758_stop_device(&indio_dev->dev);
8210cfe9 925 ade7758_remove_trigger(indio_dev);
1aa04278 926 ade7758_uninitialize_ring(indio_dev);
8210cfe9
BS		 927 ade7758_unconfigure_ring(indio_dev);
928 kfree(st->tx);
929 kfree(st->rx);
8210cfe9 930
7cbb7537 931 iio_device_free(indio_dev);
d2fffd6c 932
4922fd69 933 return 0;
8210cfe9
BS		 934}
935
8a27a023
MH		 936static const struct spi_device_id ade7758_id[] = {
937 {"ade7758", 0},
938 {}
939};
55e4390c 940MODULE_DEVICE_TABLE(spi, ade7758_id);
8a27a023 941
8210cfe9
BS		 942static struct spi_driver ade7758_driver = {
943 .driver = {
944 .name = "ade7758",
945 .owner = THIS_MODULE,
946 },
947 .probe = ade7758_probe,
e543acf0 948 .remove = ade7758_remove,
8a27a023 949 .id_table = ade7758_id,
8210cfe9 950};
ae6ae6fe 951module_spi_driver(ade7758_driver);
8210cfe9
BS		 952
953MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
954MODULE_DESCRIPTION("Analog Devices ADE7758 Polyphase Multifunction Energy Metering IC Driver");
955MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)