Commit | Line | Data |
---|---|---|
bd41b99d | 1 | /* |
c103de24 | 2 | * U300 GPIO module. |
bd41b99d | 3 | * |
04b13de6 | 4 | * Copyright (C) 2007-2012 ST-Ericsson AB |
bd41b99d | 5 | * License terms: GNU General Public License (GPL) version 2 |
bd41b99d | 6 | * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) |
cc890cd7 | 7 | * Author: Linus Walleij <linus.walleij@linaro.org> |
bd41b99d | 8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
bd41b99d LW |
9 | */ |
10 | #include <linux/module.h> | |
cc890cd7 | 11 | #include <linux/irq.h> |
bd41b99d LW |
12 | #include <linux/interrupt.h> |
13 | #include <linux/delay.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/io.h> | |
a6c45b99 | 16 | #include <linux/irqdomain.h> |
bd41b99d LW |
17 | #include <linux/clk.h> |
18 | #include <linux/err.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/gpio.h> | |
cc890cd7 LW |
21 | #include <linux/list.h> |
22 | #include <linux/slab.h> | |
28a8d14c | 23 | #include <linux/pinctrl/consumer.h> |
dc0b1aa3 | 24 | #include <linux/pinctrl/pinconf-generic.h> |
65172850 | 25 | #include <linux/platform_data/pinctrl-coh901.h> |
dc0b1aa3 | 26 | #include "pinctrl-coh901.h" |
bd41b99d | 27 | |
04b13de6 | 28 | #define U300_GPIO_PORT_STRIDE (0x30) |
cc890cd7 | 29 | /* |
04b13de6 LW |
30 | * Control Register 32bit (R/W) |
31 | * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores | |
32 | * gives the number of GPIO pins. | |
33 | * bit 8-2 (mask 0x000001FC) contains the core version ID. | |
cc890cd7 | 34 | */ |
04b13de6 LW |
35 | #define U300_GPIO_CR (0x00) |
36 | #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) | |
37 | #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) | |
38 | #define U300_GPIO_PXPDIR (0x04) | |
39 | #define U300_GPIO_PXPDOR (0x08) | |
40 | #define U300_GPIO_PXPCR (0x0C) | |
cc890cd7 LW |
41 | #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) |
42 | #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) | |
43 | #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) | |
44 | #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) | |
45 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) | |
46 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) | |
47 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) | |
04b13de6 LW |
48 | #define U300_GPIO_PXPER (0x10) |
49 | #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) | |
50 | #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) | |
51 | #define U300_GPIO_PXIEV (0x14) | |
52 | #define U300_GPIO_PXIEN (0x18) | |
53 | #define U300_GPIO_PXIFR (0x1C) | |
54 | #define U300_GPIO_PXICR (0x20) | |
cc890cd7 LW |
55 | #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) |
56 | #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) | |
57 | #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) | |
58 | #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) | |
cc890cd7 LW |
59 | |
60 | /* 8 bits per port, no version has more than 7 ports */ | |
61 | #define U300_GPIO_PINS_PER_PORT 8 | |
62 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) | |
63 | ||
64 | struct u300_gpio { | |
65 | struct gpio_chip chip; | |
66 | struct list_head port_list; | |
67 | struct clk *clk; | |
68 | struct resource *memres; | |
69 | void __iomem *base; | |
70 | struct device *dev; | |
cc890cd7 LW |
71 | u32 stride; |
72 | /* Register offsets */ | |
73 | u32 pcr; | |
74 | u32 dor; | |
75 | u32 dir; | |
76 | u32 per; | |
77 | u32 icr; | |
78 | u32 ien; | |
79 | u32 iev; | |
80 | }; | |
bd41b99d LW |
81 | |
82 | struct u300_gpio_port { | |
cc890cd7 LW |
83 | struct list_head node; |
84 | struct u300_gpio *gpio; | |
85 | char name[8]; | |
a6c45b99 | 86 | struct irq_domain *domain; |
bd41b99d LW |
87 | int irq; |
88 | int number; | |
cc890cd7 | 89 | u8 toggle_edge_mode; |
bd41b99d LW |
90 | }; |
91 | ||
cc890cd7 LW |
92 | /* |
93 | * Macro to expand to read a specific register found in the "gpio" | |
94 | * struct. It requires the struct u300_gpio *gpio variable to exist in | |
95 | * its context. It calculates the port offset from the given pin | |
96 | * offset, muliplies by the port stride and adds the register offset | |
97 | * so it provides a pointer to the desired register. | |
98 | */ | |
99 | #define U300_PIN_REG(pin, reg) \ | |
100 | (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) | |
bd41b99d | 101 | |
cc890cd7 LW |
102 | /* |
103 | * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO | |
104 | * register. | |
105 | */ | |
106 | #define U300_PIN_BIT(pin) \ | |
107 | (1 << (pin & 0x07)) | |
bd41b99d | 108 | |
cc890cd7 LW |
109 | struct u300_gpio_confdata { |
110 | u16 bias_mode; | |
111 | bool output; | |
112 | int outval; | |
bd41b99d LW |
113 | }; |
114 | ||
cc890cd7 LW |
115 | /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ |
116 | #define BS335_GPIO_NUM_PORTS 7 | |
bd41b99d | 117 | |
cc890cd7 | 118 | #define U300_FLOATING_INPUT { \ |
a050b3ee | 119 | .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ |
cc890cd7 LW |
120 | .output = false, \ |
121 | } | |
bd41b99d | 122 | |
cc890cd7 | 123 | #define U300_PULL_UP_INPUT { \ |
a050b3ee | 124 | .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ |
cc890cd7 LW |
125 | .output = false, \ |
126 | } | |
bd41b99d | 127 | |
cc890cd7 LW |
128 | #define U300_OUTPUT_LOW { \ |
129 | .output = true, \ | |
130 | .outval = 0, \ | |
131 | } | |
bd41b99d | 132 | |
cc890cd7 LW |
133 | #define U300_OUTPUT_HIGH { \ |
134 | .output = true, \ | |
135 | .outval = 1, \ | |
136 | } | |
bd41b99d | 137 | |
bd41b99d | 138 | /* Initial configuration */ |
122dbe7e | 139 | static const struct __initconst u300_gpio_confdata |
cc890cd7 | 140 | bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { |
bd41b99d LW |
141 | /* Port 0, pins 0-7 */ |
142 | { | |
cc890cd7 LW |
143 | U300_FLOATING_INPUT, |
144 | U300_OUTPUT_HIGH, | |
145 | U300_FLOATING_INPUT, | |
146 | U300_OUTPUT_LOW, | |
147 | U300_OUTPUT_LOW, | |
148 | U300_OUTPUT_LOW, | |
149 | U300_OUTPUT_LOW, | |
150 | U300_OUTPUT_LOW, | |
bd41b99d LW |
151 | }, |
152 | /* Port 1, pins 0-7 */ | |
153 | { | |
cc890cd7 LW |
154 | U300_OUTPUT_LOW, |
155 | U300_OUTPUT_LOW, | |
156 | U300_OUTPUT_LOW, | |
157 | U300_PULL_UP_INPUT, | |
158 | U300_FLOATING_INPUT, | |
159 | U300_OUTPUT_HIGH, | |
160 | U300_OUTPUT_LOW, | |
161 | U300_OUTPUT_LOW, | |
bd41b99d LW |
162 | }, |
163 | /* Port 2, pins 0-7 */ | |
164 | { | |
cc890cd7 LW |
165 | U300_FLOATING_INPUT, |
166 | U300_FLOATING_INPUT, | |
167 | U300_FLOATING_INPUT, | |
168 | U300_FLOATING_INPUT, | |
169 | U300_OUTPUT_LOW, | |
170 | U300_PULL_UP_INPUT, | |
171 | U300_OUTPUT_LOW, | |
172 | U300_PULL_UP_INPUT, | |
bd41b99d LW |
173 | }, |
174 | /* Port 3, pins 0-7 */ | |
175 | { | |
cc890cd7 LW |
176 | U300_PULL_UP_INPUT, |
177 | U300_OUTPUT_LOW, | |
178 | U300_FLOATING_INPUT, | |
179 | U300_FLOATING_INPUT, | |
180 | U300_FLOATING_INPUT, | |
181 | U300_FLOATING_INPUT, | |
182 | U300_FLOATING_INPUT, | |
183 | U300_FLOATING_INPUT, | |
bd41b99d LW |
184 | }, |
185 | /* Port 4, pins 0-7 */ | |
186 | { | |
cc890cd7 LW |
187 | U300_FLOATING_INPUT, |
188 | U300_FLOATING_INPUT, | |
189 | U300_FLOATING_INPUT, | |
190 | U300_FLOATING_INPUT, | |
191 | U300_FLOATING_INPUT, | |
192 | U300_FLOATING_INPUT, | |
193 | U300_FLOATING_INPUT, | |
194 | U300_FLOATING_INPUT, | |
bd41b99d LW |
195 | }, |
196 | /* Port 5, pins 0-7 */ | |
197 | { | |
cc890cd7 LW |
198 | U300_FLOATING_INPUT, |
199 | U300_FLOATING_INPUT, | |
200 | U300_FLOATING_INPUT, | |
201 | U300_FLOATING_INPUT, | |
202 | U300_FLOATING_INPUT, | |
203 | U300_FLOATING_INPUT, | |
204 | U300_FLOATING_INPUT, | |
205 | U300_FLOATING_INPUT, | |
bd41b99d LW |
206 | }, |
207 | /* Port 6, pind 0-7 */ | |
208 | { | |
cc890cd7 LW |
209 | U300_FLOATING_INPUT, |
210 | U300_FLOATING_INPUT, | |
211 | U300_FLOATING_INPUT, | |
212 | U300_FLOATING_INPUT, | |
213 | U300_FLOATING_INPUT, | |
214 | U300_FLOATING_INPUT, | |
215 | U300_FLOATING_INPUT, | |
216 | U300_FLOATING_INPUT, | |
bd41b99d | 217 | } |
cc890cd7 | 218 | }; |
bd41b99d | 219 | |
cc890cd7 LW |
220 | /** |
221 | * to_u300_gpio() - get the pointer to u300_gpio | |
222 | * @chip: the gpio chip member of the structure u300_gpio | |
bd41b99d | 223 | */ |
cc890cd7 | 224 | static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) |
bd41b99d | 225 | { |
cc890cd7 | 226 | return container_of(chip, struct u300_gpio, chip); |
bd41b99d | 227 | } |
bd41b99d | 228 | |
b4e3ac74 LW |
229 | static int u300_gpio_request(struct gpio_chip *chip, unsigned offset) |
230 | { | |
231 | /* | |
232 | * Map back to global GPIO space and request muxing, the direction | |
233 | * parameter does not matter for this controller. | |
234 | */ | |
235 | int gpio = chip->base + offset; | |
236 | ||
e93bcee0 | 237 | return pinctrl_request_gpio(gpio); |
b4e3ac74 LW |
238 | } |
239 | ||
240 | static void u300_gpio_free(struct gpio_chip *chip, unsigned offset) | |
241 | { | |
242 | int gpio = chip->base + offset; | |
243 | ||
e93bcee0 | 244 | pinctrl_free_gpio(gpio); |
b4e3ac74 LW |
245 | } |
246 | ||
cc890cd7 | 247 | static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 248 | { |
cc890cd7 | 249 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 250 | |
cc890cd7 | 251 | return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); |
bd41b99d | 252 | } |
bd41b99d | 253 | |
cc890cd7 | 254 | static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
ee17962e | 255 | { |
cc890cd7 LW |
256 | struct u300_gpio *gpio = to_u300_gpio(chip); |
257 | unsigned long flags; | |
258 | u32 val; | |
ee17962e | 259 | |
cc890cd7 | 260 | local_irq_save(flags); |
bd41b99d | 261 | |
cc890cd7 LW |
262 | val = readl(U300_PIN_REG(offset, dor)); |
263 | if (value) | |
264 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
265 | else | |
266 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
bd41b99d | 267 | |
cc890cd7 | 268 | local_irq_restore(flags); |
bd41b99d | 269 | } |
bd41b99d | 270 | |
cc890cd7 | 271 | static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 272 | { |
cc890cd7 LW |
273 | struct u300_gpio *gpio = to_u300_gpio(chip); |
274 | unsigned long flags; | |
275 | u32 val; | |
bd41b99d | 276 | |
cc890cd7 LW |
277 | local_irq_save(flags); |
278 | val = readl(U300_PIN_REG(offset, pcr)); | |
279 | /* Mask out this pin, note 2 bits per setting */ | |
280 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
281 | writel(val, U300_PIN_REG(offset, pcr)); | |
282 | local_irq_restore(flags); | |
283 | return 0; | |
bd41b99d | 284 | } |
bd41b99d | 285 | |
cc890cd7 LW |
286 | static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
287 | int value) | |
bd41b99d | 288 | { |
cc890cd7 | 289 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 290 | unsigned long flags; |
cc890cd7 LW |
291 | u32 oldmode; |
292 | u32 val; | |
bd41b99d LW |
293 | |
294 | local_irq_save(flags); | |
cc890cd7 LW |
295 | val = readl(U300_PIN_REG(offset, pcr)); |
296 | /* | |
297 | * Drive mode must be set by the special mode set function, set | |
298 | * push/pull mode by default if no mode has been selected. | |
299 | */ | |
300 | oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << | |
301 | ((offset & 0x07) << 1)); | |
302 | /* mode = 0 means input, else some mode is already set */ | |
303 | if (oldmode == 0) { | |
304 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << | |
305 | ((offset & 0x07) << 1)); | |
306 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
307 | << ((offset & 0x07) << 1)); | |
308 | writel(val, U300_PIN_REG(offset, pcr)); | |
bd41b99d | 309 | } |
cc890cd7 | 310 | u300_gpio_set(chip, offset, value); |
bd41b99d | 311 | local_irq_restore(flags); |
cc890cd7 | 312 | return 0; |
bd41b99d | 313 | } |
bd41b99d | 314 | |
cc890cd7 | 315 | static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 316 | { |
cc890cd7 | 317 | struct u300_gpio *gpio = to_u300_gpio(chip); |
a6c45b99 LW |
318 | int portno = offset >> 3; |
319 | struct u300_gpio_port *port = NULL; | |
320 | struct list_head *p; | |
321 | int retirq; | |
cc890cd7 | 322 | |
a6c45b99 LW |
323 | list_for_each(p, &gpio->port_list) { |
324 | port = list_entry(p, struct u300_gpio_port, node); | |
325 | if (port->number == portno) | |
326 | break; | |
327 | } | |
328 | if (port == NULL) { | |
329 | dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n", | |
330 | offset); | |
331 | return -EINVAL; | |
332 | } | |
333 | ||
334 | /* | |
335 | * The local hwirqs on the port are the lower three bits, there | |
336 | * are exactly 8 IRQs per port since they are 8-bit | |
337 | */ | |
338 | retirq = irq_find_mapping(port->domain, (offset & 0x7)); | |
339 | ||
340 | dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n", | |
341 | offset, retirq, port->number); | |
cc890cd7 LW |
342 | return retirq; |
343 | } | |
344 | ||
dc0b1aa3 LW |
345 | /* Returning -EINVAL means "supported but not available" */ |
346 | int u300_gpio_config_get(struct gpio_chip *chip, | |
347 | unsigned offset, | |
348 | unsigned long *config) | |
349 | { | |
350 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
351 | enum pin_config_param param = (enum pin_config_param) *config; | |
352 | bool biasmode; | |
353 | u32 drmode; | |
354 | ||
355 | /* One bit per pin, clamp to bool range */ | |
356 | biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); | |
357 | ||
358 | /* Mask out the two bits for this pin and shift to bits 0,1 */ | |
359 | drmode = readl(U300_PIN_REG(offset, pcr)); | |
360 | drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
361 | drmode >>= ((offset & 0x07) << 1); | |
362 | ||
363 | switch(param) { | |
364 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
365 | *config = 0; | |
366 | if (biasmode) | |
367 | return 0; | |
368 | else | |
369 | return -EINVAL; | |
370 | break; | |
371 | case PIN_CONFIG_BIAS_PULL_UP: | |
372 | *config = 0; | |
373 | if (!biasmode) | |
374 | return 0; | |
375 | else | |
376 | return -EINVAL; | |
377 | break; | |
378 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
379 | *config = 0; | |
380 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) | |
381 | return 0; | |
382 | else | |
383 | return -EINVAL; | |
384 | break; | |
385 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
386 | *config = 0; | |
387 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) | |
388 | return 0; | |
389 | else | |
390 | return -EINVAL; | |
391 | break; | |
392 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: | |
393 | *config = 0; | |
394 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) | |
395 | return 0; | |
396 | else | |
397 | return -EINVAL; | |
398 | break; | |
399 | default: | |
400 | break; | |
401 | } | |
402 | return -ENOTSUPP; | |
403 | } | |
404 | ||
405 | int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, | |
406 | enum pin_config_param param) | |
cc890cd7 LW |
407 | { |
408 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
bd41b99d LW |
409 | unsigned long flags; |
410 | u32 val; | |
411 | ||
bd41b99d | 412 | local_irq_save(flags); |
cc890cd7 | 413 | switch (param) { |
a050b3ee LW |
414 | case PIN_CONFIG_BIAS_DISABLE: |
415 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
cc890cd7 LW |
416 | val = readl(U300_PIN_REG(offset, per)); |
417 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
418 | break; | |
a050b3ee | 419 | case PIN_CONFIG_BIAS_PULL_UP: |
cc890cd7 LW |
420 | val = readl(U300_PIN_REG(offset, per)); |
421 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
422 | break; | |
a050b3ee | 423 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
cc890cd7 LW |
424 | val = readl(U300_PIN_REG(offset, pcr)); |
425 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
426 | << ((offset & 0x07) << 1)); | |
427 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
428 | << ((offset & 0x07) << 1)); | |
429 | writel(val, U300_PIN_REG(offset, pcr)); | |
430 | break; | |
a050b3ee | 431 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
cc890cd7 LW |
432 | val = readl(U300_PIN_REG(offset, pcr)); |
433 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
434 | << ((offset & 0x07) << 1)); | |
435 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN | |
436 | << ((offset & 0x07) << 1)); | |
437 | writel(val, U300_PIN_REG(offset, pcr)); | |
438 | break; | |
a050b3ee | 439 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
cc890cd7 LW |
440 | val = readl(U300_PIN_REG(offset, pcr)); |
441 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
442 | << ((offset & 0x07) << 1)); | |
443 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE | |
444 | << ((offset & 0x07) << 1)); | |
445 | writel(val, U300_PIN_REG(offset, pcr)); | |
446 | break; | |
447 | default: | |
448 | local_irq_restore(flags); | |
449 | dev_err(gpio->dev, "illegal configuration requested\n"); | |
450 | return -EINVAL; | |
451 | } | |
bd41b99d LW |
452 | local_irq_restore(flags); |
453 | return 0; | |
454 | } | |
bd41b99d | 455 | |
cc890cd7 LW |
456 | static struct gpio_chip u300_gpio_chip = { |
457 | .label = "u300-gpio-chip", | |
458 | .owner = THIS_MODULE, | |
b4e3ac74 LW |
459 | .request = u300_gpio_request, |
460 | .free = u300_gpio_free, | |
cc890cd7 LW |
461 | .get = u300_gpio_get, |
462 | .set = u300_gpio_set, | |
463 | .direction_input = u300_gpio_direction_input, | |
464 | .direction_output = u300_gpio_direction_output, | |
465 | .to_irq = u300_gpio_to_irq, | |
466 | }; | |
467 | ||
468 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) | |
bd41b99d | 469 | { |
bd41b99d LW |
470 | u32 val; |
471 | ||
cc890cd7 LW |
472 | val = readl(U300_PIN_REG(offset, icr)); |
473 | /* Set mode depending on state */ | |
474 | if (u300_gpio_get(&gpio->chip, offset)) { | |
475 | /* High now, let's trigger on falling edge next then */ | |
476 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
477 | dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", | |
478 | offset); | |
479 | } else { | |
480 | /* Low now, let's trigger on rising edge next then */ | |
481 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
482 | dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", | |
483 | offset); | |
484 | } | |
bd41b99d | 485 | } |
bd41b99d | 486 | |
cc890cd7 | 487 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
bd41b99d | 488 | { |
cc890cd7 LW |
489 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
490 | struct u300_gpio *gpio = port->gpio; | |
a6c45b99 | 491 | int offset = (port->number << 3) + d->hwirq; |
bd41b99d | 492 | u32 val; |
bd41b99d | 493 | |
cc890cd7 LW |
494 | if ((trigger & IRQF_TRIGGER_RISING) && |
495 | (trigger & IRQF_TRIGGER_FALLING)) { | |
496 | /* | |
497 | * The GPIO block can only trigger on falling OR rising edges, | |
498 | * not both. So we need to toggle the mode whenever the pin | |
499 | * goes from one state to the other with a special state flag | |
500 | */ | |
501 | dev_dbg(gpio->dev, | |
502 | "trigger on both rising and falling edge on pin %d\n", | |
503 | offset); | |
504 | port->toggle_edge_mode |= U300_PIN_BIT(offset); | |
505 | u300_toggle_trigger(gpio, offset); | |
506 | } else if (trigger & IRQF_TRIGGER_RISING) { | |
507 | dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", | |
508 | offset); | |
509 | val = readl(U300_PIN_REG(offset, icr)); | |
510 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
511 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
512 | } else if (trigger & IRQF_TRIGGER_FALLING) { | |
513 | dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", | |
514 | offset); | |
515 | val = readl(U300_PIN_REG(offset, icr)); | |
516 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
517 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
518 | } | |
519 | ||
520 | return 0; | |
bd41b99d | 521 | } |
bd41b99d | 522 | |
cc890cd7 | 523 | static void u300_gpio_irq_enable(struct irq_data *d) |
bd41b99d | 524 | { |
cc890cd7 LW |
525 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
526 | struct u300_gpio *gpio = port->gpio; | |
a6c45b99 | 527 | int offset = (port->number << 3) + d->hwirq; |
bd41b99d LW |
528 | u32 val; |
529 | unsigned long flags; | |
530 | ||
a6c45b99 LW |
531 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", |
532 | d->hwirq, port->name, offset); | |
bd41b99d | 533 | local_irq_save(flags); |
cc890cd7 LW |
534 | val = readl(U300_PIN_REG(offset, ien)); |
535 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
536 | local_irq_restore(flags); |
537 | } | |
bd41b99d | 538 | |
cc890cd7 | 539 | static void u300_gpio_irq_disable(struct irq_data *d) |
bd41b99d | 540 | { |
cc890cd7 LW |
541 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
542 | struct u300_gpio *gpio = port->gpio; | |
a6c45b99 | 543 | int offset = (port->number << 3) + d->hwirq; |
bd41b99d LW |
544 | u32 val; |
545 | unsigned long flags; | |
546 | ||
547 | local_irq_save(flags); | |
cc890cd7 LW |
548 | val = readl(U300_PIN_REG(offset, ien)); |
549 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
550 | local_irq_restore(flags); |
551 | } | |
bd41b99d | 552 | |
cc890cd7 LW |
553 | static struct irq_chip u300_gpio_irqchip = { |
554 | .name = "u300-gpio-irqchip", | |
555 | .irq_enable = u300_gpio_irq_enable, | |
556 | .irq_disable = u300_gpio_irq_disable, | |
557 | .irq_set_type = u300_gpio_irq_type, | |
558 | ||
559 | }; | |
560 | ||
561 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
bd41b99d | 562 | { |
cc890cd7 LW |
563 | struct u300_gpio_port *port = irq_get_handler_data(irq); |
564 | struct u300_gpio *gpio = port->gpio; | |
565 | int pinoffset = port->number << 3; /* get the right stride */ | |
566 | unsigned long val; | |
bd41b99d | 567 | |
cc890cd7 | 568 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
bd41b99d | 569 | /* Read event register */ |
cc890cd7 | 570 | val = readl(U300_PIN_REG(pinoffset, iev)); |
bd41b99d | 571 | /* Mask relevant bits */ |
cc890cd7 | 572 | val &= 0xFFU; /* 8 bits per port */ |
bd41b99d | 573 | /* ACK IRQ (clear event) */ |
cc890cd7 LW |
574 | writel(val, U300_PIN_REG(pinoffset, iev)); |
575 | ||
576 | /* Call IRQ handler */ | |
577 | if (val != 0) { | |
578 | int irqoffset; | |
579 | ||
580 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { | |
a6c45b99 | 581 | int pin_irq = irq_find_mapping(port->domain, irqoffset); |
cc890cd7 LW |
582 | int offset = pinoffset + irqoffset; |
583 | ||
584 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", | |
585 | pin_irq, offset); | |
586 | generic_handle_irq(pin_irq); | |
587 | /* | |
588 | * Triggering IRQ on both rising and falling edge | |
589 | * needs mockery | |
590 | */ | |
591 | if (port->toggle_edge_mode & U300_PIN_BIT(offset)) | |
592 | u300_toggle_trigger(gpio, offset); | |
593 | } | |
bd41b99d | 594 | } |
cc890cd7 LW |
595 | |
596 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
bd41b99d LW |
597 | } |
598 | ||
cc890cd7 LW |
599 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
600 | int offset, | |
601 | const struct u300_gpio_confdata *conf) | |
bd41b99d | 602 | { |
cc890cd7 LW |
603 | /* Set mode: input or output */ |
604 | if (conf->output) { | |
605 | u300_gpio_direction_output(&gpio->chip, offset, conf->outval); | |
bd41b99d | 606 | |
cc890cd7 | 607 | /* Deactivate bias mode for output */ |
dc0b1aa3 LW |
608 | u300_gpio_config_set(&gpio->chip, offset, |
609 | PIN_CONFIG_BIAS_HIGH_IMPEDANCE); | |
cc890cd7 LW |
610 | |
611 | /* Set drive mode for output */ | |
dc0b1aa3 LW |
612 | u300_gpio_config_set(&gpio->chip, offset, |
613 | PIN_CONFIG_DRIVE_PUSH_PULL); | |
cc890cd7 LW |
614 | |
615 | dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", | |
616 | offset, conf->outval); | |
617 | } else { | |
618 | u300_gpio_direction_input(&gpio->chip, offset); | |
619 | ||
620 | /* Always set output low on input pins */ | |
621 | u300_gpio_set(&gpio->chip, offset, 0); | |
622 | ||
623 | /* Set bias mode for input */ | |
dc0b1aa3 | 624 | u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); |
cc890cd7 LW |
625 | |
626 | dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", | |
627 | offset, conf->bias_mode); | |
bd41b99d | 628 | } |
cc890cd7 | 629 | } |
bd41b99d | 630 | |
cc890cd7 LW |
631 | static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, |
632 | struct u300_gpio_platform *plat) | |
633 | { | |
634 | int i, j; | |
635 | ||
636 | /* Write default config and values to all pins */ | |
637 | for (i = 0; i < plat->ports; i++) { | |
638 | for (j = 0; j < 8; j++) { | |
639 | const struct u300_gpio_confdata *conf; | |
640 | int offset = (i*8) + j; | |
641 | ||
04b13de6 | 642 | conf = &bs335_gpio_config[i][j]; |
cc890cd7 | 643 | u300_gpio_init_pin(gpio, offset, conf); |
bd41b99d LW |
644 | } |
645 | } | |
cc890cd7 | 646 | } |
bd41b99d | 647 | |
cc890cd7 LW |
648 | static inline void u300_gpio_free_ports(struct u300_gpio *gpio) |
649 | { | |
650 | struct u300_gpio_port *port; | |
651 | struct list_head *p, *n; | |
652 | ||
653 | list_for_each_safe(p, n, &gpio->port_list) { | |
654 | port = list_entry(p, struct u300_gpio_port, node); | |
655 | list_del(&port->node); | |
a6c45b99 LW |
656 | if (port->domain) |
657 | irq_domain_remove(port->domain); | |
cc890cd7 | 658 | kfree(port); |
bd41b99d | 659 | } |
bd41b99d LW |
660 | } |
661 | ||
cc890cd7 | 662 | static int __init u300_gpio_probe(struct platform_device *pdev) |
bd41b99d | 663 | { |
cc890cd7 LW |
664 | struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); |
665 | struct u300_gpio *gpio; | |
bd41b99d | 666 | int err = 0; |
cc890cd7 LW |
667 | int portno; |
668 | u32 val; | |
669 | u32 ifr; | |
bd41b99d | 670 | int i; |
bd41b99d | 671 | |
cc890cd7 LW |
672 | gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL); |
673 | if (gpio == NULL) { | |
674 | dev_err(&pdev->dev, "failed to allocate memory\n"); | |
675 | return -ENOMEM; | |
676 | } | |
677 | ||
678 | gpio->chip = u300_gpio_chip; | |
679 | gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; | |
cc890cd7 LW |
680 | gpio->chip.dev = &pdev->dev; |
681 | gpio->chip.base = plat->gpio_base; | |
682 | gpio->dev = &pdev->dev; | |
bd41b99d LW |
683 | |
684 | /* Get GPIO clock */ | |
cc890cd7 LW |
685 | gpio->clk = clk_get(gpio->dev, NULL); |
686 | if (IS_ERR(gpio->clk)) { | |
687 | err = PTR_ERR(gpio->clk); | |
688 | dev_err(gpio->dev, "could not get GPIO clock\n"); | |
bd41b99d LW |
689 | goto err_no_clk; |
690 | } | |
27e8461c | 691 | err = clk_prepare_enable(gpio->clk); |
bd41b99d | 692 | if (err) { |
cc890cd7 | 693 | dev_err(gpio->dev, "could not enable GPIO clock\n"); |
bd41b99d LW |
694 | goto err_no_clk_enable; |
695 | } | |
696 | ||
cc890cd7 LW |
697 | gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
698 | if (!gpio->memres) { | |
699 | dev_err(gpio->dev, "could not get GPIO memory resource\n"); | |
700 | err = -ENODEV; | |
bd41b99d | 701 | goto err_no_resource; |
cc890cd7 | 702 | } |
bd41b99d | 703 | |
cc890cd7 LW |
704 | if (!request_mem_region(gpio->memres->start, |
705 | resource_size(gpio->memres), | |
28f65c11 | 706 | "GPIO Controller")) { |
bd41b99d LW |
707 | err = -ENODEV; |
708 | goto err_no_ioregion; | |
709 | } | |
710 | ||
cc890cd7 LW |
711 | gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres)); |
712 | if (!gpio->base) { | |
bd41b99d LW |
713 | err = -ENOMEM; |
714 | goto err_no_ioremap; | |
715 | } | |
cc890cd7 | 716 | |
04b13de6 LW |
717 | dev_info(gpio->dev, |
718 | "initializing GPIO Controller COH 901 571/3\n"); | |
719 | gpio->stride = U300_GPIO_PORT_STRIDE; | |
720 | gpio->pcr = U300_GPIO_PXPCR; | |
721 | gpio->dor = U300_GPIO_PXPDOR; | |
722 | gpio->dir = U300_GPIO_PXPDIR; | |
723 | gpio->per = U300_GPIO_PXPER; | |
724 | gpio->icr = U300_GPIO_PXICR; | |
725 | gpio->ien = U300_GPIO_PXIEN; | |
726 | gpio->iev = U300_GPIO_PXIEV; | |
727 | ifr = U300_GPIO_PXIFR; | |
728 | ||
729 | val = readl(gpio->base + U300_GPIO_CR); | |
730 | dev_info(gpio->dev, "COH901571/3 block version: %d, " \ | |
731 | "number of cores: %d totalling %d pins\n", | |
732 | ((val & 0x000001FC) >> 2), | |
733 | ((val & 0x0000FE00) >> 9), | |
734 | ((val & 0x0000FE00) >> 9) * 8); | |
735 | writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, | |
736 | gpio->base + U300_GPIO_CR); | |
737 | u300_gpio_init_coh901571(gpio, plat); | |
cc890cd7 LW |
738 | |
739 | /* Add each port with its IRQ separately */ | |
740 | INIT_LIST_HEAD(&gpio->port_list); | |
741 | for (portno = 0 ; portno < plat->ports; portno++) { | |
742 | struct u300_gpio_port *port = | |
743 | kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); | |
744 | ||
745 | if (!port) { | |
746 | dev_err(gpio->dev, "out of memory\n"); | |
747 | err = -ENOMEM; | |
748 | goto err_no_port; | |
bd41b99d | 749 | } |
cc890cd7 LW |
750 | |
751 | snprintf(port->name, 8, "gpio%d", portno); | |
752 | port->number = portno; | |
753 | port->gpio = gpio; | |
754 | ||
755 | port->irq = platform_get_irq_byname(pdev, | |
756 | port->name); | |
757 | ||
a6c45b99 | 758 | dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, |
cc890cd7 LW |
759 | port->name); |
760 | ||
a6c45b99 LW |
761 | port->domain = irq_domain_add_linear(pdev->dev.of_node, |
762 | U300_GPIO_PINS_PER_PORT, | |
763 | &irq_domain_simple_ops, | |
764 | port); | |
765 | if (!port->domain) | |
766 | goto err_no_domain; | |
767 | ||
cc890cd7 LW |
768 | irq_set_chained_handler(port->irq, u300_gpio_irq_handler); |
769 | irq_set_handler_data(port->irq, port); | |
770 | ||
771 | /* For each GPIO pin set the unique IRQ handler */ | |
772 | for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) { | |
a6c45b99 | 773 | int irqno = irq_create_mapping(port->domain, i); |
cc890cd7 | 774 | |
a6c45b99 LW |
775 | dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n", |
776 | gpio->chip.base + (port->number << 3) + i, | |
777 | port->name, irqno); | |
cc890cd7 LW |
778 | irq_set_chip_and_handler(irqno, &u300_gpio_irqchip, |
779 | handle_simple_irq); | |
780 | set_irq_flags(irqno, IRQF_VALID); | |
781 | irq_set_chip_data(irqno, port); | |
782 | } | |
783 | ||
784 | /* Turns off irq force (test register) for this port */ | |
785 | writel(0x0, gpio->base + portno * gpio->stride + ifr); | |
786 | ||
787 | list_add_tail(&port->node, &gpio->port_list); | |
bd41b99d | 788 | } |
cc890cd7 LW |
789 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
790 | ||
791 | err = gpiochip_add(&gpio->chip); | |
792 | if (err) { | |
793 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); | |
794 | goto err_no_chip; | |
795 | } | |
796 | ||
128a06d4 LW |
797 | /* Spawn pin controller device as child of the GPIO, pass gpio chip */ |
798 | plat->pinctrl_device->dev.platform_data = &gpio->chip; | |
799 | err = platform_device_register(plat->pinctrl_device); | |
800 | if (err) | |
801 | goto err_no_pinctrl; | |
802 | ||
cc890cd7 | 803 | platform_set_drvdata(pdev, gpio); |
bd41b99d LW |
804 | |
805 | return 0; | |
806 | ||
128a06d4 LW |
807 | err_no_pinctrl: |
808 | err = gpiochip_remove(&gpio->chip); | |
cc890cd7 | 809 | err_no_chip: |
a6c45b99 | 810 | err_no_domain: |
cc890cd7 LW |
811 | err_no_port: |
812 | u300_gpio_free_ports(gpio); | |
cc890cd7 LW |
813 | iounmap(gpio->base); |
814 | err_no_ioremap: | |
815 | release_mem_region(gpio->memres->start, resource_size(gpio->memres)); | |
816 | err_no_ioregion: | |
817 | err_no_resource: | |
27e8461c | 818 | clk_disable_unprepare(gpio->clk); |
cc890cd7 LW |
819 | err_no_clk_enable: |
820 | clk_put(gpio->clk); | |
821 | err_no_clk: | |
822 | kfree(gpio); | |
823 | dev_info(&pdev->dev, "module ERROR:%d\n", err); | |
bd41b99d LW |
824 | return err; |
825 | } | |
826 | ||
cc890cd7 | 827 | static int __exit u300_gpio_remove(struct platform_device *pdev) |
bd41b99d | 828 | { |
cc890cd7 LW |
829 | struct u300_gpio *gpio = platform_get_drvdata(pdev); |
830 | int err; | |
bd41b99d LW |
831 | |
832 | /* Turn off the GPIO block */ | |
04b13de6 | 833 | writel(0x00000000U, gpio->base + U300_GPIO_CR); |
cc890cd7 LW |
834 | |
835 | err = gpiochip_remove(&gpio->chip); | |
836 | if (err < 0) { | |
837 | dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); | |
838 | return err; | |
839 | } | |
840 | u300_gpio_free_ports(gpio); | |
841 | iounmap(gpio->base); | |
842 | release_mem_region(gpio->memres->start, | |
843 | resource_size(gpio->memres)); | |
27e8461c | 844 | clk_disable_unprepare(gpio->clk); |
cc890cd7 LW |
845 | clk_put(gpio->clk); |
846 | platform_set_drvdata(pdev, NULL); | |
847 | kfree(gpio); | |
bd41b99d LW |
848 | return 0; |
849 | } | |
850 | ||
cc890cd7 | 851 | static struct platform_driver u300_gpio_driver = { |
bd41b99d LW |
852 | .driver = { |
853 | .name = "u300-gpio", | |
854 | }, | |
cc890cd7 | 855 | .remove = __exit_p(u300_gpio_remove), |
bd41b99d LW |
856 | }; |
857 | ||
bd41b99d LW |
858 | static int __init u300_gpio_init(void) |
859 | { | |
cc890cd7 | 860 | return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); |
bd41b99d LW |
861 | } |
862 | ||
863 | static void __exit u300_gpio_exit(void) | |
864 | { | |
cc890cd7 | 865 | platform_driver_unregister(&u300_gpio_driver); |
bd41b99d LW |
866 | } |
867 | ||
868 | arch_initcall(u300_gpio_init); | |
869 | module_exit(u300_gpio_exit); | |
870 | ||
871 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
cc890cd7 | 872 | MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); |
bd41b99d | 873 | MODULE_LICENSE("GPL"); |