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drivers/pinctrl/pinctrl-at91.c: convert kfree to devm_kfree
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-at91.c
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6732ae5c
JCPV		 1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/slab.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
6732ae5c
JCPV		 23#include <linux/pinctrl/machine.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27/* Since we request GPIOs from ourself */
28#include <linux/pinctrl/consumer.h>
29
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h>
33#include <mach/at91_pio.h>
34
35#include "core.h"
36
37#define MAX_NB_GPIO_PER_BANK 32
38
39struct at91_pinctrl_mux_ops;
40
41struct at91_gpio_chip {
42 struct gpio_chip chip;
43 struct pinctrl_gpio_range range;
44 struct at91_gpio_chip *next; /* Bank sharing same clock */
45 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
46 int pioc_virq; /* PIO bank Linux virtual interrupt */
47 int pioc_idx; /* PIO bank index */
48 void __iomem *regbase; /* PIO bank virtual address */
49 struct clk *clock; /* associated clock */
50 struct irq_domain *domain; /* associated irq domain */
51 struct at91_pinctrl_mux_ops *ops; /* ops */
52};
53
54#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
55
56static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
57
58static int gpio_banks;
59
525fae21 60#define PULL_UP (1 << 0)
6732ae5c 61#define MULTI_DRIVE (1 << 1)
7ebd7a3a
JCPV		 62#define DEGLITCH (1 << 2)
63#define PULL_DOWN (1 << 3)
64#define DIS_SCHMIT (1 << 4)
65#define DEBOUNCE (1 << 16)
66#define DEBOUNCE_VAL_SHIFT 17
67#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
6732ae5c
JCPV		 68
69/**
70 * struct at91_pmx_func - describes AT91 pinmux functions
71 * @name: the name of this specific function
72 * @groups: corresponding pin groups
73 * @ngroups: the number of groups
74 */
75struct at91_pmx_func {
76 const char *name;
77 const char **groups;
78 unsigned ngroups;
79};
80
81enum at91_mux {
82 AT91_MUX_GPIO = 0,
83 AT91_MUX_PERIPH_A = 1,
84 AT91_MUX_PERIPH_B = 2,
85 AT91_MUX_PERIPH_C = 3,
86 AT91_MUX_PERIPH_D = 4,
87};
88
89/**
90 * struct at91_pmx_pin - describes an At91 pin mux
91 * @bank: the bank of the pin
92 * @pin: the pin number in the @bank
93 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
94 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
95 */
96struct at91_pmx_pin {
97 uint32_t bank;
98 uint32_t pin;
99 enum at91_mux mux;
100 unsigned long conf;
101};
102
103/**
104 * struct at91_pin_group - describes an At91 pin group
105 * @name: the name of this specific pin group
106 * @pins_conf: the mux mode for each pin in this group. The size of this
107 * array is the same as pins.
108 * @pins: an array of discrete physical pins used in this group, taken
109 * from the driver-local pin enumeration space
110 * @npins: the number of pins in this group array, i.e. the number of
111 * elements in .pins so we can iterate over that array
112 */
113struct at91_pin_group {
114 const char *name;
115 struct at91_pmx_pin *pins_conf;
116 unsigned int *pins;
117 unsigned npins;
118};
119
120/**
121 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
122 * on new IP with support for periph C and D the way to mux in
123 * periph A and B has changed
124 * So provide the right call back
125 * if not present means the IP does not support it
126 * @get_periph: return the periph mode configured
127 * @mux_A_periph: mux as periph A
128 * @mux_B_periph: mux as periph B
129 * @mux_C_periph: mux as periph C
130 * @mux_D_periph: mux as periph D
7ebd7a3a
JCPV		 131 * @get_deglitch: get deglitch status
132 * @set_deglitch: enable/disable deglitch
133 * @get_debounce: get debounce status
134 * @set_debounce: enable/disable debounce
135 * @get_pulldown: get pulldown status
136 * @set_pulldown: enable/disable pulldown
137 * @get_schmitt_trig: get schmitt trigger status
138 * @disable_schmitt_trig: disable schmitt trigger
6732ae5c
JCPV		 139 * @irq_type: return irq type
140 */
141struct at91_pinctrl_mux_ops {
142 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
146 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
7ebd7a3a
JCPV		 147 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
148 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
149 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
150 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
151 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
152 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
153 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
154 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
6732ae5c
JCPV		 155 /* irq */
156 int (*irq_type)(struct irq_data *d, unsigned type);
157};
158
159static int gpio_irq_type(struct irq_data *d, unsigned type);
160static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
161
162struct at91_pinctrl {
163 struct device *dev;
164 struct pinctrl_dev *pctl;
165
166 int nbanks;
167
168 uint32_t *mux_mask;
169 int nmux;
170
171 struct at91_pmx_func *functions;
172 int nfunctions;
173
174 struct at91_pin_group *groups;
175 int ngroups;
176
177 struct at91_pinctrl_mux_ops *ops;
178};
179
180static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
181 const struct at91_pinctrl *info,
182 const char *name)
183{
184 const struct at91_pin_group *grp = NULL;
185 int i;
186
187 for (i = 0; i < info->ngroups; i++) {
188 if (strcmp(info->groups[i].name, name))
189 continue;
190
191 grp = &info->groups[i];
192 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
193 break;
194 }
195
196 return grp;
197}
198
199static int at91_get_groups_count(struct pinctrl_dev *pctldev)
200{
201 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
202
203 return info->ngroups;
204}
205
206static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
207 unsigned selector)
208{
209 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
210
211 return info->groups[selector].name;
212}
213
214static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
215 const unsigned **pins,
216 unsigned *npins)
217{
218 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
219
220 if (selector >= info->ngroups)
221 return -EINVAL;
222
223 *pins = info->groups[selector].pins;
224 *npins = info->groups[selector].npins;
225
226 return 0;
227}
228
229static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
230 unsigned offset)
231{
232 seq_printf(s, "%s", dev_name(pctldev->dev));
233}
234
235static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
236 struct device_node *np,
237 struct pinctrl_map **map, unsigned *num_maps)
238{
239 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
240 const struct at91_pin_group *grp;
241 struct pinctrl_map *new_map;
242 struct device_node *parent;
243 int map_num = 1;
244 int i;
6732ae5c
JCPV		 245
246 /*
247 * first find the group of this node and check if we need create
248 * config maps for pins
249 */
250 grp = at91_pinctrl_find_group_by_name(info, np->name);
251 if (!grp) {
252 dev_err(info->dev, "unable to find group for node %s\n",
253 np->name);
254 return -EINVAL;
255 }
256
257 map_num += grp->npins;
258 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
259 if (!new_map)
260 return -ENOMEM;
261
262 *map = new_map;
263 *num_maps = map_num;
264
265 /* create mux map */
266 parent = of_get_parent(np);
267 if (!parent) {
c62b2b34 268 devm_kfree(pctldev->dev, new_map);
6732ae5c
JCPV		 269 return -EINVAL;
270 }
271 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
272 new_map[0].data.mux.function = parent->name;
273 new_map[0].data.mux.group = np->name;
274 of_node_put(parent);
275
276 /* create config map */
277 new_map++;
278 for (i = 0; i < grp->npins; i++) {
6732ae5c
JCPV		 279 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
280 new_map[i].data.configs.group_or_pin =
281 pin_get_name(pctldev, grp->pins[i]);
282 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
283 new_map[i].data.configs.num_configs = 1;
284 }
285
286 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
287 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
288
289 return 0;
290}
291
292static void at91_dt_free_map(struct pinctrl_dev *pctldev,
293 struct pinctrl_map *map, unsigned num_maps)
294{
295}
296
297static struct pinctrl_ops at91_pctrl_ops = {
298 .get_groups_count = at91_get_groups_count,
299 .get_group_name = at91_get_group_name,
300 .get_group_pins = at91_get_group_pins,
301 .pin_dbg_show = at91_pin_dbg_show,
302 .dt_node_to_map = at91_dt_node_to_map,
303 .dt_free_map = at91_dt_free_map,
304};
305
306static void __iomem * pin_to_controller(struct at91_pinctrl *info,
307 unsigned int bank)
308{
309 return gpio_chips[bank]->regbase;
310}
311
312static inline int pin_to_bank(unsigned pin)
313{
314 return pin /= MAX_NB_GPIO_PER_BANK;
315}
316
317static unsigned pin_to_mask(unsigned int pin)
318{
319 return 1 << pin;
320}
321
322static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
323{
324 writel_relaxed(mask, pio + PIO_IDR);
325}
326
327static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
328{
329 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
330}
331
332static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
333{
334 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
335}
336
337static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
338{
339 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
340}
341
342static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
343{
344 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
345}
346
347static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
348{
349 writel_relaxed(mask, pio + PIO_ASR);
350}
351
352static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
353{
354 writel_relaxed(mask, pio + PIO_BSR);
355}
356
357static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
358{
359
360 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
361 pio + PIO_ABCDSR1);
362 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
363 pio + PIO_ABCDSR2);
364}
365
366static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
367{
368 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
369 pio + PIO_ABCDSR1);
370 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
371 pio + PIO_ABCDSR2);
372}
373
374static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
375{
376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
377 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
378}
379
380static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
381{
382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
383 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
384}
385
386static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
387{
388 unsigned select;
389
390 if (readl_relaxed(pio + PIO_PSR) & mask)
391 return AT91_MUX_GPIO;
392
393 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
394 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
395
396 return select + 1;
397}
398
399static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
400{
401 unsigned select;
402
403 if (readl_relaxed(pio + PIO_PSR) & mask)
404 return AT91_MUX_GPIO;
405
406 select = readl_relaxed(pio + PIO_ABSR) & mask;
407
408 return select + 1;
409}
410
7ebd7a3a
JCPV		 411static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
412{
413 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
414}
415
416static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
417{
418 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
419}
420
421static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
422{
423 if (is_on)
424 __raw_writel(mask, pio + PIO_IFSCDR);
425 at91_mux_set_deglitch(pio, mask, is_on);
426}
427
428static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
429{
430 *div = __raw_readl(pio + PIO_SCDR);
431
432 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
433}
434
435static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
436 bool is_on, u32 div)
437{
438 if (is_on) {
439 __raw_writel(mask, pio + PIO_IFSCER);
440 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
441 __raw_writel(mask, pio + PIO_IFER);
442 } else {
443 __raw_writel(mask, pio + PIO_IFDR);
444 }
445}
446
447static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
448{
449 return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
450}
451
452static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
453{
454 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
455}
456
457static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
458{
459 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
460}
461
462static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
463{
464 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
465}
466
6732ae5c
JCPV		 467static struct at91_pinctrl_mux_ops at91rm9200_ops = {
468 .get_periph = at91_mux_get_periph,
469 .mux_A_periph = at91_mux_set_A_periph,
470 .mux_B_periph = at91_mux_set_B_periph,
7ebd7a3a
JCPV		 471 .get_deglitch = at91_mux_get_deglitch,
472 .set_deglitch = at91_mux_set_deglitch,
6732ae5c
JCPV		 473 .irq_type = gpio_irq_type,
474};
475
476static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
477 .get_periph = at91_mux_pio3_get_periph,
478 .mux_A_periph = at91_mux_pio3_set_A_periph,
479 .mux_B_periph = at91_mux_pio3_set_B_periph,
480 .mux_C_periph = at91_mux_pio3_set_C_periph,
481 .mux_D_periph = at91_mux_pio3_set_D_periph,
7ebd7a3a
JCPV		 482 .get_deglitch = at91_mux_get_deglitch,
483 .set_deglitch = at91_mux_pio3_set_deglitch,
484 .get_debounce = at91_mux_pio3_get_debounce,
485 .set_debounce = at91_mux_pio3_set_debounce,
486 .get_pulldown = at91_mux_pio3_get_pulldown,
487 .set_pulldown = at91_mux_pio3_set_pulldown,
488 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
489 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
6732ae5c
JCPV		 490 .irq_type = alt_gpio_irq_type,
491};
492
493static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
494{
495 if (pin->mux) {
496 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
497 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
498 } else {
499 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
500 pin->bank + 'A', pin->pin, pin->conf);
501 }
502}
503
504static int pin_check_config(struct at91_pinctrl *info, const char* name,
505 int index, const struct at91_pmx_pin *pin)
506{
507 int mux;
508
509 /* check if it's a valid config */
510 if (pin->bank >= info->nbanks) {
511 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
512 name, index, pin->bank, info->nbanks);
513 return -EINVAL;
514 }
515
516 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
517 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
518 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
519 return -EINVAL;
520 }
521
522 if (!pin->mux)
523 return 0;
524
525 mux = pin->mux - 1;
526
527 if (mux >= info->nmux) {
528 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
529 name, index, mux, info->nmux);
530 return -EINVAL;
531 }
532
533 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
534 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
535 name, index, mux, pin->bank + 'A', pin->pin);
536 return -EINVAL;
537 }
538
539 return 0;
540}
541
542static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
543{
544 writel_relaxed(mask, pio + PIO_PDR);
545}
546
547static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
548{
549 writel_relaxed(mask, pio + PIO_PER);
550 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
551}
552
553static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
554 unsigned group)
555{
556 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
557 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
558 const struct at91_pmx_pin *pin;
559 uint32_t npins = info->groups[group].npins;
560 int i, ret;
561 unsigned mask;
562 void __iomem *pio;
563
564 dev_dbg(info->dev, "enable function %s group %s\n",
565 info->functions[selector].name, info->groups[group].name);
566
567 /* first check that all the pins of the group are valid with a valid
568 * paramter */
569 for (i = 0; i < npins; i++) {
570 pin = &pins_conf[i];
571 ret = pin_check_config(info, info->groups[group].name, i, pin);
572 if (ret)
573 return ret;
574 }
575
576 for (i = 0; i < npins; i++) {
577 pin = &pins_conf[i];
578 at91_pin_dbg(info->dev, pin);
579 pio = pin_to_controller(info, pin->bank);
580 mask = pin_to_mask(pin->pin);
581 at91_mux_disable_interrupt(pio, mask);
582 switch(pin->mux) {
583 case AT91_MUX_GPIO:
584 at91_mux_gpio_enable(pio, mask, 1);
585 break;
586 case AT91_MUX_PERIPH_A:
587 info->ops->mux_A_periph(pio, mask);
588 break;
589 case AT91_MUX_PERIPH_B:
590 info->ops->mux_B_periph(pio, mask);
591 break;
592 case AT91_MUX_PERIPH_C:
593 if (!info->ops->mux_C_periph)
594 return -EINVAL;
595 info->ops->mux_C_periph(pio, mask);
596 break;
597 case AT91_MUX_PERIPH_D:
598 if (!info->ops->mux_D_periph)
599 return -EINVAL;
600 info->ops->mux_D_periph(pio, mask);
601 break;
602 }
603 if (pin->mux)
604 at91_mux_gpio_disable(pio, mask);
605 }
606
607 return 0;
608}
609
610static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
611 unsigned group)
612{
613 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
614 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
615 const struct at91_pmx_pin *pin;
616 uint32_t npins = info->groups[group].npins;
617 int i;
618 unsigned mask;
619 void __iomem *pio;
620
621 for (i = 0; i < npins; i++) {
622 pin = &pins_conf[i];
623 at91_pin_dbg(info->dev, pin);
624 pio = pin_to_controller(info, pin->bank);
625 mask = pin_to_mask(pin->pin);
626 at91_mux_gpio_enable(pio, mask, 1);
627 }
628}
629
630static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
631{
632 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
633
634 return info->nfunctions;
635}
636
637static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
638 unsigned selector)
639{
640 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
641
642 return info->functions[selector].name;
643}
644
645static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
646 const char * const **groups,
647 unsigned * const num_groups)
648{
649 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
650
651 *groups = info->functions[selector].groups;
652 *num_groups = info->functions[selector].ngroups;
653
654 return 0;
655}
656
f6f94f66
AL		 657static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
658 struct pinctrl_gpio_range *range,
659 unsigned offset)
6732ae5c
JCPV		 660{
661 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
662 struct at91_gpio_chip *at91_chip;
663 struct gpio_chip *chip;
664 unsigned mask;
665
666 if (!range) {
667 dev_err(npct->dev, "invalid range\n");
668 return -EINVAL;
669 }
670 if (!range->gc) {
671 dev_err(npct->dev, "missing GPIO chip in range\n");
672 return -EINVAL;
673 }
674 chip = range->gc;
675 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
676
677 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
678
679 mask = 1 << (offset - chip->base);
680
681 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
682 offset, 'A' + range->id, offset - chip->base, mask);
683
684 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
685
686 return 0;
687}
688
f6f94f66
AL		 689static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
690 struct pinctrl_gpio_range *range,
691 unsigned offset)
6732ae5c
JCPV		 692{
693 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
694
695 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
696 /* Set the pin to some default state, GPIO is usually default */
697}
698
699static struct pinmux_ops at91_pmx_ops = {
700 .get_functions_count = at91_pmx_get_funcs_count,
701 .get_function_name = at91_pmx_get_func_name,
702 .get_function_groups = at91_pmx_get_groups,
703 .enable = at91_pmx_enable,
704 .disable = at91_pmx_disable,
705 .gpio_request_enable = at91_gpio_request_enable,
706 .gpio_disable_free = at91_gpio_disable_free,
707};
708
709static int at91_pinconf_get(struct pinctrl_dev *pctldev,
710 unsigned pin_id, unsigned long *config)
711{
712 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
713 void __iomem *pio;
714 unsigned pin;
7ebd7a3a 715 int div;
6732ae5c
JCPV		 716
717 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
718 pio = pin_to_controller(info, pin_to_bank(pin_id));
719 pin = pin_id % MAX_NB_GPIO_PER_BANK;
720
721 if (at91_mux_get_multidrive(pio, pin))
722 *config |= MULTI_DRIVE;
723
724 if (at91_mux_get_pullup(pio, pin))
725 *config |= PULL_UP;
726
7ebd7a3a
JCPV		 727 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
728 *config |= DEGLITCH;
729 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
730 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
731 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
732 *config |= PULL_DOWN;
733 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
734 *config |= DIS_SCHMIT;
735
6732ae5c
JCPV		 736 return 0;
737}
738
739static int at91_pinconf_set(struct pinctrl_dev *pctldev,
740 unsigned pin_id, unsigned long config)
741{
742 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
743 unsigned mask;
744 void __iomem *pio;
745
746 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
747 pio = pin_to_controller(info, pin_to_bank(pin_id));
748 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
749
7ebd7a3a
JCPV		 750 if (config & PULL_UP && config & PULL_DOWN)
751 return -EINVAL;
752
6732ae5c
JCPV		 753 at91_mux_set_pullup(pio, mask, config & PULL_UP);
754 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
7ebd7a3a
JCPV		 755 if (info->ops->set_deglitch)
756 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
757 if (info->ops->set_debounce)
758 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
759 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
760 if (info->ops->set_pulldown)
761 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
762 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
763 info->ops->disable_schmitt_trig(pio, mask);
764
6732ae5c
JCPV		 765 return 0;
766}
767
768static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
769 struct seq_file *s, unsigned pin_id)
770{
771
772}
773
774static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
775 struct seq_file *s, unsigned group)
776{
777}
778
6bb0700b 779static struct pinconf_ops at91_pinconf_ops = {
6732ae5c
JCPV		 780 .pin_config_get = at91_pinconf_get,
781 .pin_config_set = at91_pinconf_set,
782 .pin_config_dbg_show = at91_pinconf_dbg_show,
783 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
784};
785
786static struct pinctrl_desc at91_pinctrl_desc = {
787 .pctlops = &at91_pctrl_ops,
788 .pmxops = &at91_pmx_ops,
789 .confops = &at91_pinconf_ops,
790 .owner = THIS_MODULE,
791};
792
793static const char *gpio_compat = "atmel,at91rm9200-gpio";
794
795static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info,
796 struct device_node *np)
797{
798 struct device_node *child;
799
800 for_each_child_of_node(np, child) {
801 if (of_device_is_compatible(child, gpio_compat)) {
802 info->nbanks++;
803 } else {
804 info->nfunctions++;
805 info->ngroups += of_get_child_count(child);
806 }
807 }
808}
809
810static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info,
811 struct device_node *np)
812{
813 int ret = 0;
814 int size;
815 const const __be32 *list;
816
817 list = of_get_property(np, "atmel,mux-mask", &size);
818 if (!list) {
819 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
820 return -EINVAL;
821 }
822
823 size /= sizeof(*list);
824 if (!size || size % info->nbanks) {
825 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
826 return -EINVAL;
827 }
828 info->nmux = size / info->nbanks;
829
830 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
831 if (!info->mux_mask) {
832 dev_err(info->dev, "could not alloc mux_mask\n");
833 return -ENOMEM;
834 }
835
836 ret = of_property_read_u32_array(np, "atmel,mux-mask",
837 info->mux_mask, size);
838 if (ret)
839 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
840 return ret;
841}
842
843static int __devinit at91_pinctrl_parse_groups(struct device_node *np,
844 struct at91_pin_group *grp,
845 struct at91_pinctrl *info,
846 u32 index)
847{
848 struct at91_pmx_pin *pin;
849 int size;
850 const const __be32 *list;
851 int i, j;
852
853 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
854
855 /* Initialise group */
856 grp->name = np->name;
857
858 /*
859 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
860 * do sanity check and calculate pins number
861 */
862 list = of_get_property(np, "atmel,pins", &size);
863 /* we do not check return since it's safe node passed down */
864 size /= sizeof(*list);
865 if (!size || size % 4) {
866 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
867 return -EINVAL;
868 }
869
870 grp->npins = size / 4;
871 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
872 GFP_KERNEL);
873 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
874 GFP_KERNEL);
875 if (!grp->pins_conf || !grp->pins)
876 return -ENOMEM;
877
878 for (i = 0, j = 0; i < size; i += 4, j++) {
879 pin->bank = be32_to_cpu(*list++);
880 pin->pin = be32_to_cpu(*list++);
881 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
882 pin->mux = be32_to_cpu(*list++);
883 pin->conf = be32_to_cpu(*list++);
884
885 at91_pin_dbg(info->dev, pin);
886 pin++;
887 }
888
889 return 0;
890}
891
892static int __devinit at91_pinctrl_parse_functions(struct device_node *np,
893 struct at91_pinctrl *info, u32 index)
894{
895 struct device_node *child;
896 struct at91_pmx_func *func;
897 struct at91_pin_group *grp;
898 int ret;
899 static u32 grp_index;
900 u32 i = 0;
901
902 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
903
904 func = &info->functions[index];
905
906 /* Initialise function */
907 func->name = np->name;
908 func->ngroups = of_get_child_count(np);
909 if (func->ngroups <= 0) {
910 dev_err(info->dev, "no groups defined\n");
911 return -EINVAL;
912 }
913 func->groups = devm_kzalloc(info->dev,
914 func->ngroups * sizeof(char *), GFP_KERNEL);
915 if (!func->groups)
916 return -ENOMEM;
917
918 for_each_child_of_node(np, child) {
919 func->groups[i] = child->name;
920 grp = &info->groups[grp_index++];
921 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
922 if (ret)
923 return ret;
924 }
925
926 return 0;
927}
928
929static struct of_device_id at91_pinctrl_of_match[] __devinitdata = {
930 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
931 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
932 { /* sentinel */ }
933};
934
935static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
936 struct at91_pinctrl *info)
937{
938 int ret = 0;
939 int i, j;
940 uint32_t *tmp;
941 struct device_node *np = pdev->dev.of_node;
942 struct device_node *child;
943
944 if (!np)
945 return -ENODEV;
946
947 info->dev = &pdev->dev;
dffa9123 948 info->ops = (struct at91_pinctrl_mux_ops*)
6732ae5c
JCPV		 949 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
950 at91_pinctrl_child_count(info, np);
951
952 if (info->nbanks < 1) {
953 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
954 return -EINVAL;
955 }
956
957 ret = at91_pinctrl_mux_mask(info, np);
958 if (ret)
959 return ret;
960
961 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
962
963 dev_dbg(&pdev->dev, "mux-mask\n");
964 tmp = info->mux_mask;
965 for (i = 0; i < info->nbanks; i++) {
966 for (j = 0; j < info->nmux; j++, tmp++) {
967 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
968 }
969 }
970
971 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
972 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
973 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
974 GFP_KERNEL);
975 if (!info->functions)
976 return -ENOMEM;
977
978 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
979 GFP_KERNEL);
980 if (!info->groups)
981 return -ENOMEM;
982
983 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
984 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
985 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
986
987 i = 0;
988
989 for_each_child_of_node(np, child) {
990 if (of_device_is_compatible(child, gpio_compat))
991 continue;
992 ret = at91_pinctrl_parse_functions(child, info, i++);
993 if (ret) {
994 dev_err(&pdev->dev, "failed to parse function\n");
995 return ret;
996 }
997 }
998
999 return 0;
1000}
1001
1002static int __devinit at91_pinctrl_probe(struct platform_device *pdev)
1003{
1004 struct at91_pinctrl *info;
1005 struct pinctrl_pin_desc *pdesc;
1006 int ret, i, j ,k;
1007
1008 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1009 if (!info)
1010 return -ENOMEM;
1011
1012 ret = at91_pinctrl_probe_dt(pdev, info);
1013 if (ret)
1014 return ret;
1015
1016 /*
1017 * We need all the GPIO drivers to probe FIRST, or we will not be able
1018 * to obtain references to the struct gpio_chip * for them, and we
1019 * need this to proceed.
1020 */
1021 for (i = 0; i < info->nbanks; i++) {
1022 if (!gpio_chips[i]) {
1023 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1024 devm_kfree(&pdev->dev, info);
1025 return -EPROBE_DEFER;
1026 }
1027 }
1028
1029 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1030 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1031 at91_pinctrl_desc.pins = pdesc =
1032 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1033
1034 if (!at91_pinctrl_desc.pins)
1035 return -ENOMEM;
1036
1037 for (i = 0 , k = 0; i < info->nbanks; i++) {
1038 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1039 pdesc->number = k;
1040 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1041 pdesc++;
1042 }
1043 }
1044
1045 platform_set_drvdata(pdev, info);
1046 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1047
1048 if (!info->pctl) {
1049 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1050 ret = -EINVAL;
1051 goto err;
1052 }
1053
1054 /* We will handle a range of GPIO pins */
1055 for (i = 0; i < info->nbanks; i++)
1056 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1057
1058 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1059
1060 return 0;
1061
1062err:
1063 return ret;
1064}
1065
f6f94f66 1066static int __devexit at91_pinctrl_remove(struct platform_device *pdev)
6732ae5c
JCPV		 1067{
1068 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1069
1070 pinctrl_unregister(info->pctl);
1071
1072 return 0;
1073}
1074
1075static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1076{
1077 /*
1078 * Map back to global GPIO space and request muxing, the direction
1079 * parameter does not matter for this controller.
1080 */
1081 int gpio = chip->base + offset;
1082 int bank = chip->base / chip->ngpio;
1083
1084 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1085 'A' + bank, offset, gpio);
1086
1087 return pinctrl_request_gpio(gpio);
1088}
1089
1090static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1091{
1092 int gpio = chip->base + offset;
1093
1094 pinctrl_free_gpio(gpio);
1095}
1096
1097static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1098{
1099 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1100 void __iomem *pio = at91_gpio->regbase;
1101 unsigned mask = 1 << offset;
1102
1103 writel_relaxed(mask, pio + PIO_ODR);
1104 return 0;
1105}
1106
1107static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1108{
1109 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1110 void __iomem *pio = at91_gpio->regbase;
1111 unsigned mask = 1 << offset;
1112 u32 pdsr;
1113
1114 pdsr = readl_relaxed(pio + PIO_PDSR);
1115 return (pdsr & mask) != 0;
1116}
1117
1118static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1119 int val)
1120{
1121 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1122 void __iomem *pio = at91_gpio->regbase;
1123 unsigned mask = 1 << offset;
1124
1125 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1126}
1127
1128static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1129 int val)
1130{
1131 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1132 void __iomem *pio = at91_gpio->regbase;
1133 unsigned mask = 1 << offset;
1134
1135 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1136 writel_relaxed(mask, pio + PIO_OER);
1137
1138 return 0;
1139}
1140
1141static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1142{
1143 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1144 int virq;
1145
1146 if (offset < chip->ngpio)
1147 virq = irq_create_mapping(at91_gpio->domain, offset);
1148 else
1149 virq = -ENXIO;
1150
1151 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1152 chip->label, offset + chip->base, virq);
1153 return virq;
1154}
1155
1156#ifdef CONFIG_DEBUG_FS
1157static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1158{
1159 enum at91_mux mode;
1160 int i;
1161 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1162 void __iomem *pio = at91_gpio->regbase;
1163
1164 for (i = 0; i < chip->ngpio; i++) {
1165 unsigned pin = chip->base + i;
1166 unsigned mask = pin_to_mask(pin);
1167 const char *gpio_label;
1168 u32 pdsr;
1169
1170 gpio_label = gpiochip_is_requested(chip, i);
1171 if (!gpio_label)
1172 continue;
1173 mode = at91_gpio->ops->get_periph(pio, mask);
1174 seq_printf(s, "[%s] GPIO%s%d: ",
1175 gpio_label, chip->label, i);
1176 if (mode == AT91_MUX_GPIO) {
1177 pdsr = readl_relaxed(pio + PIO_PDSR);
1178
1179 seq_printf(s, "[gpio] %s\n",
1180 pdsr & mask ?
1181 "set" : "clear");
1182 } else {
1183 seq_printf(s, "[periph %c]\n",
1184 mode + 'A' - 1);
1185 }
1186 }
1187}
1188#else
1189#define at91_gpio_dbg_show NULL
1190#endif
1191
1192/* Several AIC controller irqs are dispatched through this GPIO handler.
1193 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1194 * at91_set_gpio_input() then maybe enable its glitch filter.
1195 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1196 * handler.
1197 * First implementation always triggers on rising and falling edges
1198 * whereas the newer PIO3 can be additionally configured to trigger on
1199 * level, edge with any polarity.
1200 *
1201 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1202 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1203 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1204 */
1205
1206static void gpio_irq_mask(struct irq_data *d)
1207{
1208 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1209 void __iomem *pio = at91_gpio->regbase;
1210 unsigned mask = 1 << d->hwirq;
1211
1212 if (pio)
1213 writel_relaxed(mask, pio + PIO_IDR);
1214}
1215
1216static void gpio_irq_unmask(struct irq_data *d)
1217{
1218 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1219 void __iomem *pio = at91_gpio->regbase;
1220 unsigned mask = 1 << d->hwirq;
1221
1222 if (pio)
1223 writel_relaxed(mask, pio + PIO_IER);
1224}
1225
1226static int gpio_irq_type(struct irq_data *d, unsigned type)
1227{
1228 switch (type) {
1229 case IRQ_TYPE_NONE:
1230 case IRQ_TYPE_EDGE_BOTH:
1231 return 0;
1232 default:
1233 return -EINVAL;
1234 }
1235}
1236
1237/* Alternate irq type for PIO3 support */
1238static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1239{
1240 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1241 void __iomem *pio = at91_gpio->regbase;
1242 unsigned mask = 1 << d->hwirq;
1243
1244 switch (type) {
1245 case IRQ_TYPE_EDGE_RISING:
1246 writel_relaxed(mask, pio + PIO_ESR);
1247 writel_relaxed(mask, pio + PIO_REHLSR);
1248 break;
1249 case IRQ_TYPE_EDGE_FALLING:
1250 writel_relaxed(mask, pio + PIO_ESR);
1251 writel_relaxed(mask, pio + PIO_FELLSR);
1252 break;
1253 case IRQ_TYPE_LEVEL_LOW:
1254 writel_relaxed(mask, pio + PIO_LSR);
1255 writel_relaxed(mask, pio + PIO_FELLSR);
1256 break;
1257 case IRQ_TYPE_LEVEL_HIGH:
1258 writel_relaxed(mask, pio + PIO_LSR);
1259 writel_relaxed(mask, pio + PIO_REHLSR);
1260 break;
1261 case IRQ_TYPE_EDGE_BOTH:
1262 /*
1263 * disable additional interrupt modes:
1264 * fall back to default behavior
1265 */
1266 writel_relaxed(mask, pio + PIO_AIMDR);
1267 return 0;
1268 case IRQ_TYPE_NONE:
1269 default:
1270 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1271 return -EINVAL;
1272 }
1273
1274 /* enable additional interrupt modes */
1275 writel_relaxed(mask, pio + PIO_AIMER);
1276
1277 return 0;
1278}
1279
1280#ifdef CONFIG_PM
1281static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1282{
1283 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1284 unsigned bank = at91_gpio->pioc_idx;
1285
1286 if (unlikely(bank >= MAX_GPIO_BANKS))
1287 return -EINVAL;
1288
1289 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1290
1291 return 0;
1292}
1293#else
1294#define gpio_irq_set_wake NULL
1295#endif
1296
1297static struct irq_chip gpio_irqchip = {
1298 .name = "GPIO",
1299 .irq_disable = gpio_irq_mask,
1300 .irq_mask = gpio_irq_mask,
1301 .irq_unmask = gpio_irq_unmask,
1302 /* .irq_set_type is set dynamically */
1303 .irq_set_wake = gpio_irq_set_wake,
1304};
1305
1306static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1307{
1308 struct irq_chip *chip = irq_desc_get_chip(desc);
1309 struct irq_data *idata = irq_desc_get_irq_data(desc);
1310 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1311 void __iomem *pio = at91_gpio->regbase;
1312 unsigned long isr;
1313 int n;
1314
1315 chained_irq_enter(chip, desc);
1316 for (;;) {
1317 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1318 * When there none are pending, we're finished unless we need
1319 * to process multiple banks (like ID_PIOCDE on sam9263).
1320 */
1321 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1322 if (!isr) {
1323 if (!at91_gpio->next)
1324 break;
1325 at91_gpio = at91_gpio->next;
1326 pio = at91_gpio->regbase;
1327 continue;
1328 }
1329
05daa16a 1330 for_each_set_bit(n, &isr, BITS_PER_LONG) {
6732ae5c 1331 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
6732ae5c
JCPV		 1332 }
1333 }
1334 chained_irq_exit(chip, desc);
1335 /* now it may re-trigger */
1336}
1337
1338/*
1339 * This lock class tells lockdep that GPIO irqs are in a different
1340 * category than their parents, so it won't report false recursion.
1341 */
1342static struct lock_class_key gpio_lock_class;
1343
1344static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1345 irq_hw_number_t hw)
1346{
1347 struct at91_gpio_chip *at91_gpio = h->host_data;
1348
1349 irq_set_lockdep_class(virq, &gpio_lock_class);
1350
1351 /*
1352 * Can use the "simple" and not "edge" handler since it's
1353 * shorter, and the AIC handles interrupts sanely.
1354 */
1355 irq_set_chip_and_handler(virq, &gpio_irqchip,
1356 handle_simple_irq);
1357 set_irq_flags(virq, IRQF_VALID);
1358 irq_set_chip_data(virq, at91_gpio);
1359
1360 return 0;
1361}
1362
f6f94f66
AL		 1363static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1364 struct device_node *ctrlr,
1365 const u32 *intspec, unsigned int intsize,
1366 irq_hw_number_t *out_hwirq,
1367 unsigned int *out_type)
a728c7cd
JCPV		 1368{
1369 struct at91_gpio_chip *at91_gpio = d->host_data;
1370 int ret;
1371 int pin = at91_gpio->chip.base + intspec[0];
1372
1373 if (WARN_ON(intsize < 2))
1374 return -EINVAL;
1375 *out_hwirq = intspec[0];
1376 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1377
1378 ret = gpio_request(pin, ctrlr->full_name);
1379 if (ret)
1380 return ret;
1381
1382 ret = gpio_direction_input(pin);
1383 if (ret)
1384 return ret;
1385
1386 return 0;
1387}
1388
6732ae5c
JCPV		 1389static struct irq_domain_ops at91_gpio_ops = {
1390 .map = at91_gpio_irq_map,
a728c7cd 1391 .xlate = at91_gpio_irq_domain_xlate,
6732ae5c
JCPV		 1392};
1393
1394static int at91_gpio_of_irq_setup(struct device_node *node,
1395 struct at91_gpio_chip *at91_gpio)
1396{
1397 struct at91_gpio_chip *prev = NULL;
1398 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1399
1400 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1401
1402 /* Setup proper .irq_set_type function */
1403 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1404
1405 /* Disable irqs of this PIO controller */
1406 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1407
1408 /* Setup irq domain */
1409 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1410 &at91_gpio_ops, at91_gpio);
1411 if (!at91_gpio->domain)
1412 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1413 at91_gpio->pioc_idx);
1414
1415 /* Setup chained handler */
1416 if (at91_gpio->pioc_idx)
1417 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1418
1419 /* The toplevel handler handles one bank of GPIOs, except
1420 * on some SoC it can handles up to three...
1421 * We only set up the handler for the first of the list.
1422 */
1423 if (prev && prev->next == at91_gpio)
1424 return 0;
1425
1426 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1427 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1428
1429 return 0;
1430}
1431
1432/* This structure is replicated for each GPIO block allocated at probe time */
1433static struct gpio_chip at91_gpio_template = {
1434 .request = at91_gpio_request,
1435 .free = at91_gpio_free,
1436 .direction_input = at91_gpio_direction_input,
1437 .get = at91_gpio_get,
1438 .direction_output = at91_gpio_direction_output,
1439 .set = at91_gpio_set,
1440 .to_irq = at91_gpio_to_irq,
1441 .dbg_show = at91_gpio_dbg_show,
1442 .can_sleep = 0,
1443 .ngpio = MAX_NB_GPIO_PER_BANK,
1444};
1445
1446static void __devinit at91_gpio_probe_fixup(void)
1447{
1448 unsigned i;
1449 struct at91_gpio_chip *at91_gpio, *last = NULL;
1450
1451 for (i = 0; i < gpio_banks; i++) {
1452 at91_gpio = gpio_chips[i];
1453
1454 /*
1455 * GPIO controller are grouped on some SoC:
1456 * PIOC, PIOD and PIOE can share the same IRQ line
1457 */
1458 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1459 last->next = at91_gpio;
1460 last = at91_gpio;
1461 }
1462}
1463
1464static struct of_device_id at91_gpio_of_match[] __devinitdata = {
1465 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1466 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1467 { /* sentinel */ }
1468};
1469
1470static int __devinit at91_gpio_probe(struct platform_device *pdev)
1471{
1472 struct device_node *np = pdev->dev.of_node;
1473 struct resource *res;
1474 struct at91_gpio_chip *at91_chip = NULL;
1475 struct gpio_chip *chip;
1476 struct pinctrl_gpio_range *range;
1477 int ret = 0;
32b01a36 1478 int irq, i;
6732ae5c
JCPV		 1479 int alias_idx = of_alias_get_id(np, "gpio");
1480 uint32_t ngpio;
32b01a36 1481 char **names;
6732ae5c
JCPV		 1482
1483 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1484 if (gpio_chips[alias_idx]) {
1485 ret = -EBUSY;
1486 goto err;
1487 }
1488
1489 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1490 if (!res) {
1491 ret = -ENOENT;
1492 goto err;
1493 }
1494
1495 irq = platform_get_irq(pdev, 0);
1496 if (irq < 0) {
1497 ret = irq;
1498 goto err;
1499 }
1500
1501 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1502 if (!at91_chip) {
1503 ret = -ENOMEM;
1504 goto err;
1505 }
1506
1507 at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res);
1508 if (!at91_chip->regbase) {
1509 dev_err(&pdev->dev, "failed to map registers, ignoring.\n");
1510 ret = -EBUSY;
1511 goto err;
1512 }
1513
dffa9123 1514 at91_chip->ops = (struct at91_pinctrl_mux_ops*)
6732ae5c
JCPV		 1515 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1516 at91_chip->pioc_virq = irq;
1517 at91_chip->pioc_idx = alias_idx;
1518
1519 at91_chip->clock = clk_get(&pdev->dev, NULL);
1520 if (IS_ERR(at91_chip->clock)) {
1521 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1522 goto err;
1523 }
1524
1525 if (clk_prepare(at91_chip->clock))
1526 goto clk_prep_err;
1527
1528 /* enable PIO controller's clock */
1529 if (clk_enable(at91_chip->clock)) {
1530 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1531 goto clk_err;
1532 }
1533
1534 at91_chip->chip = at91_gpio_template;
1535
1536 chip = &at91_chip->chip;
1537 chip->of_node = np;
1538 chip->label = dev_name(&pdev->dev);
1539 chip->dev = &pdev->dev;
1540 chip->owner = THIS_MODULE;
1541 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1542
1543 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1544 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1545 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1546 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1547 else
1548 chip->ngpio = ngpio;
1549 }
1550
32b01a36
JCPV		 1551 names = devm_kzalloc(&pdev->dev, sizeof(char*) * chip->ngpio, GFP_KERNEL);
1552
1553 if (!names) {
1554 ret = -ENOMEM;
1555 goto clk_err;
1556 }
1557
1558 for (i = 0; i < chip->ngpio; i++)
1559 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1560
1561 chip->names = (const char*const*)names;
1562
6732ae5c
JCPV		 1563 range = &at91_chip->range;
1564 range->name = chip->label;
1565 range->id = alias_idx;
1566 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1567
1568 range->npins = chip->ngpio;
1569 range->gc = chip;
1570
1571 ret = gpiochip_add(chip);
1572 if (ret)
1573 goto clk_err;
1574
1575 gpio_chips[alias_idx] = at91_chip;
1576 gpio_banks = max(gpio_banks, alias_idx + 1);
1577
1578 at91_gpio_probe_fixup();
1579
1580 at91_gpio_of_irq_setup(np, at91_chip);
1581
1582 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1583
1584 return 0;
1585
1586clk_err:
1587 clk_unprepare(at91_chip->clock);
1588clk_prep_err:
1589 clk_put(at91_chip->clock);
1590err:
1591 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1592
1593 return ret;
1594}
1595
1596static struct platform_driver at91_gpio_driver = {
1597 .driver = {
1598 .name = "gpio-at91",
1599 .owner = THIS_MODULE,
1600 .of_match_table = of_match_ptr(at91_gpio_of_match),
1601 },
1602 .probe = at91_gpio_probe,
1603};
1604
1605static struct platform_driver at91_pinctrl_driver = {
1606 .driver = {
1607 .name = "pinctrl-at91",
1608 .owner = THIS_MODULE,
1609 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1610 },
1611 .probe = at91_pinctrl_probe,
1612 .remove = __devexit_p(at91_pinctrl_remove),
1613};
1614
1615static int __init at91_pinctrl_init(void)
1616{
1617 int ret;
1618
1619 ret = platform_driver_register(&at91_gpio_driver);
1620 if (ret)
1621 return ret;
1622 return platform_driver_register(&at91_pinctrl_driver);
1623}
1624arch_initcall(at91_pinctrl_init);
1625
1626static void __exit at91_pinctrl_exit(void)
1627{
1628 platform_driver_unregister(&at91_pinctrl_driver);
1629}
1630
1631module_exit(at91_pinctrl_exit);
1632MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1633MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1634MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)