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PCI: Wait for pending transactions to complete before 82599 FLR
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
363c75db 20#include <linux/export.h>
1da177e4
LT		 21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
25be5e6c 24#include <linux/acpi.h>
9f23ed3b 25#include <linux/kallsyms.h>
75e07fc3 26#include <linux/dmi.h>
649426ef 27#include <linux/pci-aspm.h>
32a9a682 28#include <linux/ioport.h>
3209874a
AV		 29#include <linux/sched.h>
30#include <linux/ktime.h>
93177a74 31#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 32#include "pci.h"
1da177e4 33
253d2e54
JP		 34/*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
39 */
40static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
41{
52d21b5e 42 dev->mmio_always_on = 1;
253d2e54 43}
52d21b5e
YL		 44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
253d2e54 46
bd8481e1
DT		 47/* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
50 */
51static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
52{
53 dev->broken_parity_status = 1; /* This device gives false positives */
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
57
1da177e4
LT		 58/* Deal with broken BIOS'es that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 60static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 61{
62 struct pci_dev *d = NULL;
63 unsigned char dlc;
64
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
69 if (!(dlc & 1<<1)) {
999da9fd 70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 71 dlc |= 1<<1;
72 pci_write_config_byte(d, 0x82, dlc);
73 }
74 }
75}
652c538e
AM		 76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 78
79/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
82
83 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */
1da177e4
LT		 85
86static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
87{
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1;
f0fda801 90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 91 }
92}
93 /*
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
96 */
652c538e
AM		 97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 104
4731fdcf
LB		 105/*
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
108 */
109static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
110{
111 u32 pmbase;
112 u16 pm1a;
113
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
116 pm1a = inw(pmbase);
117
118 if (pm1a & 0x10) {
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 outw(0x10, pmbase);
121 }
122}
123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
124
1da177e4
LT		 125/*
126 * Chipsets where PCI->PCI transfers vanish or hang
127 */
128static void __devinit quirk_nopcipci(struct pci_dev *dev)
129{
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 132 pci_pci_problems |= PCIPCI_FAIL;
133 }
134}
652c538e
AM		 135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 137
138static void __devinit quirk_nopciamd(struct pci_dev *dev)
139{
140 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev);
142 if (rev == 0x13) {
143 /* Erratum 24 */
f0fda801 144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 145 pci_pci_problems |= PCIAGP_FAIL;
146 }
147}
652c538e 148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 149
150/*
151 * Triton requires workarounds to be used by the drivers
152 */
153static void __devinit quirk_triton(struct pci_dev *dev)
154{
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 157 pci_pci_problems |= PCIPCI_TRITON;
158 }
159}
652c538e
AM		 160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 164
165/*
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
631dd1a8 169 * and http://www.georgebreese.com/net/software/#PCI
1da177e4
LT		 170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
1597cacb 176static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 177{
178 struct pci_dev *p;
1da177e4
LT		 179 u8 busarb;
180 /* Ok we have a potential problem chipset here. Now see if we have
181 a buggy southbridge */
182
183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 if (p!=NULL) {
1da177e4
LT		 185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
186 /* Check for buggy part revisions */
2b1afa87 187 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 188 goto exit;
189 } else {
190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
191 if (p==NULL) /* No problem parts */
192 goto exit;
1da177e4 193 /* Check for buggy part revisions */
2b1afa87 194 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 195 goto exit;
196 }
197
198 /*
199 * Ok we have the problem. Now set the PCI master grant to
200 * occur every master grant. The apparent bug is that under high
201 * PCI load (quite common in Linux of course) you can get data
202 * loss when the CPU is held off the bus for 3 bus master requests
203 * This happens to include the IDE controllers....
204 *
205 * VIA only apply this fix when an SB Live! is present but under
25985edc 206 * both Linux and Windows this isn't enough, and we have seen
1da177e4
LT		 207 * corruption without SB Live! but with things like 3 UDMA IDE
208 * controllers. So we ignore that bit of the VIA recommendation..
209 */
210
211 pci_read_config_byte(dev, 0x76, &busarb);
212 /* Set bit 4 and bi 5 of byte 76 to 0x01
213 "Master priority rotation on every PCI master grant */
214 busarb &= ~(1<<5);
215 busarb |= (1<<4);
216 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 218exit:
219 pci_dev_put(p);
220}
652c538e
AM		 221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 224/* Must restore this on a resume from RAM */
652c538e
AM		 225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 228
229/*
230 * VIA Apollo VP3 needs ETBF on BT848/878
231 */
232static void __devinit quirk_viaetbf(struct pci_dev *dev)
233{
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 236 pci_pci_problems |= PCIPCI_VIAETBF;
237 }
238}
652c538e 239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 240
241static void __devinit quirk_vsfx(struct pci_dev *dev)
242{
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 245 pci_pci_problems |= PCIPCI_VSFX;
246 }
247}
652c538e 248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 249
250/*
251 * Ali Magik requires workarounds to be used by the drivers
252 * that DMA to AGP space. Latency must be set to 0xA and triton
253 * workaround applied too
254 * [Info kindly provided by ALi]
255 */
b99ea85a 256static void __devinit quirk_alimagik(struct pci_dev *dev)
1da177e4
LT		 257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
261 }
262}
652c538e
AM		 263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 265
266/*
267 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least
269 */
270static void __devinit quirk_natoma(struct pci_dev *dev)
271{
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 274 pci_pci_problems |= PCIPCI_NATOMA;
275 }
276}
652c538e
AM		 277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 283
284/*
285 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring.
287 */
288static void __devinit quirk_citrine(struct pci_dev *dev)
289{
290 dev->cfg_size = 0xA0;
291}
652c538e 292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 293
294/*
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region.
297 */
298static void __devinit quirk_s3_64M(struct pci_dev *dev)
299{
300 struct resource *r = &dev->resource[0];
301
302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
303 r->start = 0;
304 r->end = 0x3ffffff;
305 }
306}
652c538e
AM		 307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 309
73d2eaac
AS		 310/*
311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range).
315 */
316static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
317{
318 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0];
320 res->end = res->start + 8 - 1;
321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
322 "(incorrect header); workaround applied.\n");
323 }
324}
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326
6693e74a
LT		 327static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
328 unsigned size, int nr, const char *name)
1da177e4
LT		 329{
330 region &= ~(size-1);
331 if (region) {
085ae41f 332 struct pci_bus_region bus_region;
1da177e4
LT		 333 struct resource *res = dev->resource + nr;
334
335 res->name = pci_name(dev);
336 res->start = region;
337 res->end = region + size - 1;
338 res->flags = IORESOURCE_IO;
085ae41f
DM		 339
340 /* Convert from PCI bus to resource space. */
341 bus_region.start = res->start;
342 bus_region.end = res->end;
343 pcibios_bus_to_resource(dev, res, &bus_region);
344
f967a443
BH		 345 if (pci_claim_resource(dev, nr) == 0)
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
347 res, name);
1da177e4
LT		 348 }
349}
350
351/*
352 * ATI Northbridge setups MCE the processor if you even
353 * read somewhere between 0x3b0->0x3bb or read 0x3d3
354 */
355static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
356{
f0fda801 357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
359 request_region(0x3b0, 0x0C, "RadeonIGP");
360 request_region(0x3d3, 0x01, "RadeonIGP");
361}
652c538e 362DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 363
364/*
365 * Let's make the southbridge information explicit instead
366 * of having to worry about people probing the ACPI areas,
367 * for example.. (Yes, it happens, and if you read the wrong
368 * ACPI register it will put the machine to sleep with no
369 * way of waking it up again. Bummer).
370 *
371 * ALI M7101: Two IO regions pointed to by words at
372 * 0xE0 (64 bytes of ACPI registers)
373 * 0xE2 (32 bytes of SMB registers)
374 */
375static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
376{
377 u16 region;
378
379 pci_read_config_word(dev, 0xE0, &region);
6693e74a 380 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 381 pci_read_config_word(dev, 0xE2, &region);
6693e74a 382 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 383}
652c538e 384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 385
6693e74a
LT		 386static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
387{
388 u32 devres;
389 u32 mask, size, base;
390
391 pci_read_config_dword(dev, port, &devres);
392 if ((devres & enable) != enable)
393 return;
394 mask = (devres >> 16) & 15;
395 base = devres & 0xffff;
396 size = 16;
397 for (;;) {
398 unsigned bit = size >> 1;
399 if ((bit & mask) == bit)
400 break;
401 size = bit;
402 }
403 /*
404 * For now we only print it out. Eventually we'll want to
405 * reserve it (at least if it's in the 0x1000+ range), but
406 * let's get enough confirmation reports first.
407 */
408 base &= -size;
f0fda801 409 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 410}
411
412static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
413{
414 u32 devres;
415 u32 mask, size, base;
416
417 pci_read_config_dword(dev, port, &devres);
418 if ((devres & enable) != enable)
419 return;
420 base = devres & 0xffff0000;
421 mask = (devres & 0x3f) << 16;
422 size = 128 << 16;
423 for (;;) {
424 unsigned bit = size >> 1;
425 if ((bit & mask) == bit)
426 break;
427 size = bit;
428 }
429 /*
430 * For now we only print it out. Eventually we'll want to
431 * reserve it, but let's get enough confirmation reports first.
432 */
433 base &= -size;
f0fda801 434 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 435}
436
1da177e4
LT		 437/*
438 * PIIX4 ACPI: Two IO regions pointed to by longwords at
439 * 0x40 (64 bytes of ACPI registers)
08db2a70 440 * 0x90 (16 bytes of SMB registers)
6693e74a 441 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 442 */
443static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
444{
6693e74a 445 u32 region, res_a;
1da177e4
LT		 446
447 pci_read_config_dword(dev, 0x40, &region);
6693e74a 448 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 449 pci_read_config_dword(dev, 0x90, &region);
08db2a70 450 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 451
452 /* Device resource A has enables for some of the other ones */
453 pci_read_config_dword(dev, 0x5c, &res_a);
454
455 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
456 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
457
458 /* Device resource D is just bitfields for static resources */
459
460 /* Device 12 enabled? */
461 if (res_a & (1 << 29)) {
462 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
463 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
464 }
465 /* Device 13 enabled? */
466 if (res_a & (1 << 30)) {
467 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
468 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
469 }
470 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
471 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 472}
652c538e
AM		 473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4 475
cdb97558
JS		 476#define ICH_PMBASE 0x40
477#define ICH_ACPI_CNTL 0x44
478#define ICH4_ACPI_EN 0x10
479#define ICH6_ACPI_EN 0x80
480#define ICH4_GPIOBASE 0x58
481#define ICH4_GPIO_CNTL 0x5c
482#define ICH4_GPIO_EN 0x10
483#define ICH6_GPIOBASE 0x48
484#define ICH6_GPIO_CNTL 0x4c
485#define ICH6_GPIO_EN 0x10
486
1da177e4
LT		 487/*
488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space)
491 */
492static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
493{
494 u32 region;
cdb97558 495 u8 enable;
1da177e4 496
87e3dc38
JS		 497 /*
498 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
499 * with low legacy (and fixed) ports. We don't know the decoding
500 * priority and can't tell whether the legacy device or the one created
501 * here is really at that address. This happens on boards with broken
502 * BIOSes.
503 */
504
cdb97558
JS		 505 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
506 if (enable & ICH4_ACPI_EN) {
507 pci_read_config_dword(dev, ICH_PMBASE, &region);
87e3dc38
JS		 508 region &= PCI_BASE_ADDRESS_IO_MASK;
509 if (region >= PCIBIOS_MIN_IO)
510 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
511 "ICH4 ACPI/GPIO/TCO");
cdb97558 512 }
1da177e4 513
cdb97558
JS		 514 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
515 if (enable & ICH4_GPIO_EN) {
516 pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
87e3dc38
JS		 517 region &= PCI_BASE_ADDRESS_IO_MASK;
518 if (region >= PCIBIOS_MIN_IO)
519 quirk_io_region(dev, region, 64,
520 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
cdb97558 521 }
1da177e4 522}
652c538e
AM		 523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 533
894886e5 534static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
RM		 535{
536 u32 region;
cdb97558 537 u8 enable;
2cea752f 538
cdb97558
JS		 539 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
540 if (enable & ICH6_ACPI_EN) {
541 pci_read_config_dword(dev, ICH_PMBASE, &region);
87e3dc38
JS		 542 region &= PCI_BASE_ADDRESS_IO_MASK;
543 if (region >= PCIBIOS_MIN_IO)
544 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
545 "ICH6 ACPI/GPIO/TCO");
cdb97558 546 }
2cea752f 547
cdb97558 548 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
b6d95bb6 549 if (enable & ICH6_GPIO_EN) {
cdb97558 550 pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
87e3dc38
JS		 551 region &= PCI_BASE_ADDRESS_IO_MASK;
552 if (region >= PCIBIOS_MIN_IO)
553 quirk_io_region(dev, region, 64,
554 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
cdb97558 555 }
2cea752f 556}
894886e5
LT		 557
558static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
559{
560 u32 val;
561 u32 size, base;
562
563 pci_read_config_dword(dev, reg, &val);
564
565 /* Enabled? */
566 if (!(val & 1))
567 return;
568 base = val & 0xfffc;
569 if (dynsize) {
570 /*
571 * This is not correct. It is 16, 32 or 64 bytes depending on
572 * register D31:F0:ADh bits 5:4.
573 *
574 * But this gets us at least _part_ of it.
575 */
576 size = 16;
577 } else {
578 size = 128;
579 }
580 base &= ~(size-1);
581
582 /* Just print it out for now. We should reserve it after more debugging */
583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
584}
585
586static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
587{
588 /* Shared ACPI/GPIO decode with all ICH6+ */
589 ich6_lpc_acpi_gpio(dev);
590
591 /* ICH6-specific generic IO decode */
592 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
593 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
594}
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
597
598static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
599{
600 u32 val;
601 u32 mask, base;
602
603 pci_read_config_dword(dev, reg, &val);
604
605 /* Enabled? */
606 if (!(val & 1))
607 return;
608
609 /*
610 * IO base in bits 15:2, mask in bits 23:18, both
611 * are dword-based
612 */
613 base = val & 0xfffc;
614 mask = (val >> 16) & 0xfc;
615 mask |= 3;
616
617 /* Just print it out for now. We should reserve it after more debugging */
618 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
619}
620
621/* ICH7-10 has the same common LPC generic IO decode registers */
622static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
623{
5d9c0a79 624 /* We share the common ACPI/GPIO decode with ICH6 */
894886e5
LT		 625 ich6_lpc_acpi_gpio(dev);
626
627 /* And have 4 ICH7+ generic decodes */
628 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
629 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
630 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
631 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
632}
633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 646
1da177e4
LT		 647/*
648 * VIA ACPI: One IO region pointed to by longword at
649 * 0x48 or 0x20 (256 bytes of ACPI registers)
650 */
651static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
652{
1da177e4
LT		 653 u32 region;
654
651472fb 655 if (dev->revision & 0x10) {
1da177e4
LT		 656 pci_read_config_dword(dev, 0x48, &region);
657 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 658 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 659 }
660}
652c538e 661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 662
663/*
664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
665 * 0x48 (256 bytes of ACPI registers)
666 * 0x70 (128 bytes of hardware monitoring register)
667 * 0x90 (16 bytes of SMB registers)
668 */
669static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
670{
671 u16 hm;
672 u32 smb;
673
674 quirk_vt82c586_acpi(dev);
675
676 pci_read_config_word(dev, 0x70, &hm);
677 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 678 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 679
680 pci_read_config_dword(dev, 0x90, &smb);
681 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 683}
652c538e 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 685
6d85f29b
IK		 686/*
687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
688 * 0x88 (128 bytes of power management registers)
689 * 0xd0 (16 bytes of SMB registers)
690 */
691static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
692{
693 u16 pm, smb;
694
695 pci_read_config_word(dev, 0x88, &pm);
696 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 697 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 698
699 pci_read_config_word(dev, 0xd0, &smb);
700 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 701 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 702}
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
704
1f56f4a2
GB		 705/*
706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
707 * Disable fast back-to-back on the secondary bus segment
708 */
709static void __devinit quirk_xio2000a(struct pci_dev *dev)
710{
711 struct pci_dev *pdev;
712 u16 command;
713
714 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
715 "secondary bus fast back-to-back transfers disabled\n");
716 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
717 pci_read_config_word(pdev, PCI_COMMAND, &command);
718 if (command & PCI_COMMAND_FAST_BACK)
719 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
720 }
721}
722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
723 quirk_xio2000a);
1da177e4
LT		 724
725#ifdef CONFIG_X86_IO_APIC
726
727#include <asm/io_apic.h>
728
729/*
730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
731 * devices to the external APIC.
732 *
733 * TODO: When we have device-specific interrupt routers,
734 * this code will go away from quirks.
735 */
1597cacb 736static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 737{
738 u8 tmp;
739
740 if (nr_ioapics < 1)
741 tmp = 0; /* nothing routed to external APIC */
742 else
743 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
744
f0fda801 745 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 746 tmp == 0 ? "Disa" : "Ena");
747
748 /* Offset 0x58: External APIC IRQ output control */
749 pci_write_config_byte (dev, 0x58, tmp);
750}
652c538e 751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 753
a1740913
KW		 754/*
755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
756 * This leads to doubled level interrupt rates.
757 * Set this bit to get rid of cycle wastage.
758 * Otherwise uncritical.
759 */
1597cacb 760static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 761{
762 u8 misc_control2;
763#define BYPASS_APIC_DEASSERT 8
764
765 pci_read_config_byte(dev, 0x5B, &misc_control2);
766 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 767 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 768 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
769 }
770}
771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 773
1da177e4
LT		 774/*
775 * The AMD io apic can hang the box when an apic irq is masked.
776 * We check all revs >= B0 (yet not in the pre production!) as the bug
777 * is currently marked NoFix
778 *
779 * We have multiple reports of hangs with this chipset that went away with
236561e5 780 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 781 * of course. However the advice is demonstrably good even if so..
782 */
783static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
784{
44c10138 785 if (dev->revision >= 0x02) {
f0fda801 786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
787 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 788 }
789}
652c538e 790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4 791
b99ea85a 792static void __devinit quirk_ioapic_rmw(struct pci_dev *dev)
1da177e4
LT		 793{
794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1;
796}
652c538e 797DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 798#endif /* CONFIG_X86_IO_APIC */
799
d556ad4b
PO		 800/*
801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */
b99ea85a 804static void __devinit quirk_amd_8131_mmrbc(struct pci_dev *dev)
d556ad4b 805{
aa288d4d 806 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
808 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
810 }
811}
812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 813
1da177e4
LT		 814/*
815 * FIXME: it is questionable that quirk_via_acpi
816 * is needed. It shows up as an ISA bridge, and does not
817 * support the PCI_INTERRUPT_LINE register at all. Therefore
818 * it seems like setting the pci_dev's 'irq' to the
819 * value of the ACPI SCI interrupt is only done for convenience.
820 * -jgarzik
821 */
822static void __devinit quirk_via_acpi(struct pci_dev *d)
823{
824 /*
825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
826 */
827 u8 irq;
828 pci_read_config_byte(d, 0x42, &irq);
829 irq &= 0xf;
830 if (irq && (irq != 2))
831 d->irq = irq;
832}
652c538e
AM		 833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 835
09d6029f
DD		 836
837/*
1597cacb 838 * VIA bridges which have VLink
09d6029f 839 */
1597cacb 840
c06bb5d4
JD		 841static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
842
843static void quirk_via_bridge(struct pci_dev *dev)
844{
845 /* See what bridge we have and find the device ranges */
846 switch (dev->device) {
847 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 848 /* The VT82C686 is special, it attaches to PCI and can have
849 any device number. All its subdevices are functions of
850 that single device. */
851 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
852 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 853 break;
854 case PCI_DEVICE_ID_VIA_8237:
855 case PCI_DEVICE_ID_VIA_8237A:
856 via_vlink_dev_lo = 15;
857 break;
858 case PCI_DEVICE_ID_VIA_8235:
859 via_vlink_dev_lo = 16;
860 break;
861 case PCI_DEVICE_ID_VIA_8231:
862 case PCI_DEVICE_ID_VIA_8233_0:
863 case PCI_DEVICE_ID_VIA_8233A:
864 case PCI_DEVICE_ID_VIA_8233C_0:
865 via_vlink_dev_lo = 17;
866 break;
867 }
868}
869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 877
1597cacb
AC		 878/**
879 * quirk_via_vlink - VIA VLink IRQ number update
880 * @dev: PCI device
881 *
882 * If the device we are dealing with is on a PIC IRQ we need to
883 * ensure that the IRQ line register which usually is not relevant
884 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 885 * to the right place.
886 * We only do this on systems where a VIA south bridge was detected,
887 * and only for VIA devices on the motherboard (see quirk_via_bridge
888 * above).
1597cacb
AC		 889 */
890
891static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 892{
893 u8 irq, new_irq;
894
c06bb5d4
JD		 895 /* Check if we have VLink at all */
896 if (via_vlink_dev_lo == -1)
09d6029f
DD		 897 return;
898
899 new_irq = dev->irq;
900
901 /* Don't quirk interrupts outside the legacy IRQ range */
902 if (!new_irq || new_irq > 15)
903 return;
904
1597cacb 905 /* Internal device ? */
c06bb5d4
JD		 906 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
907 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 908 return;
909
910 /* This is an internal VLink device on a PIC interrupt. The BIOS
911 ought to have set this but may not have, so we redo it */
912
25be5e6c
LB		 913 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
914 if (new_irq != irq) {
f0fda801 915 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
916 irq, new_irq);
25be5e6c
LB		 917 udelay(15); /* unknown if delay really needed */
918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
919 }
920}
1597cacb 921DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 922
1da177e4
LT		 923/*
924 * VIA VT82C598 has its device ID settable and many BIOSes
925 * set it to the ID of VT82C597 for backward compatibility.
926 * We need to switch it off to be able to recognize the real
927 * type of the chip.
928 */
929static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
930{
931 pci_write_config_byte(dev, 0xfc, 0);
932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
933}
652c538e 934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 935
936/*
937 * CardBus controllers have a legacy base address that enables them
938 * to respond as i82365 pcmcia controllers. We don't want them to
939 * do this even if the Linux CardBus driver is not loaded, because
940 * the Linux i82365 driver does not (and should not) handle CardBus.
941 */
1597cacb 942static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4 943{
1da177e4
LT		 944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
945}
ae9de56b
YL		 946DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
948DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1da177e4
LT		 950
951/*
952 * Following the PCI ordering rules is optional on the AMD762. I'm not
953 * sure what the designers were smoking but let's not inhale...
954 *
955 * To be fair to AMD, it follows the spec by default, its BIOS people
956 * who turn it off!
957 */
1597cacb 958static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 959{
960 u32 pcic;
961 pci_read_config_dword(dev, 0x4C, &pcic);
962 if ((pcic&6)!=6) {
963 pcic |= 6;
f0fda801 964 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 965 pci_write_config_dword(dev, 0x4C, pcic);
966 pci_read_config_dword(dev, 0x84, &pcic);
967 pcic |= (1<<23); /* Required in this mode */
968 pci_write_config_dword(dev, 0x84, pcic);
969 }
970}
652c538e 971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 972DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 973
974/*
975 * DreamWorks provided workaround for Dunord I-3000 problem
976 *
977 * This card decodes and responds to addresses not apparently
978 * assigned to it. We force a larger allocation to ensure that
979 * nothing gets put too close to it.
980 */
981static void __devinit quirk_dunord ( struct pci_dev * dev )
982{
983 struct resource *r = &dev->resource [1];
984 r->start = 0;
985 r->end = 0xffffff;
986}
652c538e 987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 988
989/*
990 * i82380FB mobile docking controller: its PCI-to-PCI bridge
991 * is subtractive decoding (transparent), and does indicate this
992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
993 * instead of 0x01.
994 */
995static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
996{
997 dev->transparent = 1;
998}
652c538e
AM		 999DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1000DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 1001
1002/*
1003 * Common misconfiguration of the MediaGX/Geode PCI master that will
1004 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
631dd1a8 1005 * datasheets found at http://www.national.com/analog for info on what
1da177e4
LT		 1006 * these bits do. <christer@weinigel.se>
1007 */
1597cacb 1008static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 1009{
1010 u8 reg;
1011 pci_read_config_byte(dev, 0x41, &reg);
1012 if (reg & 2) {
1013 reg &= ~2;
f0fda801 1014 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 1015 pci_write_config_byte(dev, 0x41, reg);
1016 }
1017}
652c538e
AM		 1018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1019DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 1020
1da177e4
LT		 1021/*
1022 * Ensure C0 rev restreaming is off. This is normally done by
1023 * the BIOS but in the odd case it is not the results are corruption
1024 * hence the presence of a Linux check
1025 */
1597cacb 1026static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 1027{
1028 u16 config;
1da177e4 1029
44c10138 1030 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 1031 return;
1032 pci_read_config_word(pdev, 0x40, &config);
1033 if (config & (1<<6)) {
1034 config &= ~(1<<6);
1035 pci_write_config_word(pdev, 0x40, config);
f0fda801 1036 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 1037 }
1038}
652c538e 1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1041
25e742b2 1042static void quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1043{
5deab536 1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1045 u8 tmp;
ab17443a 1046
05a7d22b
CC		 1047 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1048 if (tmp == 0x01) {
ab17443a
CH		 1049 pci_read_config_byte(pdev, 0x40, &tmp);
1050 pci_write_config_byte(pdev, 0x40, tmp|1);
1051 pci_write_config_byte(pdev, 0x9, 1);
1052 pci_write_config_byte(pdev, 0xa, 6);
1053 pci_write_config_byte(pdev, 0x40, tmp);
1054
c9f89475 1055 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1056 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1057 }
1058}
05a7d22b 1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1060DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1062DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1064DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
ab17443a 1065
1da177e4
LT		 1066/*
1067 * Serverworks CSB5 IDE does not fully support native mode
1068 */
1069static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1070{
1071 u8 prog;
1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1073 if (prog & 5) {
1074 prog &= ~5;
1075 pdev->class &= ~5;
1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1077 /* PCI layer will sort out resources */
1da177e4
LT		 1078 }
1079}
652c538e 1080DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1081
1082/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */
b99ea85a 1085static void __devinit quirk_ide_samemode(struct pci_dev *pdev)
1da177e4
LT		 1086{
1087 u8 prog;
1088
1089 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1090
1091 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1092 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1093 prog &= ~5;
1094 pdev->class &= ~5;
1095 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1096 }
1097}
368c73d4 1098DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1099
979b1791
AC		 1100/*
1101 * Some ATA devices break if put into D3
1102 */
1103
1104static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1105{
faa738bb 1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
979b1791 1107}
faa738bb
YL		 1108/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1109DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1111DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f 1113/* ALi loses some register settings that we cannot then restore */
faa738bb
YL		 1114DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f
AC		 1116/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1117 occur when mode detecting */
faa738bb
YL		 1118DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
979b1791 1120
1da177e4
LT		 1121/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */
b99ea85a 1124static void __devinit quirk_eisa_bridge(struct pci_dev *dev)
1da177e4
LT		 1125{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127}
652c538e 1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1129
7daa0c4f 1130
1da177e4
LT		 1131/*
1132 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1133 * is not activated. The myth is that Asus said that they do not want the
1134 * users to be irritated by just another PCI Device in the Win98 device
1135 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1136 * package 2.7.0 for details)
1137 *
1138 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1139 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1140 * becomes necessary to do this tweak in two steps -- the chosen trigger
1141 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1142 *
1143 * Note that we used to unhide the SMBus that way on Toshiba laptops
1144 * (Satellite A40 and Tecra M2) but then found that the thermal management
1145 * was done by SMM code, which could cause unsynchronized concurrent
1146 * accesses to the SMBus registers, with potentially bad effects. Thus you
1147 * should be very careful when adding new entries: if SMM is accessing the
1148 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1149 *
1150 * Likewise, many recent laptops use ACPI for thermal management. If the
1151 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1152 * natively, and keeping the SMBus hidden is the right thing to do. If you
1153 * are about to add an entry in the table below, please first disassemble
1154 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1155 */
9d24a81e 1156static int asus_hides_smbus;
1da177e4 1157
b99ea85a 1158static void __devinit asus_hides_smbus_hostbridge(struct pci_dev *dev)
1da177e4
LT		 1159{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1162 switch(dev->subsystem_device) {
a00db371 1163 case 0x8025: /* P4B-LX */
1da177e4
LT		 1164 case 0x8070: /* P4B */
1165 case 0x8088: /* P4B533 */
1166 case 0x1626: /* L3C notebook */
1167 asus_hides_smbus = 1;
1168 }
2f2d39d2 1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1170 switch(dev->subsystem_device) {
1171 case 0x80b1: /* P4GE-V */
1172 case 0x80b2: /* P4PE */
1173 case 0x8093: /* P4B533-V */
1174 asus_hides_smbus = 1;
1175 }
2f2d39d2 1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1177 switch(dev->subsystem_device) {
1178 case 0x8030: /* P4T533 */
1179 asus_hides_smbus = 1;
1180 }
2f2d39d2 1181 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1182 switch (dev->subsystem_device) {
1183 case 0x8070: /* P4G8X Deluxe */
1184 asus_hides_smbus = 1;
1185 }
2f2d39d2 1186 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1187 switch (dev->subsystem_device) {
1188 case 0x80c9: /* PU-DLS */
1189 asus_hides_smbus = 1;
1190 }
2f2d39d2 1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1192 switch (dev->subsystem_device) {
1193 case 0x1751: /* M2N notebook */
1194 case 0x1821: /* M5N notebook */
4096ed0f 1195 case 0x1897: /* A6L notebook */
1da177e4
LT		 1196 asus_hides_smbus = 1;
1197 }
2f2d39d2 1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1199 switch (dev->subsystem_device) {
1200 case 0x184b: /* W1N notebook */
1201 case 0x186a: /* M6Ne notebook */
1202 asus_hides_smbus = 1;
1203 }
2f2d39d2 1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1205 switch (dev->subsystem_device) {
1206 case 0x80f2: /* P4P800-X */
1207 asus_hides_smbus = 1;
1208 }
2f2d39d2 1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1210 switch (dev->subsystem_device) {
1211 case 0x1882: /* M6V notebook */
2d1e1c75 1212 case 0x1977: /* A6VA notebook */
acc06632
RM		 1213 asus_hides_smbus = 1;
1214 }
1da177e4
LT		 1215 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1216 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1217 switch(dev->subsystem_device) {
1218 case 0x088C: /* HP Compaq nc8000 */
1219 case 0x0890: /* HP Compaq nc6000 */
1220 asus_hides_smbus = 1;
1221 }
2f2d39d2 1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1223 switch (dev->subsystem_device) {
1224 case 0x12bc: /* HP D330L */
e3b1bd57 1225 case 0x12bd: /* HP D530 */
74c57428 1226 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1227 asus_hides_smbus = 1;
1228 }
677cc644
JD		 1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1230 switch (dev->subsystem_device) {
1231 case 0x12bf: /* HP xw4100 */
1232 asus_hides_smbus = 1;
1233 }
1da177e4
LT		 1234 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1235 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1236 switch(dev->subsystem_device) {
1237 case 0xC00C: /* Samsung P35 notebook */
1238 asus_hides_smbus = 1;
1239 }
c87f883e
RIZ		 1240 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1241 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch(dev->subsystem_device) {
1243 case 0x0058: /* Compaq Evo N620c */
1244 asus_hides_smbus = 1;
1245 }
d7698edc 1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1247 switch(dev->subsystem_device) {
1248 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1249 /* Motherboard doesn't have Host bridge
1250 * subvendor/subdevice IDs, therefore checking
1251 * its on-board VGA controller */
1252 asus_hides_smbus = 1;
1253 }
8293b0f6 1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
10260d9a
JD		 1255 switch(dev->subsystem_device) {
1256 case 0x00b8: /* Compaq Evo D510 CMT */
1257 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1258 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1259 /* Motherboard doesn't have Host bridge
1260 * subvendor/subdevice IDs and on-board VGA
1261 * controller is disabled if an AGP card is
1262 * inserted, therefore checking USB UHCI
1263 * Controller #1 */
10260d9a
JD		 1264 asus_hides_smbus = 1;
1265 }
27e46859
KH		 1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1267 switch (dev->subsystem_device) {
1268 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1269 /* Motherboard doesn't have host bridge
1270 * subvendor/subdevice IDs, therefore checking
1271 * its on-board VGA controller */
1272 asus_hides_smbus = 1;
1273 }
1da177e4
LT		 1274 }
1275}
652c538e
AM		 1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1286
1287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1290
1597cacb 1291static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1292{
1293 u16 val;
1294
1295 if (likely(!asus_hides_smbus))
1296 return;
1297
1298 pci_read_config_word(dev, 0xF2, &val);
1299 if (val & 0x8) {
1300 pci_write_config_word(dev, 0xF2, val & (~0x8));
1301 pci_read_config_word(dev, 0xF2, &val);
1302 if (val & 0x8)
f0fda801 1303 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1304 else
f0fda801 1305 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1306 }
1307}
652c538e
AM		 1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1315DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1316DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1320DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1322
e1a2a51e
RW		 1323/* It appears we just have one such device. If not, we have a warning */
1324static void __iomem *asus_rcba_base;
1325static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1326{
e1a2a51e 1327 u32 rcba;
acc06632
RM		 1328
1329 if (likely(!asus_hides_smbus))
1330 return;
e1a2a51e
RW		 1331 WARN_ON(asus_rcba_base);
1332
acc06632 1333 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1334 /* use bits 31:14, 16 kB aligned */
1335 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1336 if (asus_rcba_base == NULL)
1337 return;
1338}
1339
1340static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1341{
1342 u32 val;
1343
1344 if (likely(!asus_hides_smbus || !asus_rcba_base))
1345 return;
1346 /* read the Function Disable register, dword mode only */
1347 val = readl(asus_rcba_base + 0x3418);
1348 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1349}
1350
1351static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1352{
1353 if (likely(!asus_hides_smbus || !asus_rcba_base))
1354 return;
1355 iounmap(asus_rcba_base);
1356 asus_rcba_base = NULL;
f0fda801 1357 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1358}
e1a2a51e
RW		 1359
1360static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1361{
1362 asus_hides_smbus_lpc_ich6_suspend(dev);
1363 asus_hides_smbus_lpc_ich6_resume_early(dev);
1364 asus_hides_smbus_lpc_ich6_resume(dev);
1365}
652c538e 1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1367DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1368DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1369DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1370
1da177e4
LT		 1371/*
1372 * SiS 96x south bridge: BIOS typically hides SMBus device...
1373 */
1597cacb 1374static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1375{
1376 u8 val = 0;
1da177e4 1377 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1378 if (val & 0x10) {
f0fda801 1379 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1380 pci_write_config_byte(dev, 0x77, val & ~0x10);
1381 }
1da177e4 1382}
652c538e
AM		 1383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1387DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1388DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1390DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1391
1da177e4
LT		 1392/*
1393 * ... This is further complicated by the fact that some SiS96x south
1394 * bridges pretend to be 85C503/5513 instead. In that case see if we
1395 * spotted a compatible north bridge to make sure.
1396 * (pci_find_device doesn't work yet)
1397 *
1398 * We can also enable the sis96x bit in the discovery register..
1399 */
1da177e4
LT		 1400#define SIS_DETECT_REGISTER 0x40
1401
1597cacb 1402static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1403{
1404 u8 reg;
1405 u16 devid;
1406
1407 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1408 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1409 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1410 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1411 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1412 return;
1413 }
1414
1da177e4 1415 /*
2f5c33b3
MH		 1416 * Ok, it now shows up as a 96x.. run the 96x quirk by
1417 * hand in case it has already been processed.
1418 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1419 */
1420 dev->device = devid;
2f5c33b3 1421 quirk_sis_96x_smbus(dev);
1da177e4 1422}
652c538e 1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1425
1da177e4 1426
e5548e96
BJD		 1427/*
1428 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1429 * and MC97 modem controller are disabled when a second PCI soundcard is
1430 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1431 * -- bjd
1432 */
1597cacb 1433static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1434{
1435 u8 val;
1436 int asus_hides_ac97 = 0;
1437
1438 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1439 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1440 asus_hides_ac97 = 1;
1441 }
1442
1443 if (!asus_hides_ac97)
1444 return;
1445
1446 pci_read_config_byte(dev, 0x50, &val);
1447 if (val & 0xc0) {
1448 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1449 pci_read_config_byte(dev, 0x50, &val);
1450 if (val & 0xc0)
f0fda801 1451 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1452 else
f0fda801 1453 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1454 }
1455}
652c538e 1456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1457DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1458
77967052 1459#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1460
1461/*
1462 * If we are using libata we can drive this chip properly but must
1463 * do this early on to make the additional device appear during
1464 * the PCI scanning.
1465 */
5ee2ae7f 1466static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1467{
e34bb370 1468 u32 conf1, conf5, class;
15e0c694
AC		 1469 u8 hdr;
1470
1471 /* Only poke fn 0 */
1472 if (PCI_FUNC(pdev->devfn))
1473 return;
1474
5ee2ae7f
TH		 1475 pci_read_config_dword(pdev, 0x40, &conf1);
1476 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1477
5ee2ae7f
TH		 1478 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1479 conf5 &= ~(1 << 24); /* Clear bit 24 */
1480
1481 switch (pdev->device) {
4daedcfe
TH		 1482 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1483 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
5b6ae5ba 1484 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
5ee2ae7f
TH		 1485 /* The controller should be in single function ahci mode */
1486 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1487 break;
1488
1489 case PCI_DEVICE_ID_JMICRON_JMB365:
1490 case PCI_DEVICE_ID_JMICRON_JMB366:
1491 /* Redirect IDE second PATA port to the right spot */
1492 conf5 |= (1 << 24);
1493 /* Fall through */
1494 case PCI_DEVICE_ID_JMICRON_JMB361:
1495 case PCI_DEVICE_ID_JMICRON_JMB363:
5b6ae5ba 1496 case PCI_DEVICE_ID_JMICRON_JMB369:
5ee2ae7f
TH		 1497 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1498 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1499 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1500 break;
1501
1502 case PCI_DEVICE_ID_JMICRON_JMB368:
1503 /* The controller should be in single function IDE mode */
1504 conf1 |= 0x00C00000; /* Set 22, 23 */
1505 break;
15e0c694 1506 }
5ee2ae7f
TH		 1507
1508 pci_write_config_dword(pdev, 0x40, conf1);
1509 pci_write_config_dword(pdev, 0x80, conf5);
1510
1511 /* Update pdev accordingly */
1512 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1513 pdev->hdr_type = hdr & 0x7f;
1514 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1515
1516 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1517 pdev->class = class >> 8;
15e0c694 1518}
5ee2ae7f
TH		 1519DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1520DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1521DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
5ee2ae7f 1522DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1523DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
5ee2ae7f
TH		 1524DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1525DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1526DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1527DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
e1a2a51e
RW		 1528DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1529DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1530DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
e1a2a51e 1531DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
e1a2a51e
RW		 1533DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1534DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1536DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
15e0c694
AC		 1537
1538#endif
1539
1da177e4 1540#ifdef CONFIG_X86_IO_APIC
b99ea85a 1541static void __devinit quirk_alder_ioapic(struct pci_dev *pdev)
1da177e4
LT		 1542{
1543 int i;
1544
1545 if ((pdev->class >> 8) != 0xff00)
1546 return;
1547
1548 /* the first BAR is the location of the IO APIC...we must
1549 * not touch this (and it's already covered by the fixmap), so
1550 * forcibly insert it into the resource tree */
1551 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1552 insert_resource(&iomem_resource, &pdev->resource[0]);
1553
1554 /* The next five BARs all seem to be rubbish, so just clean
1555 * them out */
1556 for (i=1; i < 6; i++) {
1557 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1558 }
1559
1560}
652c538e 1561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1562#endif
1563
1da177e4
LT		 1564static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1565{
0ba379ec
EB		 1566 pci_msi_off(pdev);
1567 pdev->no_msi = 1;
1da177e4 1568}
652c538e
AM		 1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1572
4602b88d
KA		 1573
1574/*
1575 * It's possible for the MSI to get corrupted if shpc and acpi
1576 * are used together on certain PXH-based systems.
1577 */
1578static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1579{
f5f2b131 1580 pci_msi_off(dev);
4602b88d 1581 dev->no_msi = 1;
f0fda801 1582 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1583}
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1589
ffadcc2f
KCA		 1590/*
1591 * Some Intel PCI Express chipsets have trouble with downstream
1592 * device power management.
1593 */
1594static void quirk_intel_pcie_pm(struct pci_dev * dev)
1595{
1596 pci_pm_d3_delay = 120;
1597 dev->no_d1d2 = 1;
1598}
1599
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1621
426b3b8d 1622#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1623/*
1624 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1625 * remap the original interrupt in the linux kernel to the boot interrupt, so
1626 * that a PCI device's interrupt handler is installed on the boot interrupt
1627 * line instead.
1628 */
1629static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1630{
41b9eb26 1631 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1632 return;
1633
1634 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
fdcdaf6c
BH		 1635 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1636 dev->vendor, dev->device);
e1d3a908 1637}
88d1dce3
OD		 1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1646DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1647DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1648DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1649DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1650DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1654
426b3b8d
SA		 1655/*
1656 * On some chipsets we can disable the generation of legacy INTx boot
1657 * interrupts.
1658 */
1659
1660/*
1661 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1662 * 300641-004US, section 5.7.3.
1663 */
1664#define INTEL_6300_IOAPIC_ABAR 0x40
1665#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1666
1667static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1668{
1669 u16 pci_config_word;
1670
1671 if (noioapicquirk)
1672 return;
1673
1674 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1675 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1676 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1677
fdcdaf6c
BH		 1678 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1679 dev->vendor, dev->device);
426b3b8d 1680}
88d1dce3
OD		 1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1682DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1683
1684/*
1685 * disable boot interrupts on HT-1000
1686 */
1687#define BC_HT1000_FEATURE_REG 0x64
1688#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1689#define BC_HT1000_MAP_IDX 0xC00
1690#define BC_HT1000_MAP_DATA 0xC01
1691
1692static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1693{
1694 u32 pci_config_dword;
1695 u8 irq;
1696
1697 if (noioapicquirk)
1698 return;
1699
1700 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1702 BC_HT1000_PIC_REGS_ENABLE);
1703
1704 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1705 outb(irq, BC_HT1000_MAP_IDX);
1706 outb(0x00, BC_HT1000_MAP_DATA);
1707 }
1708
1709 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1710
fdcdaf6c
BH		 1711 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1712 dev->vendor, dev->device);
77251188 1713}
88d1dce3
OD		 1714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1716
1717/*
1718 * disable boot interrupts on AMD and ATI chipsets
1719 */
1720/*
1721 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1722 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1723 * (due to an erratum).
1724 */
1725#define AMD_813X_MISC 0x40
1726#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1727#define AMD_813X_REV_B1 0x12
bbe19443 1728#define AMD_813X_REV_B2 0x13
542622da
OD		 1729
1730static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1731{
1732 u32 pci_config_dword;
1733
1734 if (noioapicquirk)
1735 return;
4fd8bdc5
SA		 1736 if ((dev->revision == AMD_813X_REV_B1) ||
1737 (dev->revision == AMD_813X_REV_B2))
bbe19443 1738 return;
542622da
OD		 1739
1740 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1741 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1742 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1743
fdcdaf6c
BH		 1744 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1745 dev->vendor, dev->device);
542622da 1746}
4fd8bdc5
SA		 1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1748DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1750DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1751
1752#define AMD_8111_PCI_IRQ_ROUTING 0x56
1753
1754static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1755{
1756 u16 pci_config_word;
1757
1758 if (noioapicquirk)
1759 return;
1760
1761 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1762 if (!pci_config_word) {
fdcdaf6c
BH		 1763 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1764 "already disabled\n", dev->vendor, dev->device);
542622da
OD		 1765 return;
1766 }
1767 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
fdcdaf6c
BH		 1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
542622da 1770}
88d1dce3
OD		 1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1772DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1773#endif /* CONFIG_X86_IO_APIC */
1774
33dced2e
SS		 1775/*
1776 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed...
1779 */
b99ea85a 1780static void __devinit quirk_tc86c001_ide(struct pci_dev *dev)
33dced2e
SS		 1781{
1782 struct resource *r = &dev->resource[0];
1783
1784 if (r->start & 0x8) {
1785 r->start = 0;
1786 r->end = 0xf;
1787 }
1788}
1789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1791 quirk_tc86c001_ide);
1792
1da177e4
LT		 1793static void __devinit quirk_netmos(struct pci_dev *dev)
1794{
1795 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1796 unsigned int num_serial = dev->subsystem_device & 0xf;
1797
1798 /*
1799 * These Netmos parts are multiport serial devices with optional
1800 * parallel ports. Even when parallel ports are present, they
1801 * are identified as class SERIAL, which means the serial driver
1802 * will claim them. To prevent this, mark them as class OTHER.
1803 * These combo devices should be claimed by parport_serial.
1804 *
1805 * The subdevice ID is of the form 0x00PS, where <P> is the number
1806 * of parallel ports and <S> is the number of serial ports.
1807 */
1808 switch (dev->device) {
4c9c1686
JS		 1809 case PCI_DEVICE_ID_NETMOS_9835:
1810 /* Well, this rule doesn't hold for the following 9835 device */
1811 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1812 dev->subsystem_device == 0x0299)
1813 return;
1da177e4
LT		 1814 case PCI_DEVICE_ID_NETMOS_9735:
1815 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1816 case PCI_DEVICE_ID_NETMOS_9845:
1817 case PCI_DEVICE_ID_NETMOS_9855:
08803efe 1818 if (num_parallel) {
f0fda801 1819 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1820 "%u serial); changing class SERIAL to OTHER "
1821 "(use parport_serial)\n",
1822 dev->device, num_parallel, num_serial);
1823 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1824 (dev->class & 0xff);
1825 }
1826 }
1827}
08803efe
YL		 1828DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1829 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1da177e4 1830
16a74744
BH		 1831static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1832{
e64aeccb 1833 u16 command, pmcsr;
16a74744
BH		 1834 u8 __iomem *csr;
1835 u8 cmd_hi;
e64aeccb 1836 int pm;
16a74744
BH		 1837
1838 switch (dev->device) {
1839 /* PCI IDs taken from drivers/net/e100.c */
1840 case 0x1029:
1841 case 0x1030 ... 0x1034:
1842 case 0x1038 ... 0x103E:
1843 case 0x1050 ... 0x1057:
1844 case 0x1059:
1845 case 0x1064 ... 0x106B:
1846 case 0x1091 ... 0x1095:
1847 case 0x1209:
1848 case 0x1229:
1849 case 0x2449:
1850 case 0x2459:
1851 case 0x245D:
1852 case 0x27DC:
1853 break;
1854 default:
1855 return;
1856 }
1857
1858 /*
1859 * Some firmware hands off the e100 with interrupts enabled,
1860 * which can cause a flood of interrupts if packets are
1861 * received before the driver attaches to the device. So
1862 * disable all e100 interrupts here. The driver will
1863 * re-enable them when it's ready.
1864 */
1865 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1866
1bef7dc0 1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1868 return;
1869
e64aeccb
IK		 1870 /*
1871 * Check that the device is in the D0 power state. If it's not,
1872 * there is no point to look any further.
1873 */
1874 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1875 if (pm) {
1876 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1877 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1878 return;
1879 }
1880
1bef7dc0
BH		 1881 /* Convert from PCI bus to resource space. */
1882 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1883 if (!csr) {
f0fda801 1884 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1885 return;
1886 }
1887
1888 cmd_hi = readb(csr + 3);
1889 if (cmd_hi == 0) {
f0fda801 1890 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1891 "disabling\n");
16a74744
BH		 1892 writeb(1, csr + 3);
1893 }
1894
1895 iounmap(csr);
1896}
4c5b28e2
YL		 1897DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1898 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
a5312e28 1899
649426ef
AD		 1900/*
1901 * The 82575 and 82598 may experience data corruption issues when transitioning
1902 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1903 */
1904static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1905{
1906 dev_info(&dev->dev, "Disabling L0s\n");
1907 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1908}
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1923
a5312e28
IK		 1924static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1925{
1926 /* rev 1 ncr53c810 chips don't set the class at all which means
1927 * they don't get their resources remapped. Fix that here.
1928 */
1929
1930 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1931 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1932 dev->class = PCI_CLASS_STORAGE_SCSI;
1933 }
1934}
1935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1936
9d265124
DY		 1937/* Enable 1k I/O space granularity on the Intel P64H2 */
1938static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1939{
1940 u16 en1k;
9d265124
DY		 1941
1942 pci_read_config_word(dev, 0x40, &en1k);
1943
1944 if (en1k & 0x200) {
f0fda801 1945 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2b28ae19 1946 dev->io_window_1k = 1;
9d265124
DY		 1947 }
1948}
1949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1950
cf34a8e0
BG		 1951/* Under some circumstances, AER is not linked with extended capabilities.
1952 * Force it to be linked by setting the corresponding control bit in the
1953 * config space.
1954 */
1597cacb 1955static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1956{
1957 uint8_t b;
1958 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1959 if (!(b & 0x20)) {
1960 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1961 dev_info(&dev->dev,
1962 "Linking AER extended capability\n");
cf34a8e0
BG		 1963 }
1964 }
1965}
1966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1967 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1968DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1969 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1970
53a9bf42
TY		 1971static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1972{
1973 /*
1974 * Disable PCI Bus Parking and PCI Master read caching on CX700
1975 * which causes unspecified timing errors with a VT6212L on the PCI
ca846392
TY		 1976 * bus leading to USB2.0 packet loss.
1977 *
1978 * This quirk is only enabled if a second (on the external PCI bus)
1979 * VT6212L is found -- the CX700 core itself also contains a USB
1980 * host controller with the same PCI ID as the VT6212L.
53a9bf42
TY		 1981 */
1982
ca846392
TY		 1983 /* Count VT6212L instances */
1984 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1985 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
53a9bf42 1986 uint8_t b;
ca846392
TY		 1987
1988 /* p should contain the first (internal) VT6212L -- see if we have
1989 an external one by searching again */
1990 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1991 if (!p)
1992 return;
1993 pci_dev_put(p);
1994
53a9bf42
TY		 1995 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1996 if (b & 0x40) {
1997 /* Turn off PCI Bus Parking */
1998 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1999
bc043274
TY		 2000 dev_info(&dev->dev,
2001 "Disabling VIA CX700 PCI parking\n");
2002 }
2003 }
2004
2005 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2006 if (b != 0) {
53a9bf42
TY		 2007 /* Turn off PCI Master read caching */
2008 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 2009
2010 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2011 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2012
2013 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2014 pci_write_config_byte(dev, 0x77, 0x0);
2015
d6505a52 2016 dev_info(&dev->dev,
bc043274 2017 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2018 }
2019 }
2020}
ca846392 2021DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
53a9bf42 2022
99cb233d
BL		 2023/*
2024 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2025 * VPD end tag will hang the device. This problem was initially
2026 * observed when a vpd entry was created in sysfs
2027 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2028 * will dump 32k of data. Reading a full 32k will cause an access
2029 * beyond the VPD end tag causing the device to hang. Once the device
2030 * is hung, the bnx2 driver will not be able to reset the device.
2031 * We believe that it is legal to read beyond the end tag and
2032 * therefore the solution is to limit the read/write length.
2033 */
2034static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2035{
9d82d8ea 2036 /*
35405f25
DH		 2037 * Only disable the VPD capability for 5706, 5706S, 5708,
2038 * 5708S and 5709 rev. A
9d82d8ea 2039 */
99cb233d 2040 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 2041 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 2042 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 2043 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 2044 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2045 (dev->revision & 0xf0) == 0x0)) {
2046 if (dev->vpd)
2047 dev->vpd->len = 0x80;
2048 }
2049}
2050
bffadffd
YZ		 2051DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2052 PCI_DEVICE_ID_NX2_5706,
2053 quirk_brcm_570x_limit_vpd);
2054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2055 PCI_DEVICE_ID_NX2_5706S,
2056 quirk_brcm_570x_limit_vpd);
2057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2058 PCI_DEVICE_ID_NX2_5708,
2059 quirk_brcm_570x_limit_vpd);
2060DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2061 PCI_DEVICE_ID_NX2_5708S,
2062 quirk_brcm_570x_limit_vpd);
2063DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2064 PCI_DEVICE_ID_NX2_5709,
2065 quirk_brcm_570x_limit_vpd);
2066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2067 PCI_DEVICE_ID_NX2_5709S,
2068 quirk_brcm_570x_limit_vpd);
99cb233d 2069
25e742b2 2070static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
0b471506
MC		 2071{
2072 u32 rev;
2073
2074 pci_read_config_dword(dev, 0xf4, &rev);
2075
2076 /* Only CAP the MRRS if the device is a 5719 A0 */
2077 if (rev == 0x05719000) {
2078 int readrq = pcie_get_readrq(dev);
2079 if (readrq > 2048)
2080 pcie_set_readrq(dev, 2048);
2081 }
2082}
2083
2084DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2085 PCI_DEVICE_ID_TIGON3_5719,
2086 quirk_brcm_5719_limit_mrrs);
2087
26c56dc0
MM		 2088/* Originally in EDAC sources for i82875P:
2089 * Intel tells BIOS developers to hide device 6 which
2090 * configures the overflow device access containing
2091 * the DRBs - this is where we expose device 6.
2092 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2093 */
2094static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2095{
2096 u8 reg;
2097
2098 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2099 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2100 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2101 }
2102}
2103
2104DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2105 quirk_unhide_mch_dev6);
2106DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2107 quirk_unhide_mch_dev6);
2108
12962267 2109#ifdef CONFIG_TILEPRO
f02cbbe6 2110/*
12962267 2111 * The Tilera TILEmpower tilepro platform needs to set the link speed
f02cbbe6
CM		 2112 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2113 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2114 * capability register of the PEX8624 PCIe switch. The switch
2115 * supports link speed auto negotiation, but falsely sets
2116 * the link speed to 5GT/s.
2117 */
2118static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2119{
2120 if (tile_plx_gen1) {
2121 pci_write_config_dword(dev, 0x98, 0x1);
2122 mdelay(50);
2123 }
2124}
2125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
12962267 2126#endif /* CONFIG_TILEPRO */
26c56dc0 2127
3f79e107 2128#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2129/* Some chipsets do not support MSI. We cannot easily rely on setting
2130 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2131 * some other busses controlled by the chipset even if Linux is not
2132 * aware of it. Instead of setting the flag on all busses in the
2133 * machine, simply disable MSI globally.
3f79e107 2134 */
b99ea85a 2135static void __devinit quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2136{
88187dfa 2137 pci_no_msi();
f0fda801 2138 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2139}
ebdf7d39
TH		 2140DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
549e1561 2146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
3f79e107
BG		 2147
2148/* Disable MSI on chipsets that are known to not support it */
2149static void __devinit quirk_disable_msi(struct pci_dev *dev)
2150{
2151 if (dev->subordinate) {
f0fda801 2152 dev_warn(&dev->dev, "MSI quirk detected; "
2153 "subordinate MSI disabled\n");
3f79e107
BG		 2154 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2155 }
2156}
2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
134b3450 2158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
9313ff45 2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
6397c75c 2160
aff61369
CL		 2161/*
2162 * The APC bridge device in AMD 780 family northbridges has some random
2163 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2164 * we use the possible vendor/device IDs of the host bridge for the
2165 * declared quirk, and search for the APC bridge by slot number.
2166 */
2167static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2168{
2169 struct pci_dev *apc_bridge;
2170
2171 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2172 if (apc_bridge) {
2173 if (apc_bridge->device == 0x9602)
2174 quirk_disable_msi(apc_bridge);
2175 pci_dev_put(apc_bridge);
2176 }
2177}
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2180
6397c75c
BG		 2181/* Go through the list of Hypertransport capabilities and
2182 * return 1 if a HT MSI capability is found and enabled */
25e742b2 2183static int msi_ht_cap_enabled(struct pci_dev *dev)
6397c75c 2184{
7a380507
ME		 2185 int pos, ttl = 48;
2186
2187 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2188 while (pos && ttl--) {
2189 u8 flags;
2190
2191 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2192 &flags) == 0)
2193 {
f0fda801 2194 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2195 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2196 "enabled" : "disabled");
7a380507 2197 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2198 }
7a380507
ME		 2199
2200 pos = pci_find_next_ht_capability(dev, pos,
2201 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2202 }
2203 return 0;
2204}
2205
2206/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
25e742b2 2207static void quirk_msi_ht_cap(struct pci_dev *dev)
6397c75c
BG		 2208{
2209 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2210 dev_warn(&dev->dev, "MSI quirk detected; "
2211 "subordinate MSI disabled\n");
6397c75c
BG		 2212 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2213 }
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2216 quirk_msi_ht_cap);
6bae1d96 2217
6397c75c
BG		 2218/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2219 * MSI are supported if the MSI capability set in any of these mappings.
2220 */
25e742b2 2221static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
6397c75c
BG		 2222{
2223 struct pci_dev *pdev;
2224
2225 if (!dev->subordinate)
2226 return;
2227
2228 /* check HT MSI cap on this chipset and the root one.
2229 * a single one having MSI is enough to be sure that MSI are supported.
2230 */
11f242f0 2231 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2232 if (!pdev)
2233 return;
0c875c28 2234 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2235 dev_warn(&dev->dev, "MSI quirk detected; "
2236 "subordinate MSI disabled\n");
6397c75c
BG		 2237 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2238 }
11f242f0 2239 pci_dev_put(pdev);
6397c75c
BG		 2240}
2241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2242 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2243
415b6d0e 2244/* Force enable MSI mapping capability on HT bridges */
25e742b2 2245static void ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2246{
2247 int pos, ttl = 48;
2248
2249 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2250 while (pos && ttl--) {
2251 u8 flags;
2252
2253 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2254 &flags) == 0) {
2255 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2256
2257 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2258 flags | HT_MSI_FLAGS_ENABLE);
2259 }
2260 pos = pci_find_next_ht_capability(dev, pos,
2261 HT_CAPTYPE_MSI_MAPPING);
2262 }
2263}
415b6d0e
BH		 2264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2265 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2266 ht_enable_msi_mapping);
9dc625e7 2267
e0ae4f55
YL		 2268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2269 ht_enable_msi_mapping);
2270
e4146bb9 2271/* The P5N32-SLI motherboards from Asus have a problem with msi
75e07fc3
AP		 2272 * for the MCP55 NIC. It is not yet determined whether the msi problem
2273 * also affects other devices. As for now, turn off msi for this device.
2274 */
2275static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2276{
9251bac9
JD		 2277 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2278
2279 if (board_name &&
2280 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2281 strstr(board_name, "P5N32-E SLI"))) {
75e07fc3 2282 dev_info(&dev->dev,
e4146bb9 2283 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
75e07fc3
AP		 2284 dev->no_msi = 1;
2285 }
2286}
2287DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2288 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2289 nvenet_msi_disable);
2290
66db60ea
NH		 2291/*
2292 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2293 * config register. This register controls the routing of legacy interrupts
2294 * from devices that route through the MCP55. If this register is misprogramed
2295 * interrupts are only sent to the bsp, unlike conventional systems where the
2296 * irq is broadxast to all online cpus. Not having this register set
2297 * properly prevents kdump from booting up properly, so lets make sure that
2298 * we have it set correctly.
2299 * Note this is an undocumented register.
2300 */
2301static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2302{
2303 u32 cfg;
2304
49c2fa08
NH		 2305 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2306 return;
2307
66db60ea
NH		 2308 pci_read_config_dword(dev, 0x74, &cfg);
2309
2310 if (cfg & ((1 << 2) | (1 << 15))) {
2311 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2312 cfg &= ~((1 << 2) | (1 << 15));
2313 pci_write_config_dword(dev, 0x74, cfg);
2314 }
2315}
2316
2317DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2318 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2319 nvbridge_check_legacy_irq_routing);
2320
2321DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2322 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2323 nvbridge_check_legacy_irq_routing);
2324
25e742b2 2325static int ht_check_msi_mapping(struct pci_dev *dev)
de745306
YL		 2326{
2327 int pos, ttl = 48;
2328 int found = 0;
2329
2330 /* check if there is HT MSI cap or enabled on this device */
2331 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2332 while (pos && ttl--) {
2333 u8 flags;
2334
2335 if (found < 1)
2336 found = 1;
2337 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2338 &flags) == 0) {
2339 if (flags & HT_MSI_FLAGS_ENABLE) {
2340 if (found < 2) {
2341 found = 2;
2342 break;
2343 }
2344 }
2345 }
2346 pos = pci_find_next_ht_capability(dev, pos,
2347 HT_CAPTYPE_MSI_MAPPING);
2348 }
2349
2350 return found;
2351}
2352
25e742b2 2353static int host_bridge_with_leaf(struct pci_dev *host_bridge)
de745306
YL		 2354{
2355 struct pci_dev *dev;
2356 int pos;
2357 int i, dev_no;
2358 int found = 0;
2359
2360 dev_no = host_bridge->devfn >> 3;
2361 for (i = dev_no + 1; i < 0x20; i++) {
2362 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2363 if (!dev)
2364 continue;
2365
2366 /* found next host bridge ?*/
2367 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2368 if (pos != 0) {
2369 pci_dev_put(dev);
2370 break;
2371 }
2372
2373 if (ht_check_msi_mapping(dev)) {
2374 found = 1;
2375 pci_dev_put(dev);
2376 break;
2377 }
2378 pci_dev_put(dev);
2379 }
2380
2381 return found;
2382}
2383
eeafda70
YL		 2384#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2385#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2386
25e742b2 2387static int is_end_of_ht_chain(struct pci_dev *dev)
eeafda70
YL		 2388{
2389 int pos, ctrl_off;
2390 int end = 0;
2391 u16 flags, ctrl;
2392
2393 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2394
2395 if (!pos)
2396 goto out;
2397
2398 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2399
2400 ctrl_off = ((flags >> 10) & 1) ?
2401 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2402 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2403
2404 if (ctrl & (1 << 6))
2405 end = 1;
2406
2407out:
2408 return end;
2409}
2410
25e742b2 2411static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2412{
2413 struct pci_dev *host_bridge;
1dec6b05
YL		 2414 int pos;
2415 int i, dev_no;
2416 int found = 0;
2417
2418 dev_no = dev->devfn >> 3;
2419 for (i = dev_no; i >= 0; i--) {
2420 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2421 if (!host_bridge)
2422 continue;
2423
2424 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2425 if (pos != 0) {
2426 found = 1;
2427 break;
2428 }
2429 pci_dev_put(host_bridge);
2430 }
2431
2432 if (!found)
2433 return;
2434
eeafda70
YL		 2435 /* don't enable end_device/host_bridge with leaf directly here */
2436 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2437 host_bridge_with_leaf(host_bridge))
de745306
YL		 2438 goto out;
2439
1dec6b05
YL		 2440 /* root did that ! */
2441 if (msi_ht_cap_enabled(host_bridge))
2442 goto out;
2443
2444 ht_enable_msi_mapping(dev);
2445
2446out:
2447 pci_dev_put(host_bridge);
2448}
2449
25e742b2 2450static void ht_disable_msi_mapping(struct pci_dev *dev)
1dec6b05
YL		 2451{
2452 int pos, ttl = 48;
2453
2454 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2455 while (pos && ttl--) {
2456 u8 flags;
2457
2458 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2459 &flags) == 0) {
6a958d5b 2460 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2461
2462 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2463 flags & ~HT_MSI_FLAGS_ENABLE);
2464 }
2465 pos = pci_find_next_ht_capability(dev, pos,
2466 HT_CAPTYPE_MSI_MAPPING);
2467 }
2468}
2469
25e742b2 2470static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2471{
2472 struct pci_dev *host_bridge;
2473 int pos;
2474 int found;
2475
3d2a5318
RW		 2476 if (!pci_msi_enabled())
2477 return;
2478
1dec6b05
YL		 2479 /* check if there is HT MSI cap or enabled on this device */
2480 found = ht_check_msi_mapping(dev);
2481
2482 /* no HT MSI CAP */
2483 if (found == 0)
2484 return;
9dc625e7
PC		 2485
2486 /*
2487 * HT MSI mapping should be disabled on devices that are below
2488 * a non-Hypertransport host bridge. Locate the host bridge...
2489 */
2490 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2491 if (host_bridge == NULL) {
2492 dev_warn(&dev->dev,
2493 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2494 return;
2495 }
2496
2497 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2498 if (pos != 0) {
2499 /* Host bridge is to HT */
1dec6b05
YL		 2500 if (found == 1) {
2501 /* it is not enabled, try to enable it */
de745306
YL		 2502 if (all)
2503 ht_enable_msi_mapping(dev);
2504 else
2505 nv_ht_enable_msi_mapping(dev);
1dec6b05 2506 }
dff3aef7 2507 goto out;
9dc625e7
PC		 2508 }
2509
1dec6b05
YL		 2510 /* HT MSI is not enabled */
2511 if (found == 1)
dff3aef7 2512 goto out;
9dc625e7 2513
1dec6b05
YL		 2514 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2515 ht_disable_msi_mapping(dev);
dff3aef7
MS		 2516
2517out:
2518 pci_dev_put(host_bridge);
9dc625e7 2519}
de745306 2520
25e742b2 2521static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
de745306
YL		 2522{
2523 return __nv_msi_ht_cap_quirk(dev, 1);
2524}
2525
25e742b2 2526static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
de745306
YL		 2527{
2528 return __nv_msi_ht_cap_quirk(dev, 0);
2529}
2530
2531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306
YL		 2533
2534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
6dab62ee 2535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
9dc625e7 2536
ba698ad4
DM		 2537static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2538{
2539 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2540}
4600c9d7
SH		 2541static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2542{
2543 struct pci_dev *p;
2544
2545 /* SB700 MSI issue will be fixed at HW level from revision A21,
2546 * we need check PCI REVISION ID of SMBus controller to get SB700
2547 * revision.
2548 */
2549 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2550 NULL);
2551 if (!p)
2552 return;
2553
2554 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2555 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2556 pci_dev_put(p);
2557}
ba698ad4
DM		 2558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2559 PCI_DEVICE_ID_TIGON3_5780,
2560 quirk_msi_intx_disable_bug);
2561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2562 PCI_DEVICE_ID_TIGON3_5780S,
2563 quirk_msi_intx_disable_bug);
2564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2565 PCI_DEVICE_ID_TIGON3_5714,
2566 quirk_msi_intx_disable_bug);
2567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2568 PCI_DEVICE_ID_TIGON3_5714S,
2569 quirk_msi_intx_disable_bug);
2570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2571 PCI_DEVICE_ID_TIGON3_5715,
2572 quirk_msi_intx_disable_bug);
2573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2574 PCI_DEVICE_ID_TIGON3_5715S,
2575 quirk_msi_intx_disable_bug);
2576
bc38b411 2577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2578 quirk_msi_intx_disable_ati_bug);
bc38b411 2579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2580 quirk_msi_intx_disable_ati_bug);
bc38b411 2581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2582 quirk_msi_intx_disable_ati_bug);
bc38b411 2583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2584 quirk_msi_intx_disable_ati_bug);
bc38b411 2585DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2586 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2587
2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2589 quirk_msi_intx_disable_bug);
2590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2591 quirk_msi_intx_disable_bug);
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2593 quirk_msi_intx_disable_bug);
2594
7cb6a291
HX		 2595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2596 quirk_msi_intx_disable_bug);
2597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2598 quirk_msi_intx_disable_bug);
2599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2600 quirk_msi_intx_disable_bug);
2601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2602 quirk_msi_intx_disable_bug);
2603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2604 quirk_msi_intx_disable_bug);
2605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2606 quirk_msi_intx_disable_bug);
3f79e107 2607#endif /* CONFIG_PCI_MSI */
3d137310 2608
3322340a
FR		 2609/* Allow manual resource allocation for PCI hotplug bridges
2610 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2611 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2612 * kernel fails to allocate resources when hotplug device is
2613 * inserted and PCI bus is rescanned.
2614 */
2615static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2616{
2617 dev->is_hotplug_bridge = 1;
2618}
2619
2620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2621
03cd8f7e
ML		 2622/*
2623 * This is a quirk for the Ricoh MMC controller found as a part of
2624 * some mulifunction chips.
2625
25985edc 2626 * This is very similar and based on the ricoh_mmc driver written by
03cd8f7e
ML		 2627 * Philip Langdale. Thank you for these magic sequences.
2628 *
2629 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2630 * and one or both of cardbus or firewire.
2631 *
2632 * It happens that they implement SD and MMC
2633 * support as separate controllers (and PCI functions). The linux SDHCI
2634 * driver supports MMC cards but the chip detects MMC cards in hardware
2635 * and directs them to the MMC controller - so the SDHCI driver never sees
2636 * them.
2637 *
2638 * To get around this, we must disable the useless MMC controller.
2639 * At that point, the SDHCI controller will start seeing them
2640 * It seems to be the case that the relevant PCI registers to deactivate the
2641 * MMC controller live on PCI function 0, which might be the cardbus controller
2642 * or the firewire controller, depending on the particular chip in question
2643 *
2644 * This has to be done early, because as soon as we disable the MMC controller
2645 * other pci functions shift up one level, e.g. function #2 becomes function
2646 * #1, and this will confuse the pci core.
2647 */
2648
2649#ifdef CONFIG_MMC_RICOH_MMC
2650static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2651{
2652 /* disable via cardbus interface */
2653 u8 write_enable;
2654 u8 write_target;
2655 u8 disable;
2656
2657 /* disable must be done via function #0 */
2658 if (PCI_FUNC(dev->devfn))
2659 return;
2660
2661 pci_read_config_byte(dev, 0xB7, &disable);
2662 if (disable & 0x02)
2663 return;
2664
2665 pci_read_config_byte(dev, 0x8E, &write_enable);
2666 pci_write_config_byte(dev, 0x8E, 0xAA);
2667 pci_read_config_byte(dev, 0x8D, &write_target);
2668 pci_write_config_byte(dev, 0x8D, 0xB7);
2669 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2670 pci_write_config_byte(dev, 0x8E, write_enable);
2671 pci_write_config_byte(dev, 0x8D, write_target);
2672
2673 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2674 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2675}
2676DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2677DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2678
2679static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2680{
2681 /* disable via firewire interface */
2682 u8 write_enable;
2683 u8 disable;
2684
2685 /* disable must be done via function #0 */
2686 if (PCI_FUNC(dev->devfn))
2687 return;
15bed0f2
MI		 2688 /*
2689 * RICOH 0xe823 SD/MMC card reader fails to recognize
2690 * certain types of SD/MMC cards. Lowering the SD base
2691 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2692 *
2693 * 0x150 - SD2.0 mode enable for changing base clock
2694 * frequency to 50Mhz
2695 * 0xe1 - Base clock frequency
2696 * 0x32 - 50Mhz new clock frequency
2697 * 0xf9 - Key register for 0x150
2698 * 0xfc - key register for 0xe1
2699 */
2700 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2701 pci_write_config_byte(dev, 0xf9, 0xfc);
2702 pci_write_config_byte(dev, 0x150, 0x10);
2703 pci_write_config_byte(dev, 0xf9, 0x00);
2704 pci_write_config_byte(dev, 0xfc, 0x01);
2705 pci_write_config_byte(dev, 0xe1, 0x32);
2706 pci_write_config_byte(dev, 0xfc, 0x00);
2707
2708 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2709 }
3e309cdf
JB		 2710
2711 pci_read_config_byte(dev, 0xCB, &disable);
2712
2713 if (disable & 0x02)
2714 return;
2715
2716 pci_read_config_byte(dev, 0xCA, &write_enable);
2717 pci_write_config_byte(dev, 0xCA, 0x57);
2718 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2719 pci_write_config_byte(dev, 0xCA, write_enable);
2720
2721 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2722 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2723
03cd8f7e
ML		 2724}
2725DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2726DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
be98ca65
MI		 2727DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2728DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
03cd8f7e
ML		 2729#endif /*CONFIG_MMC_RICOH_MMC*/
2730
d3f13810 2731#ifdef CONFIG_DMAR_TABLE
254e4200
SS		 2732#define VTUNCERRMSK_REG 0x1ac
2733#define VTD_MSK_SPEC_ERRORS (1 << 31)
2734/*
2735 * This is a quirk for masking vt-d spec defined errors to platform error
2736 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2737 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2738 * on the RAS config settings of the platform) when a vt-d fault happens.
2739 * The resulting SMI caused the system to hang.
2740 *
2741 * VT-d spec related errors are already handled by the VT-d OS code, so no
2742 * need to report the same error through other channels.
2743 */
2744static void vtd_mask_spec_errors(struct pci_dev *dev)
2745{
2746 u32 word;
2747
2748 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2749 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2750}
2751DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2752DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2753#endif
03cd8f7e 2754
63c44080
HP		 2755static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2756{
2757 /* TI 816x devices do not have class code set when in PCIe boot mode */
40c96236
YL		 2758 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2759 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
63c44080 2760}
40c96236
YL		 2761DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2762 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
63c44080 2763
a94d072b
BH		 2764/* Some PCIe devices do not work reliably with the claimed maximum
2765 * payload size supported.
2766 */
2767static void __devinit fixup_mpss_256(struct pci_dev *dev)
2768{
2769 dev->pcie_mpss = 1; /* 256 bytes */
2770}
2771DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2772 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2773DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2774 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2775DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2776 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2777
d387a8d6
JM		 2778/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2779 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2780 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2781 * until all of the devices are discovered and buses walked, read completion
2782 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2783 * it is possible to hotplug a device with MPS of 256B.
2784 */
2785static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2786{
2787 int err;
2788 u16 rcc;
2789
2790 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2791 return;
2792
2793 /* Intel errata specifies bits to change but does not say what they are.
2794 * Keeping them magical until such time as the registers and values can
2795 * be explained.
2796 */
2797 err = pci_read_config_word(dev, 0x48, &rcc);
2798 if (err) {
2799 dev_err(&dev->dev, "Error attempting to read the read "
2800 "completion coalescing register.\n");
2801 return;
2802 }
2803
2804 if (!(rcc & (1 << 10)))
2805 return;
2806
2807 rcc &= ~(1 << 10);
2808
2809 err = pci_write_config_word(dev, 0x48, rcc);
2810 if (err) {
2811 dev_err(&dev->dev, "Error attempting to write the read "
2812 "completion coalescing register.\n");
2813 return;
2814 }
2815
2816 pr_info_once("Read completion coalescing disabled due to hardware "
2817 "errata relating to 256B MPS.\n");
2818}
2819/* Intel 5000 series memory controllers and ports 2-7 */
2820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2821DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2824DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2825DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2826DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2834/* Intel 5100 series memory controllers and ports 2-7 */
2835DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2836DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2837DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2838DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2846
3209874a 2847
2729d5b1
MS		 2848static ktime_t fixup_debug_start(struct pci_dev *dev,
2849 void (*fn)(struct pci_dev *dev))
3209874a 2850{
2729d5b1
MS		 2851 ktime_t calltime = ktime_set(0, 0);
2852
2853 dev_dbg(&dev->dev, "calling %pF\n", fn);
2854 if (initcall_debug) {
2855 pr_debug("calling %pF @ %i for %s\n",
2856 fn, task_pid_nr(current), dev_name(&dev->dev));
2857 calltime = ktime_get();
2858 }
2859
2860 return calltime;
2861}
2862
2863static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2864 void (*fn)(struct pci_dev *dev))
3209874a 2865{
2729d5b1 2866 ktime_t delta, rettime;
3209874a
AV		 2867 unsigned long long duration;
2868
2729d5b1
MS		 2869 if (initcall_debug) {
2870 rettime = ktime_get();
2871 delta = ktime_sub(rettime, calltime);
2872 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2873 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2874 fn, duration, dev_name(&dev->dev));
2875 }
3209874a
AV		 2876}
2877
f67fd55f
TJ		 2878/*
2879 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2880 * even though no one is handling them (f.e. i915 driver is never loaded).
2881 * Additionally the interrupt destination is not set up properly
2882 * and the interrupt ends up -somewhere-.
2883 *
2884 * These spurious interrupts are "sticky" and the kernel disables
2885 * the (shared) interrupt line after 100.000+ generated interrupts.
2886 *
2887 * Fix it by disabling the still enabled interrupts.
2888 * This resolves crashes often seen on monitor unplug.
2889 */
2890#define I915_DEIER_REG 0x4400c
2891static void __devinit disable_igfx_irq(struct pci_dev *dev)
2892{
2893 void __iomem *regs = pci_iomap(dev, 0, 0);
2894 if (regs == NULL) {
2895 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2896 return;
2897 }
2898
2899 /* Check if any interrupt line is still enabled */
2900 if (readl(regs + I915_DEIER_REG) != 0) {
2901 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2902 "disabling\n");
2903
2904 writel(0, regs + I915_DEIER_REG);
2905 }
2906
2907 pci_iounmap(dev, regs);
2908}
2909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2911
fbebb9fd
BH		 2912/*
2913 * Some devices may pass our check in pci_intx_mask_supported if
2914 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2915 * support this feature.
2916 */
2917static void __devinit quirk_broken_intx_masking(struct pci_dev *dev)
2918{
2919 dev->broken_intx_masking = 1;
2920}
de509f9f
JK		 2921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2922 quirk_broken_intx_masking);
0bdb3b21
AW		 2923DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2924 quirk_broken_intx_masking);
fbebb9fd 2925
bfb0f330
JB		 2926static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2927 struct pci_fixup *end)
3d137310 2928{
2729d5b1
MS		 2929 ktime_t calltime;
2930
f4ca5c6a
YL		 2931 for (; f < end; f++)
2932 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2933 f->class == (u32) PCI_ANY_ID) &&
2934 (f->vendor == dev->vendor ||
2935 f->vendor == (u16) PCI_ANY_ID) &&
2936 (f->device == dev->device ||
2937 f->device == (u16) PCI_ANY_ID)) {
2729d5b1
MS		 2938 calltime = fixup_debug_start(dev, f->hook);
2939 f->hook(dev);
2940 fixup_debug_report(dev, calltime, f->hook);
3d137310 2941 }
3d137310
TP		 2942}
2943
2944extern struct pci_fixup __start_pci_fixups_early[];
2945extern struct pci_fixup __end_pci_fixups_early[];
2946extern struct pci_fixup __start_pci_fixups_header[];
2947extern struct pci_fixup __end_pci_fixups_header[];
2948extern struct pci_fixup __start_pci_fixups_final[];
2949extern struct pci_fixup __end_pci_fixups_final[];
2950extern struct pci_fixup __start_pci_fixups_enable[];
2951extern struct pci_fixup __end_pci_fixups_enable[];
2952extern struct pci_fixup __start_pci_fixups_resume[];
2953extern struct pci_fixup __end_pci_fixups_resume[];
2954extern struct pci_fixup __start_pci_fixups_resume_early[];
2955extern struct pci_fixup __end_pci_fixups_resume_early[];
2956extern struct pci_fixup __start_pci_fixups_suspend[];
2957extern struct pci_fixup __end_pci_fixups_suspend[];
2958
95df8b87 2959static bool pci_apply_fixup_final_quirks;
3d137310
TP		 2960
2961void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2962{
2963 struct pci_fixup *start, *end;
2964
2965 switch(pass) {
2966 case pci_fixup_early:
2967 start = __start_pci_fixups_early;
2968 end = __end_pci_fixups_early;
2969 break;
2970
2971 case pci_fixup_header:
2972 start = __start_pci_fixups_header;
2973 end = __end_pci_fixups_header;
2974 break;
2975
2976 case pci_fixup_final:
95df8b87
MS		 2977 if (!pci_apply_fixup_final_quirks)
2978 return;
3d137310
TP		 2979 start = __start_pci_fixups_final;
2980 end = __end_pci_fixups_final;
2981 break;
2982
2983 case pci_fixup_enable:
2984 start = __start_pci_fixups_enable;
2985 end = __end_pci_fixups_enable;
2986 break;
2987
2988 case pci_fixup_resume:
2989 start = __start_pci_fixups_resume;
2990 end = __end_pci_fixups_resume;
2991 break;
2992
2993 case pci_fixup_resume_early:
2994 start = __start_pci_fixups_resume_early;
2995 end = __end_pci_fixups_resume_early;
2996 break;
2997
2998 case pci_fixup_suspend:
2999 start = __start_pci_fixups_suspend;
3000 end = __end_pci_fixups_suspend;
3001 break;
3002
3003 default:
3004 /* stupid compiler warning, you would think with an enum... */
3005 return;
3006 }
3007 pci_do_fixups(dev, start, end);
3008}
93177a74 3009EXPORT_SYMBOL(pci_fixup_device);
8d86fb2c 3010
735bff10 3011
00010268 3012static int __init pci_apply_final_quirks(void)
8d86fb2c
DW		 3013{
3014 struct pci_dev *dev = NULL;
ac1aa47b
JB		 3015 u8 cls = 0;
3016 u8 tmp;
3017
3018 if (pci_cache_line_size)
3019 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3020 pci_cache_line_size << 2);
8d86fb2c 3021
95df8b87 3022 pci_apply_fixup_final_quirks = true;
4e344b1c 3023 for_each_pci_dev(dev) {
8d86fb2c 3024 pci_fixup_device(pci_fixup_final, dev);
ac1aa47b
JB		 3025 /*
3026 * If arch hasn't set it explicitly yet, use the CLS
3027 * value shared by all PCI devices. If there's a
3028 * mismatch, fall back to the default value.
3029 */
3030 if (!pci_cache_line_size) {
3031 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3032 if (!cls)
3033 cls = tmp;
3034 if (!tmp || cls == tmp)
3035 continue;
3036
3037 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3038 "using %u bytes\n", cls << 2, tmp << 2,
3039 pci_dfl_cache_line_size << 2);
3040 pci_cache_line_size = pci_dfl_cache_line_size;
3041 }
3042 }
735bff10 3043
ac1aa47b
JB		 3044 if (!pci_cache_line_size) {
3045 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3046 cls << 2, pci_dfl_cache_line_size << 2);
2820f333 3047 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
8d86fb2c
DW		 3048 }
3049
3050 return 0;
3051}
3052
cf6f3bf7 3053fs_initcall_sync(pci_apply_final_quirks);
b9c3b266
DC		 3054
3055/*
3056 * Followings are device-specific reset methods which can be used to
3057 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3058 * not available.
3059 */
aeb30016
DC		 3060static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3061{
3062 int pos;
3063
3064 /* only implement PCI_CLASS_SERIAL_USB at present */
3065 if (dev->class == PCI_CLASS_SERIAL_USB) {
3066 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3067 if (!pos)
3068 return -ENOTTY;
3069
3070 if (probe)
3071 return 0;
3072
3073 pci_write_config_byte(dev, pos + 0x4, 1);
3074 msleep(100);
3075
3076 return 0;
3077 } else {
3078 return -ENOTTY;
3079 }
3080}
3081
c763e7b5
DC		 3082static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3083{
76b57c67
BH		 3084 int i;
3085 u16 status;
3086
3087 /*
3088 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3089 *
3090 * The 82599 supports FLR on VFs, but FLR support is reported only
3091 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3092 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3093 */
3094
c763e7b5
DC		 3095 if (probe)
3096 return 0;
3097
76b57c67
BH		 3098 /* Wait for Transaction Pending bit clean */
3099 for (i = 0; i < 4; i++) {
3100 if (i)
3101 msleep((1 << (i - 1)) * 100);
3102
3103 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3104 if (!(status & PCI_EXP_DEVSTA_TRPND))
3105 goto clear;
3106 }
3107
3108 dev_err(&dev->dev, "transaction is not cleared; "
3109 "proceeding with reset anyway\n");
3110
3111clear:
3112 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3113
c763e7b5
DC		 3114 msleep(100);
3115
3116 return 0;
3117}
3118
df558de1
XH		 3119#include "../gpu/drm/i915/i915_reg.h"
3120#define MSG_CTL 0x45010
3121#define NSDE_PWR_STATE 0xd0100
3122#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3123
3124static int reset_ivb_igd(struct pci_dev *dev, int probe)
3125{
3126 void __iomem *mmio_base;
3127 unsigned long timeout;
3128 u32 val;
3129
3130 if (probe)
3131 return 0;
3132
3133 mmio_base = pci_iomap(dev, 0, 0);
3134 if (!mmio_base)
3135 return -ENOMEM;
3136
3137 iowrite32(0x00000002, mmio_base + MSG_CTL);
3138
3139 /*
3140 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3141 * driver loaded sets the right bits. However, this's a reset and
3142 * the bits have been set by i915 previously, so we clobber
3143 * SOUTH_CHICKEN2 register directly here.
3144 */
3145 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3146
3147 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3148 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3149
3150 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3151 do {
3152 val = ioread32(mmio_base + PCH_PP_STATUS);
3153 if ((val & 0xb0000000) == 0)
3154 goto reset_complete;
3155 msleep(10);
3156 } while (time_before(jiffies, timeout));
3157 dev_warn(&dev->dev, "timeout during reset\n");
3158
3159reset_complete:
3160 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3161
3162 pci_iounmap(dev, mmio_base);
3163 return 0;
3164}
3165
c763e7b5 3166#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
df558de1
XH		 3167#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3168#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
c763e7b5 3169
5b889bf2 3170static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 3171 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3172 reset_intel_82599_sfp_virtfn },
df558de1
XH		 3173 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3174 reset_ivb_igd },
3175 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3176 reset_ivb_igd },
aeb30016
DC		 3177 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3178 reset_intel_generic_dev },
b9c3b266
DC		 3179 { 0 }
3180};
5b889bf2 3181
df558de1
XH		 3182/*
3183 * These device-specific reset methods are here rather than in a driver
3184 * because when a host assigns a device to a guest VM, the host may need
3185 * to reset the device but probably doesn't have a driver for it.
3186 */
5b889bf2
RW		 3187int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3188{
df9d1e8a 3189 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 3190
3191 for (i = pci_dev_reset_methods; i->reset; i++) {
3192 if ((i->vendor == dev->vendor ||
3193 i->vendor == (u16)PCI_ANY_ID) &&
3194 (i->device == dev->device ||
3195 i->device == (u16)PCI_ANY_ID))
3196 return i->reset(dev, probe);
3197 }
3198
3199 return -ENOTTY;
3200}
12ea6cad
AW		 3201
3202static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3203{
3204 if (!PCI_FUNC(dev->devfn))
3205 return pci_dev_get(dev);
3206
3207 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3208}
3209
3210static const struct pci_dev_dma_source {
3211 u16 vendor;
3212 u16 device;
3213 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3214} pci_dev_dma_source[] = {
3215 /*
3216 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3217 *
3218 * Some Ricoh devices use the function 0 source ID for DMA on
3219 * other functions of a multifunction device. The DMA devices
3220 * is therefore function 0, which will have implications of the
3221 * iommu grouping of these devices.
3222 */
3223 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3224 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3225 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3226 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3227 { 0 }
3228};
3229
3230/*
3231 * IOMMUs with isolation capabilities need to be programmed with the
3232 * correct source ID of a device. In most cases, the source ID matches
3233 * the device doing the DMA, but sometimes hardware is broken and will
3234 * tag the DMA as being sourced from a different device. This function
3235 * allows that translation. Note that the reference count of the
3236 * returned device is incremented on all paths.
3237 */
3238struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3239{
3240 const struct pci_dev_dma_source *i;
3241
3242 for (i = pci_dev_dma_source; i->dma_source; i++) {
3243 if ((i->vendor == dev->vendor ||
3244 i->vendor == (u16)PCI_ANY_ID) &&
3245 (i->device == dev->device ||
3246 i->device == (u16)PCI_ANY_ID))
3247 return i->dma_source(dev);
3248 }
3249
3250 return pci_dev_get(dev);
3251}
ad805758
AW		 3252
3253static const struct pci_dev_acs_enabled {
3254 u16 vendor;
3255 u16 device;
3256 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3257} pci_dev_acs_enabled[] = {
3258 { 0 }
3259};
3260
3261int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3262{
3263 const struct pci_dev_acs_enabled *i;
3264 int ret;
3265
3266 /*
3267 * Allow devices that do not expose standard PCIe ACS capabilities
3268 * or control to indicate their support here. Multi-function express
3269 * devices which do not allow internal peer-to-peer between functions,
3270 * but do not implement PCIe ACS may wish to return true here.
3271 */
3272 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3273 if ((i->vendor == dev->vendor ||
3274 i->vendor == (u16)PCI_ANY_ID) &&
3275 (i->device == dev->device ||
3276 i->device == (u16)PCI_ANY_ID)) {
3277 ret = i->acs_enabled(dev, acs_flags);
3278 if (ret >= 0)
3279 return ret;
3280 }
3281 }
3282
3283 return -ENOTTY;
3284}
kernel source for telekom puls (alcatel/mediatek)