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76b10467 SW |
1 | /* Freescale Enhanced Local Bus Controller NAND driver |
2 | * | |
3ab8f2a2 | 3 | * Copyright © 2006-2007, 2010 Freescale Semiconductor |
76b10467 SW |
4 | * |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
3ab8f2a2 RZ |
7 | * Jack Lan <jack.lan@freescale.com> |
8 | * Roy Zang <tie-fei.zang@freescale.com> | |
76b10467 SW |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/of_platform.h> | |
3ab8f2a2 | 32 | #include <linux/platform_device.h> |
76b10467 SW |
33 | #include <linux/slab.h> |
34 | #include <linux/interrupt.h> | |
35 | ||
36 | #include <linux/mtd/mtd.h> | |
37 | #include <linux/mtd/nand.h> | |
38 | #include <linux/mtd/nand_ecc.h> | |
39 | #include <linux/mtd/partitions.h> | |
40 | ||
41 | #include <asm/io.h> | |
d4a32fe4 | 42 | #include <asm/fsl_lbc.h> |
76b10467 SW |
43 | |
44 | #define MAX_BANKS 8 | |
45 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
46 | #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ | |
47 | ||
76b10467 SW |
48 | /* mtd information per set */ |
49 | ||
50 | struct fsl_elbc_mtd { | |
51 | struct mtd_info mtd; | |
52 | struct nand_chip chip; | |
3ab8f2a2 | 53 | struct fsl_lbc_ctrl *ctrl; |
76b10467 SW |
54 | |
55 | struct device *dev; | |
56 | int bank; /* Chip select bank number */ | |
57 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
58 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
59 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
60 | }; | |
61 | ||
25985edc | 62 | /* Freescale eLBC FCM controller information */ |
76b10467 | 63 | |
3ab8f2a2 | 64 | struct fsl_elbc_fcm_ctrl { |
76b10467 SW |
65 | struct nand_hw_control controller; |
66 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
67 | ||
76b10467 SW |
68 | u8 __iomem *addr; /* Address of assigned FCM buffer */ |
69 | unsigned int page; /* Last page written to / read from */ | |
70 | unsigned int read_bytes; /* Number of bytes read during command */ | |
71 | unsigned int column; /* Saved column from SEQIN */ | |
72 | unsigned int index; /* Pointer to next byte to 'read' */ | |
73 | unsigned int status; /* status read from LTESR after last op */ | |
74 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
75 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
76 | unsigned int oob; /* Non zero if operating on OOB data */ | |
3ab8f2a2 | 77 | unsigned int counter; /* counter for the initializations */ |
76b10467 SW |
78 | }; |
79 | ||
80 | /* These map to the positions used by the FCM hardware ECC generator */ | |
81 | ||
82 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
83 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
84 | .eccbytes = 3, | |
85 | .eccpos = {6, 7, 8}, | |
86 | .oobfree = { {0, 5}, {9, 7} }, | |
76b10467 SW |
87 | }; |
88 | ||
89 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
90 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
91 | .eccbytes = 3, | |
92 | .eccpos = {8, 9, 10}, | |
93 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
76b10467 SW |
94 | }; |
95 | ||
96 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
97 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
98 | .eccbytes = 12, | |
99 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
100 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
76b10467 SW |
101 | }; |
102 | ||
103 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
104 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
105 | .eccbytes = 12, | |
106 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
107 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
76b10467 SW |
108 | }; |
109 | ||
452db272 AV |
110 | /* |
111 | * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset | |
112 | * 1, so we have to adjust bad block pattern. This pattern should be used for | |
113 | * x8 chips only. So far hardware does not support x16 chips anyway. | |
114 | */ | |
115 | static u8 scan_ff_pattern[] = { 0xff, }; | |
116 | ||
117 | static struct nand_bbt_descr largepage_memorybased = { | |
118 | .options = 0, | |
119 | .offs = 0, | |
120 | .len = 1, | |
121 | .pattern = scan_ff_pattern, | |
122 | }; | |
123 | ||
ec6e0ea3 AV |
124 | /* |
125 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | |
126 | * interfere with ECC positions, that's why we implement our own descriptors. | |
127 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | |
128 | */ | |
129 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
130 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
131 | ||
132 | static struct nand_bbt_descr bbt_main_descr = { | |
133 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
134 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
135 | .offs = 11, | |
136 | .len = 4, | |
137 | .veroffs = 15, | |
138 | .maxblocks = 4, | |
139 | .pattern = bbt_pattern, | |
140 | }; | |
141 | ||
142 | static struct nand_bbt_descr bbt_mirror_descr = { | |
143 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
144 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
145 | .offs = 11, | |
146 | .len = 4, | |
147 | .veroffs = 15, | |
148 | .maxblocks = 4, | |
149 | .pattern = mirror_pattern, | |
150 | }; | |
151 | ||
76b10467 SW |
152 | /*=================================*/ |
153 | ||
154 | /* | |
155 | * Set up the FCM hardware block and page address fields, and the fcm | |
156 | * structure addr field to point to the correct FCM buffer in memory | |
157 | */ | |
158 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
159 | { | |
160 | struct nand_chip *chip = mtd->priv; | |
161 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 162 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 163 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 164 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
165 | int buf_num; |
166 | ||
3ab8f2a2 | 167 | elbc_fcm_ctrl->page = page_addr; |
76b10467 | 168 | |
76b10467 | 169 | if (priv->page_size) { |
9ae84fe8 LS |
170 | /* |
171 | * large page size chip : FPAR[PI] save the lowest 6 bits, | |
172 | * FBAR[BLK] save the other bits. | |
173 | */ | |
174 | out_be32(&lbc->fbar, page_addr >> 6); | |
76b10467 SW |
175 | out_be32(&lbc->fpar, |
176 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | | |
177 | (oob ? FPAR_LP_MS : 0) | column); | |
178 | buf_num = (page_addr & 1) << 2; | |
179 | } else { | |
9ae84fe8 LS |
180 | /* |
181 | * small page size chip : FPAR[PI] save the lowest 5 bits, | |
182 | * FBAR[BLK] save the other bits. | |
183 | */ | |
184 | out_be32(&lbc->fbar, page_addr >> 5); | |
76b10467 SW |
185 | out_be32(&lbc->fpar, |
186 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | | |
187 | (oob ? FPAR_SP_MS : 0) | column); | |
188 | buf_num = page_addr & 7; | |
189 | } | |
190 | ||
3ab8f2a2 RZ |
191 | elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; |
192 | elbc_fcm_ctrl->index = column; | |
76b10467 SW |
193 | |
194 | /* for OOB data point to the second half of the buffer */ | |
195 | if (oob) | |
3ab8f2a2 | 196 | elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; |
76b10467 | 197 | |
3ab8f2a2 RZ |
198 | dev_vdbg(priv->dev, "set_addr: bank=%d, " |
199 | "elbc_fcm_ctrl->addr=0x%p (0x%p), " | |
76b10467 | 200 | "index %x, pes %d ps %d\n", |
3ab8f2a2 RZ |
201 | buf_num, elbc_fcm_ctrl->addr, priv->vbase, |
202 | elbc_fcm_ctrl->index, | |
76b10467 SW |
203 | chip->phys_erase_shift, chip->page_shift); |
204 | } | |
205 | ||
206 | /* | |
207 | * execute FCM command and wait for it to complete | |
208 | */ | |
209 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
210 | { | |
211 | struct nand_chip *chip = mtd->priv; | |
212 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
213 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
214 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 215 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
216 | |
217 | /* Setup the FMR[OP] to execute without write protection */ | |
218 | out_be32(&lbc->fmr, priv->fmr | 3); | |
3ab8f2a2 RZ |
219 | if (elbc_fcm_ctrl->use_mdr) |
220 | out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); | |
76b10467 | 221 | |
3ab8f2a2 | 222 | dev_vdbg(priv->dev, |
76b10467 SW |
223 | "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", |
224 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
3ab8f2a2 | 225 | dev_vdbg(priv->dev, |
76b10467 SW |
226 | "fsl_elbc_run_command: fbar=%08x fpar=%08x " |
227 | "fbcr=%08x bank=%d\n", | |
228 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
229 | in_be32(&lbc->fbcr), priv->bank); | |
230 | ||
1938de46 | 231 | ctrl->irq_status = 0; |
76b10467 SW |
232 | /* execute special operation */ |
233 | out_be32(&lbc->lsor, priv->bank); | |
234 | ||
235 | /* wait for FCM complete flag or timeout */ | |
76b10467 SW |
236 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
237 | FCM_TIMEOUT_MSECS * HZ/1000); | |
3ab8f2a2 | 238 | elbc_fcm_ctrl->status = ctrl->irq_status; |
76b10467 | 239 | /* store mdr value in case it was needed */ |
3ab8f2a2 RZ |
240 | if (elbc_fcm_ctrl->use_mdr) |
241 | elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); | |
76b10467 | 242 | |
3ab8f2a2 | 243 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 | 244 | |
3ab8f2a2 RZ |
245 | if (elbc_fcm_ctrl->status != LTESR_CC) { |
246 | dev_info(priv->dev, | |
c1317f71 SW |
247 | "command failed: fir %x fcr %x status %x mdr %x\n", |
248 | in_be32(&lbc->fir), in_be32(&lbc->fcr), | |
3ab8f2a2 | 249 | elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); |
c1317f71 SW |
250 | return -EIO; |
251 | } | |
76b10467 | 252 | |
f975c6bc MH |
253 | if (chip->ecc.mode != NAND_ECC_HW) |
254 | return 0; | |
255 | ||
256 | if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { | |
257 | uint32_t lteccr = in_be32(&lbc->lteccr); | |
258 | /* | |
259 | * if command was a full page read and the ELBC | |
260 | * has the LTECCR register, then bits 12-15 (ppc order) of | |
261 | * LTECCR indicates which 512 byte sub-pages had fixed errors. | |
262 | * bits 28-31 are uncorrectable errors, marked elsewhere. | |
263 | * for small page nand only 1 bit is used. | |
264 | * if the ELBC doesn't have the lteccr register it reads 0 | |
265 | */ | |
266 | if (lteccr & 0x000F000F) | |
267 | out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ | |
268 | if (lteccr & 0x000F0000) | |
269 | mtd->ecc_stats.corrected++; | |
270 | } | |
271 | ||
c1317f71 | 272 | return 0; |
76b10467 SW |
273 | } |
274 | ||
275 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
276 | { | |
277 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 278 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 279 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
280 | |
281 | if (priv->page_size) { | |
282 | out_be32(&lbc->fir, | |
476459a6 | 283 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
284 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
285 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
476459a6 | 286 | (FIR_OP_CM1 << FIR_OP3_SHIFT) | |
76b10467 SW |
287 | (FIR_OP_RBW << FIR_OP4_SHIFT)); |
288 | ||
289 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
290 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
291 | } else { | |
292 | out_be32(&lbc->fir, | |
476459a6 | 293 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
294 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
295 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
296 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
297 | ||
298 | if (oob) | |
299 | out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); | |
300 | else | |
301 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
302 | } | |
303 | } | |
304 | ||
305 | /* cmdfunc send commands to the FCM */ | |
306 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
307 | int column, int page_addr) | |
308 | { | |
309 | struct nand_chip *chip = mtd->priv; | |
310 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
311 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
312 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 313 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 | 314 | |
3ab8f2a2 | 315 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 SW |
316 | |
317 | /* clear the read buffer */ | |
3ab8f2a2 | 318 | elbc_fcm_ctrl->read_bytes = 0; |
76b10467 | 319 | if (command != NAND_CMD_PAGEPROG) |
3ab8f2a2 | 320 | elbc_fcm_ctrl->index = 0; |
76b10467 SW |
321 | |
322 | switch (command) { | |
323 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
324 | case NAND_CMD_READ1: | |
325 | column += 256; | |
326 | ||
327 | /* fall-through */ | |
328 | case NAND_CMD_READ0: | |
3ab8f2a2 | 329 | dev_dbg(priv->dev, |
76b10467 SW |
330 | "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" |
331 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
332 | ||
333 | ||
334 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
335 | set_addr(mtd, 0, page_addr, 0); | |
336 | ||
3ab8f2a2 RZ |
337 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
338 | elbc_fcm_ctrl->index += column; | |
76b10467 SW |
339 | |
340 | fsl_elbc_do_read(chip, 0); | |
341 | fsl_elbc_run_command(mtd); | |
342 | return; | |
343 | ||
344 | /* READOOB reads only the OOB because no ECC is performed. */ | |
345 | case NAND_CMD_READOOB: | |
3ab8f2a2 | 346 | dev_vdbg(priv->dev, |
76b10467 SW |
347 | "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" |
348 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
349 | ||
350 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
351 | set_addr(mtd, column, page_addr, 1); | |
352 | ||
3ab8f2a2 | 353 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
76b10467 SW |
354 | |
355 | fsl_elbc_do_read(chip, 1); | |
356 | fsl_elbc_run_command(mtd); | |
357 | return; | |
358 | ||
359 | /* READID must read all 5 possible bytes while CEB is active */ | |
360 | case NAND_CMD_READID: | |
3ab8f2a2 | 361 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); |
76b10467 | 362 | |
476459a6 | 363 | out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
364 | (FIR_OP_UA << FIR_OP1_SHIFT) | |
365 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
366 | out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); | |
c02a02ee SX |
367 | /* nand_get_flash_type() reads 8 bytes of entire ID string */ |
368 | out_be32(&lbc->fbcr, 8); | |
369 | elbc_fcm_ctrl->read_bytes = 8; | |
3ab8f2a2 RZ |
370 | elbc_fcm_ctrl->use_mdr = 1; |
371 | elbc_fcm_ctrl->mdr = 0; | |
76b10467 SW |
372 | |
373 | set_addr(mtd, 0, 0, 0); | |
374 | fsl_elbc_run_command(mtd); | |
375 | return; | |
376 | ||
377 | /* ERASE1 stores the block and page address */ | |
378 | case NAND_CMD_ERASE1: | |
3ab8f2a2 | 379 | dev_vdbg(priv->dev, |
76b10467 SW |
380 | "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " |
381 | "page_addr: 0x%x.\n", page_addr); | |
382 | set_addr(mtd, 0, page_addr, 0); | |
383 | return; | |
384 | ||
385 | /* ERASE2 uses the block and page address from ERASE1 */ | |
386 | case NAND_CMD_ERASE2: | |
3ab8f2a2 | 387 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); |
76b10467 SW |
388 | |
389 | out_be32(&lbc->fir, | |
476459a6 | 390 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 | 391 | (FIR_OP_PA << FIR_OP1_SHIFT) | |
476459a6 SW |
392 | (FIR_OP_CM2 << FIR_OP2_SHIFT) | |
393 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
394 | (FIR_OP_RS << FIR_OP4_SHIFT)); | |
76b10467 SW |
395 | |
396 | out_be32(&lbc->fcr, | |
397 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | | |
476459a6 SW |
398 | (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
399 | (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT)); | |
76b10467 SW |
400 | |
401 | out_be32(&lbc->fbcr, 0); | |
3ab8f2a2 RZ |
402 | elbc_fcm_ctrl->read_bytes = 0; |
403 | elbc_fcm_ctrl->use_mdr = 1; | |
76b10467 SW |
404 | |
405 | fsl_elbc_run_command(mtd); | |
406 | return; | |
407 | ||
408 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
409 | case NAND_CMD_SEQIN: { | |
410 | __be32 fcr; | |
3ab8f2a2 RZ |
411 | dev_vdbg(priv->dev, |
412 | "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
76b10467 SW |
413 | "page_addr: 0x%x, column: 0x%x.\n", |
414 | page_addr, column); | |
415 | ||
eeda667a | 416 | elbc_fcm_ctrl->column = column; |
3ab8f2a2 | 417 | elbc_fcm_ctrl->use_mdr = 1; |
76b10467 | 418 | |
a9a552f0 LS |
419 | if (column >= mtd->writesize) { |
420 | /* OOB area */ | |
421 | column -= mtd->writesize; | |
422 | elbc_fcm_ctrl->oob = 1; | |
423 | } else { | |
424 | WARN_ON(column != 0); | |
425 | elbc_fcm_ctrl->oob = 0; | |
426 | } | |
427 | ||
476459a6 SW |
428 | fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
429 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | | |
430 | (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); | |
57650664 | 431 | |
476459a6 | 432 | if (priv->page_size) { |
76b10467 | 433 | out_be32(&lbc->fir, |
476459a6 | 434 | (FIR_OP_CM2 << FIR_OP0_SHIFT) | |
76b10467 SW |
435 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
436 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
437 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
476459a6 SW |
438 | (FIR_OP_CM3 << FIR_OP4_SHIFT) | |
439 | (FIR_OP_CW1 << FIR_OP5_SHIFT) | | |
440 | (FIR_OP_RS << FIR_OP6_SHIFT)); | |
76b10467 SW |
441 | } else { |
442 | out_be32(&lbc->fir, | |
476459a6 | 443 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
444 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | |
445 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
446 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
447 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
476459a6 SW |
448 | (FIR_OP_CM3 << FIR_OP5_SHIFT) | |
449 | (FIR_OP_CW1 << FIR_OP6_SHIFT) | | |
450 | (FIR_OP_RS << FIR_OP7_SHIFT)); | |
76b10467 | 451 | |
a9a552f0 | 452 | if (elbc_fcm_ctrl->oob) |
76b10467 | 453 | /* OOB area --> READOOB */ |
76b10467 | 454 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; |
a9a552f0 | 455 | else |
76b10467 SW |
456 | /* First 256 bytes --> READ0 */ |
457 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
76b10467 SW |
458 | } |
459 | ||
460 | out_be32(&lbc->fcr, fcr); | |
3ab8f2a2 | 461 | set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); |
76b10467 SW |
462 | return; |
463 | } | |
464 | ||
465 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
466 | case NAND_CMD_PAGEPROG: { | |
3ab8f2a2 | 467 | dev_vdbg(priv->dev, |
76b10467 | 468 | "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " |
3ab8f2a2 | 469 | "writing %d bytes.\n", elbc_fcm_ctrl->index); |
76b10467 SW |
470 | |
471 | /* if the write did not start at 0 or is not a full page | |
472 | * then set the exact length, otherwise use a full page | |
473 | * write so the HW generates the ECC. | |
474 | */ | |
3ab8f2a2 | 475 | if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || |
52a474de | 476 | elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) |
e32de766 LS |
477 | out_be32(&lbc->fbcr, |
478 | elbc_fcm_ctrl->index - elbc_fcm_ctrl->column); | |
52a474de | 479 | else |
76b10467 | 480 | out_be32(&lbc->fbcr, 0); |
76b10467 SW |
481 | |
482 | fsl_elbc_run_command(mtd); | |
76b10467 SW |
483 | return; |
484 | } | |
485 | ||
486 | /* CMD_STATUS must read the status byte while CEB is active */ | |
487 | /* Note - it does not wait for the ready line */ | |
488 | case NAND_CMD_STATUS: | |
489 | out_be32(&lbc->fir, | |
490 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | | |
491 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
492 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
493 | out_be32(&lbc->fbcr, 1); | |
494 | set_addr(mtd, 0, 0, 0); | |
3ab8f2a2 | 495 | elbc_fcm_ctrl->read_bytes = 1; |
76b10467 SW |
496 | |
497 | fsl_elbc_run_command(mtd); | |
498 | ||
499 | /* The chip always seems to report that it is | |
500 | * write-protected, even when it is not. | |
501 | */ | |
3ab8f2a2 | 502 | setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); |
76b10467 SW |
503 | return; |
504 | ||
505 | /* RESET without waiting for the ready line */ | |
506 | case NAND_CMD_RESET: | |
3ab8f2a2 | 507 | dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); |
76b10467 SW |
508 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); |
509 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
510 | fsl_elbc_run_command(mtd); | |
511 | return; | |
512 | ||
513 | default: | |
3ab8f2a2 | 514 | dev_err(priv->dev, |
76b10467 SW |
515 | "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", |
516 | command); | |
517 | } | |
518 | } | |
519 | ||
520 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
521 | { | |
522 | /* The hardware does not seem to support multiple | |
523 | * chips per bank. | |
524 | */ | |
525 | } | |
526 | ||
527 | /* | |
528 | * Write buf to the FCM Controller Data Buffer | |
529 | */ | |
530 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
531 | { | |
532 | struct nand_chip *chip = mtd->priv; | |
533 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 534 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
535 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
536 | ||
0ff6631b | 537 | if (len <= 0) { |
3ab8f2a2 RZ |
538 | dev_err(priv->dev, "write_buf of %d bytes", len); |
539 | elbc_fcm_ctrl->status = 0; | |
76b10467 SW |
540 | return; |
541 | } | |
542 | ||
3ab8f2a2 RZ |
543 | if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { |
544 | dev_err(priv->dev, | |
76b10467 SW |
545 | "write_buf beyond end of buffer " |
546 | "(%d requested, %u available)\n", | |
3ab8f2a2 RZ |
547 | len, bufsize - elbc_fcm_ctrl->index); |
548 | len = bufsize - elbc_fcm_ctrl->index; | |
76b10467 SW |
549 | } |
550 | ||
3ab8f2a2 | 551 | memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); |
0ff6631b AV |
552 | /* |
553 | * This is workaround for the weird elbc hangs during nand write, | |
554 | * Scott Wood says: "...perhaps difference in how long it takes a | |
555 | * write to make it through the localbus compared to a write to IMMR | |
556 | * is causing problems, and sync isn't helping for some reason." | |
557 | * Reading back the last byte helps though. | |
558 | */ | |
3ab8f2a2 | 559 | in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); |
0ff6631b | 560 | |
3ab8f2a2 | 561 | elbc_fcm_ctrl->index += len; |
76b10467 SW |
562 | } |
563 | ||
564 | /* | |
565 | * read a byte from either the FCM hardware buffer if it has any data left | |
566 | * otherwise issue a command to read a single byte. | |
567 | */ | |
568 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
569 | { | |
570 | struct nand_chip *chip = mtd->priv; | |
571 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 572 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
573 | |
574 | /* If there are still bytes in the FCM, then use the next byte. */ | |
3ab8f2a2 RZ |
575 | if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) |
576 | return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); | |
76b10467 | 577 | |
3ab8f2a2 | 578 | dev_err(priv->dev, "read_byte beyond end of buffer\n"); |
76b10467 SW |
579 | return ERR_BYTE; |
580 | } | |
581 | ||
582 | /* | |
583 | * Read from the FCM Controller Data Buffer | |
584 | */ | |
585 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
586 | { | |
587 | struct nand_chip *chip = mtd->priv; | |
588 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 589 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
590 | int avail; |
591 | ||
592 | if (len < 0) | |
593 | return; | |
594 | ||
3ab8f2a2 RZ |
595 | avail = min((unsigned int)len, |
596 | elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); | |
597 | memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); | |
598 | elbc_fcm_ctrl->index += avail; | |
76b10467 SW |
599 | |
600 | if (len > avail) | |
3ab8f2a2 | 601 | dev_err(priv->dev, |
76b10467 SW |
602 | "read_buf beyond end of buffer " |
603 | "(%d requested, %d available)\n", | |
604 | len, avail); | |
605 | } | |
606 | ||
607 | /* | |
608 | * Verify buffer against the FCM Controller Data Buffer | |
609 | */ | |
610 | static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
611 | { | |
612 | struct nand_chip *chip = mtd->priv; | |
613 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 614 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
615 | int i; |
616 | ||
617 | if (len < 0) { | |
3ab8f2a2 | 618 | dev_err(priv->dev, "write_buf of %d bytes", len); |
76b10467 SW |
619 | return -EINVAL; |
620 | } | |
621 | ||
3ab8f2a2 RZ |
622 | if ((unsigned int)len > |
623 | elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) { | |
624 | dev_err(priv->dev, | |
625 | "verify_buf beyond end of buffer " | |
626 | "(%d requested, %u available)\n", | |
627 | len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); | |
76b10467 | 628 | |
3ab8f2a2 | 629 | elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes; |
76b10467 SW |
630 | return -EINVAL; |
631 | } | |
632 | ||
633 | for (i = 0; i < len; i++) | |
3ab8f2a2 RZ |
634 | if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i]) |
635 | != buf[i]) | |
76b10467 SW |
636 | break; |
637 | ||
3ab8f2a2 RZ |
638 | elbc_fcm_ctrl->index += len; |
639 | return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO; | |
76b10467 SW |
640 | } |
641 | ||
642 | /* This function is called after Program and Erase Operations to | |
643 | * check for success or failure. | |
644 | */ | |
645 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
646 | { | |
647 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 648 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 | 649 | |
3ab8f2a2 | 650 | if (elbc_fcm_ctrl->status != LTESR_CC) |
76b10467 SW |
651 | return NAND_STATUS_FAIL; |
652 | ||
653 | /* The chip always seems to report that it is | |
654 | * write-protected, even when it is not. | |
655 | */ | |
3ab8f2a2 | 656 | return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; |
76b10467 SW |
657 | } |
658 | ||
659 | static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |
660 | { | |
661 | struct nand_chip *chip = mtd->priv; | |
662 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 663 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 664 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
665 | unsigned int al; |
666 | ||
667 | /* calculate FMR Address Length field */ | |
668 | al = 0; | |
669 | if (chip->pagemask & 0xffff0000) | |
670 | al++; | |
671 | if (chip->pagemask & 0xff000000) | |
672 | al++; | |
673 | ||
d8251108 | 674 | priv->fmr |= al << FMR_AL_SHIFT; |
76b10467 | 675 | |
3ab8f2a2 | 676 | dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", |
76b10467 | 677 | chip->numchips); |
3ab8f2a2 | 678 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", |
76b10467 | 679 | chip->chipsize); |
3ab8f2a2 | 680 | dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", |
76b10467 | 681 | chip->pagemask); |
3ab8f2a2 | 682 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n", |
76b10467 | 683 | chip->chip_delay); |
3ab8f2a2 | 684 | dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", |
76b10467 | 685 | chip->badblockpos); |
3ab8f2a2 | 686 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", |
76b10467 | 687 | chip->chip_shift); |
3ab8f2a2 | 688 | dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", |
76b10467 | 689 | chip->page_shift); |
3ab8f2a2 | 690 | dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", |
76b10467 | 691 | chip->phys_erase_shift); |
3ab8f2a2 | 692 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n", |
76b10467 | 693 | chip->ecclayout); |
3ab8f2a2 | 694 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", |
76b10467 | 695 | chip->ecc.mode); |
3ab8f2a2 | 696 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", |
76b10467 | 697 | chip->ecc.steps); |
3ab8f2a2 | 698 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", |
76b10467 | 699 | chip->ecc.bytes); |
3ab8f2a2 | 700 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", |
76b10467 | 701 | chip->ecc.total); |
3ab8f2a2 | 702 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n", |
76b10467 | 703 | chip->ecc.layout); |
3ab8f2a2 RZ |
704 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); |
705 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); | |
706 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", | |
76b10467 | 707 | mtd->erasesize); |
3ab8f2a2 | 708 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", |
76b10467 | 709 | mtd->writesize); |
3ab8f2a2 | 710 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", |
76b10467 SW |
711 | mtd->oobsize); |
712 | ||
713 | /* adjust Option Register and ECC to match Flash page size */ | |
714 | if (mtd->writesize == 512) { | |
715 | priv->page_size = 0; | |
1938de46 | 716 | clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
76b10467 SW |
717 | } else if (mtd->writesize == 2048) { |
718 | priv->page_size = 1; | |
719 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | |
720 | /* adjust ecc setup if needed */ | |
721 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
722 | BR_DECC_CHK_GEN) { | |
723 | chip->ecc.size = 512; | |
724 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
725 | &fsl_elbc_oob_lp_eccm1 : | |
726 | &fsl_elbc_oob_lp_eccm0; | |
452db272 | 727 | chip->badblock_pattern = &largepage_memorybased; |
76b10467 SW |
728 | } |
729 | } else { | |
3ab8f2a2 | 730 | dev_err(priv->dev, |
76b10467 SW |
731 | "fsl_elbc_init: page size %d is not supported\n", |
732 | mtd->writesize); | |
733 | return -1; | |
734 | } | |
735 | ||
76b10467 SW |
736 | return 0; |
737 | } | |
738 | ||
739 | static int fsl_elbc_read_page(struct mtd_info *mtd, | |
740 | struct nand_chip *chip, | |
46a8cf2d SN |
741 | uint8_t *buf, |
742 | int page) | |
76b10467 SW |
743 | { |
744 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); | |
745 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
746 | ||
747 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
748 | mtd->ecc_stats.failed++; | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | /* ECC will be calculated automatically, and errors will be detected in | |
754 | * waitfunc. | |
755 | */ | |
756 | static void fsl_elbc_write_page(struct mtd_info *mtd, | |
757 | struct nand_chip *chip, | |
758 | const uint8_t *buf) | |
759 | { | |
76b10467 SW |
760 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); |
761 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
76b10467 SW |
762 | } |
763 | ||
764 | static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) | |
765 | { | |
3ab8f2a2 | 766 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 767 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 768 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
769 | struct nand_chip *chip = &priv->chip; |
770 | ||
771 | dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); | |
772 | ||
773 | /* Fill in fsl_elbc_mtd structure */ | |
774 | priv->mtd.priv = chip; | |
775 | priv->mtd.owner = THIS_MODULE; | |
03ed1078 | 776 | |
d8251108 SL |
777 | /* set timeout to maximum */ |
778 | priv->fmr = 15 << FMR_CWTO_SHIFT; | |
779 | if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) | |
780 | priv->fmr |= FMR_ECCM; | |
76b10467 SW |
781 | |
782 | /* fill in nand_chip structure */ | |
783 | /* set up function call table */ | |
784 | chip->read_byte = fsl_elbc_read_byte; | |
785 | chip->write_buf = fsl_elbc_write_buf; | |
786 | chip->read_buf = fsl_elbc_read_buf; | |
787 | chip->verify_buf = fsl_elbc_verify_buf; | |
788 | chip->select_chip = fsl_elbc_select_chip; | |
789 | chip->cmdfunc = fsl_elbc_cmdfunc; | |
790 | chip->waitfunc = fsl_elbc_wait; | |
791 | ||
ec6e0ea3 AV |
792 | chip->bbt_td = &bbt_main_descr; |
793 | chip->bbt_md = &bbt_mirror_descr; | |
794 | ||
76b10467 | 795 | /* set up nand options */ |
a40f7341 | 796 | chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR; |
bb9ebd4e | 797 | chip->bbt_options = NAND_BBT_USE_FLASH; |
76b10467 | 798 | |
3ab8f2a2 | 799 | chip->controller = &elbc_fcm_ctrl->controller; |
76b10467 SW |
800 | chip->priv = priv; |
801 | ||
802 | chip->ecc.read_page = fsl_elbc_read_page; | |
803 | chip->ecc.write_page = fsl_elbc_write_page; | |
804 | ||
805 | /* If CS Base Register selects full hardware ECC then use it */ | |
806 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
807 | BR_DECC_CHK_GEN) { | |
808 | chip->ecc.mode = NAND_ECC_HW; | |
809 | /* put in small page settings and adjust later if needed */ | |
810 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
811 | &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; | |
812 | chip->ecc.size = 512; | |
813 | chip->ecc.bytes = 3; | |
814 | } else { | |
815 | /* otherwise fall back to default software ECC */ | |
816 | chip->ecc.mode = NAND_ECC_SOFT; | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
822 | static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) | |
823 | { | |
3ab8f2a2 | 824 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
825 | nand_release(&priv->mtd); |
826 | ||
9ebed3e6 AV |
827 | kfree(priv->mtd.name); |
828 | ||
76b10467 SW |
829 | if (priv->vbase) |
830 | iounmap(priv->vbase); | |
831 | ||
3ab8f2a2 | 832 | elbc_fcm_ctrl->chips[priv->bank] = NULL; |
76b10467 | 833 | kfree(priv); |
76b10467 SW |
834 | return 0; |
835 | } | |
836 | ||
3ab8f2a2 RZ |
837 | static DEFINE_MUTEX(fsl_elbc_nand_mutex); |
838 | ||
839 | static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev) | |
76b10467 | 840 | { |
3ab8f2a2 | 841 | struct fsl_lbc_regs __iomem *lbc; |
76b10467 SW |
842 | struct fsl_elbc_mtd *priv; |
843 | struct resource res; | |
3ab8f2a2 | 844 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl; |
76b10467 | 845 | static const char *part_probe_types[] |
b6b0fae7 | 846 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; |
76b10467 SW |
847 | int ret; |
848 | int bank; | |
3ab8f2a2 RZ |
849 | struct device *dev; |
850 | struct device_node *node = pdev->dev.of_node; | |
b6b0fae7 | 851 | struct mtd_part_parser_data ppdata; |
3ab8f2a2 | 852 | |
b6b0fae7 | 853 | ppdata.of_node = pdev->dev.of_node; |
3ab8f2a2 RZ |
854 | if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) |
855 | return -ENODEV; | |
856 | lbc = fsl_lbc_ctrl_dev->regs; | |
857 | dev = fsl_lbc_ctrl_dev->dev; | |
76b10467 SW |
858 | |
859 | /* get, allocate and map the memory resource */ | |
860 | ret = of_address_to_resource(node, 0, &res); | |
861 | if (ret) { | |
3ab8f2a2 | 862 | dev_err(dev, "failed to get resource\n"); |
76b10467 SW |
863 | return ret; |
864 | } | |
865 | ||
866 | /* find which chip select it is connected to */ | |
867 | for (bank = 0; bank < MAX_BANKS; bank++) | |
868 | if ((in_be32(&lbc->bank[bank].br) & BR_V) && | |
869 | (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && | |
870 | (in_be32(&lbc->bank[bank].br) & | |
871 | in_be32(&lbc->bank[bank].or) & BR_BA) | |
0b824d2b | 872 | == fsl_lbc_addr(res.start)) |
76b10467 SW |
873 | break; |
874 | ||
875 | if (bank >= MAX_BANKS) { | |
3ab8f2a2 | 876 | dev_err(dev, "address did not match any chip selects\n"); |
76b10467 SW |
877 | return -ENODEV; |
878 | } | |
879 | ||
880 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
881 | if (!priv) | |
882 | return -ENOMEM; | |
883 | ||
3ab8f2a2 RZ |
884 | mutex_lock(&fsl_elbc_nand_mutex); |
885 | if (!fsl_lbc_ctrl_dev->nand) { | |
886 | elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL); | |
887 | if (!elbc_fcm_ctrl) { | |
888 | dev_err(dev, "failed to allocate memory\n"); | |
889 | mutex_unlock(&fsl_elbc_nand_mutex); | |
890 | ret = -ENOMEM; | |
891 | goto err; | |
892 | } | |
893 | elbc_fcm_ctrl->counter++; | |
894 | ||
895 | spin_lock_init(&elbc_fcm_ctrl->controller.lock); | |
896 | init_waitqueue_head(&elbc_fcm_ctrl->controller.wq); | |
897 | fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; | |
898 | } else { | |
899 | elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; | |
900 | } | |
901 | mutex_unlock(&fsl_elbc_nand_mutex); | |
902 | ||
903 | elbc_fcm_ctrl->chips[bank] = priv; | |
76b10467 | 904 | priv->bank = bank; |
3ab8f2a2 RZ |
905 | priv->ctrl = fsl_lbc_ctrl_dev; |
906 | priv->dev = dev; | |
76b10467 | 907 | |
8a19b558 | 908 | priv->vbase = ioremap(res.start, resource_size(&res)); |
76b10467 | 909 | if (!priv->vbase) { |
3ab8f2a2 | 910 | dev_err(dev, "failed to map chip region\n"); |
76b10467 SW |
911 | ret = -ENOMEM; |
912 | goto err; | |
913 | } | |
914 | ||
650da9d0 | 915 | priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); |
9ebed3e6 AV |
916 | if (!priv->mtd.name) { |
917 | ret = -ENOMEM; | |
918 | goto err; | |
919 | } | |
920 | ||
76b10467 SW |
921 | ret = fsl_elbc_chip_init(priv); |
922 | if (ret) | |
923 | goto err; | |
924 | ||
5e81e88a | 925 | ret = nand_scan_ident(&priv->mtd, 1, NULL); |
76b10467 SW |
926 | if (ret) |
927 | goto err; | |
928 | ||
929 | ret = fsl_elbc_chip_init_tail(&priv->mtd); | |
930 | if (ret) | |
931 | goto err; | |
932 | ||
933 | ret = nand_scan_tail(&priv->mtd); | |
934 | if (ret) | |
935 | goto err; | |
936 | ||
76b10467 SW |
937 | /* First look for RedBoot table or partitions on the command |
938 | * line, these take precedence over device tree information */ | |
99add422 DES |
939 | mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata, |
940 | NULL, 0); | |
76b10467 | 941 | |
4712fff9 SR |
942 | printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n", |
943 | (unsigned long long)res.start, priv->bank); | |
76b10467 SW |
944 | return 0; |
945 | ||
946 | err: | |
947 | fsl_elbc_chip_remove(priv); | |
948 | return ret; | |
949 | } | |
950 | ||
3ab8f2a2 | 951 | static int fsl_elbc_nand_remove(struct platform_device *pdev) |
76b10467 | 952 | { |
76b10467 | 953 | int i; |
3ab8f2a2 | 954 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; |
76b10467 | 955 | for (i = 0; i < MAX_BANKS; i++) |
3ab8f2a2 RZ |
956 | if (elbc_fcm_ctrl->chips[i]) |
957 | fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]); | |
958 | ||
959 | mutex_lock(&fsl_elbc_nand_mutex); | |
960 | elbc_fcm_ctrl->counter--; | |
961 | if (!elbc_fcm_ctrl->counter) { | |
962 | fsl_lbc_ctrl_dev->nand = NULL; | |
963 | kfree(elbc_fcm_ctrl); | |
76b10467 | 964 | } |
3ab8f2a2 | 965 | mutex_unlock(&fsl_elbc_nand_mutex); |
76b10467 SW |
966 | |
967 | return 0; | |
968 | ||
76b10467 SW |
969 | } |
970 | ||
3ab8f2a2 RZ |
971 | static const struct of_device_id fsl_elbc_nand_match[] = { |
972 | { .compatible = "fsl,elbc-fcm-nand", }, | |
76b10467 SW |
973 | {} |
974 | }; | |
975 | ||
3ab8f2a2 | 976 | static struct platform_driver fsl_elbc_nand_driver = { |
76b10467 | 977 | .driver = { |
3ab8f2a2 | 978 | .name = "fsl,elbc-fcm-nand", |
4018294b | 979 | .owner = THIS_MODULE, |
3ab8f2a2 | 980 | .of_match_table = fsl_elbc_nand_match, |
76b10467 | 981 | }, |
3ab8f2a2 RZ |
982 | .probe = fsl_elbc_nand_probe, |
983 | .remove = fsl_elbc_nand_remove, | |
76b10467 SW |
984 | }; |
985 | ||
f99640de | 986 | module_platform_driver(fsl_elbc_nand_driver); |
76b10467 SW |
987 | |
988 | MODULE_LICENSE("GPL"); | |
989 | MODULE_AUTHOR("Freescale"); | |
990 | MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); |