[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / devices / lart.c


/*
 * MTD driver for the 28F160F3 Flash Memory (non-CFI) on LART.
 *
 * Author: Abraham vd Merwe <abraham@2d3d.co.za>
 *
 * Copyright (c) 2001, 2d3D, Inc.
 *
 * This code is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * References:
 *
 *    [1] 3 Volt Fast Boot Block Flash Memory" Intel Datasheet
 *           - Order Number: 290644-005
 *           - January 2000
 *
 *    [2] MTD internal API documentation
 *           - http://www.linux-mtd.infradead.org/ 
 *
 * Limitations:
 *
 *    Even though this driver is written for 3 Volt Fast Boot
 *    Block Flash Memory, it is rather specific to LART. With
 *    Minor modifications, notably the without data/address line
 *    mangling and different bus settings, etc. it should be
 *    trivial to adapt to other platforms.
 *
 *    If somebody would sponsor me a different board, I'll
 *    adapt the driver (:
 */

/* debugging */
//#define LART_DEBUG

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>

#ifndef CONFIG_SA1100_LART
#error This is for LART architecture only
#endif

static char module_name[] = "lart";

/*
 * These values is specific to 28Fxxxx3 flash memory.
 * See section 2.3.1 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
 */
#define FLASH_BLOCKSIZE_PARAM		(4096 * BUSWIDTH)
#define FLASH_NUMBLOCKS_16m_PARAM	8
#define FLASH_NUMBLOCKS_8m_PARAM	8

/*
 * These values is specific to 28Fxxxx3 flash memory.
 * See section 2.3.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
 */
#define FLASH_BLOCKSIZE_MAIN		(32768 * BUSWIDTH)
#define FLASH_NUMBLOCKS_16m_MAIN	31
#define FLASH_NUMBLOCKS_8m_MAIN		15

/*
 * These values are specific to LART
 */

/* general */
#define BUSWIDTH			4				/* don't change this - a lot of the code _will_ break if you change this */
#define FLASH_OFFSET		0xe8000000		/* see linux/arch/arm/mach-sa1100/lart.c */

/* blob */
#define NUM_BLOB_BLOCKS		FLASH_NUMBLOCKS_16m_PARAM
#define BLOB_START			0x00000000
#define BLOB_LEN			(NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)

/* kernel */
#define NUM_KERNEL_BLOCKS	7
#define KERNEL_START		(BLOB_START + BLOB_LEN)
#define KERNEL_LEN			(NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)

/* initial ramdisk */
#define NUM_INITRD_BLOCKS	24
#define INITRD_START		(KERNEL_START + KERNEL_LEN)
#define INITRD_LEN			(NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)

/*
 * See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
 */
#define READ_ARRAY			0x00FF00FF		/* Read Array/Reset */
#define READ_ID_CODES		0x00900090		/* Read Identifier Codes */
#define ERASE_SETUP			0x00200020		/* Block Erase */
#define ERASE_CONFIRM		0x00D000D0		/* Block Erase and Program Resume */
#define PGM_SETUP			0x00400040		/* Program */
#define STATUS_READ			0x00700070		/* Read Status Register */
#define STATUS_CLEAR		0x00500050		/* Clear Status Register */
#define STATUS_BUSY			0x00800080		/* Write State Machine Status (WSMS) */
#define STATUS_ERASE_ERR	0x00200020		/* Erase Status (ES) */
#define STATUS_PGM_ERR		0x00100010		/* Program Status (PS) */

/*
 * See section 4.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
 */
#define FLASH_MANUFACTURER			0x00890089
#define FLASH_DEVICE_8mbit_TOP		0x88f188f1
#define FLASH_DEVICE_8mbit_BOTTOM	0x88f288f2
#define FLASH_DEVICE_16mbit_TOP		0x88f388f3
#define FLASH_DEVICE_16mbit_BOTTOM	0x88f488f4

/***************************************************************************************************/

/*
 * The data line mapping on LART is as follows:
 *
 *   	 U2  CPU |   U3  CPU
 *   	 -------------------
 *   	  0  20  |   0   12
 *   	  1  22  |   1   14
 *   	  2  19  |   2   11
 *   	  3  17  |   3   9
 *   	  4  24  |   4   0
 *   	  5  26  |   5   2
 *   	  6  31  |   6   7
 *   	  7  29  |   7   5
 *   	  8  21  |   8   13
 *   	  9  23  |   9   15
 *   	  10 18  |   10  10
 *   	  11 16  |   11  8
 *   	  12 25  |   12  1
 *   	  13 27  |   13  3
 *   	  14 30  |   14  6
 *   	  15 28  |   15  4
 */

/* Mangle data (x) */
#define DATA_TO_FLASH(x)				\
	(									\
		(((x) & 0x08009000) >> 11)	+	\
		(((x) & 0x00002000) >> 10)	+	\
		(((x) & 0x04004000) >> 8)	+	\
		(((x) & 0x00000010) >> 4)	+	\
		(((x) & 0x91000820) >> 3)	+	\
		(((x) & 0x22080080) >> 2)	+	\
		((x) & 0x40000400)			+	\
		(((x) & 0x00040040) << 1)	+	\
		(((x) & 0x00110000) << 4)	+	\
		(((x) & 0x00220100) << 5)	+	\
		(((x) & 0x00800208) << 6)	+	\
		(((x) & 0x00400004) << 9)	+	\
		(((x) & 0x00000001) << 12)	+	\
		(((x) & 0x00000002) << 13)		\
	)

/* Unmangle data (x) */
#define FLASH_TO_DATA(x)				\
	(									\
		(((x) & 0x00010012) << 11)	+	\
		(((x) & 0x00000008) << 10)	+	\
		(((x) & 0x00040040) << 8)	+	\
		(((x) & 0x00000001) << 4)	+	\
		(((x) & 0x12200104) << 3)	+	\
		(((x) & 0x08820020) << 2)	+	\
		((x) & 0x40000400)			+	\
		(((x) & 0x00080080) >> 1)	+	\
		(((x) & 0x01100000) >> 4)	+	\
		(((x) & 0x04402000) >> 5)	+	\
		(((x) & 0x20008200) >> 6)	+	\
		(((x) & 0x80000800) >> 9)	+	\
		(((x) & 0x00001000) >> 12)	+	\
		(((x) & 0x00004000) >> 13)		\
	)

/*
 * The address line mapping on LART is as follows:
 *
 *   	 U3  CPU |   U2  CPU
 *   	 -------------------
 *   	  0  2   |   0   2
 *   	  1  3   |   1   3
 *   	  2  9   |   2   9
 *   	  3  13  |   3   8
 *   	  4  8   |   4   7
 *   	  5  12  |   5   6
 *   	  6  11  |   6   5
 *   	  7  10  |   7   4
 *   	  8  4   |   8   10
 *   	  9  5   |   9   11
 *   	 10  6   |   10  12
 *   	 11  7   |   11  13
 *
 *   	 BOOT BLOCK BOUNDARY
 *
 *   	 12  15  |   12  15
 *   	 13  14  |   13  14
 *   	 14  16  |   14  16
 *
 *   	 MAIN BLOCK BOUNDARY
 *
 *   	 15  17  |   15  18
 *   	 16  18  |   16  17
 *   	 17  20  |   17  20
 *   	 18  19  |   18  19
 *   	 19  21  |   19  21
 *
 * As we can see from above, the addresses aren't mangled across
 * block boundaries, so we don't need to worry about address
 * translations except for sending/reading commands during
 * initialization
 */

/* Mangle address (x) on chip U2 */
#define ADDR_TO_FLASH_U2(x)				\
	(									\
		(((x) & 0x00000f00) >> 4)	+	\
		(((x) & 0x00042000) << 1)	+	\
		(((x) & 0x0009c003) << 2)	+	\
		(((x) & 0x00021080) << 3)	+	\
		(((x) & 0x00000010) << 4)	+	\
		(((x) & 0x00000040) << 5)	+	\
		(((x) & 0x00000024) << 7)	+	\
		(((x) & 0x00000008) << 10)		\
	)

/* Unmangle address (x) on chip U2 */
#define FLASH_U2_TO_ADDR(x)				\
	(									\
		(((x) << 4) & 0x00000f00)	+	\
		(((x) >> 1) & 0x00042000)	+	\
		(((x) >> 2) & 0x0009c003)	+	\
		(((x) >> 3) & 0x00021080)	+	\
		(((x) >> 4) & 0x00000010)	+	\
		(((x) >> 5) & 0x00000040)	+	\
		(((x) >> 7) & 0x00000024)	+	\
		(((x) >> 10) & 0x00000008)		\
	)

/* Mangle address (x) on chip U3 */
#define ADDR_TO_FLASH_U3(x)				\
	(									\
		(((x) & 0x00000080) >> 3)	+	\
		(((x) & 0x00000040) >> 1)	+	\
		(((x) & 0x00052020) << 1)	+	\
		(((x) & 0x00084f03) << 2)	+	\
		(((x) & 0x00029010) << 3)	+	\
		(((x) & 0x00000008) << 5)	+	\
		(((x) & 0x00000004) << 7)		\
	)

/* Unmangle address (x) on chip U3 */
#define FLASH_U3_TO_ADDR(x)				\
	(									\
		(((x) << 3) & 0x00000080)	+	\
		(((x) << 1) & 0x00000040)	+	\
		(((x) >> 1) & 0x00052020)	+	\
		(((x) >> 2) & 0x00084f03)	+	\
		(((x) >> 3) & 0x00029010)	+	\
		(((x) >> 5) & 0x00000008)	+	\
		(((x) >> 7) & 0x00000004)		\
	)

/***************************************************************************************************/

static __u8 read8 (__u32 offset)
{
   volatile __u8 *data = (__u8 *) (FLASH_OFFSET + offset);
#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(): 0x%.8x -> 0x%.2x\n", __func__, offset, *data);
#endif
   return (*data);
}

static __u32 read32 (__u32 offset)
{
   volatile __u32 *data = (__u32 *) (FLASH_OFFSET + offset);
#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(): 0x%.8x -> 0x%.8x\n", __func__, offset, *data);
#endif
   return (*data);
}

static void write32 (__u32 x,__u32 offset)
{
   volatile __u32 *data = (__u32 *) (FLASH_OFFSET + offset);
   *data = x;
#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(): 0x%.8x <- 0x%.8x\n", __func__, offset, *data);
#endif
}

/***************************************************************************************************/

/*
 * Probe for 16mbit flash memory on a LART board without doing
 * too much damage. Since we need to write 1 dword to memory,
 * we're f**cked if this happens to be DRAM since we can't
 * restore the memory (otherwise we might exit Read Array mode).
 *
 * Returns 1 if we found 16mbit flash memory on LART, 0 otherwise.
 */
static int flash_probe (void)
{
   __u32 manufacturer,devtype;

   /* setup "Read Identifier Codes" mode */
   write32 (DATA_TO_FLASH (READ_ID_CODES),0x00000000);

   /* probe U2. U2/U3 returns the same data since the first 3
	* address lines is mangled in the same way */
   manufacturer = FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000000)));
   devtype = FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000001)));

   /* put the flash back into command mode */
   write32 (DATA_TO_FLASH (READ_ARRAY),0x00000000);

   return (manufacturer == FLASH_MANUFACTURER && (devtype == FLASH_DEVICE_16mbit_TOP || devtype == FLASH_DEVICE_16mbit_BOTTOM));
}

/*
 * Erase one block of flash memory at offset ``offset'' which is any
 * address within the block which should be erased.
 *
 * Returns 1 if successful, 0 otherwise.
 */
static inline int erase_block (__u32 offset)
{
   __u32 status;

#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(): 0x%.8x\n", __func__, offset);
#endif

   /* erase and confirm */
   write32 (DATA_TO_FLASH (ERASE_SETUP),offset);
   write32 (DATA_TO_FLASH (ERASE_CONFIRM),offset);

   /* wait for block erase to finish */
   do
	 {
		write32 (DATA_TO_FLASH (STATUS_READ),offset);
		status = FLASH_TO_DATA (read32 (offset));
	 }
   while ((~status & STATUS_BUSY) != 0);

   /* put the flash back into command mode */
   write32 (DATA_TO_FLASH (READ_ARRAY),offset);

   /* was the erase successful? */
   if ((status & STATUS_ERASE_ERR))
	 {
		printk (KERN_WARNING "%s: erase error at address 0x%.8x.\n",module_name,offset);
		return (0);
	 }

   return (1);
}

static int flash_erase (struct mtd_info *mtd,struct erase_info *instr)
{
   __u32 addr,len;
   int i,first;

#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n", __func__, instr->addr, instr->len);
#endif

   /*
	* check that both start and end of the requested erase are
	* aligned with the erasesize at the appropriate addresses.
	*
	* skip all erase regions which are ended before the start of
	* the requested erase. Actually, to save on the calculations,
	* we skip to the first erase region which starts after the
	* start of the requested erase, and then go back one.
	*/
   for (i = 0; i < mtd->numeraseregions && instr->addr >= mtd->eraseregions[i].offset; i++) ;
   i--;

   /*
	* ok, now i is pointing at the erase region in which this
	* erase request starts. Check the start of the requested
	* erase range is aligned with the erase size which is in
	* effect here.
	*/
   if (i < 0 || (instr->addr & (mtd->eraseregions[i].erasesize - 1)))
      return -EINVAL;

   /* Remember the erase region we start on */
   first = i;

   /*
	* next, check that the end of the requested erase is aligned
	* with the erase region at that address.
	*
	* as before, drop back one to point at the region in which
	* the address actually falls
	*/
   for (; i < mtd->numeraseregions && instr->addr + instr->len >= mtd->eraseregions[i].offset; i++) ;
   i--;

   /* is the end aligned on a block boundary? */
   if (i < 0 || ((instr->addr + instr->len) & (mtd->eraseregions[i].erasesize - 1)))
      return -EINVAL;

   addr = instr->addr;
   len = instr->len;

   i = first;

   /* now erase those blocks */
   while (len)
	 {
		if (!erase_block (addr))
		  {
			 instr->state = MTD_ERASE_FAILED;
			 return (-EIO);
		  }

		addr += mtd->eraseregions[i].erasesize;
		len -= mtd->eraseregions[i].erasesize;

		if (addr == mtd->eraseregions[i].offset + (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++;
	 }

   instr->state = MTD_ERASE_DONE;
   mtd_erase_callback(instr);

   return (0);
}

static int flash_read (struct mtd_info *mtd,loff_t from,size_t len,size_t *retlen,u_char *buf)
{
#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(from = 0x%.8x, len = %d)\n", __func__, (__u32)from, len);
#endif

   /* sanity checks */
   if (!len) return (0);

   /* we always read len bytes */
   *retlen = len;

   /* first, we read bytes until we reach a dword boundary */
   if (from & (BUSWIDTH - 1))
	 {
		int gap = BUSWIDTH - (from & (BUSWIDTH - 1));

		while (len && gap--) *buf++ = read8 (from++), len--;
	 }

   /* now we read dwords until we reach a non-dword boundary */
   while (len >= BUSWIDTH)
	 {
		*((__u32 *) buf) = read32 (from);

		buf += BUSWIDTH;
		from += BUSWIDTH;
		len -= BUSWIDTH;
	 }

   /* top up the last unaligned bytes */
   if (len & (BUSWIDTH - 1))
	 while (len--) *buf++ = read8 (from++);

   return (0);
}

/*
 * Write one dword ``x'' to flash memory at offset ``offset''. ``offset''
 * must be 32 bits, i.e. it must be on a dword boundary.
 *
 * Returns 1 if successful, 0 otherwise.
 */
static inline int write_dword (__u32 offset,__u32 x)
{
   __u32 status;

#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(): 0x%.8x <- 0x%.8x\n", __func__, offset, x);
#endif

   /* setup writing */
   write32 (DATA_TO_FLASH (PGM_SETUP),offset);

   /* write the data */
   write32 (x,offset);

   /* wait for the write to finish */
   do
	 {
		write32 (DATA_TO_FLASH (STATUS_READ),offset);
		status = FLASH_TO_DATA (read32 (offset));
	 }
   while ((~status & STATUS_BUSY) != 0);

   /* put the flash back into command mode */
   write32 (DATA_TO_FLASH (READ_ARRAY),offset);

   /* was the write successful? */
   if ((status & STATUS_PGM_ERR) || read32 (offset) != x)
	 {
		printk (KERN_WARNING "%s: write error at address 0x%.8x.\n",module_name,offset);
		return (0);
	 }

   return (1);
}

static int flash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
{
   __u8 tmp[4];
   int i,n;

#ifdef LART_DEBUG
   printk (KERN_DEBUG "%s(to = 0x%.8x, len = %d)\n", __func__, (__u32)to, len);
#endif

   /* sanity checks */
   if (!len) return (0);

   /* first, we write a 0xFF.... padded byte until we reach a dword boundary */
   if (to & (BUSWIDTH - 1))
	 {
		__u32 aligned = to & ~(BUSWIDTH - 1);
		int gap = to - aligned;

		i = n = 0;

		while (gap--) tmp[i++] = 0xFF;
		while (len && i < BUSWIDTH) tmp[i++] = buf[n++], len--;
		while (i < BUSWIDTH) tmp[i++] = 0xFF;

		if (!write_dword (aligned,*((__u32 *) tmp))) return (-EIO);

		to += n;
		buf += n;
		*retlen += n;
	 }

   /* now we write dwords until we reach a non-dword boundary */
   while (len >= BUSWIDTH)
	 {
		if (!write_dword (to,*((__u32 *) buf))) return (-EIO);

		to += BUSWIDTH;
		buf += BUSWIDTH;
		*retlen += BUSWIDTH;
		len -= BUSWIDTH;
	 }

   /* top up the last unaligned bytes, padded with 0xFF.... */
   if (len & (BUSWIDTH - 1))
	 {
		i = n = 0;

		while (len--) tmp[i++] = buf[n++];
		while (i < BUSWIDTH) tmp[i++] = 0xFF;

		if (!write_dword (to,*((__u32 *) tmp))) return (-EIO);

		*retlen += n;
	 }

   return (0);
}

/***************************************************************************************************/

static struct mtd_info mtd;

static struct mtd_erase_region_info erase_regions[] = {
	/* parameter blocks */
	{
		.offset		= 0x00000000,
		.erasesize	= FLASH_BLOCKSIZE_PARAM,
		.numblocks	= FLASH_NUMBLOCKS_16m_PARAM,
	},
	/* main blocks */
	{
		.offset	 = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM,
		.erasesize	= FLASH_BLOCKSIZE_MAIN,
		.numblocks	= FLASH_NUMBLOCKS_16m_MAIN,
	}
};

static struct mtd_partition lart_partitions[] = {
	/* blob */
	{
		.name	= "blob",
		.offset	= BLOB_START,
		.size	= BLOB_LEN,
	},
	/* kernel */
	{
		.name	= "kernel",
		.offset	= KERNEL_START,		/* MTDPART_OFS_APPEND */
		.size	= KERNEL_LEN,
	},
	/* initial ramdisk / file system */
	{
		.name	= "file system",
		.offset	= INITRD_START,		/* MTDPART_OFS_APPEND */
		.size	= INITRD_LEN,		/* MTDPART_SIZ_FULL */
	}
};
#define NUM_PARTITIONS ARRAY_SIZE(lart_partitions)

static int __init lart_flash_init (void)
{
   int result;
   memset (&mtd,0,sizeof (mtd));
   printk ("MTD driver for LART. Written by Abraham vd Merwe <abraham@2d3d.co.za>\n");
   printk ("%s: Probing for 28F160x3 flash on LART...\n",module_name);
   if (!flash_probe ())
	 {
		printk (KERN_WARNING "%s: Found no LART compatible flash device\n",module_name);
		return (-ENXIO);
	 }
   printk ("%s: This looks like a LART board to me.\n",module_name);
   mtd.name = module_name;
   mtd.type = MTD_NORFLASH;
   mtd.writesize = 1;
   mtd.writebufsize = 4;
   mtd.flags = MTD_CAP_NORFLASH;
   mtd.size = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM + FLASH_BLOCKSIZE_MAIN * FLASH_NUMBLOCKS_16m_MAIN;
   mtd.erasesize = FLASH_BLOCKSIZE_MAIN;
   mtd.numeraseregions = ARRAY_SIZE(erase_regions);
   mtd.eraseregions = erase_regions;
   mtd._erase = flash_erase;
   mtd._read = flash_read;
   mtd._write = flash_write;
   mtd.owner = THIS_MODULE;

#ifdef LART_DEBUG
   printk (KERN_DEBUG
		   "mtd.name = %s\n"
		   "mtd.size = 0x%.8x (%uM)\n"
		   "mtd.erasesize = 0x%.8x (%uK)\n"
		   "mtd.numeraseregions = %d\n",
		   mtd.name,
		   mtd.size,mtd.size / (1024*1024),
		   mtd.erasesize,mtd.erasesize / 1024,
		   mtd.numeraseregions);

   if (mtd.numeraseregions)
	 for (result = 0; result < mtd.numeraseregions; result++)
	   printk (KERN_DEBUG
			   "\n\n"
			   "mtd.eraseregions[%d].offset = 0x%.8x\n"
			   "mtd.eraseregions[%d].erasesize = 0x%.8x (%uK)\n"
			   "mtd.eraseregions[%d].numblocks = %d\n",
			   result,mtd.eraseregions[result].offset,
			   result,mtd.eraseregions[result].erasesize,mtd.eraseregions[result].erasesize / 1024,
			   result,mtd.eraseregions[result].numblocks);

   printk ("\npartitions = %d\n", ARRAY_SIZE(lart_partitions));

   for (result = 0; result < ARRAY_SIZE(lart_partitions); result++)
	 printk (KERN_DEBUG
			 "\n\n"
			 "lart_partitions[%d].name = %s\n"
			 "lart_partitions[%d].offset = 0x%.8x\n"
			 "lart_partitions[%d].size = 0x%.8x (%uK)\n",
			 result,lart_partitions[result].name,
			 result,lart_partitions[result].offset,
			 result,lart_partitions[result].size,lart_partitions[result].size / 1024);
#endif

   result = mtd_device_register(&mtd, lart_partitions,
                                ARRAY_SIZE(lart_partitions));

   return (result);
}

static void __exit lart_flash_exit (void)
{
   mtd_device_unregister(&mtd);
}

module_init (lart_flash_init);
module_exit (lart_flash_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Abraham vd Merwe <abraham@2d3d.co.za>");
MODULE_DESCRIPTION("MTD driver for Intel 28F160F3 on LART board");
Commit	Line	Data
1da177e4 LT	1
	2	/*
	3	* MTD driver for the 28F160F3 Flash Memory (non-CFI) on LART.
	4	*
1da177e4 LT	5	* Author: Abraham vd Merwe <abraham@2d3d.co.za>
	6	*
	7	* Copyright (c) 2001, 2d3D, Inc.
	8	*
	9	* This code is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* References:
	14	*
	15	* [1] 3 Volt Fast Boot Block Flash Memory" Intel Datasheet
	16	* - Order Number: 290644-005
	17	* - January 2000
	18	*
	19	* [2] MTD internal API documentation
631dd1a8	20	* - http://www.linux-mtd.infradead.org/
1da177e4 LT	21	*
	22	* Limitations:
	23	*
	24	* Even though this driver is written for 3 Volt Fast Boot
	25	* Block Flash Memory, it is rather specific to LART. With
	26	* Minor modifications, notably the without data/address line
	27	* mangling and different bus settings, etc. it should be
	28	* trivial to adapt to other platforms.
	29	*
	30	* If somebody would sponsor me a different board, I'll
	31	* adapt the driver (:
	32	*/
	33
	34	/* debugging */
	35	//#define LART_DEBUG
	36
1da177e4 LT	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/types.h>
	40	#include <linux/init.h>
	41	#include <linux/errno.h>
4e57b681	42	#include <linux/string.h>
1da177e4	43	#include <linux/mtd/mtd.h>
1da177e4	44	#include <linux/mtd/partitions.h>
1da177e4 LT	45
	46	#ifndef CONFIG_SA1100_LART
	47	#error This is for LART architecture only
	48	#endif
	49
	50	static char module_name[] = "lart";
	51
	52	/*
	53	* These values is specific to 28Fxxxx3 flash memory.
	54	* See section 2.3.1 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
	55	*/
	56	#define FLASH_BLOCKSIZE_PARAM (4096 * BUSWIDTH)
	57	#define FLASH_NUMBLOCKS_16m_PARAM 8
	58	#define FLASH_NUMBLOCKS_8m_PARAM 8
	59
	60	/*
	61	* These values is specific to 28Fxxxx3 flash memory.
	62	* See section 2.3.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
	63	*/
	64	#define FLASH_BLOCKSIZE_MAIN (32768 * BUSWIDTH)
	65	#define FLASH_NUMBLOCKS_16m_MAIN 31
	66	#define FLASH_NUMBLOCKS_8m_MAIN 15
	67
	68	/*
	69	* These values are specific to LART
	70	*/
	71
	72	/* general */
	73	#define BUSWIDTH 4 /* don't change this - a lot of the code _will_ break if you change this */
	74	#define FLASH_OFFSET 0xe8000000 /* see linux/arch/arm/mach-sa1100/lart.c */
	75
	76	/* blob */
	77	#define NUM_BLOB_BLOCKS FLASH_NUMBLOCKS_16m_PARAM
	78	#define BLOB_START 0x00000000
	79	#define BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM)
	80
	81	/* kernel */
	82	#define NUM_KERNEL_BLOCKS 7
	83	#define KERNEL_START (BLOB_START + BLOB_LEN)
	84	#define KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN)
	85
	86	/* initial ramdisk */
	87	#define NUM_INITRD_BLOCKS 24
	88	#define INITRD_START (KERNEL_START + KERNEL_LEN)
	89	#define INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN)
	90
	91	/*
	92	* See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
	93	*/
	94	#define READ_ARRAY 0x00FF00FF /* Read Array/Reset */
	95	#define READ_ID_CODES 0x00900090 /* Read Identifier Codes */
	96	#define ERASE_SETUP 0x00200020 /* Block Erase */
	97	#define ERASE_CONFIRM 0x00D000D0 /* Block Erase and Program Resume */
	98	#define PGM_SETUP 0x00400040 /* Program */
	99	#define STATUS_READ 0x00700070 /* Read Status Register */
	100	#define STATUS_CLEAR 0x00500050 /* Clear Status Register */
	101	#define STATUS_BUSY 0x00800080 /* Write State Machine Status (WSMS) */
	102	#define STATUS_ERASE_ERR 0x00200020 /* Erase Status (ES) */
	103	#define STATUS_PGM_ERR 0x00100010 /* Program Status (PS) */
	104
	105	/*
	106	* See section 4.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet
	107	*/
	108	#define FLASH_MANUFACTURER 0x00890089
109	#define FLASH_DEVICE_8mbit_TOP 0x88f188f1
110	#define FLASH_DEVICE_8mbit_BOTTOM 0x88f288f2
111	#define FLASH_DEVICE_16mbit_TOP 0x88f388f3
112	#define FLASH_DEVICE_16mbit_BOTTOM 0x88f488f4
113
114	/***************************************************************************************************/
115
116	/*
117	* The data line mapping on LART is as follows:
e5580fbe	118	*
1da177e4 LT	119	* U2 CPU \| U3 CPU
	120	* -------------------
	121	* 0 20 \| 0 12
	122	* 1 22 \| 1 14
	123	* 2 19 \| 2 11
	124	* 3 17 \| 3 9
	125	* 4 24 \| 4 0
	126	* 5 26 \| 5 2
	127	* 6 31 \| 6 7
	128	* 7 29 \| 7 5
	129	* 8 21 \| 8 13
	130	* 9 23 \| 9 15
	131	* 10 18 \| 10 10
	132	* 11 16 \| 11 8
	133	* 12 25 \| 12 1
	134	* 13 27 \| 13 3
	135	* 14 30 \| 14 6
	136	* 15 28 \| 15 4
	137	*/
	138
	139	/* Mangle data (x) */
	140	#define DATA_TO_FLASH(x) \
	141	( \
	142	(((x) & 0x08009000) >> 11) + \
	143	(((x) & 0x00002000) >> 10) + \
	144	(((x) & 0x04004000) >> 8) + \
	145	(((x) & 0x00000010) >> 4) + \
	146	(((x) & 0x91000820) >> 3) + \
	147	(((x) & 0x22080080) >> 2) + \
	148	((x) & 0x40000400) + \
	149	(((x) & 0x00040040) << 1) + \
	150	(((x) & 0x00110000) << 4) + \
	151	(((x) & 0x00220100) << 5) + \
	152	(((x) & 0x00800208) << 6) + \
	153	(((x) & 0x00400004) << 9) + \
	154	(((x) & 0x00000001) << 12) + \
	155	(((x) & 0x00000002) << 13) \
	156	)
	157
	158	/* Unmangle data (x) */
	159	#define FLASH_TO_DATA(x) \
	160	( \
	161	(((x) & 0x00010012) << 11) + \
	162	(((x) & 0x00000008) << 10) + \
	163	(((x) & 0x00040040) << 8) + \
	164	(((x) & 0x00000001) << 4) + \
	165	(((x) & 0x12200104) << 3) + \
	166	(((x) & 0x08820020) << 2) + \
	167	((x) & 0x40000400) + \
	168	(((x) & 0x00080080) >> 1) + \
	169	(((x) & 0x01100000) >> 4) + \
	170	(((x) & 0x04402000) >> 5) + \
	171	(((x) & 0x20008200) >> 6) + \
	172	(((x) & 0x80000800) >> 9) + \
	173	(((x) & 0x00001000) >> 12) + \
	174	(((x) & 0x00004000) >> 13) \
	175	)
	176
e5580fbe	177	/*
1da177e4 LT	178	* The address line mapping on LART is as follows:
	179	*
	180	* U3 CPU \| U2 CPU
	181	* -------------------
	182	* 0 2 \| 0 2
	183	* 1 3 \| 1 3
	184	* 2 9 \| 2 9
	185	* 3 13 \| 3 8
	186	* 4 8 \| 4 7
	187	* 5 12 \| 5 6
	188	* 6 11 \| 6 5
	189	* 7 10 \| 7 4
	190	* 8 4 \| 8 10
	191	* 9 5 \| 9 11
	192	* 10 6 \| 10 12
	193	* 11 7 \| 11 13
	194	*
	195	* BOOT BLOCK BOUNDARY
	196	*
	197	* 12 15 \| 12 15
	198	* 13 14 \| 13 14
	199	* 14 16 \| 14 16
e5580fbe	200	*
1da177e4 LT	201	* MAIN BLOCK BOUNDARY
	202	*
	203	* 15 17 \| 15 18
	204	* 16 18 \| 16 17
	205	* 17 20 \| 17 20
	206	* 18 19 \| 18 19
	207	* 19 21 \| 19 21
	208	*
	209	* As we can see from above, the addresses aren't mangled across
	210	* block boundaries, so we don't need to worry about address
	211	* translations except for sending/reading commands during
	212	* initialization
	213	*/
	214
	215	/* Mangle address (x) on chip U2 */
	216	#define ADDR_TO_FLASH_U2(x) \
	217	( \
	218	(((x) & 0x00000f00) >> 4) + \
	219	(((x) & 0x00042000) << 1) + \
	220	(((x) & 0x0009c003) << 2) + \
	221	(((x) & 0x00021080) << 3) + \
	222	(((x) & 0x00000010) << 4) + \
	223	(((x) & 0x00000040) << 5) + \
	224	(((x) & 0x00000024) << 7) + \
	225	(((x) & 0x00000008) << 10) \
	226	)
	227
	228	/* Unmangle address (x) on chip U2 */
	229	#define FLASH_U2_TO_ADDR(x) \
	230	( \
	231	(((x) << 4) & 0x00000f00) + \
	232	(((x) >> 1) & 0x00042000) + \
	233	(((x) >> 2) & 0x0009c003) + \
	234	(((x) >> 3) & 0x00021080) + \
	235	(((x) >> 4) & 0x00000010) + \
	236	(((x) >> 5) & 0x00000040) + \
	237	(((x) >> 7) & 0x00000024) + \
	238	(((x) >> 10) & 0x00000008) \
	239	)
	240
	241	/* Mangle address (x) on chip U3 */
	242	#define ADDR_TO_FLASH_U3(x) \
	243	( \
	244	(((x) & 0x00000080) >> 3) + \
	245	(((x) & 0x00000040) >> 1) + \
	246	(((x) & 0x00052020) << 1) + \
	247	(((x) & 0x00084f03) << 2) + \
	248	(((x) & 0x00029010) << 3) + \
	249	(((x) & 0x00000008) << 5) + \
	250	(((x) & 0x00000004) << 7) \
	251	)
	252
	253	/* Unmangle address (x) on chip U3 */
	254	#define FLASH_U3_TO_ADDR(x) \
	255	( \
	256	(((x) << 3) & 0x00000080) + \
	257	(((x) << 1) & 0x00000040) + \
	258	(((x) >> 1) & 0x00052020) + \
	259	(((x) >> 2) & 0x00084f03) + \
	260	(((x) >> 3) & 0x00029010) + \
	261	(((x) >> 5) & 0x00000008) + \
	262	(((x) >> 7) & 0x00000004) \
	263	)
	264
265	/***************************************************************************************************/
266
267	static __u8 read8 (__u32 offset)
268	{
269	volatile __u8 data = (__u8 ) (FLASH_OFFSET + offset);
270	#ifdef LART_DEBUG
cb53b3b9	271	printk (KERN_DEBUG "%s(): 0x%.8x -> 0x%.2x\n", __func__, offset, *data);
1da177e4 LT	272	#endif
	273	return (*data);
	274	}
	275
	276	static __u32 read32 (__u32 offset)
	277	{
	278	volatile __u32 data = (__u32 ) (FLASH_OFFSET + offset);
	279	#ifdef LART_DEBUG
cb53b3b9	280	printk (KERN_DEBUG "%s(): 0x%.8x -> 0x%.8x\n", __func__, offset, *data);
1da177e4 LT	281	#endif
	282	return (*data);
	283	}
	284
	285	static void write32 (__u32 x,__u32 offset)
	286	{
	287	volatile __u32 data = (__u32 ) (FLASH_OFFSET + offset);
	288	*data = x;
	289	#ifdef LART_DEBUG
cb53b3b9	290	printk (KERN_DEBUG "%s(): 0x%.8x <- 0x%.8x\n", __func__, offset, *data);
1da177e4 LT	291	#endif
	292	}
	293
	294	/***************************************************************************************************/
	295
	296	/*
	297	* Probe for 16mbit flash memory on a LART board without doing
	298	* too much damage. Since we need to write 1 dword to memory,
	299	* we're f**cked if this happens to be DRAM since we can't
	300	* restore the memory (otherwise we might exit Read Array mode).
	301	*
	302	* Returns 1 if we found 16mbit flash memory on LART, 0 otherwise.
	303	*/
	304	static int flash_probe (void)
	305	{
	306	__u32 manufacturer,devtype;
	307
	308	/* setup "Read Identifier Codes" mode */
	309	write32 (DATA_TO_FLASH (READ_ID_CODES),0x00000000);
	310
	311	/* probe U2. U2/U3 returns the same data since the first 3
	312	* address lines is mangled in the same way */
	313	manufacturer = FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000000)));
	314	devtype = FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000001)));
	315
	316	/* put the flash back into command mode */
	317	write32 (DATA_TO_FLASH (READ_ARRAY),0x00000000);
	318
0bdf77f8	319	return (manufacturer == FLASH_MANUFACTURER && (devtype == FLASH_DEVICE_16mbit_TOP \|\| devtype == FLASH_DEVICE_16mbit_BOTTOM));
1da177e4 LT	320	}
	321
	322	/*
	323	* Erase one block of flash memory at offset ``offset'' which is any
	324	* address within the block which should be erased.
	325	*
	326	* Returns 1 if successful, 0 otherwise.
	327	*/
	328	static inline int erase_block (__u32 offset)
	329	{
	330	__u32 status;
	331
	332	#ifdef LART_DEBUG
cb53b3b9	333	printk (KERN_DEBUG "%s(): 0x%.8x\n", __func__, offset);
1da177e4 LT	334	#endif
	335
	336	/* erase and confirm */
	337	write32 (DATA_TO_FLASH (ERASE_SETUP),offset);
	338	write32 (DATA_TO_FLASH (ERASE_CONFIRM),offset);
	339
	340	/* wait for block erase to finish */
	341	do
	342	{
	343	write32 (DATA_TO_FLASH (STATUS_READ),offset);
	344	status = FLASH_TO_DATA (read32 (offset));
	345	}
	346	while ((~status & STATUS_BUSY) != 0);
	347
	348	/* put the flash back into command mode */
	349	write32 (DATA_TO_FLASH (READ_ARRAY),offset);
	350
25985edc	351	/* was the erase successful? */
1da177e4 LT	352	if ((status & STATUS_ERASE_ERR))
	353	{
	354	printk (KERN_WARNING "%s: erase error at address 0x%.8x.\n",module_name,offset);
	355	return (0);
	356	}
	357
	358	return (1);
	359	}
	360
	361	static int flash_erase (struct mtd_info mtd,struct erase_info instr)
	362	{
	363	__u32 addr,len;
	364	int i,first;
	365
	366	#ifdef LART_DEBUG
cb53b3b9	367	printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n", __func__, instr->addr, instr->len);
1da177e4 LT	368	#endif
1da177e4 LT	369
1da177e4 LT	370	/*
	371	* check that both start and end of the requested erase are
	372	* aligned with the erasesize at the appropriate addresses.
	373	*
	374	* skip all erase regions which are ended before the start of
	375	* the requested erase. Actually, to save on the calculations,
	376	* we skip to the first erase region which starts after the
	377	* start of the requested erase, and then go back one.
	378	*/
	379	for (i = 0; i < mtd->numeraseregions && instr->addr >= mtd->eraseregions[i].offset; i++) ;
	380	i--;
	381
	382	/*
	383	* ok, now i is pointing at the erase region in which this
	384	* erase request starts. Check the start of the requested
	385	* erase range is aligned with the erase size which is in
	386	* effect here.
	387	*/
4c1e6b2c RK	388	if (i < 0 \|\| (instr->addr & (mtd->eraseregions[i].erasesize - 1)))
4c1e6b2c RK	389	return -EINVAL;
1da177e4 LT	390
	391	/* Remember the erase region we start on */
	392	first = i;
	393
	394	/*
	395	* next, check that the end of the requested erase is aligned
	396	* with the erase region at that address.
	397	*
	398	* as before, drop back one to point at the region in which
	399	* the address actually falls
	400	*/
	401	for (; i < mtd->numeraseregions && instr->addr + instr->len >= mtd->eraseregions[i].offset; i++) ;
	402	i--;
	403
	404	/* is the end aligned on a block boundary? */
4c1e6b2c RK	405	if (i < 0 \|\| ((instr->addr + instr->len) & (mtd->eraseregions[i].erasesize - 1)))
4c1e6b2c RK	406	return -EINVAL;
1da177e4 LT	407
	408	addr = instr->addr;
	409	len = instr->len;
	410
	411	i = first;
	412
	413	/* now erase those blocks */
	414	while (len)
	415	{
	416	if (!erase_block (addr))
	417	{
	418	instr->state = MTD_ERASE_FAILED;
	419	return (-EIO);
	420	}
	421
	422	addr += mtd->eraseregions[i].erasesize;
	423	len -= mtd->eraseregions[i].erasesize;
	424
	425	if (addr == mtd->eraseregions[i].offset + (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++;
	426	}
	427
	428	instr->state = MTD_ERASE_DONE;
	429	mtd_erase_callback(instr);
	430
	431	return (0);
	432	}
	433
	434	static int flash_read (struct mtd_info mtd,loff_t from,size_t len,size_t retlen,u_char *buf)
	435	{
	436	#ifdef LART_DEBUG
cb53b3b9	437	printk (KERN_DEBUG "%s(from = 0x%.8x, len = %d)\n", __func__, (__u32)from, len);
1da177e4 LT	438	#endif
	439
	440	/* sanity checks */
	441	if (!len) return (0);
1da177e4 LT	442
	443	/* we always read len bytes */
	444	*retlen = len;
	445
	446	/* first, we read bytes until we reach a dword boundary */
	447	if (from & (BUSWIDTH - 1))
	448	{
	449	int gap = BUSWIDTH - (from & (BUSWIDTH - 1));
	450
	451	while (len && gap--) *buf++ = read8 (from++), len--;
	452	}
	453
	454	/* now we read dwords until we reach a non-dword boundary */
	455	while (len >= BUSWIDTH)
	456	{
	457	((__u32 ) buf) = read32 (from);
	458
	459	buf += BUSWIDTH;
	460	from += BUSWIDTH;
	461	len -= BUSWIDTH;
	462	}
	463
	464	/* top up the last unaligned bytes */
	465	if (len & (BUSWIDTH - 1))
	466	while (len--) *buf++ = read8 (from++);
	467
	468	return (0);
	469	}
	470
	471	/*
	472	* Write one dword ``x'' to flash memory at offset ``offset''. ``offset''
	473	* must be 32 bits, i.e. it must be on a dword boundary.
	474	*
	475	* Returns 1 if successful, 0 otherwise.
	476	*/
	477	static inline int write_dword (__u32 offset,__u32 x)
	478	{
	479	__u32 status;
	480
	481	#ifdef LART_DEBUG
cb53b3b9	482	printk (KERN_DEBUG "%s(): 0x%.8x <- 0x%.8x\n", __func__, offset, x);
1da177e4 LT	483	#endif
	484
	485	/* setup writing */
	486	write32 (DATA_TO_FLASH (PGM_SETUP),offset);
	487
	488	/* write the data */
	489	write32 (x,offset);
	490
	491	/* wait for the write to finish */
	492	do
	493	{
	494	write32 (DATA_TO_FLASH (STATUS_READ),offset);
	495	status = FLASH_TO_DATA (read32 (offset));
	496	}
	497	while ((~status & STATUS_BUSY) != 0);
	498
	499	/* put the flash back into command mode */
	500	write32 (DATA_TO_FLASH (READ_ARRAY),offset);
	501
25985edc	502	/* was the write successful? */
1da177e4 LT	503	if ((status & STATUS_PGM_ERR) \|\| read32 (offset) != x)
	504	{
	505	printk (KERN_WARNING "%s: write error at address 0x%.8x.\n",module_name,offset);
	506	return (0);
	507	}
	508
	509	return (1);
	510	}
	511
	512	static int flash_write (struct mtd_info mtd,loff_t to,size_t len,size_t retlen,const u_char *buf)
	513	{
	514	__u8 tmp[4];
	515	int i,n;
	516
	517	#ifdef LART_DEBUG
cb53b3b9	518	printk (KERN_DEBUG "%s(to = 0x%.8x, len = %d)\n", __func__, (__u32)to, len);
1da177e4 LT	519	#endif
1da177e4 LT	520
1da177e4 LT	521	/* sanity checks */
1da177e4 LT	522	if (!len) return (0);
1da177e4 LT	523
	524	/* first, we write a 0xFF.... padded byte until we reach a dword boundary */
	525	if (to & (BUSWIDTH - 1))
	526	{
	527	__u32 aligned = to & ~(BUSWIDTH - 1);
	528	int gap = to - aligned;
	529
	530	i = n = 0;
	531
	532	while (gap--) tmp[i++] = 0xFF;
	533	while (len && i < BUSWIDTH) tmp[i++] = buf[n++], len--;
	534	while (i < BUSWIDTH) tmp[i++] = 0xFF;
	535
	536	if (!write_dword (aligned,((__u32 ) tmp))) return (-EIO);
	537
	538	to += n;
	539	buf += n;
	540	*retlen += n;
	541	}
	542
	543	/* now we write dwords until we reach a non-dword boundary */
	544	while (len >= BUSWIDTH)
	545	{
	546	if (!write_dword (to,((__u32 ) buf))) return (-EIO);
	547
	548	to += BUSWIDTH;
	549	buf += BUSWIDTH;
	550	*retlen += BUSWIDTH;
	551	len -= BUSWIDTH;
	552	}
	553
	554	/* top up the last unaligned bytes, padded with 0xFF.... */
	555	if (len & (BUSWIDTH - 1))
	556	{
	557	i = n = 0;
	558
	559	while (len--) tmp[i++] = buf[n++];
	560	while (i < BUSWIDTH) tmp[i++] = 0xFF;
	561
	562	if (!write_dword (to,((__u32 ) tmp))) return (-EIO);
	563
	564	*retlen += n;
	565	}
	566
	567	return (0);
	568	}
	569
	570	/***************************************************************************************************/
	571
1da177e4 LT	572	static struct mtd_info mtd;
	573
	574	static struct mtd_erase_region_info erase_regions[] = {
	575	/* parameter blocks */
	576	{
	577	.offset = 0x00000000,
	578	.erasesize = FLASH_BLOCKSIZE_PARAM,
	579	.numblocks = FLASH_NUMBLOCKS_16m_PARAM,
	580	},
	581	/* main blocks */
	582	{
	583	.offset = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM,
	584	.erasesize = FLASH_BLOCKSIZE_MAIN,
	585	.numblocks = FLASH_NUMBLOCKS_16m_MAIN,
	586	}
	587	};
	588
1da177e4 LT	589	static struct mtd_partition lart_partitions[] = {
	590	/* blob */
	591	{
	592	.name = "blob",
	593	.offset = BLOB_START,
	594	.size = BLOB_LEN,
	595	},
	596	/* kernel */
	597	{
	598	.name = "kernel",
	599	.offset = KERNEL_START, /* MTDPART_OFS_APPEND */
	600	.size = KERNEL_LEN,
	601	},
	602	/* initial ramdisk / file system */
	603	{
	604	.name = "file system",
	605	.offset = INITRD_START, /* MTDPART_OFS_APPEND */
	606	.size = INITRD_LEN, /* MTDPART_SIZ_FULL */
	607	}
	608	};
3761a6dd	609	#define NUM_PARTITIONS ARRAY_SIZE(lart_partitions)
1da177e4	610
e4582ea7	611	static int __init lart_flash_init (void)
1da177e4 LT	612	{
	613	int result;
	614	memset (&mtd,0,sizeof (mtd));
	615	printk ("MTD driver for LART. Written by Abraham vd Merwe <abraham@2d3d.co.za>\n");
	616	printk ("%s: Probing for 28F160x3 flash on LART...\n",module_name);
	617	if (!flash_probe ())
	618	{
	619	printk (KERN_WARNING "%s: Found no LART compatible flash device\n",module_name);
	620	return (-ENXIO);
	621	}
	622	printk ("%s: This looks like a LART board to me.\n",module_name);
	623	mtd.name = module_name;
	624	mtd.type = MTD_NORFLASH;
783ed81f	625	mtd.writesize = 1;
fcc44a07	626	mtd.writebufsize = 4;
1da177e4 LT	627	mtd.flags = MTD_CAP_NORFLASH;
	628	mtd.size = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM + FLASH_BLOCKSIZE_MAIN * FLASH_NUMBLOCKS_16m_MAIN;
	629	mtd.erasesize = FLASH_BLOCKSIZE_MAIN;
87d10f3c	630	mtd.numeraseregions = ARRAY_SIZE(erase_regions);
1da177e4	631	mtd.eraseregions = erase_regions;
3c3c10bb AB	632	mtd._erase = flash_erase;
	633	mtd._read = flash_read;
	634	mtd._write = flash_write;
1da177e4 LT	635	mtd.owner = THIS_MODULE;
	636
	637	#ifdef LART_DEBUG
	638	printk (KERN_DEBUG
	639	"mtd.name = %s\n"
	640	"mtd.size = 0x%.8x (%uM)\n"
	641	"mtd.erasesize = 0x%.8x (%uK)\n"
	642	"mtd.numeraseregions = %d\n",
	643	mtd.name,
	644	mtd.size,mtd.size / (1024*1024),
	645	mtd.erasesize,mtd.erasesize / 1024,
	646	mtd.numeraseregions);
	647
	648	if (mtd.numeraseregions)
	649	for (result = 0; result < mtd.numeraseregions; result++)
	650	printk (KERN_DEBUG
	651	"\n\n"
	652	"mtd.eraseregions[%d].offset = 0x%.8x\n"
	653	"mtd.eraseregions[%d].erasesize = 0x%.8x (%uK)\n"
	654	"mtd.eraseregions[%d].numblocks = %d\n",
	655	result,mtd.eraseregions[result].offset,
	656	result,mtd.eraseregions[result].erasesize,mtd.eraseregions[result].erasesize / 1024,
	657	result,mtd.eraseregions[result].numblocks);
	658
87d10f3c	659	printk ("\npartitions = %d\n", ARRAY_SIZE(lart_partitions));
1da177e4	660
87d10f3c	661	for (result = 0; result < ARRAY_SIZE(lart_partitions); result++)
1da177e4 LT	662	printk (KERN_DEBUG
	663	"\n\n"
	664	"lart_partitions[%d].name = %s\n"
	665	"lart_partitions[%d].offset = 0x%.8x\n"
	666	"lart_partitions[%d].size = 0x%.8x (%uK)\n",
	667	result,lart_partitions[result].name,
	668	result,lart_partitions[result].offset,
	669	result,lart_partitions[result].size,lart_partitions[result].size / 1024);
	670	#endif
1da177e4	671
ee0e87b1 JI	672	result = mtd_device_register(&mtd, lart_partitions,
ee0e87b1 JI	673	ARRAY_SIZE(lart_partitions));
1da177e4 LT	674
	675	return (result);
	676	}
	677
e4582ea7	678	static void __exit lart_flash_exit (void)
1da177e4	679	{
ee0e87b1	680	mtd_device_unregister(&mtd);
1da177e4 LT	681	}
	682
	683	module_init (lart_flash_init);
	684	module_exit (lart_flash_exit);
	685
	686	MODULE_LICENSE("GPL");
	687	MODULE_AUTHOR("Abraham vd Merwe <abraham@2d3d.co.za>");
	688	MODULE_DESCRIPTION("MTD driver for Intel 28F160F3 on LART board");