projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fa3eb70 S |
1 | |
| 2 | static void test_instr_NEON(int printlog) | |
| 3 | { | |
| 4 | unsigned long copy_size; | |
| 5 | unsigned long flags; | |
| 6 | unsigned long i, j, avg, pld_dst; | |
| 7 | unsigned long temp; | |
| 8 | unsigned long result[10]; | |
| 9 | copy_size = 256; | |
| 10 | /* copy_size = 1024*8; */ | |
| 11 | /* copy_size = 1024*64; */ | |
| 12 | /* copy_size = 1024*1024; */ | |
| 13 | ||
| 14 | if (printlog == 1) | |
| 15 | pr_err("\n\n\r == Start test Pattern 1 ===\n\r"); | |
| 16 | /* for(i = 0; i< 256 + 16 + 4; i++, copy_size += 256){ */ | |
| 17 | i = 0; | |
| 18 | while (i < 256 + 16 + 4) { | |
| 19 | if (i < 256) { | |
| 20 | copy_size = 256 + i * 256; /* inc 256 byte from 0~64 KBytes */ | |
| 21 | } else if (i < 256 + 16) { | |
| 22 | copy_size = 1024 * 64 + (i - 256) * 1024 * 64; /* inc 64Kbyte form 64KB~1MB */ | |
| 23 | } else if (i < 256 + 16 + 4) { | |
| 24 | copy_size = 1024 * 1024 + (i - 256 - 16) * 1024 * 1024; /* inc 1MB from 1MB~4MB */ | |
| 25 | } | |
| 26 | i++; | |
| 27 | mdelay(5); | |
| 28 | preempt_disable(); | |
| 29 | local_irq_save(flags); | |
| 30 | /* for(i = 0; i< 8; i++, copy_size += 1024*8){ */ | |
| 31 | /* for(i = 0; i< 16; i++, copy_size += 1024*64){ */ | |
| 32 | /* for(i = 0; i< 4; i++, copy_size += 1024*1024){ */ | |
| 33 | inner_dcache_flush_all(); | |
| 34 | if (printlog == 1) | |
| 35 | pr_err(" %lu :", copy_size); | |
| 36 | avg = 0; | |
| 37 | /* no pld */ | |
| 38 | for (j = 0; j < 8; j++) { | |
| 39 | mdelay(3); | |
| 40 | /* if(flush_cache == 1) */ | |
| 41 | inner_dcache_flush_all(); | |
| 42 | #if 1 | |
| 43 | temp = 0; | |
| 44 | ||
| 45 | /* enable ARM CPU PMU */ | |
| 46 | asm volatile ("mov %0, #0\n" "MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 47 | "ORR %0, %0, #1 << 2\n" /* reset cycle count */ | |
| 48 | "BIC %0, %0, #1 << 3\n" /* count every clock cycle */ | |
| 49 | "MCR p15, 0, %0, c9, c12, 0\n":"+r" (temp) | |
| 50 | : : "cc"); | |
| 51 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "ORR %0, %0, #1 << 0\n" /* enable */ | |
| 52 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 53 | "MRC p15, 0, %0, c9, c12, 1\n" | |
| 54 | "ORR %0, %0, #1 << 31\n" | |
| 55 | "MCR p15, 0, %0, c9, c12, 1\n":"+r" (temp) | |
| 56 | : : "cc"); | |
| 57 | #endif | |
| 58 | ||
| 59 | asm volatile ("push {r0,r1,r2,r9}\n" | |
| 60 | "stmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 61 | "mov r0, %0\n" | |
| 62 | "mov r1, %1\n" | |
| 63 | "mov r2, %2\n" | |
| 64 | "mov r3, %3\n" "subs r2, r2, #64\n" "1:\n" | |
| 65 | /* The main loop copies 64 bytes at a time. */ | |
| 66 | ".word 0xf421020d\n" | |
| 67 | /* "vld1.8 {d0 - d3}, [r1]!\n" */ | |
| 68 | ".word 0xf421420d\n" | |
| 69 | /* "vld1.8 {d4 - d7}, [r1]!\n" */ | |
| 70 | /* ".word 0xf5d1f100\n" */ | |
| 71 | /* "pld [r1, #(64*4)]\n" */ | |
| 72 | /* ".word 0xe2522040\n" */ | |
| 73 | "subs r2, r2, #64\n" ".word 0xf400022d\n" | |
| 74 | /* "vst1.8 {d0 - d3}, [r0, :128]!\n" */ | |
| 75 | ".word 0xf400422d\n" | |
| 76 | /* "vst1.8 {d4 - d7}, [r0, :128]!\n" */ | |
| 77 | "bge 1b\n" | |
| 78 | "ldmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 79 | "pop {r0,r1,r2, r9}\n" | |
| 80 | /* "pop r2\n" */ | |
| 81 | : : "r" (&buffer_dst), "r"(&buffer_src), "r"(copy_size), | |
| 82 | "r"(pld_dst) | |
| 83 | : ); | |
| 84 | ||
| 85 | /* #if defined(DEBUG_DRAMC_CALIB) */ | |
| 86 | #if 1 | |
| 87 | /* get CPU cycle count from the ARM CPU PMU */ | |
| 88 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 89 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 90 | "MRC p15, 0, %0, c9, c13, 0\n":"+r" (temp) | |
| 91 | : : "cc"); | |
| 92 | result[j] = temp; | |
| 93 | #endif | |
| 94 | } /* 10 times loop */ | |
| 95 | avg = 0; | |
| 96 | for (j = 0; j < 8; j++) { | |
| 97 | avg += result[j]; | |
| 98 | } | |
| 99 | avg = avg >> 3; | |
| 100 | if (printlog == 1) | |
| 101 | pr_debug(" %lu ", avg); | |
| 102 | for (pld_dst = 0; pld_dst < 64 * 16; pld_dst += 64) { | |
| 103 | avg = 0; | |
| 104 | for (j = 0; j < 8; j++) { | |
| 105 | mdelay(3); | |
| 106 | if (flush_cache == 1) | |
| 107 | inner_dcache_flush_all(); | |
| 108 | #if 1 | |
| 109 | temp = 0; | |
| 110 | ||
| 111 | /* enable ARM CPU PMU */ | |
| 112 | asm volatile ("mov %0, #0\n" "MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 113 | "ORR %0, %0, #1 << 2\n" /* reset cycle count */ | |
| 114 | "BIC %0, %0, #1 << 3\n" /* count every clock cycle */ | |
| 115 | "MCR p15, 0, %0, c9, c12, 0\n":"+r" (temp) | |
| 116 | : : "cc"); | |
| 117 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "ORR %0, %0, #1 << 0\n" /* enable */ | |
| 118 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 119 | "MRC p15, 0, %0, c9, c12, 1\n" | |
| 120 | "ORR %0, %0, #1 << 31\n" | |
| 121 | "MCR p15, 0, %0, c9, c12, 1\n":"+r" (temp) | |
| 122 | : : "cc"); | |
| 123 | #endif | |
| 124 | ||
| 125 | asm volatile ("push {r0,r1,r2,r9}\n" | |
| 126 | "stmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 127 | "mov r0, %0\n" | |
| 128 | "mov r1, %1\n" | |
| 129 | "mov r2, %2\n" | |
| 130 | "mov r3, %3\n" "subs r2, r2, #64\n" "1:\n" | |
| 131 | /* The main loop copies 64 bytes at a time. */ | |
| 132 | ".word 0xf421020d\n" | |
| 133 | /* "vld1.8 {d0 - d3}, [r1]!\n" */ | |
| 134 | ".word 0xf421420d\n" | |
| 135 | /* "vld1.8 {d4 - d7}, [r1]!\n" */ | |
| 136 | /* ".word 0xf5d1f100\n" */ | |
| 137 | /* "pld [r1, r3]\n" */ | |
| 138 | "subs r2, r2, #64\n" ".word 0xf400022d\n" | |
| 139 | /* "vst1.8 {d0 - d3}, [r0, :128]!\n" */ | |
| 140 | ".word 0xf400422d\n" | |
| 141 | /* "vst1.8 {d4 - d7}, [r0, :128]!\n" */ | |
| 142 | /* ".word 0xf590f100\n" //pldw */ | |
| 143 | "bge 1b\n" | |
| 144 | "ldmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 145 | "pop {r0,r1,r2, r9}\n" | |
| 146 | /* "pop r2\n" */ | |
| 147 | : : "r" (&buffer_dst), "r"(&buffer_src), "r"(copy_size), | |
| 148 | "r"(pld_dst) : ); | |
| 149 | ||
| 150 | /* #if defined(DEBUG_DRAMC_CALIB) */ | |
| 151 | #if 1 | |
| 152 | /* get CPU cycle count from the ARM CPU PMU */ | |
| 153 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 154 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 155 | "MRC p15, 0, %0, c9, c13, 0\n":"+r" (temp) | |
| 156 | : : "cc"); | |
| 157 | /* pr_err("%lu bytes takes %d CPU cycles\n\r", copy_size,temp); */ | |
| 158 | /* pr_err(" %d ", temp); */ | |
| 159 | /* pr_debug(" %d ", temp); */ | |
| 160 | result[j] = temp; | |
| 161 | /* pr_debug(" result[%d]=%d :", j, result[j]); */ | |
| 162 | #endif | |
| 163 | } /* 10 times loop */ | |
| 164 | avg = 0; | |
| 165 | for (j = 0; j < 8; j++) { | |
| 166 | avg += result[j]; | |
| 167 | } | |
| 168 | avg = avg >> 3; | |
| 169 | if (printlog == 1) | |
| 170 | pr_debug(" %d ", avg); | |
| 171 | } /* pld dist loop */ | |
| 172 | local_irq_restore(flags); | |
| 173 | preempt_enable(); | |
| 174 | } | |
| 175 | if (printlog == 1) | |
| 176 | pr_err("\n\r ====NEON instruction test done ==== flush_cache:%d\n", flush_cache); | |
| 177 | } | |
| 178 | ||
| 179 | static void test_instr_only_pld(int printlog) | |
| 180 | { | |
| 181 | unsigned long copy_size; | |
| 182 | unsigned long flags; | |
| 183 | int i, j, avg, pld_dst; | |
| 184 | int k; | |
| 185 | int temp; | |
| 186 | int result[10]; | |
| 187 | copy_size = 256; | |
| 188 | /* copy_size = 1024*8; */ | |
| 189 | /* copy_size = 1024*64; */ | |
| 190 | /* copy_size = 1024*1024; */ | |
| 191 | if (printlog == 1) | |
| 192 | pr_err("\n\n\r == Start test Pattern PLD only ===\n\r"); | |
| 193 | /* for(i = 0; i< 256; i++, copy_size += 256){ */ | |
| 194 | i = 0; | |
| 195 | while (i < 256 + 16 + 4) { | |
| 196 | if (i < 256) { | |
| 197 | copy_size = 256 + i * 256; /* inc 256 byte from 0~64 KBytes */ | |
| 198 | } else if (i < 256 + 16) { | |
| 199 | copy_size = 1024 * 64 + (i - 256) * 1024 * 64; /* inc 64Kbyte form 64KB~1MB */ | |
| 200 | } else if (i < 256 + 16 + 4) { | |
| 201 | copy_size = 1024 * 1024 + (i - 256 - 16) * 1024 * 1024; /* inc 1MB from 1MB~4MB */ | |
| 202 | } | |
| 203 | i++; | |
| 204 | mdelay(5); | |
| 205 | preempt_disable(); | |
| 206 | local_irq_save(flags); | |
| 207 | /* for(i = 0; i< 64; i++, copy_size += 1024){ */ | |
| 208 | /* for(i = 0; i< 8; i++, copy_size += 1024*8){ */ | |
| 209 | /* for(i = 0; i< 16; i++, copy_size += 1024*64){ */ | |
| 210 | /* for(i = 0; i< 4; i++, copy_size += 1024*1024){ */ | |
| 211 | /* pr_err("\n\r %lu ",copy_size); */ | |
| 212 | inner_dcache_flush_all(); | |
| 213 | if (printlog == 1) | |
| 214 | pr_err(" %lu :", copy_size); | |
| 215 | avg = 0; | |
| 216 | for (j = 0; j < 8; j++) { | |
| 217 | mdelay(3); | |
| 218 | if (flush_cache == 1) | |
| 219 | inner_dcache_flush_all(); | |
| 220 | #if 1 | |
| 221 | /* reset RA mode */ | |
| 222 | #if 0 | |
| 223 | asm volatile ("MRC p15, 0, %0, c1, c0, 1\n" "ORR %0, %0, #1 << 11\n" /* disable */ | |
| 224 | "ORR %0, %0, #1 << 12\n" /* disable */ | |
| 225 | "MCR p15, 0, %0, c1, c0, 1\n" "MRC p15, 0, %0, c1, c0, 1\n" "BIC %0, %0, #1 << 11\n" /* enable */ | |
| 226 | "BIC %0, %0, #1 << 12\n" /* enable */ | |
| 227 | "MCR p15, 0, %0, c1, c0, 1\n":"+r" (temp) | |
| 228 | : : "cc"); | |
| 229 | #endif | |
| 230 | /* enable ARM CPU PMU */ | |
| 231 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 232 | "ORR %0, %0, #1 << 2\n" /* reset cycle count */ | |
| 233 | "BIC %0, %0, #1 << 3\n" /* count every clock cycle */ | |
| 234 | "MCR p15, 0, %0, c9, c12, 0\n":"+r" (temp) | |
| 235 | : : "cc"); | |
| 236 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "ORR %0, %0, #1 << 0\n" /* enable */ | |
| 237 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 238 | "MRC p15, 0, %0, c9, c12, 1\n" | |
| 239 | "ORR %0, %0, #1 << 31\n" | |
| 240 | "MCR p15, 0, %0, c9, c12, 1\n":"+r" (temp) | |
| 241 | : : "cc"); | |
| 242 | #endif | |
| 243 | asm volatile ("push {r0,r1,r2,r9}\n" | |
| 244 | "mov r0, %0\n" | |
| 245 | "mov r1, %1\n" | |
| 246 | "mov r2, %2\n" | |
| 247 | "mov r9, %3\n" | |
| 248 | "stmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" "1:\n" | |
| 249 | /* "pld [r1, r9]\n" */ | |
| 250 | /* "pldw [r0, r9]\n" */ | |
| 251 | /* ".word 0xf790f009\n" */ | |
| 252 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 253 | "subs r2, r2, #32 \n" | |
| 254 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 255 | "blt 2f\n" | |
| 256 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 257 | "subs r2, r2, #32 \n" | |
| 258 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 259 | "bge 1b\n" | |
| 260 | "2:\n" | |
| 261 | "ldmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 262 | "pop {r0,r1,r2,r9}\n" : : "r" (&buffer_dst), "r"(&buffer_src), | |
| 263 | "r"(copy_size), "r"(pld_dst) | |
| 264 | : ); | |
| 265 | ||
| 266 | ||
| 267 | /* #if defined(DEBUG_DRAMC_CALIB) */ | |
| 268 | #if 1 | |
| 269 | /* get CPU cycle count from the ARM CPU PMU */ | |
| 270 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 271 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 272 | "MRC p15, 0, %0, c9, c13, 0\n":"+r" (temp) | |
| 273 | : : "cc"); | |
| 274 | #endif | |
| 275 | result[j] = temp; | |
| 276 | /* pr_debug(" %d ", temp); */ | |
| 277 | } | |
| 278 | avg = 0; | |
| 279 | for (j = 0; j < 8; j++) { | |
| 280 | avg += result[j]; | |
| 281 | } | |
| 282 | avg = avg >> 3; | |
| 283 | if (printlog == 1) | |
| 284 | pr_debug(" %d ", avg); | |
| 285 | for (pld_dst = 0; pld_dst < 64 * 16; pld_dst += 64) { | |
| 286 | for (j = 0; j < 8; j++) { | |
| 287 | mdelay(3); | |
| 288 | if (flush_cache == 1) | |
| 289 | inner_dcache_flush_all(); | |
| 290 | #if 1 | |
| 291 | #if 0 | |
| 292 | /* reset RA mode */ | |
| 293 | asm volatile ("MRC p15, 0, %0, c1, c0, 1\n" "ORR %0, %0, #1 << 11\n" /* disable */ | |
| 294 | "ORR %0, %0, #1 << 12\n" /* disable */ | |
| 295 | "MCR p15, 0, %0, c1, c0, 1\n" "MRC p15, 0, %0, c1, c0, 1\n" "BIC %0, %0, #1 << 11\n" /* enable */ | |
| 296 | "BIC %0, %0, #1 << 12\n" /* enable */ | |
| 297 | "MCR p15, 0, %0, c1, c0, 1\n":"+r" (temp) | |
| 298 | : : "cc"); | |
| 299 | #endif | |
| 300 | /* enable ARM CPU PMU */ | |
| 301 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 302 | "ORR %0, %0, #1 << 2\n" /* reset cycle count */ | |
| 303 | "BIC %0, %0, #1 << 3\n" /* count every clock cycle */ | |
| 304 | "MCR p15, 0, %0, c9, c12, 0\n":"+r" (temp) | |
| 305 | : : "cc"); | |
| 306 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "ORR %0, %0, #1 << 0\n" /* enable */ | |
| 307 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 308 | "MRC p15, 0, %0, c9, c12, 1\n" | |
| 309 | "ORR %0, %0, #1 << 31\n" | |
| 310 | "MCR p15, 0, %0, c9, c12, 1\n":"+r" (temp) | |
| 311 | : : "cc"); | |
| 312 | #endif | |
| 313 | asm volatile ("push {r0,r1,r2,r9}\n" | |
| 314 | "mov r0, %0\n" | |
| 315 | "mov r1, %1\n" | |
| 316 | "mov r2, %2\n" | |
| 317 | "mov r9, %3\n" | |
| 318 | "stmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 319 | "1:\n" "pld [r1, r9]\n" | |
| 320 | /* "pldw [r0, r9]\n" */ | |
| 321 | /* ".word 0xf790f009\n" */ | |
| 322 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 323 | "subs r2, r2, #32 \n" | |
| 324 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 325 | "blt 2f\n" | |
| 326 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 327 | "subs r2, r2, #32 \n" | |
| 328 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 329 | "bge 1b\n" | |
| 330 | "2:\n" | |
| 331 | "ldmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 332 | "pop {r0,r1,r2,r9}\n" : : "r" (&buffer_dst), | |
| 333 | "r"(&buffer_src), "r"(copy_size), "r"(pld_dst) | |
| 334 | : ); | |
| 335 | ||
| 336 | ||
| 337 | /* #if defined(DEBUG_DRAMC_CALIB) */ | |
| 338 | #if 1 | |
| 339 | /* get CPU cycle count from the ARM CPU PMU */ | |
| 340 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 341 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 342 | "MRC p15, 0, %0, c9, c13, 0\n":"+r" (temp) | |
| 343 | : : "cc"); | |
| 344 | #endif | |
| 345 | result[j] = temp; | |
| 346 | /* pr_debug(" %d ", temp); */ | |
| 347 | } | |
| 348 | avg = 0; | |
| 349 | for (j = 0; j < 8; j++) { | |
| 350 | avg += result[j]; | |
| 351 | } | |
| 352 | avg = avg >> 3; | |
| 353 | if (printlog == 1) | |
| 354 | pr_debug(" %d ", avg); | |
| 355 | } | |
| 356 | local_irq_restore(flags); | |
| 357 | preempt_enable(); | |
| 358 | } | |
| 359 | if (printlog == 1) | |
| 360 | pr_err("\n\r ==== test done only pld ==== flush_cache:%d\n", flush_cache); | |
| 361 | } | |
| 362 | ||
| 363 | static void test_instr_pld_pldw(int printlog) | |
| 364 | { | |
| 365 | unsigned long copy_size; | |
| 366 | unsigned long flags; | |
| 367 | int i, j, avg, pld_dst; | |
| 368 | int k; | |
| 369 | int temp; | |
| 370 | int result[10]; | |
| 371 | copy_size = 1024 * 64; | |
| 372 | if (printlog == 1) | |
| 373 | pr_err("\n\n\r == Start test pld+pldw ===\n\r"); | |
| 374 | /* for(i = 0; i< 256; i++, copy_size += 256){ */ | |
| 375 | /* for(i = 0; i< 4; i++, copy_size += 1024*1024){ */ | |
| 376 | /* for(i = 0; i< 8; i++, copy_size += 1024*8){ */ | |
| 377 | /* for(i = 0; i< 16; i++, copy_size += 1024*64){ */ | |
| 378 | i = 0; | |
| 379 | while (i < 256 + 16 + 4) { | |
| 380 | if (i < 256) { | |
| 381 | copy_size = 256 + i * 256; /* inc 256 byte from 0~64 KBytes */ | |
| 382 | } else if (i < 256 + 16) { | |
| 383 | copy_size = 1024 * 64 + (i - 256) * 1024 * 64; /* inc 64Kbyte form 64KB~1MB */ | |
| 384 | } else if (i < 256 + 16 + 4) { | |
| 385 | copy_size = 1024 * 1024 + (i - 256 - 16) * 1024 * 1024; /* inc 1MB from 1MB~4MB */ | |
| 386 | } | |
| 387 | i++; | |
| 388 | mdelay(5); | |
| 389 | preempt_disable(); | |
| 390 | local_irq_save(flags); | |
| 391 | /* pr_err("\n\r %lu ",copy_size); */ | |
| 392 | inner_dcache_flush_all(); | |
| 393 | if (printlog == 1) | |
| 394 | pr_err(" %lu :", copy_size); | |
| 395 | avg = 0; | |
| 396 | for (j = 0; j < 8; j++) { | |
| 397 | mdelay(3); | |
| 398 | if (flush_cache == 1) | |
| 399 | inner_dcache_flush_all(); | |
| 400 | #if 1 | |
| 401 | /* reset RA mode */ | |
| 402 | #if 0 | |
| 403 | asm volatile ("MRC p15, 0, %0, c1, c0, 1\n" "ORR %0, %0, #1 << 11\n" /* disable */ | |
| 404 | "ORR %0, %0, #1 << 12\n" /* disable */ | |
| 405 | "MCR p15, 0, %0, c1, c0, 1\n" "MRC p15, 0, %0, c1, c0, 1\n" "BIC %0, %0, #1 << 11\n" /* enable */ | |
| 406 | "BIC %0, %0, #1 << 12\n" /* enable */ | |
| 407 | "MCR p15, 0, %0, c1, c0, 1\n":"+r" (temp) | |
| 408 | : : "cc"); | |
| 409 | #endif | |
| 410 | /* enable ARM CPU PMU */ | |
| 411 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 412 | "ORR %0, %0, #1 << 2\n" /* reset cycle count */ | |
| 413 | "BIC %0, %0, #1 << 3\n" /* count every clock cycle */ | |
| 414 | "MCR p15, 0, %0, c9, c12, 0\n":"+r" (temp) | |
| 415 | : : "cc"); | |
| 416 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "ORR %0, %0, #1 << 0\n" /* enable */ | |
| 417 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 418 | "MRC p15, 0, %0, c9, c12, 1\n" | |
| 419 | "ORR %0, %0, #1 << 31\n" | |
| 420 | "MCR p15, 0, %0, c9, c12, 1\n":"+r" (temp) | |
| 421 | : : "cc"); | |
| 422 | #endif | |
| 423 | asm volatile ("push {r0,r1,r2,r9}\n" | |
| 424 | "mov r0, %0\n" | |
| 425 | "mov r1, %1\n" | |
| 426 | "mov r2, %2\n" | |
| 427 | "mov r9, %3\n" | |
| 428 | "stmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" "1:\n" | |
| 429 | /* "pld [r1, r9]\n" */ | |
| 430 | /* "pldw [r0, r9]\n" */ | |
| 431 | /* ".word 0xf790f009\n" */ | |
| 432 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 433 | "subs r2, r2, #32 \n" | |
| 434 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 435 | "blt 2f\n" | |
| 436 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 437 | "subs r2, r2, #32 \n" | |
| 438 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 439 | "bge 1b\n" | |
| 440 | "2:\n" | |
| 441 | "ldmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 442 | "pop {r0,r1,r2,r9}\n" : : "r" (&buffer_dst), "r"(&buffer_src), | |
| 443 | "r"(copy_size), "r"(pld_dst) | |
| 444 | : ); | |
| 445 | ||
| 446 | ||
| 447 | /* #if defined(DEBUG_DRAMC_CALIB) */ | |
| 448 | #if 1 | |
| 449 | /* get CPU cycle count from the ARM CPU PMU */ | |
| 450 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 451 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 452 | "MRC p15, 0, %0, c9, c13, 0\n":"+r" (temp) | |
| 453 | : : "cc"); | |
| 454 | #endif | |
| 455 | result[j] = temp; | |
| 456 | /* pr_debug(" %d ", temp); */ | |
| 457 | } | |
| 458 | avg = 0; | |
| 459 | for (j = 0; j < 8; j++) { | |
| 460 | avg += result[j]; | |
| 461 | } | |
| 462 | avg = avg >> 3; | |
| 463 | if (printlog == 1) | |
| 464 | pr_debug(" %d ", avg); | |
| 465 | for (pld_dst = 0; pld_dst < 64 * 16; pld_dst += 64) { | |
| 466 | /* for(pld_dst = 0; pld_dst<64*16*3; pld_dst+=64*3){ */ | |
| 467 | for (j = 0; j < 8; j++) { | |
| 468 | mdelay(3); | |
| 469 | if (flush_cache == 1) | |
| 470 | inner_dcache_flush_all(); | |
| 471 | #if 1 | |
| 472 | #if 0 | |
| 473 | /* reset RA mode */ | |
| 474 | asm volatile ("MRC p15, 0, %0, c1, c0, 1\n" "ORR %0, %0, #1 << 11\n" /* disable */ | |
| 475 | "ORR %0, %0, #1 << 12\n" /* disable */ | |
| 476 | "MCR p15, 0, %0, c1, c0, 1\n" "MRC p15, 0, %0, c1, c0, 1\n" "BIC %0, %0, #1 << 11\n" /* enable */ | |
| 477 | "BIC %0, %0, #1 << 12\n" /* enable */ | |
| 478 | "MCR p15, 0, %0, c1, c0, 1\n":"+r" (temp) | |
| 479 | : : "cc"); | |
| 480 | #endif | |
| 481 | /* enable ARM CPU PMU */ | |
| 482 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 483 | "ORR %0, %0, #1 << 2\n" /* reset cycle count */ | |
| 484 | "BIC %0, %0, #1 << 3\n" /* count every clock cycle */ | |
| 485 | "MCR p15, 0, %0, c9, c12, 0\n":"+r" (temp) | |
| 486 | : : "cc"); | |
| 487 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "ORR %0, %0, #1 << 0\n" /* enable */ | |
| 488 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 489 | "MRC p15, 0, %0, c9, c12, 1\n" | |
| 490 | "ORR %0, %0, #1 << 31\n" | |
| 491 | "MCR p15, 0, %0, c9, c12, 1\n":"+r" (temp) | |
| 492 | : : "cc"); | |
| 493 | #endif | |
| 494 | asm volatile ("push {r0,r1,r2,r9}\n" | |
| 495 | "mov r0, %0\n" | |
| 496 | "mov r1, %1\n" | |
| 497 | "mov r2, %2\n" | |
| 498 | "mov r9, %3\n" | |
| 499 | "stmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 500 | "1:\n" "pld [r1, r9]\n" | |
| 501 | /* "pldw [r0, r9]\n" */ | |
| 502 | ".word 0xf790f009\n" | |
| 503 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 504 | "subs r2, r2, #32 \n" | |
| 505 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 506 | "blt 2f\n" | |
| 507 | "ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 508 | "subs r2, r2, #32 \n" | |
| 509 | "stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 510 | "bge 1b\n" "2:\n" | |
| 511 | "ldmfd sp!, {r3, r4, r5, r6, r7, r8, r12, lr}\n" | |
| 512 | "pop {r0,r1,r2,r9}\n" : : "r" (&buffer_dst), | |
| 513 | "r"(&buffer_src), "r"(copy_size), "r"(pld_dst) | |
| 514 | : ); | |
| 515 | ||
| 516 | ||
| 517 | /* #if defined(DEBUG_DRAMC_CALIB) */ | |
| 518 | #if 1 | |
| 519 | /* get CPU cycle count from the ARM CPU PMU */ | |
| 520 | asm volatile ("MRC p15, 0, %0, c9, c12, 0\n" "BIC %0, %0, #1 << 0\n" /* disable */ | |
| 521 | "MCR p15, 0, %0, c9, c12, 0\n" | |
| 522 | "MRC p15, 0, %0, c9, c13, 0\n":"+r" (temp) | |
| 523 | : : "cc"); | |
| 524 | #endif | |
| 525 | result[j] = temp; | |
| 526 | /* pr_debug(" %d ", temp); */ | |
| 527 | } | |
| 528 | avg = 0; | |
| 529 | for (j = 0; j < 8; j++) { | |
| 530 | avg += result[j]; | |
| 531 | } | |
| 532 | avg = avg >> 3; | |
| 533 | if (printlog == 1) | |
| 534 | pr_debug(" %d ", avg); | |
| 535 | } | |
| 536 | local_irq_restore(flags); | |
| 537 | preempt_enable(); | |
| 538 | } | |
| 539 | if (printlog == 1) | |
| 540 | pr_err("\n\r ==== test done pld+pldw==== flush_cache:%d\n", flush_cache); | |
| 541 | } |