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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / lcm / it6151_edp_dsi_video_sharp / it6151_edp_dsi_video_sharp.c
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6fa3eb70
S		 1#ifndef BUILD_LK
2#include <linux/string.h>
3#else
4#include <string.h>
5#endif
6#include "lcm_drv.h"
7
8#ifdef BUILD_LK
9 #include <platform/mt_gpio.h>
10 #include <platform/mt_pmic.h>
11 #include <platform/mt_i2c.h>
12#elif defined(BUILD_UBOOT)
13#else
14 #include <mach/mt_gpio.h>
15 #include <mach/mt_pm_ldo.h>
16#endif
17
18// ---------------------------------------------------------------------------
19// Local Constants
20// ---------------------------------------------------------------------------
21
22#define FRAME_WIDTH (2048) //(800)
23#define FRAME_HEIGHT (1536) //(1280)
24
25#define LCM_ID_NT35590 (0x90)
26// TODO. This LCM ID is NT51012 not 35590.
27#define GPIO_LCD_PWR_EN (GPIO74|0x80000000) //GPIO142
28#define GPIO_LCD_RST_EN (GPIO80|0x80000000)
29#define GPIO_LCD_STB_EN (GPIO79|0x80000000)
30#define GPIO_LCD_LED_EN GPIO_LCM_LED_EN //GPIO76
31
32#define GPIO_LCD_LED_PWM_EN (GPIO116 | 0x80000000) //GPIO116
33
34
35// ---------------------------------------------------------------------------
36// Local Variables
37// ---------------------------------------------------------------------------
38
39//static LCM_UTIL_FUNCS lcm_util = {0}; //for fixed warning issue
40static LCM_UTIL_FUNCS lcm_util =
41{
42 .set_reset_pin = NULL,
43 .udelay = NULL,
44 .mdelay = NULL,
45};
46
47
48#define SET_RESET_PIN(v) (lcm_util.set_reset_pin((v)))
49
50#define UDELAY(n) (lcm_util.udelay(n))
51#define MDELAY(n) (lcm_util.mdelay(n))
52
53
54// ---------------------------------------------------------------------------
55// Local Functions
56// ---------------------------------------------------------------------------
57
58#define dsi_set_cmdq_V2(cmd, count, ppara, force_update) lcm_util.dsi_set_cmdq_V2(cmd, count, ppara, force_update)
59#define dsi_set_cmdq(pdata, queue_size, force_update) lcm_util.dsi_set_cmdq(pdata, queue_size, force_update)
60#define wrtie_cmd(cmd) lcm_util.dsi_write_cmd(cmd)
61#define write_regs(addr, pdata, byte_nums) lcm_util.dsi_write_regs(addr, pdata, byte_nums)
62#define read_reg(cmd) lcm_util.dsi_dcs_read_lcm_reg(cmd)
63#define read_reg_v2(cmd, buffer, buffer_size) lcm_util.dsi_dcs_read_lcm_reg_v2(cmd, buffer, buffer_size)
64
65
66#define LCM_DSI_CMD_MODE 0
67
68#if 0
69static void init_lcm_registers(void)
70{
71 unsigned int data_array[16];
72
73#if 1
74
75 data_array[0] = 0x00011500; //software reset
76 dsi_set_cmdq(data_array, 1, 1);
77
78 MDELAY(20);
79
80 data_array[0]=0x0bae1500;
81 data_array[1]=0xeaee1500;
82 data_array[2]=0x5fef1500;
83 data_array[3]=0x68f21500;
84 data_array[4]=0x00ee1500;
85 data_array[5]=0x00ef1500;
86 dsi_set_cmdq(&data_array, 6, 1);
87
88#if 0
89
90 data_array[0] = 0x7DB21500;
91 dsi_set_cmdq(data_array, 1, 1);
92
93 data_array[0] = 0x0BAE1500;
94 dsi_set_cmdq(data_array, 1, 1);
95
96 data_array[0] = 0x18B61500;
97 dsi_set_cmdq(data_array, 1, 1);
98
99 data_array[0] = 0xEAEE1500;
100 dsi_set_cmdq(data_array, 1, 1);
101
102 data_array[0] = 0x5FEF1500;
103 dsi_set_cmdq(data_array, 1, 1);
104
105 data_array[0] = 0x68F21500;
106 dsi_set_cmdq(data_array, 1, 1);
107
108 data_array[0] = 0x00EE1500;
109 dsi_set_cmdq(data_array, 1, 1);
110
111 data_array[0] = 0x00EF1500;
112 dsi_set_cmdq(data_array, 1, 1);
113
114 data_array[0] = 0x64D21500;
115 dsi_set_cmdq(data_array, 1, 1);
116
117 data_array[0] = 0x00101500; //sleep out
118 dsi_set_cmdq(data_array, 1, 1);
119 MDELAY(20);
120#endif
121
122 //data_array[0] = 0xEFB11500;
123 //dsi_set_cmdq(data_array, 1, 1);
124 //MDELAY(1);
125
126 //data_array[0] = 0x00290500; //display on
127 //dsi_set_cmdq(data_array, 1, 1);
128#endif
129
130#if 0
131 data_array[0] = 0x00010500; //software reset
132 dsi_set_cmdq(data_array, 1, 1);
133
134 MDELAY(20);
135
136 data_array[0] = 0x00023902;
137 data_array[1] = 0x00000BAE;
138 dsi_set_cmdq(data_array, 2, 1);
139 MDELAY(1);
140
141 data_array[0] = 0x00023902;
142 data_array[1] = 0x0000EAEE;
143 dsi_set_cmdq(data_array, 2, 1);
144 MDELAY(1);
145
146 data_array[0] = 0x00023902;
147 data_array[1] = 0x00005FEF;
148 dsi_set_cmdq(data_array, 2, 1);
149 MDELAY(1);
150
151 data_array[0] = 0x00023902;
152 data_array[1] = 0x000068F2;
153 dsi_set_cmdq(data_array, 2, 1);
154 MDELAY(1);
155
156 data_array[0] = 0x00023902;
157 data_array[1] = 0x000000EE;
158 dsi_set_cmdq(data_array, 2, 1);
159 MDELAY(1);
160
161 data_array[0] = 0x00023902;
162 data_array[1] = 0x000000EF;
163 dsi_set_cmdq(data_array, 2, 1);
164 MDELAY(1);
165
166 data_array[0] = 0x00100500; //sleep out
167 dsi_set_cmdq(data_array, 1, 1);
168 MDELAY(20);
169
170 data_array[0] = 0x00290500; //display on
171 dsi_set_cmdq(data_array, 1, 1);
172#endif
173 //MDELAY(5);
174}
175#endif
176
177// ---------------------------------------------------------------------------
178// LCM Driver Implementations
179// ---------------------------------------------------------------------------
180
181static void lcm_set_util_funcs(const LCM_UTIL_FUNCS *util)
182{
183 memcpy(&lcm_util, util, sizeof(LCM_UTIL_FUNCS));
184}
185
186#if 1
187#ifdef BUILD_LK
188
189#define IT6151_BUSNUM I2C2
190#define it6151_SLAVE_ADDR/*it6151_I2C_ADDR*/ 0x58 //0x2d //write ;0x5b read
191
192
193U32 it6151_reg_i2c_write_byte (U8 dev_addr,U8 cmd, U8 data)
194{
195 U8 cmdBufferLen = 1;
196 U8 dataBufferLen = 1;
197 U32 ret_code = I2C_OK;
198 U8 write_data[I2C_FIFO_SIZE];
199 int transfer_len = 0;
200 int i=0, cmdIndex=0, dataIndex=0;
201
202 dev_addr = dev_addr<<1; // for write
203
204 transfer_len = cmdBufferLen + dataBufferLen;
205 if(I2C_FIFO_SIZE < (cmdBufferLen + dataBufferLen))
206 {
207 dprintf(CRITICAL, "[it6151_i2c_write] exceed I2C FIFO length!! \n");
208 return 0;
209 }
210
211 //write_data[0] = cmd;
212 //write_data[1] = writeData;
213
214 while(cmdIndex < cmdBufferLen)
215 {
216 write_data[i] = cmd;
217 cmdIndex++;
218 i++;
219 }
220
221 while(dataIndex < dataBufferLen)
222 {
223 write_data[i] = data;
224 dataIndex++;
225 i++;
226 }
227
228
229 /* dump write_data for check */
230 for( i=0 ; i < transfer_len ; i++ )
231 {
232 dprintf(CRITICAL, "[it6151_i2c_write] write_data[%d]=%x\n", i, write_data[i]);
233 }
234
235 ret_code = mt_i2c_write(IT6151_BUSNUM, dev_addr, write_data, transfer_len,0);
236
237
238 return ret_code;
239}
240
241
242static U32 it6151_reg_i2c_read_byte (U8 dev_addr,U8 *cmdBuffer, U8 *dataBuffer)
243{
244 U32 ret_code = I2C_OK;
245
246 dev_addr = (dev_addr<<1) | 1; // for read
247 ret_code = mt_i2c_write(IT6151_BUSNUM, dev_addr, cmdBuffer, 1, 0); // set register command
248 if (ret_code != I2C_OK)
249 return ret_code;
250
251 ret_code = mt_i2c_read(IT6151_BUSNUM, dev_addr, dataBuffer, 1, 0);
252
253 if (ret_code != I2C_OK)
254 return ret_code;
255
256
257 return ret_code;
258}
259
260 //end
261
262 /******************************************************************************
263 *IIC drvier,:protocol type 2 add by chenguangjian end
264 ******************************************************************************/
265#else
266extern UINT8 it6151_reg_i2c_read_byte(U8 dev_addr,U8 *cmdBuffer, U8 *dataBuffer);
267extern void it6151_reg_i2c_write_byte(U8 dev_addr,U8 cmd, U8 data);
268#endif
269#endif
270
271/////////////////////////////////////////////////////////////////////
272/// for it6151 defines start ///////////////////////////////////////
273/////////////////////////////////////////////////////////////////////
274
275
276//#define PANEL_RESOLUTION_1280x800_NOUFO
277//#define PANEL_RESOLUTION_2048x1536_NOUFO_18B
278#define PANEL_RESOLUTION_2048x1536
279// #define PANEL_RESOLUTION_2048x1536_NOUFO // FOR INTEL Platform
280// #define PANEL_RESOLUTION_1920x1200p60RB
281//#define PANEL_RESOLUTION_1920x1080p60
282//#define PANEL_RESULUTION_1536x2048
283
284///////////////////////////////////////////////////////////////
285
286//#define DP_I2C_ADDR (0xB8)
287//#define MIPI_I2C_ADDR (0xD8)
288
289
290///////////////////////////////////////////////////////////////
291#define MIPI_4_LANE (3)
292#define MIPI_3_LANE (2)
293#define MIPI_2_LANE (1)
294#define MIPI_1_LANE (0)
295
296// MIPI Packed Pixel Stream
297#define RGB_24b (0x3E)
298#define RGB_30b (0x0D)
299#define RGB_36b (0x1D)
300#define RGB_18b_P (0x1E)
301#define RGB_18b_L (0x2E)
302#define YCbCr_16b (0x2C)
303#define YCbCr_20b (0x0C)
304#define YCbCr_24b (0x1C)
305
306
307// DPTX reg62[3:0]
308#define B_DPTXIN_6Bpp (0)
309#define B_DPTXIN_8Bpp (1)
310#define B_DPTXIN_10Bpp (2)
311#define B_DPTXIN_12Bpp (3)
312
313#define B_LBR (1)
314#define B_HBR (0)
315
316#define B_4_LANE (3)
317#define B_2_LANE (1)
318#define B_1_LANE (0)
319
320#define B_SSC_ENABLE (1)
321#define B_SSC_DISABLE (0)
322
323///////////////////////////////////////////////////////////////////////////
324//CONFIGURE
325///////////////////////////////////////////////////////////////////////////
326#define TRAINING_BITRATE (B_HBR)
327#define DPTX_SSC_SETTING (B_SSC_ENABLE)//(B_SSC_DISABLE)
328#define HIGH_PCLK (1)
329#define MP_MCLK_INV (0)
330#define MP_CONTINUOUS_CLK (1)
331#define MP_LANE_DESKEW (1)
332#define MP_PCLK_DIV (2)
333#define MP_LANE_SWAP (0)
334#define MP_PN_SWAP (0)
335
336#define DP_PN_SWAP (0)
337#define DP_AUX_PN_SWAP (0)
338#define DP_LANE_SWAP (0)
339
340#define FRAME_RESYNC (0)
341
342#define LVDS_LANE_SWAP (0)
343#define LVDS_PN_SWAP (0)
344#define LVDS_DC_BALANCE (0)
345
346#define LVDS_6BIT (0) // '0' for 8 bit, '1' for 6 bit
347#define VESA_MAP (1) // '0' for JEIDA , '1' for VESA MAP
348
349#define INT_MASK (3)
350#define MIPI_INT_MASK (0)
351#define TIMER_CNT (0x0A)
352#define IT6151_DEBUG (0)
353///////////////////////////////////////////////////////////////////////
354// Global Setting
355///////////////////////////////////////////////////////////////////////
356#ifdef PANEL_RESOLUTION_1280x800_NOUFO
357#define PANEL_WIDTH 1280
358#define VIC 0
359#define MP_HPOL 0
360#define MP_VPOL 1
361#define DPTX_LANE_COUNT B_2_LANE
362#define MIPI_LANE_COUNT MIPI_4_LANE
363#define EN_UFO 0
364#define MIPI_PACKED_FMT RGB_24b
365#define MP_H_RESYNC 1
366#define MP_V_RESYNC 0
367#endif
368
369#ifdef PANEL_RESOLUTION_1920x1080p60
370#define PANEL_WIDTH 1920
371#define VIC 0x10
372#define MP_HPOL 1
373#define MP_VPOL 1
374#define DPTX_LANE_COUNT B_2_LANE
375#define MIPI_LANE_COUNT MIPI_4_LANE
376#define EN_UFO 0
377#define MIPI_PACKED_FMT RGB_24b
378#define MP_H_RESYNC 1
379#define MP_V_RESYNC 0
380#endif
381
382#ifdef PANEL_RESOLUTION_1920x1200p60RB
383#define PANEL_WIDTH 1920
384#define VIC 0 // non-Zero value for CEA setting, check the given input format.
385#define MP_HPOL 1
386#define MP_VPOL 0
387#define DPTX_LANE_COUNT B_2_LANE
388#define MIPI_LANE_COUNT MIPI_4_LANE
389#define EN_UFO 0
390#define MIPI_PACKED_FMT RGB_24b
391#define MP_H_RESYNC 1
392#define MP_V_RESYNC 0
393#endif
394
395#ifdef PANEL_RESOLUTION_2048x1536
396#define PANEL_WIDTH 2048
397#define VIC 0 // non-Zero value for CEA setting, check the given input format.
398#define MP_HPOL 0
399#define MP_VPOL 1
400#define MIPI_LANE_COUNT MIPI_4_LANE
401#define DPTX_LANE_COUNT B_4_LANE
402#define EN_UFO 1
403#define MIPI_PACKED_FMT RGB_24b
404#define MP_H_RESYNC 0
405#define MP_V_RESYNC 0
406#endif
407
408#ifdef PANEL_RESOLUTION_2048x1536_NOUFO
409#define PANEL_WIDTH 2048
410#define VIC 0 // non-Zero value for CEA setting, check the given input format.
411#define MP_HPOL 0
412#define MP_VPOL 1
413#define MIPI_LANE_COUNT MIPI_4_LANE
414#define DPTX_LANE_COUNT B_4_LANE
415#define EN_UFO 0
416#define MIPI_PACKED_FMT RGB_24b
417#define MP_H_RESYNC 1
418#define MP_V_RESYNC 0
419#endif
420
421#ifdef PANEL_RESOLUTION_2048x1536_NOUFO_18B
422#define PANEL_WIDTH 2048
423#define VIC 0 // non-Zero value for CEA setting, check the given input format.
424#define MP_HPOL 0
425#define MP_VPOL 1
426#define MIPI_LANE_COUNT MIPI_4_LANE
427#define DPTX_LANE_COUNT B_4_LANE
428#define EN_UFO 0
429#define MIPI_PACKED_FMT RGB_18b_P
430#define MP_H_RESYNC 1
431#define MP_V_RESYNC 0
432#endif
433
434#ifdef PANEL_RESULUTION_1536x2048
435#define PANEL_WIDTH 1536
436#define VIC 0 // non-Zero value for CEA setting, check the given input format.
437#define MP_HPOL 0
438#define MP_VPOL 1
439#define MIPI_LANE_COUNT MIPI_4_LANE
440#define DPTX_LANE_COUNT B_4_LANE
441#define EN_UFO 1
442#define MIPI_PACKED_FMT RGB_24b
443#define MP_H_RESYNC 1
444#define MP_V_RESYNC 0
445#endif
446///////////////////////////////////////////////////////////////////////////
447
448#define DP_I2C_ADDR 0x5C
449#define MIPI_I2C_ADDR 0x6C
450
451//#ifdef BUILD_LK
452//#define iTE_DEBUG_PRINTF(x) dprintf(INFO, x)
453//#else
454//#define iTE_DEBUG_PRINTF(x) printk(x)
455//#endif
456
457/////////////////////////////////////////////////////////////////////
458/// for it6151 defines end /////////////////////////////////
459/////////////////////////////////////////////////////////////////////
460/////////////////////////////////////////////////////////
461// Function
462/////////////////////////////////////////////////////////
463/////////////////////////////////////////////////////////////////////////////
464void IT6151_DPTX_init(void)
465{
466#ifndef BUILD_LK
467 printk("\IT6151_DPTX_init !!!\n");
468#else
469 printf("[LK/LCM] IT6151_DPTX_init\n");
470#endif
471 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x05,0x29);
472 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x05,0x00);
473
474 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x09,INT_MASK);// Enable HPD_IRQ,HPD_CHG,VIDSTABLE
475 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x0A,0x00);
476 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x0B,0x00);
477 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xC5,0xC1);
478 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xB5,0x00);
479 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xB7,0x80);
480 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xC4,0xF0);
481 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x06,0xFF);// Clear all interrupt
482 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x07,0xFF);// Clear all interrupt
483 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x08,0xFF);// Clear all interrupt
484
485 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x05,0x00);
486 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x0c,0x08);
487 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x21,0x05);
488 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x3a,0x04);
489 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x5f,0x06);
490 // {DP_I2C_ADDR,0xb5,0xFF,0x80},
491 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xc9,0xf5);
492 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xca,0x4c);
493 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xcb,0x37);
494 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xce,0x80);
495 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xd3,0x03);
496 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xd4,0x60);
497 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xe8,0x11);
498 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xec,VIC);
499MDELAY(5);
500
501 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x23,0x42);
502 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x24,0x07);
503 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x25,0x01);
504 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x26,0x00);
505 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x27,0x10);
506 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x2B,0x05);
507 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x23,0x40);
508 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x22,(DP_AUX_PN_SWAP<<3)|(DP_PN_SWAP<<2)|0x03);
509 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x16,(DPTX_SSC_SETTING<<4)|(DP_LANE_SWAP<<3)|(DPTX_LANE_COUNT<<1)|TRAINING_BITRATE);
510 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x0f,0x01);
511 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x76,0xa7);
512 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x77,0xaf);
513 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x7e,0x8f);
514 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x7f,0x07);
515 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x80,0xef);
516 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x81,0x5f);
517 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x82,0xef);
518 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x83,0x07);
519 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x88,0x38);
520 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x89,0x1f);
521 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x8a,0x48);
522 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x0f,0x00);
523 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x5c,0xf3);
524 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x17,0x04);
525 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x17,0x01);
526MDELAY(5);
527}
528
529int vit6151_init(void)
530{
531
532 unsigned char VenID[2], DevID[2], RevID;
533 unsigned char cmdBuffer;
534
535#ifdef BUILD_LK
536 dprintf(INFO, "[LK/LCM] vit6151_init\n");
537#else
538 printk("vit6151_init\n");
539#endif
540
541#ifdef BUILD_LK
542 cmdBuffer = 0x00;
543 it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &VenID[0]);
544 cmdBuffer = 0x01;
545 it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &VenID[1]);
546 cmdBuffer = 0x02;
547 it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &DevID[0]);
548 cmdBuffer = 0x03;
549 it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &DevID[1]);
550 cmdBuffer = 0x04;
551 it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &RevID);
552 #else
553 cmdBuffer = 0x00;
554 VenID[0] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &VenID[0]);
555 cmdBuffer = 0x01;
556 VenID[1] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &VenID[1]);
557 cmdBuffer = 0x02;
558 DevID[0] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &DevID[0]);
559 cmdBuffer = 0x03;
560 DevID[1] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &DevID[1]);
561 cmdBuffer = 0x04;
562 RevID = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &RevID);
563 #endif
564
565
566#ifndef BUILD_LK
567 printk("Current DPDevID=%02X%02X\n", DevID[1], DevID[0]);
568 printk("Current DPVenID=%02X%02X\n", VenID[1], VenID[0]);
569 printk("Current DPRevID=%02X\n\n", RevID);
570#endif
571
572 if( VenID[0]==0x54 && VenID[1]==0x49 && DevID[0]==0x51 && DevID[1]==0x61 ){
573
574#ifndef BUILD_LK
575 printk(" Test 1 DP_I2C_ADDR=0x%x, MIPI_I2C_ADDR=0x%x\n", DP_I2C_ADDR, MIPI_I2C_ADDR);
576#else
577 dprintf(INFO, "[LK/LCM] Test 1 DP_I2C_ADDR=0x%x, MIPI_I2C_ADDR=0x%x\n", DP_I2C_ADDR, MIPI_I2C_ADDR);
578#endif
579 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0x05,0x04);// DP SW Reset
580 it6151_reg_i2c_write_byte(DP_I2C_ADDR,0xfd,(MIPI_I2C_ADDR<<1)|1);
581 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x05,0x00);
582 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x0c,(MP_LANE_SWAP<<7)|(MP_PN_SWAP<<6)|(MIPI_LANE_COUNT<<4)|EN_UFO);
583 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x11,MP_MCLK_INV);
584 //{MIPI_I2C_ADDR,0x12,0xFF,0x03},
585 if(RevID == 0xA1){
586 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x19, MP_LANE_DESKEW);
587 }else{
588 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x19,(MP_CONTINUOUS_CLK<<1) | MP_LANE_DESKEW);
589 }
590
591 //it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x19,0x01);
592
593 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x27, MIPI_PACKED_FMT);
594 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x28,((PANEL_WIDTH/4-1)>>2)&0xC0);
595 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x29,(PANEL_WIDTH/4-1)&0xFF);
596
597 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x2e,0x34);
598 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x2f,0x01);
599
600
601 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x4e,(MP_V_RESYNC<<3)|(MP_H_RESYNC<<2)|(MP_VPOL<<1)|(MP_HPOL));
602 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x80,(EN_UFO<<5)|MP_PCLK_DIV);
603 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x84,0x8f);
604 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x09,MIPI_INT_MASK);
605 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x92,TIMER_CNT);
606 IT6151_DPTX_init();
607
608 return 0;
609 }
610
611#ifndef BUILD_LK
612 printk(" Test 2 DP_I2C_ADDR=0x%x, MIPI_I2C_ADDR=0x%x\n", DP_I2C_ADDR, MIPI_I2C_ADDR);
613#endif
614
615#ifdef BUILD_LK
616 cmdBuffer = 0x00;
617 it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &VenID[0]);
618 cmdBuffer = 0x01;
619 it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &VenID[1]);
620 cmdBuffer = 0x02;
621 it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &DevID[0]);
622 cmdBuffer = 0x03;
623 it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &DevID[1]);
624
625 cmdBuffer = 0x04;
626 it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &RevID);
627#else
628 cmdBuffer = 0x00;
629 VenID[0] = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &VenID[0]);
630 cmdBuffer = 0x01;
631 VenID[1] = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &VenID[1]);
632 cmdBuffer = 0x02;
633 DevID[0] = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &DevID[0]);
634 cmdBuffer = 0x03;
635 DevID[1] = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &DevID[1]);
636
637 cmdBuffer = 0x04;
638 RevID = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &RevID);
639
640#endif
641
642#ifndef BUILD_LK
643 printk("Current MPDevID=%02X%02X\n", DevID[1], DevID[0]);
644 printk("Current MPVenID=%02X%02X\n", VenID[1], VenID[0]);
645 printk("Current MPRevID=%02X\n\n", RevID);
646#endif
647
648 if(VenID[0]==0x54 && VenID[1]==0x49 && DevID[0]==0x21 && DevID[1]==0x61 ){
649 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x05,0x33);
650 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x05,0x40);
651 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x05,0x00);
652 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x0c,(MP_LANE_SWAP<<7)|(MP_PN_SWAP<<6)|(MIPI_LANE_COUNT<<4));
653 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x11, MP_MCLK_INV);
654 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x19,(MP_CONTINUOUS_CLK<<1) | MP_LANE_DESKEW);
655 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x4B,(FRAME_RESYNC<<4));
656 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x4E,(MP_V_RESYNC<<3)|(MP_H_RESYNC<<2)|(MP_VPOL<<1)|(MP_HPOL));
657 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x72,0x01);
658 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x73,0x03);
659 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0x80,MP_PCLK_DIV);
660 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0xC0,(HIGH_PCLK<< 4) | 0x0F);
661 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0xC1,0x01);
662 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0xC2,0x47);
663 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0xC3,0x67);
664 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0xC4,0x04);
665 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR,0xCB,(LVDS_PN_SWAP<<5)|(LVDS_LANE_SWAP<<4)|(LVDS_6BIT<<2)|(LVDS_DC_BALANCE<<1)| VESA_MAP);
666 return 1;
667 }
668 return -1;
669}
670
671static unsigned int IT6151_ESD_Check(void)
672{
673#ifndef BUILD_LK
674 static unsigned char ucIsIT6151=0xFF;
675 unsigned char ucReg, ucStat;
676 unsigned char cmdBuffer;
677
678 if(ucIsIT6151==0xFF){
679 unsigned char VenID[2], DevID[2];
680
681#ifndef BUILD_LK
682 pr_info("\nIT6151 1st IRQ !!!\n");
683#endif
684 cmdBuffer = 0x00;
685 VenID[0] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &VenID[0]);
686 cmdBuffer = 0x01;
687 VenID[1] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &VenID[1]);
688 cmdBuffer = 0x02;
689 DevID[0] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &DevID[0]);
690 cmdBuffer = 0x03;
691 DevID[1] = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &DevID[1]);
692
693#ifndef BUILD_LK
694 pr_info("Current DevID=%02X%02X\n", DevID[1], DevID[0]);
695 pr_info("Current VenID=%02X%02X\n", VenID[1], VenID[0]);
696#endif
697
698 if( VenID[0]==0x54 && VenID[1]==0x49 && DevID[0]==0x51 && DevID[1]==0x61){
699 ucIsIT6151 = 1;
700 }else{
701 ucIsIT6151 = 0;
702 }
703 }
704 if(ucIsIT6151==1){
705
706#if IT6151_DEBUG
707#ifndef BUILD_LK
708 cmdBuffer = 0x06;
709 ucReg = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucReg);
710 printk("\nIT6151 Reg0x06=0x%x !!!\n", ucReg);
711 cmdBuffer = 0x07;
712 ucReg = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucReg);
713 printk("\nIT6151 Reg0x07=0x%x !!!\n", ucReg);
714 cmdBuffer = 0x08;
715 ucReg = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucReg);
716 printk("\nIT6151 Reg0x08=0x%x !!!\n", ucReg);
717 cmdBuffer = 0x0E;
718 ucReg = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucReg);
719 printk("\nIT6151 Reg0x0E=0x%x !!!\n", ucReg);
720#endif
721#endif
722 cmdBuffer = 0x0D;
723 ucReg = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucReg);
724#ifndef BUILD_LK
725 pr_info("\nIT6151 Reg0x0D=0x%x !!!\n", ucReg);
726#endif
727 if(ucReg & 0x80){
728 cmdBuffer = 0x06;
729 ucStat = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &ucStat);
730 if(ucStat & 0x01){
731 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x06, ucStat);
732
733 cmdBuffer = 0x0D;
734 ucStat = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &ucStat);
735 if(ucStat & 0x10){
736 //disable timer
737 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x0B, 0x00);
738 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x08, 0x40);
739 }else{
740 //enable timer
741 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x0B, 0x40);
742 }
743 }
744 cmdBuffer = 0x08;
745 ucStat = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &ucStat);
746 if(ucStat & 0x40){
747 if(ucStat & 0x20){
748 //disable timer
749 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x0B, 0x00);
750 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x08, 0x40);
751 }else{
752 return TRUE;
753 }
754 }
755 }
756 if(ucReg & 0x01){ //DP_IRQ
757 cmdBuffer = 0x21;
758 ucStat = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucStat);
759 if(ucStat & 0x02){
760 it6151_reg_i2c_write_byte(DP_I2C_ADDR, 0x21, ucStat);
761 }
762 cmdBuffer = 0x06;
763 ucReg = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucReg);
764 cmdBuffer = 0x0D;
765 ucStat = it6151_reg_i2c_read_byte(DP_I2C_ADDR, &cmdBuffer, &ucStat);
766 if(ucReg & 0x03){
767 if(ucStat & 0x02){
768 return TRUE;
769 }
770 }
771 }
772 }
773 return FALSE;
774#endif
775}
776
777static void IT6151_ESD_Recover(void)
778{
779 unsigned char ucStat;
780 unsigned char cmdBuffer;
781 #ifndef BUILD_LK
782 printk("\nIT6151_ESD_Recover\n");
783 #endif
784 cmdBuffer = 0x08;
785 ucStat = it6151_reg_i2c_read_byte(MIPI_I2C_ADDR, &cmdBuffer, &ucStat);
786
787 if(ucStat & 0x40){
788 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x0B, 0x00);
789 it6151_reg_i2c_write_byte(MIPI_I2C_ADDR, 0x08, 0x40);
790 vit6151_init();
791 }else{
792 IT6151_DPTX_init();
793 }
794}
795
796static void lcm_get_params(LCM_PARAMS *params)
797{
798
799 memset(params, 0, sizeof(LCM_PARAMS));
800
801 params->type = LCM_TYPE_DSI;
802
803 params->width = FRAME_WIDTH;
804 params->height = FRAME_HEIGHT;
805
806#if 0
807 // enable tearing-free
808 params->dbi.te_mode = LCM_DBI_TE_MODE_VSYNC_ONLY;
809 params->dbi.te_edge_polarity = LCM_POLARITY_RISING;
810#endif
811
812 #if (LCM_DSI_CMD_MODE)
813 params->dsi.mode = CMD_MODE;
814 #else
815 params->dsi.mode = SYNC_PULSE_VDO_MODE; //SYNC_PULSE_VDO_MODE; //BURST_VDO_MODE; //;
816 #endif
817
818 // DSI
819 /* Command mode setting */
820 //1 Three lane or Four lane
821 params->dsi.LANE_NUM = LCM_FOUR_LANE;
822 //The following defined the fomat for data coming from LCD engine.
823 params->dsi.data_format.color_order = LCM_COLOR_ORDER_RGB;
824 params->dsi.data_format.trans_seq = LCM_DSI_TRANS_SEQ_MSB_FIRST;
825 params->dsi.data_format.padding = LCM_DSI_PADDING_ON_LSB;
826 params->dsi.data_format.format = LCM_DSI_FORMAT_RGB888;
827
828 // Highly depends on LCD driver capability.
829 // Not support in MT6573
830 params->dsi.packet_size=256;
831
832 // Video mode setting
833 params->dsi.intermediat_buffer_num = 0;//because DSI/DPI HW design change, this parameters should be 0 when video mode in MT658X; or memory leakage
834
835 params->dsi.PS=LCM_PACKED_PS_24BIT_RGB888;
836 params->dsi.word_count=1920*3; //720*3;
837
838 params->dsi.ufoe_enable = 1;
839 params->dsi.edp_panel = 1;
840 params->dsi.vertical_sync_active = 2; //4; //6; //(12-4-4); //1;
841 params->dsi.vertical_backporch = 1; //4; //6; //4; //6; //10;
842 params->dsi.vertical_frontporch = 2; //4;//6; //4//6; //10;
843 params->dsi.vertical_active_line = FRAME_HEIGHT;
844
845 params->dsi.horizontal_sync_active = 8; //40; //44; //(120-40-40); //1;
846 params->dsi.horizontal_backporch = 8; //40;//44; //40; //44; //57;
847 params->dsi.horizontal_frontporch = 29; //40;//44; //40; //44; //32;
848 params->dsi.horizontal_active_pixel = FRAME_WIDTH;
849
850 // Bit rate calculation
851 //1 Every lane speed
852 //params->dsi.pll_div1=1; //0; // div1=0,1,2,3;div1_real=1,2,4,4 ----0: 546Mbps 1:273Mbps
853 //params->dsi.pll_div2=1; // div2=0,1,2,3;div1_real=1,2,4,4
854 //params->dsi.fbk_div =22;//31; // fref=26MHz, fvco=fref*(fbk_div+1)*2/(div1_real*div2_real)
855 //params->dsi.fbk_sel =0;
856 //params->dsi.fbk_div =45;
857 params->dsi.PLL_CLOCK = LCM_DSI_6589_PLL_CLOCK_299;//LCM_DSI_6589_PLL_CLOCK_NULL; //LCM_DSI_6589_PLL_CLOCK_396_5;
858
859 //params->dsi.CLK_ZERO = 262; //47;
860 //params->dsi.HS_ZERO = 117; //36;
861
862 params->dsi.cont_clock = 1;
863 //params->dsi.noncont_clock = TRUE;
864 //params->dsi.noncont_clock_period = 2; // Unit : frames
865
866 params->dsi.HS_TRAIL = 0x8; //36;
867 params->dsi.HS_ZERO = 0xA; //36;
868 params->dsi.HS_PRPR = 0x6; //36;
869 params->dsi.LPX = 0x5; //36;
870
871 params->dsi.DA_HS_EXIT = 0x6; //36;
872
873}
874//extern void DSI_clk_HS_mode(unsigned char enter);
875static void lcm_init(void)
876{
877 //unsigned int data_array[16];
878#ifdef BUILD_LK
879 dprintf(INFO, "[LK/LCM] lcm_init() enter\n");
880 //VGP6 3.3V
881 pmic_config_interface(0x424, 0x1, 0x1, 15);
882 pmic_config_interface(0x45a, 0x07, 0x07, 5);
883 //vgp4 1.8V
884 pmic_config_interface(0x420, 0x1, 0x1, 15);
885 pmic_config_interface(0x43c, 0x03, 0x07, 5);
886
887#else
888 printk( "[kernel/LCM] lcm_init() enter\n");
889#endif
890 mt_set_gpio_mode(GPIO_LCD_PWR_EN, GPIO_MODE_00);
891 mt_set_gpio_dir(GPIO_LCD_PWR_EN, GPIO_DIR_OUT);
892 mt_set_gpio_out(GPIO_LCD_PWR_EN, GPIO_OUT_ONE);
893 MDELAY(10);
894 mt_set_gpio_mode(GPIO_LCD_RST_EN, GPIO_MODE_00);
895 mt_set_gpio_dir(GPIO_LCD_RST_EN, GPIO_DIR_OUT);
896 mt_set_gpio_out(GPIO_LCD_RST_EN, GPIO_OUT_ONE);
897
898 MDELAY(10);
899 mt_set_gpio_mode(GPIO_LCD_STB_EN, GPIO_MODE_00);
900 mt_set_gpio_dir(GPIO_LCD_STB_EN, GPIO_DIR_OUT);
901 mt_set_gpio_out(GPIO_LCD_STB_EN, GPIO_OUT_ONE);
902 MDELAY(10);
903
904 mt_set_gpio_mode(GPIO_LCD_LED_EN, GPIO_MODE_00);
905 mt_set_gpio_dir(GPIO_LCD_LED_EN, GPIO_DIR_OUT);
906 mt_set_gpio_out(GPIO_LCD_LED_EN, GPIO_OUT_ONE);
907
908 MDELAY(10);
909
910 SET_RESET_PIN(1);
911 SET_RESET_PIN(0);
912 MDELAY(1);
913 SET_RESET_PIN(1);
914
915
916 MDELAY(10);
917
918 vit6151_init();
919 MDELAY(20);
920
921}
922
923
924
925static void lcm_suspend(void)
926{
927 //unsigned int data_array[16];
928
929#ifdef BUILD_LK
930 dprintf(INFO, "[LK/LCM] lcm_suspend() enter\n");
931#else
932printk( "[kernel/LCM] lcm_suspend() enter\n");
933#endif
934 MDELAY(20);
935 //
936 mt_set_gpio_mode(GPIO_LCD_LED_EN, GPIO_MODE_00);
937 mt_set_gpio_dir(GPIO_LCD_LED_EN, GPIO_DIR_OUT);
938 mt_set_gpio_out(GPIO_LCD_LED_EN, GPIO_OUT_ZERO);
939 MDELAY(20);
940 mt_set_gpio_mode(GPIO_LCD_STB_EN, GPIO_MODE_00);
941 mt_set_gpio_dir(GPIO_LCD_STB_EN, GPIO_DIR_OUT);
942 mt_set_gpio_out(GPIO_LCD_STB_EN, GPIO_OUT_ZERO);
943 MDELAY(20);
944 mt_set_gpio_mode(GPIO_LCD_RST_EN, GPIO_MODE_00);
945 mt_set_gpio_dir(GPIO_LCD_RST_EN, GPIO_DIR_OUT);
946 mt_set_gpio_out(GPIO_LCD_RST_EN, GPIO_OUT_ZERO);
947 MDELAY(20);
948 mt_set_gpio_mode(GPIO_LCD_PWR_EN, GPIO_MODE_00);
949 mt_set_gpio_dir(GPIO_LCD_PWR_EN, GPIO_DIR_OUT);
950 mt_set_gpio_out(GPIO_LCD_PWR_EN, GPIO_OUT_ZERO);
951
952 MDELAY(160);
953
954}
955
956
957static void lcm_resume(void)
958{
959#ifdef BUILD_LK
960 dprintf(INFO, "[LK/LCM] lcm_resume() enter\n");
961 //VGP6 3.3V
962 pmic_config_interface(0x424, 0x1, 0x1, 15);
963 pmic_config_interface(0x45a, 0x07, 0x07, 5);
964 //vgp4 1.8V
965 pmic_config_interface(0x420, 0x1, 0x1, 15);
966 pmic_config_interface(0x43c, 0x03, 0x07, 5);
967
968#else
969printk( "[kernle/LCM] lcm_resume() enter\n");
970#endif
971 mt_set_gpio_mode(GPIO_LCD_PWR_EN, GPIO_MODE_00);
972 mt_set_gpio_dir(GPIO_LCD_PWR_EN, GPIO_DIR_OUT);
973 mt_set_gpio_out(GPIO_LCD_PWR_EN, GPIO_OUT_ONE);
974 MDELAY(10);
975 mt_set_gpio_mode(GPIO_LCD_RST_EN, GPIO_MODE_00);
976 mt_set_gpio_dir(GPIO_LCD_RST_EN, GPIO_DIR_OUT);
977 mt_set_gpio_out(GPIO_LCD_RST_EN, GPIO_OUT_ONE);
978
979 MDELAY(10);
980 mt_set_gpio_mode(GPIO_LCD_STB_EN, GPIO_MODE_00);
981 mt_set_gpio_dir(GPIO_LCD_STB_EN, GPIO_DIR_OUT);
982 mt_set_gpio_out(GPIO_LCD_STB_EN, GPIO_OUT_ONE);
983 MDELAY(10);
984
985 mt_set_gpio_mode(GPIO_LCD_LED_EN, GPIO_MODE_00);
986 mt_set_gpio_dir(GPIO_LCD_LED_EN, GPIO_DIR_OUT);
987 mt_set_gpio_out(GPIO_LCD_LED_EN, GPIO_OUT_ONE);
988 MDELAY(20);
989
990 lcm_init();
991
992
993}
994
995#if (LCM_DSI_CMD_MODE)
996static void lcm_update(unsigned int x, unsigned int y,
997 unsigned int width, unsigned int height)
998{
999 unsigned int x0 = x;
1000 unsigned int y0 = y;
1001 unsigned int x1 = x0 + width - 1;
1002 unsigned int y1 = y0 + height - 1;
1003
1004 unsigned char x0_MSB = ((x0>>8)&0xFF);
1005 unsigned char x0_LSB = (x0&0xFF);
1006 unsigned char x1_MSB = ((x1>>8)&0xFF);
1007 unsigned char x1_LSB = (x1&0xFF);
1008 unsigned char y0_MSB = ((y0>>8)&0xFF);
1009 unsigned char y0_LSB = (y0&0xFF);
1010 unsigned char y1_MSB = ((y1>>8)&0xFF);
1011 unsigned char y1_LSB = (y1&0xFF);
1012
1013 unsigned int data_array[16];
1014
1015 data_array[0]= 0x00053902;
1016 data_array[1]= (x1_MSB<<24)|(x0_LSB<<16)|(x0_MSB<<8)|0x2a;
1017 data_array[2]= (x1_LSB);
1018 dsi_set_cmdq(data_array, 3, 1);
1019
1020 data_array[0]= 0x00053902;
1021 data_array[1]= (y1_MSB<<24)|(y0_LSB<<16)|(y0_MSB<<8)|0x2b;
1022 data_array[2]= (y1_LSB);
1023 dsi_set_cmdq(data_array, 3, 1);
1024
1025 data_array[0]= 0x00290508; //HW bug, so need send one HS packet
1026 dsi_set_cmdq(data_array, 1, 1);
1027
1028 data_array[0]= 0x002c3909;
1029 dsi_set_cmdq(data_array, 1, 0);
1030
1031}
1032#endif
1033#if 0
1034static unsigned int lcm_compare_id(void)
1035{
1036 unsigned int id=0;
1037 unsigned char buffer[2];
1038 unsigned int array[16];
1039
1040 SET_RESET_PIN(1);
1041 SET_RESET_PIN(0);
1042 MDELAY(1);
1043
1044 SET_RESET_PIN(1);
1045 MDELAY(20);
1046
1047 array[0] = 0x00023700;// read id return two byte,version and id
1048 dsi_set_cmdq(array, 1, 1);
1049
1050 read_reg_v2(0xF4, buffer, 2);
1051 id = buffer[0]; //we only need ID
1052 #ifdef BUILD_LK
1053 dprintf(INFO, "%s, LK nt35590 debug: nt35590 id = 0x%08x\n", __func__, id);
1054 #else
1055 printk("%s, kernel nt35590 horse debug: nt35590 id = 0x%08x\n", __func__, id);
1056 #endif
1057
1058 if(id == LCM_ID_NT35590)
1059 return 1;
1060 else
1061 return 0;
1062
1063
1064}
1065#endif
1066static unsigned int lcm_esd_check(void)
1067{
1068#ifndef BUILD_LK
1069 pr_info("lcm_esd_check\n\n");
1070#endif
1071 return IT6151_ESD_Check();
1072}
1073static unsigned int lcm_esd_recover(void)
1074{
1075#ifndef BUILD_LK
1076 pr_info("lcm_esd_recover\n\n");
1077#endif
1078 IT6151_ESD_Recover();
1079 return 0;
1080}
1081LCM_DRIVER it6151_edp_dsi_video_sharp_lcm_drv =
1082{
1083 .name = "it6151_edp_dsi_video_sharp",
1084 .set_util_funcs = lcm_set_util_funcs,
1085 .get_params = lcm_get_params,
1086 .init = lcm_init,
1087 .suspend = lcm_suspend,
1088 .resume = lcm_resume,
1089 //.compare_id = lcm_compare_id,
1090#if (LCM_DSI_CMD_MODE)
1091 .update = lcm_update,
1092#endif
1093 .esd_check = lcm_esd_check,
1094 .esd_recover = lcm_esd_recover,
1095 };
kernel source for telekom puls (alcatel/mediatek)