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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / lcm / inc / lcm_drv.h
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6fa3eb70
S		 1#ifndef __LCM_DRV_H__
2#define __LCM_DRV_H__
3
4
5// ---------------------------------------------------------------------------
6
7#ifndef ARY_SIZE
8#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
9#endif
10
11// ---------------------------------------------------------------------------
12
13/* common enumerations */
14
15typedef enum
16{
17 LCM_TYPE_DBI = 0,
18 LCM_TYPE_DPI,
19 LCM_TYPE_DSI
20} LCM_TYPE;
21
22
23typedef enum
24{
25 LCM_CTRL_NONE = 0,
26 LCM_CTRL_SERIAL_DBI,
27 LCM_CTRL_PARALLEL_DBI,
28 LCM_CTRL_GPIO
29} LCM_CTRL;
30
31
32typedef enum
33{
34 LCM_POLARITY_RISING = 0,
35 LCM_POLARITY_FALLING = 1
36} LCM_POLARITY;
37
38
39typedef enum
40{
41 LCM_CLOCK_PHASE_0 = 0,
42 LCM_CLOCK_PHASE_90 = 1
43} LCM_CLOCK_PHASE;
44
45
46typedef enum
47{
48 LCM_COLOR_ORDER_RGB = 0,
49 LCM_COLOR_ORDER_BGR = 1
50} LCM_COLOR_ORDER;
51
52
53typedef enum
54{
55 LCM_DRIVING_CURRENT_DEFAULT,
56 LCM_DRIVING_CURRENT_8MA = (1 << 0),
57 LCM_DRIVING_CURRENT_4MA = (1 << 1),
58 LCM_DRIVING_CURRENT_2MA = (1 << 2),
59 LCM_DRIVING_CURRENT_SLEW_CNTL = (1 << 3),
60 LCM_DRIVING_CURRENT_6575_4MA = (1 << 4),
61 LCM_DRIVING_CURRENT_6575_8MA = (3 << 4),
62 LCM_DRIVING_CURRENT_6575_12MA = (2 << 4),
63 LCM_DRIVING_CURRENT_6575_16MA = (4 << 4),
64 LCM_DRIVING_CURRENT_6MA,
65 LCM_DRIVING_CURRENT_12MA,
66 LCM_DRIVING_CURRENT_16MA
67} LCM_DRIVING_CURRENT;
68
69typedef enum{
70 LCM_INTERFACE_NOTDEFINED = 0,
71 LCM_INTERFACE_DSI0,
72 LCM_INTERFACE_DSI1,
73 LCM_INTERFACE_DSI_DUAL,
74 LCM_INTERFACE_DPI0,
75 LCM_INTERFACE_DPI1,
76 LCM_INTERFACE_DBI0
77}LCM_INTERFACE_ID;
78
79typedef enum{
80 LCM_IOCTL_NULL = 0,
81}LCM_IOCTL;
82
83/* DBI related enumerations */
84
85typedef enum
86{
87 LCM_DBI_CLOCK_FREQ_104M = 0,
88 LCM_DBI_CLOCK_FREQ_52M,
89 LCM_DBI_CLOCK_FREQ_26M,
90 LCM_DBI_CLOCK_FREQ_13M,
91 LCM_DBI_CLOCK_FREQ_7M
92} LCM_DBI_CLOCK_FREQ;
93
94
95typedef enum
96{
97 LCM_DBI_DATA_WIDTH_8BITS = 0,
98 LCM_DBI_DATA_WIDTH_9BITS = 1,
99 LCM_DBI_DATA_WIDTH_16BITS = 2,
100 LCM_DBI_DATA_WIDTH_18BITS = 3,
101 LCM_DBI_DATA_WIDTH_24BITS = 4,
102 LCM_DBI_DATA_WIDTH_32BITS = 5
103} LCM_DBI_DATA_WIDTH;
104
105
106typedef enum
107{
108 LCM_DBI_CPU_WRITE_8_BITS = 8,
109 LCM_DBI_CPU_WRITE_16_BITS = 16,
110 LCM_DBI_CPU_WRITE_32_BITS = 32,
111} LCM_DBI_CPU_WRITE_BITS;
112
113
114typedef enum
115{
116 LCM_DBI_FORMAT_RGB332 = 0,
117 LCM_DBI_FORMAT_RGB444 = 1,
118 LCM_DBI_FORMAT_RGB565 = 2,
119 LCM_DBI_FORMAT_RGB666 = 3,
120 LCM_DBI_FORMAT_RGB888 = 4
121} LCM_DBI_FORMAT;
122
123
124typedef enum
125{
126 LCM_DBI_TRANS_SEQ_MSB_FIRST = 0,
127 LCM_DBI_TRANS_SEQ_LSB_FIRST = 1
128} LCM_DBI_TRANS_SEQ;
129
130
131typedef enum
132{
133 LCM_DBI_PADDING_ON_LSB = 0,
134 LCM_DBI_PADDING_ON_MSB = 1
135} LCM_DBI_PADDING;
136
137
138typedef enum
139{
140 LCM_DBI_TE_MODE_DISABLED = 0,
141 LCM_DBI_TE_MODE_VSYNC_ONLY = 1,
142 LCM_DBI_TE_MODE_VSYNC_OR_HSYNC = 2,
143} LCM_DBI_TE_MODE;
144
145
146typedef enum
147{
148 LCM_DBI_TE_VS_WIDTH_CNT_DIV_8 = 0,
149 LCM_DBI_TE_VS_WIDTH_CNT_DIV_16 = 1,
150 LCM_DBI_TE_VS_WIDTH_CNT_DIV_32 = 2,
151 LCM_DBI_TE_VS_WIDTH_CNT_DIV_64 = 3,
152} LCM_DBI_TE_VS_WIDTH_CNT_DIV;
153
154
155/* DPI related enumerations */
156
157typedef enum
158{
159 LCM_DPI_FORMAT_RGB565 = 0,
160 LCM_DPI_FORMAT_RGB666 = 1,
161 LCM_DPI_FORMAT_RGB888 = 2
162} LCM_DPI_FORMAT;
163
164typedef enum
165{
166 LCM_SERIAL_CLOCK_FREQ_104M = 0,
167 LCM_SERIAL_CLOCK_FREQ_26M,
168 LCM_SERIAL_CLOCK_FREQ_52M
169} LCM_SERIAL_CLOCK_FREQ;
170
171typedef enum
172{
173 LCM_SERIAL_CLOCK_DIV_2 = 0,
174 LCM_SERIAL_CLOCK_DIV_4 = 1,
175 LCM_SERIAL_CLOCK_DIV_8 = 2,
176 LCM_SERIAL_CLOCK_DIV_16 = 3,
177} LCM_SERIAL_CLOCK_DIV;
178
179
180/* DSI related enumerations */
181
182typedef enum
183{
184 CMD_MODE = 0,
185 SYNC_PULSE_VDO_MODE = 1,
186 SYNC_EVENT_VDO_MODE = 2,
187 BURST_VDO_MODE = 3
188} LCM_DSI_MODE_CON;
189
190
191typedef enum
192{
193 LCM_ONE_LANE = 1,
194 LCM_TWO_LANE = 2,
195 LCM_THREE_LANE = 3,
196 LCM_FOUR_LANE = 4,
197} LCM_LANE_NUM;
198
199
200typedef enum
201{
202 LCM_DSI_FORMAT_RGB565 = 0,
203 LCM_DSI_FORMAT_RGB666 = 1,
204 LCM_DSI_FORMAT_RGB888 = 2
205} LCM_DSI_FORMAT;
206
207
208typedef enum
209{
210 LCM_DSI_TRANS_SEQ_MSB_FIRST = 0,
211 LCM_DSI_TRANS_SEQ_LSB_FIRST = 1
212} LCM_DSI_TRANS_SEQ;
213
214
215typedef enum
216{
217 LCM_DSI_PADDING_ON_LSB = 0,
218 LCM_DSI_PADDING_ON_MSB = 1
219} LCM_DSI_PADDING;
220
221
222typedef enum
223{
224 LCM_PACKED_PS_16BIT_RGB565=0,
225 LCM_LOOSELY_PS_18BIT_RGB666=1,
226 LCM_PACKED_PS_24BIT_RGB888=2,
227 LCM_PACKED_PS_18BIT_RGB666=3
228} LCM_PS_TYPE;
229
230typedef enum
231{
232 LCM_DSI_6589_PLL_CLOCK_NULL = 0,
233 LCM_DSI_6589_PLL_CLOCK_201_5 = 1,
234 LCM_DSI_6589_PLL_CLOCK_208 = 2,
235 LCM_DSI_6589_PLL_CLOCK_214_5 = 3,
236 LCM_DSI_6589_PLL_CLOCK_221 = 4,
237 LCM_DSI_6589_PLL_CLOCK_227_5 = 5,
238 LCM_DSI_6589_PLL_CLOCK_234 = 6,
239 LCM_DSI_6589_PLL_CLOCK_240_5 = 7,
240 LCM_DSI_6589_PLL_CLOCK_247 = 8,
241 LCM_DSI_6589_PLL_CLOCK_253_5 = 9,
242 LCM_DSI_6589_PLL_CLOCK_260 = 10,
243 LCM_DSI_6589_PLL_CLOCK_266_5 = 11,
244 LCM_DSI_6589_PLL_CLOCK_273 = 12,
245 LCM_DSI_6589_PLL_CLOCK_279_5 = 13,
246 LCM_DSI_6589_PLL_CLOCK_286 = 14,
247 LCM_DSI_6589_PLL_CLOCK_292_5 = 15,
248 LCM_DSI_6589_PLL_CLOCK_299 = 16,
249 LCM_DSI_6589_PLL_CLOCK_305_5 = 17,
250 LCM_DSI_6589_PLL_CLOCK_312 = 18,
251 LCM_DSI_6589_PLL_CLOCK_318_5 = 19,
252 LCM_DSI_6589_PLL_CLOCK_325 = 20,
253 LCM_DSI_6589_PLL_CLOCK_331_5 = 21,
254 LCM_DSI_6589_PLL_CLOCK_338 = 22,
255 LCM_DSI_6589_PLL_CLOCK_344_5 = 23,
256 LCM_DSI_6589_PLL_CLOCK_351 = 24,
257 LCM_DSI_6589_PLL_CLOCK_357_5 = 25,
258 LCM_DSI_6589_PLL_CLOCK_364 = 26,
259 LCM_DSI_6589_PLL_CLOCK_370_5 = 27,
260 LCM_DSI_6589_PLL_CLOCK_377 = 28,
261 LCM_DSI_6589_PLL_CLOCK_383_5 = 29,
262 LCM_DSI_6589_PLL_CLOCK_390 = 30,
263 LCM_DSI_6589_PLL_CLOCK_396_5 = 31,
264 LCM_DSI_6589_PLL_CLOCK_403 = 32,
265 LCM_DSI_6589_PLL_CLOCK_409_5 = 33,
266 LCM_DSI_6589_PLL_CLOCK_416 = 34,
267 LCM_DSI_6589_PLL_CLOCK_422_5 = 35,
268 LCM_DSI_6589_PLL_CLOCK_429 = 36,
269 LCM_DSI_6589_PLL_CLOCK_435_5 = 37,
270 LCM_DSI_6589_PLL_CLOCK_442 = 38,
271 LCM_DSI_6589_PLL_CLOCK_448_5 = 39,
272 LCM_DSI_6589_PLL_CLOCK_455 = 40,
273 LCM_DSI_6589_PLL_CLOCK_461_5 = 41,
274 LCM_DSI_6589_PLL_CLOCK_468 = 42,
275 LCM_DSI_6589_PLL_CLOCK_474_5 = 43,
276 LCM_DSI_6589_PLL_CLOCK_481 = 44,
277 LCM_DSI_6589_PLL_CLOCK_487_5 = 45,
278 LCM_DSI_6589_PLL_CLOCK_494 = 46,
279 LCM_DSI_6589_PLL_CLOCK_500_5 = 47,
280 LCM_DSI_6589_PLL_CLOCK_507 = 48,
281 LCM_DSI_6589_PLL_CLOCK_513_5 = 49,
282 LCM_DSI_6589_PLL_CLOCK_520 = 50,
283} LCM_DSI_PLL_CLOCK;
284
285// ---------------------------------------------------------------------------
286
287typedef struct
288{
289 LCM_COLOR_ORDER color_order;
290 LCM_DBI_TRANS_SEQ trans_seq;
291 LCM_DBI_PADDING padding;
292 LCM_DBI_FORMAT format;
293 LCM_DBI_DATA_WIDTH width;
294} LCM_DBI_DATA_FORMAT;
295
296
297typedef struct
298{
299 LCM_POLARITY cs_polarity;
300 LCM_POLARITY clk_polarity;
301 LCM_CLOCK_PHASE clk_phase;
302 unsigned int is_non_dbi_mode;
303
304 LCM_SERIAL_CLOCK_FREQ clock_base;
305 LCM_SERIAL_CLOCK_DIV clock_div;
306////////////////////////////////////MT6575 added params, and if lcm driver is for 6575, only care these below params
307 unsigned int css;
308 unsigned int csh;
309 unsigned int rd_1st;
310 unsigned int rd_2nd;
311 unsigned int wr_1st;
312 unsigned int wr_2nd;
313
314 unsigned int sif_3wire;
315 unsigned int sif_sdi;
316 LCM_POLARITY sif_1st_pol;
317 LCM_POLARITY sif_sck_def;
318 unsigned int sif_div2;
319 unsigned int sif_hw_cs;
320////////////////////////////////////
321} LCM_DBI_SERIAL_PARAMS;
322
323
324typedef struct
325{
326 /* timing parameters */
327 unsigned int write_setup;
328 unsigned int write_hold;
329 unsigned int write_wait;
330 unsigned int read_setup;
331 unsigned int read_hold;
332 unsigned int read_latency;
333 unsigned int wait_period;
334 /*only for 6575*/
335 unsigned int cs_high_width;
336} LCM_DBI_PARALLEL_PARAMS;
337
338
339typedef struct
340{
341 LCM_COLOR_ORDER color_order;
342 LCM_DSI_TRANS_SEQ trans_seq;
343 LCM_DSI_PADDING padding;
344 LCM_DSI_FORMAT format;
345} LCM_DSI_DATA_FORMAT;
346
347typedef struct
348{
349 LCM_DSI_MODE_CON mode;
350 unsigned int cmd_if;
351 unsigned int addr;
352 unsigned int val[4];
353}LCM_DSI_MODE_SWITCH_CMD;
354
355typedef struct
356{
357 unsigned int compress_ratio;
358 unsigned int lr_mode_en;
359 unsigned int vlc_disable;
360 unsigned int vlc_config;
361}LCM_UFOE_CONFIG_PARAMS;
362// ---------------------------------------------------------------------------
363
364typedef struct
365{
366 /* common parameters for serial & parallel interface */
367 unsigned int port;
368 LCM_DBI_CLOCK_FREQ clock_freq;
369 LCM_DBI_DATA_WIDTH data_width;
370 LCM_DBI_DATA_FORMAT data_format;
371 LCM_DBI_CPU_WRITE_BITS cpu_write_bits;
372 LCM_DRIVING_CURRENT io_driving_current;
373 LCM_DRIVING_CURRENT msb_io_driving_current;
374
375 /* tearing control */
376 LCM_DBI_TE_MODE te_mode;
377 LCM_POLARITY te_edge_polarity;
378 unsigned int te_hs_delay_cnt;
379 unsigned int te_vs_width_cnt;
380 LCM_DBI_TE_VS_WIDTH_CNT_DIV te_vs_width_cnt_div;
381
382 /* particular parameters for serial & parallel interface */
383 LCM_DBI_SERIAL_PARAMS serial;
384 LCM_DBI_PARALLEL_PARAMS parallel;
385} LCM_DBI_PARAMS;
386
387
388typedef struct
389{
390 /*
391 Pixel Clock Frequency = 26MHz * mipi_pll_clk_div1
392 / (mipi_pll_clk_ref + 1)
393 / (2 * mipi_pll_clk_div2)
394 / dpi_clk_div
395 */
396 unsigned int mipi_pll_clk_ref; // 0..1
397 unsigned int mipi_pll_clk_div1; // 0..63
398 unsigned int mipi_pll_clk_div2; // 0..15
399 unsigned int mipi_pll_clk_fbk_div; //PCLK=> 8: 26MHz, 10: 35MHz, 12: 40MHz
400 unsigned int dpi_clk_div; // 2..32
401 unsigned int dpi_clk_duty; // (dpi_clk_div - 1) .. 31
402 unsigned int PLL_CLOCK;
403 unsigned int dpi_clock;
404 unsigned int ssc_disable;
405 unsigned int ssc_range;
406
407 unsigned int width;
408 unsigned int height;
409 unsigned int bg_width;
410 unsigned int bg_height;
411
412 /* polarity parameters */
413 LCM_POLARITY clk_pol;
414 LCM_POLARITY de_pol;
415 LCM_POLARITY vsync_pol;
416 LCM_POLARITY hsync_pol;
417
418 /* timing parameters */
419 unsigned int hsync_pulse_width;
420 unsigned int hsync_back_porch;
421 unsigned int hsync_front_porch;
422 unsigned int vsync_pulse_width;
423 unsigned int vsync_back_porch;
424 unsigned int vsync_front_porch;
425
426 /* output format parameters */
427 LCM_DPI_FORMAT format;
428 LCM_COLOR_ORDER rgb_order;
429 unsigned int is_serial_output;
430 unsigned int i2x_en;
431 unsigned int i2x_edge;
432 unsigned int embsync;
433 unsigned int lvds_tx_en;
434 /* intermediate buffers parameters */
435 unsigned int intermediat_buffer_num; // 2..3
436
437 /* iopad parameters */
438 LCM_DRIVING_CURRENT io_driving_current;
439 LCM_DRIVING_CURRENT lsb_io_driving_current;
440
441} LCM_DPI_PARAMS;
442
443
444// ---------------------------------------------------------------------------
445typedef struct {
446 unsigned char cmd;
447 unsigned char count;
448 unsigned char para_list[2];
449} LCM_esd_check_item;
450typedef enum
451{
452 DUAL_DSI_NONE = 0x0,
453 DUAL_DSI_CMD = 0x1,
454 DUAL_DSI_VDO = 0x2,
455}DUAL_DSI_TYPE;
456
457typedef enum
458{
459 MIPITX_PHY_LANE_0 = 0,
460 MIPITX_PHY_LANE_1,
461 MIPITX_PHY_LANE_2,
462 MIPITX_PHY_LANE_3,
463 MIPITX_PHY_LANE_CK,
464 MIPITX_PHY_LANE_RX,
465 MIPITX_PHY_LANE_NUM
466}MIPITX_PHY_LANE_SWAP;
467
468typedef enum
469{
470 MIPITX_PHY_PORT_0 = 0,
471 MIPITX_PHY_PORT_1,
472 MIPITX_PHY_PORT_NUM
473}MIPITX_PHY_PORT;
474typedef struct
475{
476 LCM_DSI_MODE_CON mode;
477 LCM_DSI_MODE_CON switch_mode;
478 unsigned int DSI_WMEM_CONTI;
479 unsigned int DSI_RMEM_CONTI;
480 unsigned int VC_NUM;
481
482 LCM_LANE_NUM LANE_NUM;
483 LCM_DSI_DATA_FORMAT data_format;
484
485 /* intermediate buffers parameters */
486 unsigned int intermediat_buffer_num; // 2..3
487
488 LCM_PS_TYPE PS;
489 unsigned int word_count;
490
491 unsigned int packet_size;
492
493 unsigned int vertical_sync_active;
494 unsigned int vertical_backporch;
495 unsigned int vertical_frontporch;
496 unsigned int vertical_frontporch_for_low_power;
497 unsigned int vertical_active_line;
498
499 unsigned int horizontal_sync_active;
500 unsigned int horizontal_backporch;
501 unsigned int horizontal_frontporch;
502 unsigned int horizontal_blanking_pixel;
503 unsigned int horizontal_active_pixel;
504 unsigned int horizontal_bllp;
505
506 unsigned int line_byte;
507 unsigned int horizontal_sync_active_byte;
508 unsigned int horizontal_backporch_byte;
509 unsigned int horizontal_frontporch_byte;
510 unsigned int rgb_byte;
511
512 unsigned int horizontal_sync_active_word_count;
513 unsigned int horizontal_backporch_word_count;
514 unsigned int horizontal_frontporch_word_count;
515
516 unsigned char HS_TRAIL;
517 unsigned char HS_ZERO;
518 unsigned char HS_PRPR;
519 unsigned char LPX;
520
521 unsigned char TA_SACK;
522 unsigned char TA_GET;
523 unsigned char TA_SURE;
524 unsigned char TA_GO;
525
526 unsigned char CLK_TRAIL;
527 unsigned char CLK_ZERO;
528 unsigned char LPX_WAIT;
529 unsigned char CONT_DET;
530
531 unsigned char CLK_HS_PRPR;
532 unsigned char CLK_HS_POST;
533 unsigned char DA_HS_EXIT;
534 unsigned char CLK_HS_EXIT;
535
536 unsigned int pll_select;
537 unsigned int pll_div1;
538 unsigned int pll_div2;
539 unsigned int fbk_div;
540 unsigned int fbk_sel;
541 unsigned int rg_bir;
542 unsigned int rg_bic;
543 unsigned int rg_bp;
544 unsigned int PLL_CLOCK;
545 unsigned int dsi_clock;
546 unsigned int ssc_disable;
547 unsigned int ssc_range;
548 unsigned int compatibility_for_nvk;
549 unsigned int cont_clock;
550 unsigned int ufoe_enable;
551 LCM_UFOE_CONFIG_PARAMS ufoe_params;
552 unsigned int edp_panel;
553 unsigned int customization_esd_check_enable;
554 unsigned int esd_check_enable;
555 unsigned int lcm_int_te_monitor;
556 unsigned int lcm_int_te_period;
557
558 unsigned int lcm_ext_te_monitor;
559 unsigned int lcm_ext_te_enable;
560
561 unsigned int noncont_clock;
562 unsigned int noncont_clock_period;
563 unsigned int clk_lp_per_line_enable;
564 LCM_esd_check_item lcm_esd_check_table[3];
565 unsigned int switch_mode_enable;
566 DUAL_DSI_TYPE dual_dsi_type;
567 unsigned int lane_swap_en;
568 MIPITX_PHY_LANE_SWAP lane_swap[MIPITX_PHY_PORT_NUM][MIPITX_PHY_LANE_NUM];
569
570 unsigned int vertical_vfp_lp;
571
572 unsigned int ulps_sw_enable;
573
574#ifdef CONFIG_MIXMODE_FOR_INCELL
575 unsigned int mixmode_enable;
576 unsigned int mixmode_mipi_clock;
577 unsigned int pwm_fps;
578#endif
579
580} LCM_DSI_PARAMS;
581
582// ---------------------------------------------------------------------------
583
584typedef struct
585{
586 LCM_TYPE type;
587 LCM_CTRL ctrl; //! how to control LCM registers
588 LCM_INTERFACE_ID lcm_if;
589 LCM_INTERFACE_ID lcm_cmd_if;
590 /* common parameters */
591 unsigned int width;
592 unsigned int height;
593 unsigned int io_select_mode; //DBI or DPI should select IO mode according to chip spec
594
595 /* particular parameters */
596 LCM_DBI_PARAMS dbi;
597 LCM_DPI_PARAMS dpi;
598 LCM_DSI_PARAMS dsi;
599 unsigned int physical_width;
600 unsigned int physical_height;
601 unsigned int od_table_size;
602 void *od_table;
603} LCM_PARAMS;
604
605
606// ---------------------------------------------------------------------------
607
608#define REGFLAG_ESCAPE_ID (0x00)
609#define REGFLAG_DELAY_MS_V3 (0xFF)
610
611typedef struct {
612 unsigned char id;
613 unsigned char cmd;
614 unsigned char count;
615 unsigned char para_list[128];
616} LCM_setting_table_V3;
617
618typedef struct
619{
620 void (*set_reset_pin)(unsigned int value);
621 void (*set_chip_select)(unsigned int value);
622 int (*set_gpio_out)(unsigned int gpio, unsigned int value);
623
624 void (*udelay)(unsigned int us);
625 void (*mdelay)(unsigned int ms);
626
627 void (*send_cmd)(unsigned int cmd);
628 void (*send_data)(unsigned int data);
629 unsigned int (*read_data)(void);
630
631 void (*dsi_set_cmdq_V3)(LCM_setting_table_V3 *para_list, unsigned int size, unsigned char force_update);
632 void (*dsi_set_cmdq_V2)(unsigned cmd, unsigned char count, unsigned char *para_list, unsigned char force_update);
633 void (*dsi_set_cmdq)(unsigned int *pdata, unsigned int queue_size, unsigned char force_update);
634 void (*dsi_write_cmd)(unsigned int cmd);
635 void (*dsi_write_regs)(unsigned int addr, unsigned int *para, unsigned int nums);
636 unsigned int (*dsi_read_reg)(void);
637 unsigned int (*dsi_dcs_read_lcm_reg)(unsigned char cmd);
638 unsigned int (*dsi_dcs_read_lcm_reg_v2)(unsigned char cmd, unsigned char *buffer, unsigned char buffer_size);
639 void (*wait_transfer_done)(void);
640
641 /** FIXME: GPIO mode should not be configured in lcm driver
642 REMOVE ME after GPIO customization is done
643 */
644 int (*set_gpio_mode)(unsigned int pin, unsigned int mode);
645 int (*set_gpio_dir)(unsigned int pin, unsigned int dir);
646 int (*set_gpio_pull_enable)(unsigned int pin, unsigned char pull_en);
647 void (*dsi_set_cmdq_V22)(void* cmdq, unsigned cmd, unsigned char count, unsigned char *para_list, unsigned char force_update);
648 void (*dsi_swap_port)(int swap);
649} LCM_UTIL_FUNCS;
650typedef enum
651{
652 LCM_DRV_IOCTL_ENABLE_CMD_MODE = 0x100,
653}LCM_DRV_IOCTL_CMD;
654
655typedef struct
656{
657 const char* name;
658 void (*set_util_funcs)(const LCM_UTIL_FUNCS *util);
659 void (*get_params)(LCM_PARAMS *params);
660
661 void (*init)(void);
662 void (*suspend)(void);
663 void (*resume)(void);
664
665 // for power-on sequence refinement
666 void (*init_power)(void);
667 void (*suspend_power)(void);
668 void (*resume_power)(void);
669
670 void (*update)(unsigned int x, unsigned int y, unsigned int width, unsigned int height);
671 unsigned int (*compare_id)(void);
672
673 ///////////////////////////CABC backlight related function
674 void (*set_backlight)(unsigned int level);
675 void (*set_pwm)(unsigned int divider);
676 unsigned int (*get_pwm)(unsigned int divider);
677 void (*set_backlight_mode)(unsigned int mode);
678 ///////////////////////////
679
680 /////////////ESD_RECOVERY//////////////////////
681 unsigned int (*esd_check)(void);
682 unsigned int (*esd_recover)(void);
683 unsigned int (*check_status)(void);
684 unsigned int (*ata_check)(unsigned char *buffer);
685 void (*read_fb)(unsigned char *buffer);
686 int (*ioctl)(LCM_DRV_IOCTL_CMD cmd, unsigned int data);
687 /////////////////////////////////////////////////
688 ////switch mode
689 void* (*switch_mode)(int mode);
690 void (*set_cmd)(void* handle,int* mode,unsigned int cmd_num);
691} LCM_DRIVER;
692
693
694// ---------------------------------------------------------------------------
695// LCM Driver Functions
696// ---------------------------------------------------------------------------
697
698const LCM_DRIVER* LCM_GetDriver(void);
699unsigned char which_lcd_module_triple(void);
700
701#endif // __LCM_DRV_H__
kernel source for telekom puls (alcatel/mediatek)