projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fa3eb70 S |
1 | |
| 2 | ||
| 3 | #ifndef _SIHDMITX_902X_TPI_H_ | |
| 4 | #define _SIHDMITX_902X_TPI_H_ | |
| 5 | ||
| 6 | /* -------------------------------------------------------------------- */ | |
| 7 | /* typedef */ | |
| 8 | /* -------------------------------------------------------------------- */ | |
| 9 | ||
| 10 | typedef unsigned char byte; | |
| 11 | typedef unsigned short word; | |
| 12 | typedef unsigned int dword; | |
| 13 | ||
| 14 | /* -------------------------------------------------------------------- */ | |
| 15 | /* System Macro definition */ | |
| 16 | /* -------------------------------------------------------------------- */ | |
| 17 | #define IIC_OK 0 | |
| 18 | ||
| 19 | ||
| 20 | #define DEV_SUPPORT_EDID 1 | |
| 21 | /* #define DEV_SUPPORT_HDCP */ | |
| 22 | /* #define DEV_SUPPORT_CEC */ | |
| 23 | /* #define DEV_SUPPORT_3D */ | |
| 24 | ||
| 25 | #define CLOCK_EDGE_RISING | |
| 26 | /* #define CLOCK_EDGE_FALLING */ | |
| 27 | ||
| 28 | #define F_9022A_9334 | |
| 29 | /* #define HW_INT_ENABLE */ | |
| 30 | ||
| 31 | ||
| 32 | ||
| 33 | /* -------------------------------------------------------------------- */ | |
| 34 | /* TPI Firmware Version */ | |
| 35 | /* -------------------------------------------------------------------- */ | |
| 36 | static const char TPI_FW_VERSION[] = "TPI Firmware v6.6.3_APP v1.3"; | |
| 37 | ||
| 38 | /* Generic Constants */ | |
| 39 | /* ==================================================== */ | |
| 40 | /* #define FALSE 0 */ | |
| 41 | /* #define TRUE 1 */ | |
| 42 | ||
| 43 | #define OFF 0 | |
| 44 | #define ON 1 | |
| 45 | ||
| 46 | #define LOW 0 | |
| 47 | #define HIGH 1 | |
| 48 | ||
| 49 | #define DISABLE 0x00 | |
| 50 | #define ENABLE 0xFF | |
| 51 | ||
| 52 | ||
| 53 | #define MAX_V_DESCRIPTORS 20 | |
| 54 | #define MAX_A_DESCRIPTORS 10 | |
| 55 | #define MAX_SPEAKER_CONFIGURATIONS 4 | |
| 56 | #define AUDIO_DESCR_SIZE 3 | |
| 57 | ||
| 58 | #define RGB 0 | |
| 59 | #define YCBCR444 1 | |
| 60 | #define YCBCR422_16BITS 2 | |
| 61 | #define YCBCR422_8BITS 3 | |
| 62 | #define XVYCC444 4 | |
| 63 | ||
| 64 | #define EXTERNAL_HSVSDE 0 | |
| 65 | #define INTERNAL_DE 1 | |
| 66 | #define EMBEDDED_SYNC 2 | |
| 67 | ||
| 68 | #define COLORIMETRY_601 0 | |
| 69 | #define COLORIMETRY_709 1 | |
| 70 | ||
| 71 | /* ==================================================== */ | |
| 72 | #define MCLK128FS 0 | |
| 73 | #define MCLK256FS 1 | |
| 74 | #define MCLK384FS 2 | |
| 75 | #define MCLK512FS 3 | |
| 76 | #define MCLK768FS 4 | |
| 77 | #define MCLK1024FS 5 | |
| 78 | #define MCLK1152FS 6 | |
| 79 | #define MCLK192FS 7 | |
| 80 | ||
| 81 | #define SCK_SAMPLE_FALLING_EDGE 0x00 | |
| 82 | #define SCK_SAMPLE_RISING_EDGE 0x80 | |
| 83 | ||
| 84 | /* ==================================================== */ | |
| 85 | /* Video mode define */ | |
| 86 | #define HDMI_480I60_4X3 1 | |
| 87 | #define HDMI_576I50_4X3 2 | |
| 88 | #define HDMI_480P60_4X3 3 | |
| 89 | #define HDMI_576P50_4X3 4 | |
| 90 | #define HDMI_720P60 5 | |
| 91 | #define HDMI_720P50 6 | |
| 92 | #define HDMI_1080I60 7 | |
| 93 | #define HDMI_1080I50 8 | |
| 94 | #define HDMI_1080P60 9 | |
| 95 | #define HDMI_1080P50 10 | |
| 96 | #define HDMI_1024_768_60 11 | |
| 97 | #define HDMI_800_600_60 12 | |
| 98 | #define HDMI_1080P30 13 | |
| 99 | #define HDMI_1080P24 14 | |
| 100 | ||
| 101 | ||
| 102 | ||
| 103 | ||
| 104 | ||
| 105 | /* ==================================================== */ | |
| 106 | #define AMODE_I2S 0 | |
| 107 | #define AMODE_SPDIF 1 | |
| 108 | #define AMODE_HBR 2 | |
| 109 | #define AMODE_DSD 3 | |
| 110 | ||
| 111 | #define ACHANNEL_2CH 1 | |
| 112 | #define ACHANNEL_3CH 2 | |
| 113 | #define ACHANNEL_4CH 3 | |
| 114 | #define ACHANNEL_5CH 4 | |
| 115 | #define ACHANNEL_6CH 5 | |
| 116 | #define ACHANNEL_7CH 6 | |
| 117 | #define ACHANNEL_8CH 7 | |
| 118 | ||
| 119 | #define AFS_44K1 0x00 | |
| 120 | #define AFS_48K 0x02 | |
| 121 | #define AFS_32K 0x03 | |
| 122 | #define AFS_88K2 0x08 | |
| 123 | #define AFS_768K 0x09 | |
| 124 | #define AFS_96K 0x0a | |
| 125 | #define AFS_176K4 0x0c | |
| 126 | #define AFS_192K 0x0e | |
| 127 | ||
| 128 | #define ALENGTH_16BITS 0x02 | |
| 129 | #define ALENGTH_17BITS 0x0c | |
| 130 | #define ALENGTH_18BITS 0x04 | |
| 131 | #define ALENGTH_19BITS 0x08 | |
| 132 | #define ALENGTH_20BITS 0x0a | |
| 133 | #define ALENGTH_21BITS 0x0d | |
| 134 | #define ALENGTH_22BITS 0x05 | |
| 135 | #define ALENGTH_23BITS 0x09 | |
| 136 | #define ALENGTH_24BITS 0x0b | |
| 137 | ||
| 138 | /* ==================================================== */ | |
| 139 | typedef struct { | |
| 140 | byte HDMIVideoFormat; /* 0 = CEA-861 VIC; 1 = HDMI_VIC; 2 = 3D */ | |
| 141 | byte VIC; /* VIC or the HDMI_VIC */ | |
| 142 | byte AspectRatio; /* 4x3 or 16x9 */ | |
| 143 | byte ColorSpace; /* 0 = RGB; 1 = YCbCr4:4:4; 2 = YCbCr4:2:2_16bits; 3 = YCbCr4:2:2_8bits; 4 = xvYCC4:4:4 */ | |
| 144 | byte ColorDepth; /* 0 = 8bits; 1 = 10bits; 2 = 12bits */ | |
| 145 | byte Colorimetry; /* 0 = 601; 1 = 709 */ | |
| 146 | byte SyncMode; /* 0 = external HS/VS/DE; 1 = external HS/VS and internal DE; 2 = embedded sync */ | |
| 147 | byte TclkSel; /* 0 = x0.5CLK; 1 = x1CLK; 2 = x2CLK; 3 = x4CLK */ | |
| 148 | byte ThreeDStructure; /* Valid when (HDMIVideoFormat == VMD_HDMIFORMAT_3D) */ | |
| 149 | byte ThreeDExtData; /* Valid when (HDMIVideoFormat == VMD_HDMIFORMAT_3D) && (ThreeDStructure == VMD_3D_SIDEBYSIDEHALF) */ | |
| 150 | ||
| 151 | byte AudioMode; /* 0 = I2S; 1 = S/PDIF; 2 = HBR; 3 = DSD; */ | |
| 152 | byte AudioChannels; /* 1 = 2chs; 2 = 3chs; 3 = 4chs; 4 = 5chs; 5 = 6chs; 6 = 7chs; 7 = 8chs; */ | |
| 153 | byte AudioFs; /* 0-44.1kHz; 2-48kHz; 3-32kHz; 8-88.2kHz; 9-768kHz; A-96kHz; C-176.4kHz; E-192kHz; 1/4/5/6/7/B/D/F-not indicated */ | |
| 154 | byte AudioWordLength; /* 0/1-not available; 2-16 bit; 4-18 bit; 8-19 bit; A-20 bit; C-17 bit; 5-22 bit; 9-23 bit; B-24 bit; D-21 bit */ | |
| 155 | byte AudioI2SFormat; /* Please refer to TPI reg0x20 for detailed. */ | |
| 156 | /* [7]_SCK Sample Edge: 0 = Falling; 1 = Rising */ | |
| 157 | /* [6:4]_MCLK Multiplier: 000:MCLK=128Fs; 001:MCLK=256Fs; 010:MCLK=384Fs; 011:MCLK=512Fs; 100:MCLK=768Fs; 101:MCLK=1024Fs; 110:MCLK=1152Fs; 111:MCLK=192Fs; */ | |
| 158 | /* [3]_WS Polarity-Left when: 0 = WS is low when Left; 1 = WS is high when Left */ | |
| 159 | /* [2]_SD Justify Data is justified: 0 = Left; 1 = Right */ | |
| 160 | /* [1]_SD Direction Byte shifted first: 0 = MSB; 1 = LSB */ | |
| 161 | /* [0]_WS to SD First Bit Shift: 0 = Yes; 1 = No */ | |
| 162 | ||
| 163 | } SIHDMITX_CONFIG; | |
| 164 | ||
| 165 | /* ==================================================== */ | |
| 166 | typedef struct { | |
| 167 | byte txPowerState; | |
| 168 | byte tmdsPoweredUp; | |
| 169 | byte hdmiCableConnected; | |
| 170 | byte dsRxPoweredUp; | |
| 171 | ||
| 172 | } GLOBAL_SYSTEM; | |
| 173 | ||
| 174 | /* ==================================================== */ | |
| 175 | typedef struct { | |
| 176 | byte HDCP_TxSupports; | |
| 177 | byte HDCP_AksvValid; | |
| 178 | byte HDCP_Started; | |
| 179 | byte HDCP_LinkProtectionLevel; | |
| 180 | byte HDCP_Override; | |
| 181 | byte HDCPAuthenticated; | |
| 182 | ||
| 183 | } GLOBAL_HDCP; | |
| 184 | ||
| 185 | /* ==================================================== */ | |
| 186 | typedef struct { /* for storing EDID parsed data */ | |
| 187 | byte edidDataValid; | |
| 188 | byte VideoDescriptor[MAX_V_DESCRIPTORS]; /* maximum number of video descriptors */ | |
| 189 | byte AudioDescriptor[MAX_A_DESCRIPTORS][3]; /* maximum number of audio descriptors */ | |
| 190 | byte SpkrAlloc[MAX_SPEAKER_CONFIGURATIONS]; /* maximum number of speaker configurations */ | |
| 191 | byte UnderScan; /* "1" if DTV monitor underscans IT video formats by default */ | |
| 192 | byte BasicAudio; /* Sink supports Basic Audio */ | |
| 193 | byte YCbCr_4_4_4; /* Sink supports YCbCr 4:4:4 */ | |
| 194 | byte YCbCr_4_2_2; /* Sink supports YCbCr 4:2:2 */ | |
| 195 | byte HDMI_Sink; /* "1" if HDMI signature found */ | |
| 196 | byte CEC_A_B; /* CEC Physical address. See HDMI 1.3 Table 8-6 */ | |
| 197 | byte CEC_C_D; | |
| 198 | byte ColorimetrySupportFlags; /* IEC 61966-2-4 colorimetry support: 1 - xvYCC601; 2 - xvYCC709 */ | |
| 199 | byte MetadataProfile; | |
| 200 | byte _3D_Supported; | |
| 201 | byte HDMI_compatible_VSDB; | |
| 202 | } GLOBAL_EDID; | |
| 203 | ||
| 204 | enum EDID_ErrorCodes { | |
| 205 | EDID_OK, | |
| 206 | EDID_INCORRECT_HEADER, | |
| 207 | EDID_CHECKSUM_ERROR, | |
| 208 | EDID_NO_861_EXTENSIONS, | |
| 209 | EDID_SHORT_DESCRIPTORS_OK, | |
| 210 | EDID_LONG_DESCRIPTORS_OK, | |
| 211 | EDID_EXT_TAG_ERROR, | |
| 212 | EDID_REV_ADDR_ERROR, | |
| 213 | EDID_V_DESCR_OVERFLOW, | |
| 214 | EDID_UNKNOWN_TAG_CODE, | |
| 215 | EDID_NO_DETAILED_DESCRIPTORS, | |
| 216 | EDID_DDC_BUS_REQ_FAILURE, | |
| 217 | EDID_DDC_BUS_RELEASE_FAILURE | |
| 218 | }; | |
| 219 | ||
| 220 | ||
| 221 | #ifdef DEV_SUPPORT_EDID | |
| 222 | #define IsHDMI_Sink() (g_edid.HDMI_Sink) | |
| 223 | #define IsCEC_DEVICE() (((g_edid.CEC_A_B != 0xFF) && (g_edid.CEC_C_D != 0xFF)) ? 1 : 0) | |
| 224 | ||
| 225 | #else | |
| 226 | #define IsHDMI_Sink() (1) | |
| 227 | #define IsCEC_DEVICE() (0) | |
| 228 | #endif | |
| 229 | ||
| 230 | ||
| 231 | ||
| 232 | /* -------------------------------------------------------------------- */ | |
| 233 | /* Debug Definitions */ | |
| 234 | /* -------------------------------------------------------------------- */ | |
| 235 | /* Compile debug prints inline or not */ | |
| 236 | #define CONF__TPI_TRACE_PRINT (DISABLE) | |
| 237 | #define CONF__TPI_DEBUG_PRINT (DISABLE) | |
| 238 | #define CONF__TPI_EDID_PRINT (DISABLE) | |
| 239 | #define CONF__CPI_DEBUG_PRINT (DISABLE) | |
| 240 | ||
| 241 | ||
| 242 | /* Trace Print Macro */ | |
| 243 | /* Note: TPI_TRACE_PRINT Requires double parenthesis */ | |
| 244 | /* Example: TPI_TRACE_PRINT(("hello, world!\n")); */ | |
| 245 | #if (CONF__TPI_TRACE_PRINT == ENABLE) | |
| 246 | #define TPI_TRACE_PRINT(x) pr_debug x; | |
| 247 | #else | |
| 248 | #define TPI_TRACE_PRINT(x) | |
| 249 | #endif | |
| 250 | ||
| 251 | /* Debug Print Macro */ | |
| 252 | /* Note: TPI_DEBUG_PRINT Requires double parenthesis */ | |
| 253 | /* Example: TPI_DEBUG_PRINT(("hello, world!\n")); */ | |
| 254 | #if (CONF__TPI_DEBUG_PRINT == ENABLE) | |
| 255 | #define TPI_DEBUG_PRINT(x) pr_debug x; | |
| 256 | #else | |
| 257 | #define TPI_DEBUG_PRINT(x) | |
| 258 | #endif | |
| 259 | ||
| 260 | /* EDID Print Macro */ | |
| 261 | /* Note: To enable EDID description printing, both CONF__TPI_EDID_PRINT and CONF__TPI_DEBUG_PRINT must be enabled */ | |
| 262 | /* Note: TPI_EDID_PRINT Requires double parenthesis */ | |
| 263 | /* Example: TPI_EDID_PRINT(("hello, world!\n")); */ | |
| 264 | #if (CONF__TPI_EDID_PRINT == ENABLE) | |
| 265 | #define TPI_EDID_PRINT(x) TPI_DEBUG_PRINT(x) | |
| 266 | #else | |
| 267 | #define TPI_EDID_PRINT(x) | |
| 268 | #endif | |
| 269 | ||
| 270 | /* CPI Debug Print Macro */ | |
| 271 | /* Note: To enable CPI description printing, both CONF__CPI_DEBUG_PRINT and CONF__TPI_DEBUG_PRINT must be enabled */ | |
| 272 | /* Note: CPI_DEBUG_PRINT Requires double parenthesis */ | |
| 273 | /* Example: CPI_DEBUG_PRINT(("hello, world!\n")); */ | |
| 274 | #if (CONF__CPI_DEBUG_PRINT == ENABLE) | |
| 275 | #define CPI_DEBUG_PRINT(x) TPI_DEBUG_PRINT(x) | |
| 276 | #else | |
| 277 | #define CPI_DEBUG_PRINT(x) | |
| 278 | #endif | |
| 279 | ||
| 280 | ||
| 281 | ||
| 282 | enum AV_ConfigErrorCodes { | |
| 283 | DE_CANNOT_BE_SET_WITH_EMBEDDED_SYNC, | |
| 284 | V_MODE_NOT_SUPPORTED, | |
| 285 | SET_EMBEDDED_SYC_FAILURE, | |
| 286 | I2S_MAPPING_SUCCESSFUL, | |
| 287 | I2S_INPUT_CONFIG_SUCCESSFUL, | |
| 288 | I2S_HEADER_SET_SUCCESSFUL, | |
| 289 | EHDMI_ARC_SINGLE_SET_SUCCESSFUL, | |
| 290 | EHDMI_ARC_COMMON_SET_SUCCESSFUL, | |
| 291 | EHDMI_HEC_SET_SUCCESSFUL, | |
| 292 | EHDMI_ARC_CM_WITH_HEC_SET_SUCCESSFUL, | |
| 293 | AUD_MODE_NOT_SUPPORTED, | |
| 294 | I2S_NOT_SET, | |
| 295 | DE_SET_OK, | |
| 296 | VIDEO_MODE_SET_OK, | |
| 297 | AUDIO_MODE_SET_OK, | |
| 298 | GBD_SET_SUCCESSFULLY, | |
| 299 | DE_CANNOT_BE_SET_WITH_3D_MODE, | |
| 300 | }; | |
| 301 | ||
| 302 | ||
| 303 | #define ClearInterrupt(x) WriteByteTPI(0x3D, x) /* write "1" to clear interrupt bit */ | |
| 304 | ||
| 305 | /* Generic Masks */ | |
| 306 | /* ==================================================== */ | |
| 307 | #define LOW_BYTE 0x00FF | |
| 308 | ||
| 309 | #define LOW_NIBBLE 0x0F | |
| 310 | #define HI_NIBBLE 0xF0 | |
| 311 | ||
| 312 | #define MSBIT 0x80 | |
| 313 | #define LSBIT 0x01 | |
| 314 | ||
| 315 | #define BIT_0 0x01 | |
| 316 | #define BIT_1 0x02 | |
| 317 | #define BIT_2 0x04 | |
| 318 | #define BIT_3 0x08 | |
| 319 | #define BIT_4 0x10 | |
| 320 | #define BIT_5 0x20 | |
| 321 | #define BIT_6 0x40 | |
| 322 | #define BIT_7 0x80 | |
| 323 | ||
| 324 | #define TWO_LSBITS 0x03 | |
| 325 | #define THREE_LSBITS 0x07 | |
| 326 | #define FOUR_LSBITS 0x0F | |
| 327 | #define FIVE_LSBITS 0x1F | |
| 328 | #define SEVEN_LSBITS 0x7F | |
| 329 | #define TWO_MSBITS 0xC0 | |
| 330 | #define EIGHT_BITS 0xFF | |
| 331 | #define BYTE_SIZE 0x08 | |
| 332 | #define BITS_1_0 0x03 | |
| 333 | #define BITS_2_1 0x06 | |
| 334 | #define BITS_2_1_0 0x07 | |
| 335 | #define BITS_3_2 0x0C | |
| 336 | #define BITS_4_3_2 0x1C | |
| 337 | #define BITS_5_4 0x30 | |
| 338 | #define BITS_5_4_3 0x38 | |
| 339 | #define BITS_6_5 0x60 | |
| 340 | #define BITS_6_5_4 0x70 | |
| 341 | #define BITS_7_6 0xC0 | |
| 342 | ||
| 343 | /* Interrupt Masks */ | |
| 344 | /* ==================================================== */ | |
| 345 | #define HOT_PLUG_EVENT 0x01 | |
| 346 | #define RX_SENSE_EVENT 0x02 | |
| 347 | #define HOT_PLUG_STATE 0x04 | |
| 348 | #define RX_SENSE_STATE 0x08 | |
| 349 | ||
| 350 | #define AUDIO_ERROR_EVENT 0x10 | |
| 351 | #define SECURITY_CHANGE_EVENT 0x20 | |
| 352 | #define V_READY_EVENT 0x40 | |
| 353 | #define HDCP_CHANGE_EVENT 0x80 | |
| 354 | ||
| 355 | #define NON_MASKABLE_INT 0xFF | |
| 356 | ||
| 357 | /* TPI Control Masks */ | |
| 358 | /* ==================================================== */ | |
| 359 | ||
| 360 | #define CS_HDMI_RGB 0x00 | |
| 361 | #define CS_DVI_RGB 0x03 | |
| 362 | ||
| 363 | #define ENABLE_AND_REPEAT 0xC0 | |
| 364 | #define EN_AND_RPT_MPEG 0xC3 | |
| 365 | #define DISABLE_MPEG 0x03 /* Also Vendor Specific InfoFrames */ | |
| 366 | ||
| 367 | /* Pixel Repetition Masks */ | |
| 368 | /* ==================================================== */ | |
| 369 | #define BIT_BUS_24 0x20 | |
| 370 | #define BIT_BUS_12 0x00 | |
| 371 | ||
| 372 | #define BIT_EDGE_RISE 0x10 | |
| 373 | ||
| 374 | /* Audio Maps */ | |
| 375 | /* ==================================================== */ | |
| 376 | #define BIT_AUDIO_MUTE 0x10 | |
| 377 | ||
| 378 | /* Input/Output Format Masks */ | |
| 379 | /* ==================================================== */ | |
| 380 | #define BITS_IN_RGB 0x00 | |
| 381 | #define BITS_IN_YCBCR444 0x01 | |
| 382 | #define BITS_IN_YCBCR422 0x02 | |
| 383 | ||
| 384 | #define BITS_IN_AUTO_RANGE 0x00 | |
| 385 | #define BITS_IN_FULL_RANGE 0x04 | |
| 386 | #define BITS_IN_LTD_RANGE 0x08 | |
| 387 | ||
| 388 | #define BIT_EN_DITHER_10_8 0x40 | |
| 389 | #define BIT_EXTENDED_MODE 0x80 | |
| 390 | ||
| 391 | #define BITS_OUT_RGB 0x00 | |
| 392 | #define BITS_OUT_YCBCR444 0x01 | |
| 393 | #define BITS_OUT_YCBCR422 0x02 | |
| 394 | ||
| 395 | #define BITS_OUT_AUTO_RANGE 0x00 | |
| 396 | #define BITS_OUT_FULL_RANGE 0x04 | |
| 397 | #define BITS_OUT_LTD_RANGE 0x08 | |
| 398 | ||
| 399 | #define BIT_BT_709 0x10 | |
| 400 | ||
| 401 | ||
| 402 | /* DE Generator Masks */ | |
| 403 | /* ==================================================== */ | |
| 404 | #define BIT_EN_DE_GEN 0x40 | |
| 405 | #define DE 0x00 | |
| 406 | #define DeDataNumBytes 12 | |
| 407 | ||
| 408 | /* Embedded Sync Masks */ | |
| 409 | /* ==================================================== */ | |
| 410 | #define BIT_EN_SYNC_EXTRACT 0x40 | |
| 411 | #define EMB 0x80 | |
| 412 | #define EmbDataNumBytes 8 | |
| 413 | ||
| 414 | ||
| 415 | /* Audio Modes */ | |
| 416 | /* ==================================================== */ | |
| 417 | #define AUD_PASS_BASIC 0x00 | |
| 418 | #define AUD_PASS_ALL 0x01 | |
| 419 | #define AUD_DOWN_SAMPLE 0x02 | |
| 420 | #define AUD_DO_NOT_CHECK 0x03 | |
| 421 | ||
| 422 | #define REFER_TO_STREAM_HDR 0x00 | |
| 423 | #define TWO_CHANNELS 0x00 | |
| 424 | #define EIGHT_CHANNELS 0x01 | |
| 425 | #define AUD_IF_SPDIF 0x40 | |
| 426 | #define AUD_IF_I2S 0x80 | |
| 427 | #define AUD_IF_DSD 0xC0 | |
| 428 | #define AUD_IF_HBR 0x04 | |
| 429 | ||
| 430 | #define TWO_CHANNEL_LAYOUT 0x00 | |
| 431 | #define EIGHT_CHANNEL_LAYOUT 0x20 | |
| 432 | ||
| 433 | ||
| 434 | /* I2C Slave Addresses */ | |
| 435 | /* ==================================================== */ | |
| 436 | #define TX_SLAVE_ADDR 0x72 | |
| 437 | #define CBUS_SLAVE_ADDR 0xC8 | |
| 438 | #define HDCP_SLAVE_ADDR 0x74 | |
| 439 | #define EDID_ROM_ADDR 0xA0 | |
| 440 | #define EDID_SEG_ADDR 0x60 | |
| 441 | ||
| 442 | /* Indexed Register Offsets, Constants */ | |
| 443 | /* ==================================================== */ | |
| 444 | #define INDEXED_PAGE_0 0x01 | |
| 445 | #define INDEXED_PAGE_1 0x02 | |
| 446 | #define INDEXED_PAGE_2 0x03 | |
| 447 | ||
| 448 | /* DDC Bus Addresses */ | |
| 449 | /* ==================================================== */ | |
| 450 | #define DDC_BSTATUS_ADDR_L 0x41 | |
| 451 | #define DDC_BSTATUS_ADDR_H 0x42 | |
| 452 | #define DDC_KSV_FIFO_ADDR 0x43 | |
| 453 | #define KSV_ARRAY_SIZE 128 | |
| 454 | ||
| 455 | /* DDC Bus Bit Masks */ | |
| 456 | /* ==================================================== */ | |
| 457 | #define BIT_DDC_HDMI 0x80 | |
| 458 | #define BIT_DDC_REPEATER 0x40 | |
| 459 | #define BIT_DDC_FIFO_RDY 0x20 | |
| 460 | #define DEVICE_COUNT_MASK 0x7F | |
| 461 | ||
| 462 | /* KSV Buffer Size */ | |
| 463 | /* ==================================================== */ | |
| 464 | #define DEVICE_COUNT 128 /* May be tweaked as needed */ | |
| 465 | ||
| 466 | /* InfoFrames */ | |
| 467 | /* ==================================================== */ | |
| 468 | #define SIZE_AVI_INFOFRAME 0x0E /* including checksum byte */ | |
| 469 | #define BITS_OUT_FORMAT 0x60 /* Y1Y0 field */ | |
| 470 | ||
| 471 | #define _4_To_3 0x10 /* Aspect ratio - 4:3 in InfoFrame DByte 1 */ | |
| 472 | #define _16_To_9 0x20 /* Aspect ratio - 16:9 in InfoFrame DByte 1 */ | |
| 473 | #define SAME_AS_AR 0x08 /* R3R2R1R0 - in AVI InfoFrame DByte 2 */ | |
| 474 | ||
| 475 | #define BT_601 0x40 | |
| 476 | #define BT_709 0x80 | |
| 477 | ||
| 478 | /* #define EN_AUDIO_INFOFRAMES 0xC2 */ | |
| 479 | #define TYPE_AUDIO_INFOFRAMES 0x84 | |
| 480 | #define AUDIO_INFOFRAMES_VERSION 0x01 | |
| 481 | #define AUDIO_INFOFRAMES_LENGTH 0x0A | |
| 482 | ||
| 483 | #define TYPE_GBD_INFOFRAME 0x0A | |
| 484 | ||
| 485 | #define ENABLE_AND_REPEAT 0xC0 | |
| 486 | ||
| 487 | #define EN_AND_RPT_MPEG 0xC3 | |
| 488 | #define DISABLE_MPEG 0x03 /* Also Vendor Specific InfoFrames */ | |
| 489 | ||
| 490 | #define EN_AND_RPT_AUDIO 0xC2 | |
| 491 | #define DISABLE_AUDIO 0x02 | |
| 492 | ||
| 493 | #define EN_AND_RPT_AVI 0xC0 /* Not normally used. Write to TPI 0x19 instead */ | |
| 494 | #define DISABLE_AVI 0x00 /* But this is used to Disable */ | |
| 495 | ||
| 496 | #define NEXT_FIELD 0x80 | |
| 497 | #define GBD_PROFILE 0x00 | |
| 498 | #define AFFECTED_GAMUT_SEQ_NUM 0x01 | |
| 499 | ||
| 500 | #define ONLY_PACKET 0x30 | |
| 501 | #define CURRENT_GAMUT_SEQ_NUM 0x01 | |
| 502 | ||
| 503 | /* FPLL Multipliers: */ | |
| 504 | /* ==================================================== */ | |
| 505 | ||
| 506 | #define X0d5 0x00 | |
| 507 | #define X1 0x01 | |
| 508 | #define X2 0x02 | |
| 509 | #define X4 0x03 | |
| 510 | ||
| 511 | /* 3D Constants */ | |
| 512 | /* ==================================================== */ | |
| 513 | ||
| 514 | #define _3D_STRUC_PRESENT 0x02 | |
| 515 | ||
| 516 | /* 3D_Stucture Constants */ | |
| 517 | /* ==================================================== */ | |
| 518 | #define FRAME_PACKING 0x00 | |
| 519 | #define FIELD_ALTERNATIVE 0x01 | |
| 520 | #define LINE_ALTERNATIVE 0x02 | |
| 521 | #define SIDE_BY_SIDE_FULL 0x03 | |
| 522 | #define L_PLUS_DEPTH 0x04 | |
| 523 | #define L_PLUS_DEPTH_PLUS_GRAPHICS 0x05 | |
| 524 | #define SIDE_BY_SIDE_HALF 0x08 | |
| 525 | ||
| 526 | /* 3D_Ext_Data Constants */ | |
| 527 | /* ==================================================== */ | |
| 528 | #define HORIZ_ODD_LEFT_ODD_RIGHT 0x00 | |
| 529 | #define HORIZ_ODD_LEFT_EVEN_RIGHT 0x01 | |
| 530 | #define HORIZ_EVEN_LEFT_ODD_RIGHT 0x02 | |
| 531 | #define HORIZ_EVEN_LEFT_EVEN_RIGHT 0x03 | |
| 532 | ||
| 533 | #define QUINCUNX_ODD_LEFT_EVEN_RIGHT 0x04 | |
| 534 | #define QUINCUNX_ODD_LEFT_ODD_RIGHT 0x05 | |
| 535 | #define QUINCUNX_EVEN_LEFT_ODD_RIGHT 0x06 | |
| 536 | #define QUINCUNX_EVEN_LEFT_EVEN_RIGHT 0x07 | |
| 537 | ||
| 538 | #define NO_3D_SUPPORT 0x0F | |
| 539 | ||
| 540 | /* InfoFrame Type Code */ | |
| 541 | /* ==================================================== */ | |
| 542 | #define AVI 0x00 | |
| 543 | #define SPD 0x01 | |
| 544 | #define AUDIO 0x02 | |
| 545 | #define MPEG 0x03 | |
| 546 | #define GEN_1 0x04 | |
| 547 | #define GEN_2 0x05 | |
| 548 | #define HDMI_VISF 0x06 | |
| 549 | #define GBD 0x07 | |
| 550 | ||
| 551 | /* Size of InfoFrame Data types */ | |
| 552 | #define MAX_SIZE_INFOFRAME_DATA 0x22 | |
| 553 | #define SIZE_AVI_INFOFRAME 0x0E /* 14 bytes */ | |
| 554 | #define SIZE_SPD_INFOFRAME 0x19 /* 25 bytes */ | |
| 555 | #define SISE_AUDIO_INFOFRAME_IFORM 0x0A /* 10 bytes */ | |
| 556 | #define SIZE_AUDIO_INFOFRAME 0x0F /* 15 bytes */ | |
| 557 | #define SIZE_MPRG_HDMI_INFOFRAME 0x1B /* 27 bytes */ | |
| 558 | #define SIZE_MPEG_INFOFRAME 0x0A /* 10 bytes */ | |
| 559 | #define SIZE_GEN_1_INFOFRAME 0x1F /* 31 bytes */ | |
| 560 | #define SIZE_GEN_2_INFOFRAME 0x1F /* 31 bytes */ | |
| 561 | #define SIZE_HDMI_VISF_INFOFRAME 0x1E /* 31 bytes */ | |
| 562 | #define SIZE_GBD_INFOFRAME 0x1C /* 28 bytes */ | |
| 563 | ||
| 564 | #define AVI_INFOFRM_OFFSET 0x0C | |
| 565 | #define OTHER_INFOFRM_OFFSET 0xC4 | |
| 566 | #define TPI_INFOFRAME_ACCESS_REG 0xBF | |
| 567 | ||
| 568 | /* Serial Communication Buffer constants */ | |
| 569 | #define MAX_COMMAND_ARGUMENTS 50 | |
| 570 | #define GLOBAL_BYTE_BUF_BLOCK_SIZE 131 | |
| 571 | ||
| 572 | ||
| 573 | /* Video Mode Constants */ | |
| 574 | /* ==================================================== */ | |
| 575 | #define VMD_ASPECT_RATIO_4x3 0x01 | |
| 576 | #define VMD_ASPECT_RATIO_16x9 0x02 | |
| 577 | ||
| 578 | #define VMD_COLOR_SPACE_RGB 0x00 | |
| 579 | #define VMD_COLOR_SPACE_YCBCR422 0x01 | |
| 580 | #define VMD_COLOR_SPACE_YCBCR444 0x02 | |
| 581 | ||
| 582 | #define VMD_COLOR_DEPTH_8BIT 0x00 | |
| 583 | #define VMD_COLOR_DEPTH_10BIT 0x01 | |
| 584 | #define VMD_COLOR_DEPTH_12BIT 0x02 | |
| 585 | #define VMD_COLOR_DEPTH_16BIT 0x03 | |
| 586 | ||
| 587 | #define VMD_HDCP_NOT_AUTHENTICATED 0x00 | |
| 588 | #define VMD_HDCP_AUTHENTICATED 0x01 | |
| 589 | ||
| 590 | #define VMD_HDMIFORMAT_CEA_VIC 0x00 | |
| 591 | #define VMD_HDMIFORMAT_HDMI_VIC 0x01 | |
| 592 | #define VMD_HDMIFORMAT_3D 0x02 | |
| 593 | #define VMD_HDMIFORMAT_PC 0x03 | |
| 594 | ||
| 595 | /* These values are from HDMI Spec 1.4 Table H-2 */ | |
| 596 | #define VMD_3D_FRAMEPACKING 0 | |
| 597 | #define VMD_3D_FIELDALTERNATIVE 1 | |
| 598 | #define VMD_3D_LINEALTERNATIVE 2 | |
| 599 | #define VMD_3D_SIDEBYSIDEFULL 3 | |
| 600 | #define VMD_3D_LDEPTH 4 | |
| 601 | #define VMD_3D_LDEPTHGRAPHICS 5 | |
| 602 | #define VMD_3D_SIDEBYSIDEHALF 8 | |
| 603 | ||
| 604 | ||
| 605 | /* -------------------------------------------------------------------- */ | |
| 606 | /* System Macro Definitions */ | |
| 607 | /* -------------------------------------------------------------------- */ | |
| 608 | #define TX_HW_RESET_PERIOD 200 | |
| 609 | #define SII902XA_DEVICE_ID 0xB0 | |
| 610 | ||
| 611 | #define T_HPD_DELAY 10 | |
| 612 | ||
| 613 | /* -------------------------------------------------------------------- */ | |
| 614 | /* HDCP Macro Definitions */ | |
| 615 | /* -------------------------------------------------------------------- */ | |
| 616 | #define AKSV_SIZE 5 | |
| 617 | #define NUM_OF_ONES_IN_KSV 20 | |
| 618 | ||
| 619 | /* -------------------------------------------------------------------- */ | |
| 620 | /* EDID Constants Definition */ | |
| 621 | /* -------------------------------------------------------------------- */ | |
| 622 | #define EDID_BLOCK_0_OFFSET 0x00 | |
| 623 | #define EDID_BLOCK_1_OFFSET 0x80 | |
| 624 | ||
| 625 | #define EDID_BLOCK_SIZE 128 | |
| 626 | #define EDID_HDR_NO_OF_FF 0x06 | |
| 627 | #define NUM_OF_EXTEN_ADDR 0x7E | |
| 628 | ||
| 629 | #define EDID_TAG_ADDR 0x00 | |
| 630 | #define EDID_REV_ADDR 0x01 | |
| 631 | #define EDID_TAG_IDX 0x02 | |
| 632 | #define LONG_DESCR_PTR_IDX 0x02 | |
| 633 | #define MISC_SUPPORT_IDX 0x03 | |
| 634 | ||
| 635 | #define ESTABLISHED_TIMING_INDEX 35 /* Offset of Established Timing in EDID block */ | |
| 636 | #define NUM_OF_STANDARD_TIMINGS 8 | |
| 637 | #define STANDARD_TIMING_OFFSET 38 | |
| 638 | #define LONG_DESCR_LEN 18 | |
| 639 | #define NUM_OF_DETAILED_DESCRIPTORS 4 | |
| 640 | ||
| 641 | #define DETAILED_TIMING_OFFSET 0x36 | |
| 642 | ||
| 643 | /* Offsets within a Long Descriptors Block */ | |
| 644 | /* ==================================================== */ | |
| 645 | #define PIX_CLK_OFFSET 0 | |
| 646 | #define H_ACTIVE_OFFSET 2 | |
| 647 | #define H_BLANKING_OFFSET 3 | |
| 648 | #define V_ACTIVE_OFFSET 5 | |
| 649 | #define V_BLANKING_OFFSET 6 | |
| 650 | #define H_SYNC_OFFSET 8 | |
| 651 | #define H_SYNC_PW_OFFSET 9 | |
| 652 | #define V_SYNC_OFFSET 10 | |
| 653 | #define V_SYNC_PW_OFFSET 10 | |
| 654 | #define H_IMAGE_SIZE_OFFSET 12 | |
| 655 | #define V_IMAGE_SIZE_OFFSET 13 | |
| 656 | #define H_BORDER_OFFSET 15 | |
| 657 | #define V_BORDER_OFFSET 16 | |
| 658 | #define FLAGS_OFFSET 17 | |
| 659 | ||
| 660 | #define AR16_10 0 | |
| 661 | #define AR4_3 1 | |
| 662 | #define AR5_4 2 | |
| 663 | #define AR16_9 3 | |
| 664 | ||
| 665 | /* Data Block Tag Codes */ | |
| 666 | /* ==================================================== */ | |
| 667 | #define AUDIO_D_BLOCK 0x01 | |
| 668 | #define VIDEO_D_BLOCK 0x02 | |
| 669 | #define VENDOR_SPEC_D_BLOCK 0x03 | |
| 670 | #define SPKR_ALLOC_D_BLOCK 0x04 | |
| 671 | #define USE_EXTENDED_TAG 0x07 | |
| 672 | ||
| 673 | /* Extended Data Block Tag Codes */ | |
| 674 | /* ==================================================== */ | |
| 675 | #define COLORIMETRY_D_BLOCK 0x05 | |
| 676 | ||
| 677 | #define HDMI_SIGNATURE_LEN 0x03 | |
| 678 | ||
| 679 | #define CEC_PHYS_ADDR_LEN 0x02 | |
| 680 | #define EDID_EXTENSION_TAG 0x02 | |
| 681 | #define EDID_REV_THREE 0x03 | |
| 682 | #define EDID_DATA_START 0x04 | |
| 683 | ||
| 684 | #define EDID_BLOCK_0 0x00 | |
| 685 | #define EDID_BLOCK_2_3 0x01 | |
| 686 | ||
| 687 | #define VIDEO_CAPABILITY_D_BLOCK 0x00 | |
| 688 | ||
| 689 | ||
| 690 | ||
| 691 | ||
| 692 | ||
| 693 | /* -------------------------------------------------------------------- */ | |
| 694 | /* TPI Register Definition */ | |
| 695 | /* -------------------------------------------------------------------- */ | |
| 696 | ||
| 697 | ||
| 698 | /* TPI AVI Input and Output Format Data */ | |
| 699 | /* / AVI Input Format Data */ | |
| 700 | #define INPUT_COLOR_SPACE_MASK (BIT_1 | BIT_0) | |
| 701 | #define INPUT_COLOR_SPACE_RGB (0x00) | |
| 702 | #define INPUT_COLOR_SPACE_YCBCR444 (0x01) | |
| 703 | #define INPUT_COLOR_SPACE_YCBCR422 (0x02) | |
| 704 | #define INPUT_COLOR_SPACE_BLACK_MODE (0x03) | |
| 705 | ||
| 706 | ||
| 707 | #define LINK_INTEGRITY_MODE_MASK (BIT_6) | |
| 708 | #define LINK_INTEGRITY_STATIC (0x00) | |
| 709 | #define LINK_INTEGRITY_DYNAMIC (0x40) | |
| 710 | ||
| 711 | #define TMDS_OUTPUT_CONTROL_MASK (BIT_4) | |
| 712 | #define TMDS_OUTPUT_CONTROL_ACTIVE (0x00) | |
| 713 | #define TMDS_OUTPUT_CONTROL_POWER_DOWN (0x10) | |
| 714 | ||
| 715 | #define AV_MUTE_MASK (BIT_3) | |
| 716 | #define AV_MUTE_NORMAL (0x00) | |
| 717 | #define AV_MUTE_MUTED (0x08) | |
| 718 | ||
| 719 | #define DDC_BUS_REQUEST_MASK (BIT_2) | |
| 720 | #define DDC_BUS_REQUEST_NOT_USING (0x00) | |
| 721 | #define DDC_BUS_REQUEST_REQUESTED (0x04) | |
| 722 | ||
| 723 | #define DDC_BUS_GRANT_MASK (BIT_1) | |
| 724 | #define DDC_BUS_GRANT_NOT_AVAILABLE (0x00) | |
| 725 | #define DDC_BUS_GRANT_GRANTED (0x02) | |
| 726 | ||
| 727 | #define OUTPUT_MODE_MASK (BIT_0) | |
| 728 | #define OUTPUT_MODE_DVI (0x00) | |
| 729 | #define OUTPUT_MODE_HDMI (0x01) | |
| 730 | ||
| 731 | #define CTRL_PIN_CONTROL_MASK (BIT_4) | |
| 732 | #define CTRL_PIN_TRISTATE (0x00) | |
| 733 | #define CTRL_PIN_DRIVEN_TX_BRIDGE (0x10) | |
| 734 | ||
| 735 | #define TX_POWER_STATE_MASK (BIT_1 | BIT_0) | |
| 736 | #define TX_POWER_STATE_D0 (0x00) | |
| 737 | #define TX_POWER_STATE_D1 (0x01) | |
| 738 | #define TX_POWER_STATE_D2 (0x02) | |
| 739 | #define TX_POWER_STATE_D3 (0x03) | |
| 740 | ||
| 741 | /* Configuration of I2S Interface */ | |
| 742 | #define SCK_SAMPLE_EDGE (BIT_7) | |
| 743 | ||
| 744 | ||
| 745 | #define AUDIO_MUTE_MASK (BIT_4) | |
| 746 | #define AUDIO_MUTE_NORMAL (0x00) | |
| 747 | #define AUDIO_MUTE_MUTED (0x10) | |
| 748 | ||
| 749 | #define AUDIO_SEL_MASK (BITS_7_6) | |
| 750 | ||
| 751 | /* -------------------------------------------------------------------- */ | |
| 752 | /* HDCP Implementation */ | |
| 753 | /* HDCP link security logic is implemented in certain transmitters; unique */ | |
| 754 | /* keys are embedded in each chip as part of the solution. The security */ | |
| 755 | /* scheme is fully automatic and handled completely by the hardware. */ | |
| 756 | /* -------------------------------------------------------------------- */ | |
| 757 | ||
| 758 | /* / HDCP Query Data Register */ | |
| 759 | #define EXTENDED_LINK_PROTECTION_MASK (BIT_7) | |
| 760 | #define EXTENDED_LINK_PROTECTION_NONE (0x00) | |
| 761 | #define EXTENDED_LINK_PROTECTION_SECURE (0x80) | |
| 762 | ||
| 763 | #define LOCAL_LINK_PROTECTION_MASK (BIT_6) | |
| 764 | #define LOCAL_LINK_PROTECTION_NONE (0x00) | |
| 765 | #define LOCAL_LINK_PROTECTION_SECURE (0x40) | |
| 766 | ||
| 767 | #define LINK_STATUS_MASK (BIT_5 | BIT_4) | |
| 768 | #define LINK_STATUS_NORMAL (0x00) | |
| 769 | #define LINK_STATUS_LINK_LOST (0x10) | |
| 770 | #define LINK_STATUS_RENEGOTIATION_REQ (0x20) | |
| 771 | #define LINK_STATUS_LINK_SUSPENDED (0x30) | |
| 772 | ||
| 773 | #define HDCP_REPEATER_MASK (BIT_3) | |
| 774 | #define HDCP_REPEATER_NO (0x00) | |
| 775 | #define HDCP_REPEATER_YES (0x08) | |
| 776 | ||
| 777 | #define CONNECTOR_TYPE_MASK (BIT_2 | BIT_0) | |
| 778 | #define CONNECTOR_TYPE_DVI (0x00) | |
| 779 | #define CONNECTOR_TYPE_RSVD (0x01) | |
| 780 | #define CONNECTOR_TYPE_HDMI (0x04) | |
| 781 | #define CONNECTOR_TYPE_FUTURE (0x05) | |
| 782 | ||
| 783 | #define PROTECTION_TYPE_MASK (BIT_1) | |
| 784 | #define PROTECTION_TYPE_NONE (0x00) | |
| 785 | #define PROTECTION_TYPE_HDCP (0x02) | |
| 786 | ||
| 787 | #define PROTECTION_LEVEL_MASK (BIT_0) | |
| 788 | #define PROTECTION_LEVEL_MIN (0x00) | |
| 789 | #define PROTECTION_LEVEL_MAX (0x01) | |
| 790 | ||
| 791 | #define KSV_FORWARD_MASK (BIT_4) | |
| 792 | #define KSV_FORWARD_ENABLE (0x10) | |
| 793 | #define KSV_FORWARD_DISABLE (0x00) | |
| 794 | ||
| 795 | ||
| 796 | /* / HDCP Revision Data Register */ | |
| 797 | #define HDCP_MAJOR_REVISION_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4) | |
| 798 | #define HDCP_MAJOR_REVISION_VALUE (0x10) | |
| 799 | ||
| 800 | #define HDCP_MINOR_REVISION_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) | |
| 801 | #define HDCP_MINOR_REVISION_VALUE (0x02) | |
| 802 | ||
| 803 | ||
| 804 | #define HDCP_AUTH_STATUS_CHANGE_EN_MASK (BIT_7) | |
| 805 | #define HDCP_AUTH_STATUS_CHANGE_DISABLE (0x00) | |
| 806 | #define HDCP_AUTH_STATUS_CHANGE_ENABLE (0x80) | |
| 807 | ||
| 808 | #define HDCP_VPRIME_VALUE_READY_EN_MASK (BIT_6) | |
| 809 | #define HDCP_VPRIME_VALUE_READY_DISABLE (0x00) | |
| 810 | #define HDCP_VPRIME_VALUE_READY_ENABLE (0x40) | |
| 811 | ||
| 812 | #define HDCP_SECURITY_CHANGE_EN_MASK (BIT_5) | |
| 813 | #define HDCP_SECURITY_CHANGE_DISABLE (0x00) | |
| 814 | #define HDCP_SECURITY_CHANGE_ENABLE (0x20) | |
| 815 | ||
| 816 | #define AUDIO_ERROR_EVENT_EN_MASK (BIT_4) | |
| 817 | #define AUDIO_ERROR_EVENT_DISABLE (0x00) | |
| 818 | #define AUDIO_ERROR_EVENT_ENABLE (0x10) | |
| 819 | ||
| 820 | #define CPI_EVENT_NO_RX_SENSE_MASK (BIT_3) | |
| 821 | #define CPI_EVENT_NO_RX_SENSE_DISABLE (0x00) | |
| 822 | #define CPI_EVENT_NO_RX_SENSE_ENABLE (0x08) | |
| 823 | ||
| 824 | #define RECEIVER_SENSE_EVENT_EN_MASK (BIT_1) | |
| 825 | #define RECEIVER_SENSE_EVENT_DISABLE (0x00) | |
| 826 | #define RECEIVER_SENSE_EVENT_ENABLE (0x02) | |
| 827 | ||
| 828 | #define HOT_PLUG_EVENT_EN_MASK (BIT_0) | |
| 829 | #define HOT_PLUG_EVENT_DISABLE (0x00) | |
| 830 | #define HOT_PLUG_EVENT_ENABLE (0x01) | |
| 831 | ||
| 832 | #define HDCP_AUTH_STATUS_CHANGE_EVENT_MASK (BIT_7) | |
| 833 | #define HDCP_AUTH_STATUS_CHANGE_EVENT_NO (0x00) | |
| 834 | #define HDCP_AUTH_STATUS_CHANGE_EVENT_YES (0x80) | |
| 835 | ||
| 836 | #define HDCP_VPRIME_VALUE_READY_EVENT_MASK (BIT_6) | |
| 837 | #define HDCP_VPRIME_VALUE_READY_EVENT_NO (0x00) | |
| 838 | #define HDCP_VPRIME_VALUE_READY_EVENT_YES (0x40) | |
| 839 | ||
| 840 | #define HDCP_SECURITY_CHANGE_EVENT_MASK (BIT_5) | |
| 841 | #define HDCP_SECURITY_CHANGE_EVENT_NO (0x00) | |
| 842 | #define HDCP_SECURITY_CHANGE_EVENT_YES (0x20) | |
| 843 | ||
| 844 | #define AUDIO_ERROR_EVENT_MASK (BIT_4) | |
| 845 | #define AUDIO_ERROR_EVENT_NO (0x00) | |
| 846 | #define AUDIO_ERROR_EVENT_YES (0x10) | |
| 847 | ||
| 848 | #define CPI_EVENT_MASK (BIT_3) | |
| 849 | #define CPI_EVENT_NO (0x00) | |
| 850 | #define CPI_EVENT_YES (0x08) | |
| 851 | #define RX_SENSE_MASK (BIT_3) /* This bit is dual purpose depending on the value of 0x3C[3] */ | |
| 852 | #define RX_SENSE_NOT_ATTACHED (0x00) | |
| 853 | #define RX_SENSE_ATTACHED (0x08) | |
| 854 | ||
| 855 | #define HOT_PLUG_PIN_STATE_MASK (BIT_2) | |
| 856 | #define HOT_PLUG_PIN_STATE_LOW (0x00) | |
| 857 | #define HOT_PLUG_PIN_STATE_HIGH (0x04) | |
| 858 | ||
| 859 | #define RECEIVER_SENSE_EVENT_MASK (BIT_1) | |
| 860 | #define RECEIVER_SENSE_EVENT_NO (0x00) | |
| 861 | #define RECEIVER_SENSE_EVENT_YES (0x02) | |
| 862 | ||
| 863 | #define HOT_PLUG_EVENT_MASK (BIT_0) | |
| 864 | #define HOT_PLUG_EVENT_NO (0x00) | |
| 865 | #define HOT_PLUG_EVENT_YES (0x01) | |
| 866 | ||
| 867 | ||
| 868 | ||
| 869 | #define KSV_FIFO_READY_MASK (BIT_1) | |
| 870 | #define KSV_FIFO_READY_NO (0x00) | |
| 871 | #define KSV_FIFO_READY_YES (0x02) | |
| 872 | ||
| 873 | ||
| 874 | #define KSV_FIFO_READY_EN_MASK (BIT_1) | |
| 875 | #define KSV_FIFO_READY_DISABLE (0x00) | |
| 876 | #define KSV_FIFO_READY_ENABLE (0x02) | |
| 877 | ||
| 878 | ||
| 879 | #define KSV_FIFO_LAST_MASK (BIT_7) | |
| 880 | #define KSV_FIFO_LAST_NO (0x00) | |
| 881 | #define KSV_FIFO_LAST_YES (0x80) | |
| 882 | ||
| 883 | #define KSV_FIFO_COUNT_MASK (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0) | |
| 884 | ||
| 885 | ||
| 886 | /* H/W Optimization Control Register #3 Set */ | |
| 887 | #define DDC_DELAY_BIT9_MASK (BIT_7) | |
| 888 | #define DDC_DELAY_BIT9_NO (0x00) | |
| 889 | #define DDC_DELAY_BIT9_YES (0x80) | |
| 890 | #define RI_CHECK_SKIP_MASK (BIT_3) | |
| 891 | #define RI_CHECK_SKIP_NO (0x00) | |
| 892 | #define RI_CHECK_SKIP_YES (0x08) | |
| 893 | ||
| 894 | /* Misc InfoFrames */ | |
| 895 | #define MISC_INFO_FRAMES_CTRL (0xBF) | |
| 896 | #define MISC_INFO_FRAMES_TYPE (0xC0) | |
| 897 | #define MISC_INFO_FRAMES_VER (0xC1) | |
| 898 | #define MISC_INFO_FRAMES_LEN (0xC2) | |
| 899 | #define MISC_INFO_FRAMES_CHKSUM (0xC3) | |
| 900 | /* -------------------------------------------------------------------- */ | |
| 901 | void DelayMS(word MS); | |
| 902 | ||
| 903 | byte I2CReadBlock(struct i2c_client *client, byte RegAddr, byte NBytes, byte *Data); | |
| 904 | byte I2CWriteBlock(struct i2c_client *client, byte RegAddr, byte NBytes, byte *Data); | |
| 905 | byte siiReadSegmentBlockEDID(struct i2c_client *client, byte Segment, byte Offset, byte *Buffer, | |
| 906 | byte Length); | |
| 907 | ||
| 908 | void WriteByteTPI(byte RegOffset, byte Data); | |
| 909 | byte ReadByteTPI(byte RegOffset); | |
| 910 | void siHdmiTx_PowerStateD2(void); | |
| 911 | void siHdmiTx_PowerStateD0fromD2(void); | |
| 912 | void siHdmiTx_PowerStateD3(void); | |
| 913 | void siHdmiTx_Init(void); | |
| 914 | byte siHdmiTx_VideoSet(void); | |
| 915 | byte siHdmiTx_AudioSet(void); | |
| 916 | byte siHdmiTx_TPI_Init(void); | |
| 917 | void siHdmiTx_TPI_Poll(void); | |
| 918 | void siHdmiTx_VideoSel(byte vmode); | |
| 919 | void siHdmiTx_AudioSel(byte Afs); | |
| 920 | #endif |