[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gpio / mt8127 / mt_gpio_base.c

/******************************************************************************
 * mt_gpio_base.c - MTKLinux GPIO Device Driver
 * 
 * Copyright 2008-2009 MediaTek Co.,Ltd.
 * 
 * DESCRIPTION:
 *     This file provid the other drivers GPIO relative functions
 *
 ******************************************************************************/

#include <mach/sync_write.h>
#include <mach/mt_reg_base.h>
#include <mach/mt_typedefs.h>
#include <mach/mt_gpio.h>
#include <mach/mt_gpio_core.h>
#include <mach/mt_gpio_base.h>
#include <cust_gpio_usage.h>

/*-------for special kpad pupd-----------*/
struct kpad_pupd {
	unsigned char 	pin;
	unsigned char	reg;
	unsigned char	bit;
};
static struct kpad_pupd kpad_pupd_spec[] = {
	{GPIO33,	0,	2},
	{GPIO34,	0,	6},
	{GPIO35,	0,	10},
	{GPIO36,	1,	2},
	{GPIO37,	1,	6},
	{GPIO38,	1,	10}
};
/*-------for msdc pupd-----------*/
struct msdc_pupd {
	unsigned char 	pin;
	unsigned char	reg;
	unsigned char	bit;
};
static struct msdc_pupd msdc_pupd_spec[2][6] = {
	{
	{GPIO121,	1,	8},
	{GPIO122,	0,	8},
	{GPIO123,	3,	0},
	{GPIO124,	3,	4},
	{GPIO125,	3,	8},
	{GPIO126,	3,	12}},
	{
	{GPIO85,	1,	8},
	{GPIO86,	0,	8},
	{GPIO87,	3,	0},
	{GPIO88,	3,	4},
	{GPIO89,	3,	8},
	{GPIO90,	3,	12}}
};
/*-------for eint14~eint17 eint21 pupd-----------*/
struct eint_pupd {
	unsigned char 	pin;
	unsigned char	reg;
	unsigned char	bit;
};
static struct eint_pupd eint_pupd_spec[] = {
	{GPIO46,	0,	2},
	{GPIO47,	0,	6},
	{GPIO48,	0,	10},
	{GPIO49,	0,	14},
	{GPIO142,	1,	2}
};

/*---------------------------------------*/
static GPIO_REGS *gpio_reg = (GPIO_REGS*)(GPIO_BASE);
/*---------------------------------------------------------------------------*/
int mt_set_gpio_dir_base(unsigned long pin, unsigned long dir)
{
    unsigned long pos;
    unsigned long bit;
    GPIO_REGS *reg = gpio_reg;

    if ((dir == GPIO_DIR_OUT) &&
    			((pin >= GPIO75 && pin <= GPIO78)||(pin >= GPIO57 && pin <= GPIO58)
    			||(pin >= GPIO138 &&pin <= GPIO141))){
    		return -ERINVAL;
    }
    pos = pin / MAX_GPIO_REG_BITS;
    bit = pin % MAX_GPIO_REG_BITS;
    
    if (dir == GPIO_DIR_IN)
        GPIO_SET_BITS((1L << bit), &reg->dir[pos].rst);
    else
        GPIO_SET_BITS((1L << bit), &reg->dir[pos].set);
    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_dir_base(unsigned long pin)
{    
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    GPIO_REGS *reg = gpio_reg;

    pos = pin / MAX_GPIO_REG_BITS;
    bit = pin % MAX_GPIO_REG_BITS;
    
    data = GPIO_RD32(&reg->dir[pos].val);
    return (((data & (1L << bit)) != 0)? 1: 0);        
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_pull_enable_base(unsigned long pin, unsigned long enable)
{
    unsigned long pos;
    unsigned long bit;
	unsigned long i,j;
    GPIO_REGS *reg = gpio_reg;

	/*for special kpad pupd*/
	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
		if (pin == kpad_pupd_spec[i].pin){
			if (enable == GPIO_PULL_DISABLE){
				GPIO_SET_BITS((3L << (kpad_pupd_spec[i].bit-2)), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].rst);
			} else {
				GPIO_SET_BITS((1L << (kpad_pupd_spec[i].bit-2)), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].set);
			}
			return RSUCCESS;
		}
	}

	/*for special eint pupd*/
	if(((pin >= GPIO46) && (pin <= GPIO49)) || (pin == GPIO142)) {
		for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
			if (pin == eint_pupd_spec[i].pin){
				if (enable == GPIO_PULL_ENABLE)
					GPIO_SET_BITS((1L << (eint_pupd_spec[i].bit-2)), &reg->eint_ctrl[eint_pupd_spec[i].reg].set);
				else
					GPIO_SET_BITS((3L << (eint_pupd_spec[i].bit-2)), &reg->eint_ctrl[eint_pupd_spec[i].reg].rst);
				return RSUCCESS;
			}
		}
	}

	if(((pin >= GPIO85)&&(pin <= GPIO90)) ||((pin >= GPIO121)&&(pin <= GPIO126))) {
		/* msdc IO */
		for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
			for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
				if (pin == msdc_pupd_spec[i][j].pin){
					if (enable == GPIO_PULL_DISABLE){
						if (i == 0) {
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
						} else if (i == 1) {
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
						}
					}else{
						if (i == 0) {
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].set);
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
						} else if (i == 1) {
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].set);
							GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
						}
					}
					return RSUCCESS;
				}
			}
		}
	}

	if ((pin >= GPIO127)&&(pin <= GPIO137)){
		return GPIO_PULL_EN_UNSUPPORTED;
	}else{
		pos = pin / MAX_GPIO_REG_BITS;
	bit = pin % MAX_GPIO_REG_BITS;

	if (enable == GPIO_PULL_DISABLE)
		GPIO_SET_BITS((1L << bit), &reg->pullen[pos].rst);
	else
		GPIO_SET_BITS((1L << bit), &reg->pullen[pos].set);
	}
    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
int mt_get_gpio_pull_enable_base(unsigned long pin)
{
    unsigned long pos=0;
    unsigned long bit=0;
    unsigned long data=0;
	unsigned long i,j;
    GPIO_REGS *reg = gpio_reg;

	/*for special kpad pupd*/
	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
		if (pin == kpad_pupd_spec[i].pin){
			data = GPIO_RD32(&reg->kpad_ctrl[kpad_pupd_spec[i].reg].val);
			return (((data & (3L << (kpad_pupd_spec[i].bit-2))) == 0)? 0: 1);
		}
	}

	/*for special eint pupd*/
	if(((pin >= GPIO46) && (pin <= GPIO49)) || (pin == GPIO142)) {
		for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
			if (pin == eint_pupd_spec[i].pin){
				data = GPIO_RD32(&reg->eint_ctrl[eint_pupd_spec[i].reg].val);
				return (((data & (3L << (eint_pupd_spec[i].bit-2))) == 0)? 0: 1);
			}
		}
	}

	if(((pin >= GPIO85)&&(pin <= GPIO90)) ||((pin >= GPIO121)&&(pin <= GPIO126))) {
			/* msdc IO */
			for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
				for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
					if (pin == msdc_pupd_spec[i][j].pin){
						if (i == 0) {
							data = GPIO_RD32(&reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].val);
						} else if (i == 1) {
							data = GPIO_RD32(&reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].val);
						}

						return (((data & (3L << (msdc_pupd_spec[i][j].bit + 1))) == 0)? 0: 1);
				}
			}
		}
	}

    if ((pin >= GPIO127)&&(pin <= GPIO137)){
		return GPIO_PULL_EN_UNSUPPORTED;
	}else{
	pos = pin / MAX_GPIO_REG_BITS;
	bit = pin % MAX_GPIO_REG_BITS;

	data = GPIO_RD32(&reg->pullen[pos].val);
	}
    return (((data & (1L << bit)) != 0)? 1: 0);        
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_ies_base(unsigned long pin, unsigned long enable)
{
    unsigned long pos;
    unsigned long bit;
    GPIO_REGS *reg = gpio_reg;

	pos = pin / MAX_GPIO_REG_BITS;
	bit = pin % MAX_GPIO_REG_BITS;

	if (enable == GPIO_IES_DISABLE)
		GPIO_SET_BITS((1L << bit), &reg->ies[pos].rst);
	else
		GPIO_SET_BITS((1L << bit), &reg->ies[pos].set);

    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_ies_base(unsigned long pin)
{
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    GPIO_REGS *reg = gpio_reg;

	pos = pin / MAX_GPIO_REG_BITS;
	bit = pin % MAX_GPIO_REG_BITS;

	data = GPIO_RD32(&reg->ies[pos].val);
    return (((data & (1L << bit)) != 0)? 1: 0);        
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_pull_select_base(unsigned long pin, unsigned long select)
{
    unsigned long pos;
    unsigned long bit;
	unsigned long i,j;

    GPIO_REGS *reg = gpio_reg;

	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
		if (pin == kpad_pupd_spec[i].pin){
			if (select == GPIO_PULL_DOWN)
				GPIO_SET_BITS((1L << kpad_pupd_spec[i].bit), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].set);
			else
				GPIO_SET_BITS((1L << kpad_pupd_spec[i].bit), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].rst);
			return RSUCCESS;
		}
	}

	/*for special eint pupd*/
	if(((pin >= GPIO46) && (pin <= GPIO49)) || (pin == GPIO142)) {
		for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
			if (pin == eint_pupd_spec[i].pin){
				if (select == GPIO_PULL_DOWN)
					GPIO_SET_BITS((1L << eint_pupd_spec[i].bit), &reg->eint_ctrl[eint_pupd_spec[i].reg].set);
				else
					GPIO_SET_BITS((1L << eint_pupd_spec[i].bit), &reg->eint_ctrl[eint_pupd_spec[i].reg].rst);
				return RSUCCESS;
			}
		}
	}


	/* msdc IO */
	if (((pin >= GPIO85)&&(pin <= GPIO90))||((pin >= GPIO121)&&(pin <= GPIO126))){
		for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
			for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
				if (pin == msdc_pupd_spec[i][j].pin){
					if (select == GPIO_PULL_DOWN){
						if (i == 0) {
							GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].set);
						} else if (i == 1) {
							GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].set);
						}
					}else{
						if (i == 0) {
							GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
						} else if (i == 1) {
							GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
						}
					}
					return RSUCCESS;
				}
			}
		}
	}

	if ((select == GPIO_PULL_UP) &&
				(((pin >= GPIO75)&&(pin <= GPIO78))||((pin >= GPIO57)&&(pin <= GPIO58))||((pin >= GPIO138)&&(pin <= GPIO141)))){
			return -ERINVAL;
	}else{
	pos = pin / MAX_GPIO_REG_BITS;
	bit = pin % MAX_GPIO_REG_BITS;
	
	if (select == GPIO_PULL_DOWN)
		GPIO_SET_BITS((1L << bit), &reg->pullsel[pos].rst);
	else
		GPIO_SET_BITS((1L << bit), &reg->pullsel[pos].set);
	}
    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_pull_select_base(unsigned long pin)
{
    unsigned long pos=0;
    unsigned long bit=0;
    unsigned long data=0;
	unsigned long i,j;
    GPIO_REGS *reg = gpio_reg;

	/*for special kpad pupd*/
	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
		if (pin == kpad_pupd_spec[i].pin){
			data = GPIO_RD32(&reg->kpad_ctrl[kpad_pupd_spec[i].reg].val);
			return (((data & (1L << kpad_pupd_spec[i].bit)) != 0)? 0: 1);
		}
	}

	/*for special eint pupd*/
	if(((pin >= GPIO46) && (pin <= GPIO49)) || (pin == GPIO142)) {
		for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
			if (pin == eint_pupd_spec[i].pin){
				data = GPIO_RD32(&reg->eint_ctrl[eint_pupd_spec[i].reg].val);
				return (((data & (1L << eint_pupd_spec[i].bit)) != 0)? 0: 1);
			}
		}
	}

	/* msdc IO */
	if (((pin >= GPIO85)&&(pin <= GPIO90))||((pin >= GPIO121)&&(pin <= GPIO126))){
		for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
			for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
				if (pin == msdc_pupd_spec[i][j].pin){
					if (i == 0) {
						data = GPIO_RD32(&reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].val);
					} else if (i == 1) {
						data = GPIO_RD32(&reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].val);
					}

					return (((data & (1L << msdc_pupd_spec[i][j].bit)) != 0)? 0: 1);
				}
			}
		}
	}


	pos = pin / MAX_GPIO_REG_BITS;
	bit = pin % MAX_GPIO_REG_BITS;

	data = GPIO_RD32(&reg->pullsel[pos].val);

    return (((data & (1L << bit)) != 0)? 1: 0);        
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_inversion_base(unsigned long pin, unsigned long enable)
{/*FIX-ME
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    unsigned long mask;
    GPIO_REGS *reg = gpio_reg;

	//GPIO44~GPIO49 is special pin for sim
	if((pin >= 44) && (pin <= 46)){
		data = GPIO_RD32(GPIO_BASE+ 0X990);
    	mask = (1L << 1) - 1;    
		//pos = pin / 4;
		bit = pin % 4;
		data &= ~(mask << (bit));
		data |= (enable << (bit));
		
		GPIO_WR32(GPIO_BASE+ 0X990, data);
	}else if((pin >= 47) && (pin <= 49)){
		pin -= 3;
		data = GPIO_RD32(GPIO_BASE+ 0X9B0);
    	mask = (1L << 1) - 1;    
		//pos = pin / 4;
		bit = pin % 4;
		data &= ~(mask << (bit));
		data |= (enable << (bit));
		
		GPIO_WR32(GPIO_BASE+ 0X9B0, data);
	}else{
		pos = pin / MAX_GPIO_REG_BITS;
		bit = pin % MAX_GPIO_REG_BITS;
		
		if (enable == GPIO_DATA_UNINV)
			GPIO_SET_BITS((1L << bit), &reg->dinv[pos].rst);
		else
			GPIO_SET_BITS((1L << bit), &reg->dinv[pos].set);
*/
    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_inversion_base(unsigned long pin)
{/*FIX-ME
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    GPIO_REGS *reg = gpio_reg;

	//GPIO44~GPIO49 is special pin for sim
	if((pin >= 44) && (pin <= 46)){
		data = GPIO_RD32(GPIO_BASE+ 0X990);
		bit = (pin % 4);
	}else if((pin >= 47) && (pin <= 49)){
		pin -= 3;
		data = GPIO_RD32(GPIO_BASE+ 0X9B0);
		bit = (pin % 4);
	}else{
		pos = pin / MAX_GPIO_REG_BITS;
		bit = pin % MAX_GPIO_REG_BITS;

		data = GPIO_RD32(&reg->dinv[pos].val);
	}
    return (((data & (1L << bit)) != 0)? 1: 0);    */
	return 0;//FIX-ME
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_out_base(unsigned long pin, unsigned long output)
{
    unsigned long pos;
    unsigned long bit;
    GPIO_REGS *reg = gpio_reg;

    pos = pin / MAX_GPIO_REG_BITS;
    bit = pin % MAX_GPIO_REG_BITS;
    
    if (output == GPIO_OUT_ZERO)
        GPIO_SET_BITS((1L << bit), &reg->dout[pos].rst);
    else
        GPIO_SET_BITS((1L << bit), &reg->dout[pos].set);
    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_out_base(unsigned long pin)
{
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    GPIO_REGS *reg = gpio_reg;

    pos = pin / MAX_GPIO_REG_BITS;
    bit = pin % MAX_GPIO_REG_BITS;

    data = GPIO_RD32(&reg->dout[pos].val);
    return (((data & (1L << bit)) != 0)? 1: 0);        
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_in_base(unsigned long pin)
{
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    GPIO_REGS *reg = gpio_reg;

    pos = pin / MAX_GPIO_REG_BITS;
    bit = pin % MAX_GPIO_REG_BITS;

    data = GPIO_RD32(&reg->din[pos].val);
    return (((data & (1L << bit)) != 0)? 1: 0);        
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_mode_base(unsigned long pin, unsigned long mode)
{
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    unsigned long mask = (1L << GPIO_MODE_BITS) - 1;    
    GPIO_REGS *reg = gpio_reg;

	pos = pin / MAX_GPIO_MODE_PER_REG;
	bit = pin % MAX_GPIO_MODE_PER_REG;
   
	data = GPIO_RD32(&reg->mode[pos].val);

	data &= ~(mask << (GPIO_MODE_BITS*bit));
	data |= (mode << (GPIO_MODE_BITS*bit));
	
	GPIO_WR32(&reg->mode[pos].val, data);

    return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_get_gpio_mode_base(unsigned long pin)
{
    unsigned long pos;
    unsigned long bit;
    unsigned long data;
    unsigned long mask = (1L << GPIO_MODE_BITS) - 1;    
    GPIO_REGS *reg = gpio_reg;

	pos = pin / MAX_GPIO_MODE_PER_REG;
	bit = pin % MAX_GPIO_MODE_PER_REG;

	data = GPIO_RD32(&reg->mode[pos].val);
	
	return ((data >> (GPIO_MODE_BITS*bit)) & mask);
}
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
#ifdef CONFIG_PM 
/*---------------------------------------------------------------------------*/
void mt_gpio_suspend(void)
{
    /* compatible with HAL */
}
/*---------------------------------------------------------------------------*/
void mt_gpio_resume(void)
{
	/* compatible with HAL */
}
/*---------------------------------------------------------------------------*/
#endif /*CONFIG_PM*/
/*---------------------------------------------------------------------------*/

/*---------------------------------------------------------------------------*/
int mt_set_gpio_smt_base(unsigned long pin, unsigned long enable)
{
	/* compatible with HAL */
	return RSUCCESS;
}

/*---------------------------------------------------------------------------*/
int mt_get_gpio_smt_base(unsigned long pin)
{
	/* compatible with HAL */
	return RSUCCESS;
}
Commit	Line	Data
6fa3eb70 S	1	/******************************************************************************
	2	* mt_gpio_base.c - MTKLinux GPIO Device Driver
	3	*
	4	* Copyright 2008-2009 MediaTek Co.,Ltd.
	5	*
	6	* DESCRIPTION:
	7	* This file provid the other drivers GPIO relative functions
	8	*
	9	******************************************************************************/
	10
	11	#include <mach/sync_write.h>
	12	#include <mach/mt_reg_base.h>
	13	#include <mach/mt_typedefs.h>
	14	#include <mach/mt_gpio.h>
	15	#include <mach/mt_gpio_core.h>
	16	#include <mach/mt_gpio_base.h>
	17	#include <cust_gpio_usage.h>
	18
	19	/-------for special kpad pupd-----------/
	20	struct kpad_pupd {
	21	unsigned char pin;
	22	unsigned char reg;
	23	unsigned char bit;
	24	};
	25	static struct kpad_pupd kpad_pupd_spec[] = {
	26	{GPIO33, 0, 2},
	27	{GPIO34, 0, 6},
	28	{GPIO35, 0, 10},
	29	{GPIO36, 1, 2},
	30	{GPIO37, 1, 6},
	31	{GPIO38, 1, 10}
	32	};
	33	/-------for msdc pupd-----------/
	34	struct msdc_pupd {
	35	unsigned char pin;
	36	unsigned char reg;
	37	unsigned char bit;
	38	};
	39	static struct msdc_pupd msdc_pupd_spec[2][6] = {
	40	{
	41	{GPIO121, 1, 8},
	42	{GPIO122, 0, 8},
	43	{GPIO123, 3, 0},
	44	{GPIO124, 3, 4},
	45	{GPIO125, 3, 8},
	46	{GPIO126, 3, 12}},
	47	{
	48	{GPIO85, 1, 8},
	49	{GPIO86, 0, 8},
	50	{GPIO87, 3, 0},
	51	{GPIO88, 3, 4},
	52	{GPIO89, 3, 8},
	53	{GPIO90, 3, 12}}
	54	};
	55	/-------for eint14~eint17 eint21 pupd-----------/
	56	struct eint_pupd {
	57	unsigned char pin;
	58	unsigned char reg;
	59	unsigned char bit;
	60	};
	61	static struct eint_pupd eint_pupd_spec[] = {
	62	{GPIO46, 0, 2},
	63	{GPIO47, 0, 6},
	64	{GPIO48, 0, 10},
65	{GPIO49, 0, 14},
66	{GPIO142, 1, 2}
67	};
68
69	/---------------------------------------/
70	static GPIO_REGS gpio_reg = (GPIO_REGS)(GPIO_BASE);
71	/---------------------------------------------------------------------------/
72	int mt_set_gpio_dir_base(unsigned long pin, unsigned long dir)
73	{
74	unsigned long pos;
75	unsigned long bit;
76	GPIO_REGS *reg = gpio_reg;
77
78	if ((dir == GPIO_DIR_OUT) &&
79	((pin >= GPIO75 && pin <= GPIO78)\|\|(pin >= GPIO57 && pin <= GPIO58)
80	\|\|(pin >= GPIO138 &&pin <= GPIO141))){
81	return -ERINVAL;
82	}
83	pos = pin / MAX_GPIO_REG_BITS;
84	bit = pin % MAX_GPIO_REG_BITS;
85
86	if (dir == GPIO_DIR_IN)
87	GPIO_SET_BITS((1L << bit), &reg->dir[pos].rst);
88	else
89	GPIO_SET_BITS((1L << bit), &reg->dir[pos].set);
90	return RSUCCESS;
91	}
92	/---------------------------------------------------------------------------/
93	int mt_get_gpio_dir_base(unsigned long pin)
94	{
95	unsigned long pos;
96	unsigned long bit;
97	unsigned long data;
98	GPIO_REGS *reg = gpio_reg;
99
100	pos = pin / MAX_GPIO_REG_BITS;
101	bit = pin % MAX_GPIO_REG_BITS;
102
103	data = GPIO_RD32(&reg->dir[pos].val);
104	return (((data & (1L << bit)) != 0)? 1: 0);
105	}
106	/---------------------------------------------------------------------------/
107	int mt_set_gpio_pull_enable_base(unsigned long pin, unsigned long enable)
108	{
109	unsigned long pos;
110	unsigned long bit;
111	unsigned long i,j;
112	GPIO_REGS *reg = gpio_reg;
113
114	/for special kpad pupd/
115	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
116	if (pin == kpad_pupd_spec[i].pin){
117	if (enable == GPIO_PULL_DISABLE){
118	GPIO_SET_BITS((3L << (kpad_pupd_spec[i].bit-2)), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].rst);
119	} else {
120	GPIO_SET_BITS((1L << (kpad_pupd_spec[i].bit-2)), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].set);
121	}
122	return RSUCCESS;
123	}
124	}
125
126	/for special eint pupd/
127	if(((pin >= GPIO46) && (pin <= GPIO49)) \|\| (pin == GPIO142)) {
128	for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
129	if (pin == eint_pupd_spec[i].pin){
130	if (enable == GPIO_PULL_ENABLE)
131	GPIO_SET_BITS((1L << (eint_pupd_spec[i].bit-2)), &reg->eint_ctrl[eint_pupd_spec[i].reg].set);
132	else
133	GPIO_SET_BITS((3L << (eint_pupd_spec[i].bit-2)), &reg->eint_ctrl[eint_pupd_spec[i].reg].rst);
134	return RSUCCESS;
135	}
136	}
137	}
138
139	if(((pin >= GPIO85)&&(pin <= GPIO90)) \|\|((pin >= GPIO121)&&(pin <= GPIO126))) {
140	/* msdc IO */
141	for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
142	for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
143	if (pin == msdc_pupd_spec[i][j].pin){
144	if (enable == GPIO_PULL_DISABLE){
145	if (i == 0) {
146	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
147	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
148	} else if (i == 1) {
149	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
150	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
151	}
152	}else{
153	if (i == 0) {
154	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].set);
155	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
156	} else if (i == 1) {
157	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 1)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].set);
158	GPIO_SET_BITS((1L << (msdc_pupd_spec[i][j].bit + 2)), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
159	}
160	}
161	return RSUCCESS;
162	}
163	}
164	}
165	}
166
167	if ((pin >= GPIO127)&&(pin <= GPIO137)){
168	return GPIO_PULL_EN_UNSUPPORTED;
169	}else{
170	pos = pin / MAX_GPIO_REG_BITS;
171	bit = pin % MAX_GPIO_REG_BITS;
172
173	if (enable == GPIO_PULL_DISABLE)
174	GPIO_SET_BITS((1L << bit), &reg->pullen[pos].rst);
175	else
176	GPIO_SET_BITS((1L << bit), &reg->pullen[pos].set);
177	}
178	return RSUCCESS;
179	}
180	/---------------------------------------------------------------------------/
181	/---------------------------------------------------------------------------/
182	int mt_get_gpio_pull_enable_base(unsigned long pin)
183	{
184	unsigned long pos=0;
185	unsigned long bit=0;
186	unsigned long data=0;
187	unsigned long i,j;
188	GPIO_REGS *reg = gpio_reg;
189
190	/for special kpad pupd/
191	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
192	if (pin == kpad_pupd_spec[i].pin){
193	data = GPIO_RD32(&reg->kpad_ctrl[kpad_pupd_spec[i].reg].val);
194	return (((data & (3L << (kpad_pupd_spec[i].bit-2))) == 0)? 0: 1);
195	}
196	}
197
198	/for special eint pupd/
199	if(((pin >= GPIO46) && (pin <= GPIO49)) \|\| (pin == GPIO142)) {
200	for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
201	if (pin == eint_pupd_spec[i].pin){
202	data = GPIO_RD32(&reg->eint_ctrl[eint_pupd_spec[i].reg].val);
203	return (((data & (3L << (eint_pupd_spec[i].bit-2))) == 0)? 0: 1);
204	}
205	}
206	}
207
208	if(((pin >= GPIO85)&&(pin <= GPIO90)) \|\|((pin >= GPIO121)&&(pin <= GPIO126))) {
209	/* msdc IO */
210	for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
211	for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
212	if (pin == msdc_pupd_spec[i][j].pin){
213	if (i == 0) {
214	data = GPIO_RD32(&reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].val);
215	} else if (i == 1) {
216	data = GPIO_RD32(&reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].val);
217	}
218
219	return (((data & (3L << (msdc_pupd_spec[i][j].bit + 1))) == 0)? 0: 1);
220	}
221	}
222	}
223	}
224
225	if ((pin >= GPIO127)&&(pin <= GPIO137)){
226	return GPIO_PULL_EN_UNSUPPORTED;
227	}else{
228	pos = pin / MAX_GPIO_REG_BITS;
229	bit = pin % MAX_GPIO_REG_BITS;
230
231	data = GPIO_RD32(&reg->pullen[pos].val);
232	}
233	return (((data & (1L << bit)) != 0)? 1: 0);
234	}
235	/---------------------------------------------------------------------------/
236	int mt_set_gpio_ies_base(unsigned long pin, unsigned long enable)
237	{
238	unsigned long pos;
239	unsigned long bit;
240	GPIO_REGS *reg = gpio_reg;
241
242	pos = pin / MAX_GPIO_REG_BITS;
243	bit = pin % MAX_GPIO_REG_BITS;
244
245	if (enable == GPIO_IES_DISABLE)
246	GPIO_SET_BITS((1L << bit), &reg->ies[pos].rst);
247	else
248	GPIO_SET_BITS((1L << bit), &reg->ies[pos].set);
249
250	return RSUCCESS;
251	}
252	/---------------------------------------------------------------------------/
253	int mt_get_gpio_ies_base(unsigned long pin)
254	{
255	unsigned long pos;
256	unsigned long bit;
257	unsigned long data;
258	GPIO_REGS *reg = gpio_reg;
259
260	pos = pin / MAX_GPIO_REG_BITS;
261	bit = pin % MAX_GPIO_REG_BITS;
262
263	data = GPIO_RD32(&reg->ies[pos].val);
264	return (((data & (1L << bit)) != 0)? 1: 0);
265	}
266	/---------------------------------------------------------------------------/
267	int mt_set_gpio_pull_select_base(unsigned long pin, unsigned long select)
268	{
269	unsigned long pos;
270	unsigned long bit;
271	unsigned long i,j;
272
273	GPIO_REGS *reg = gpio_reg;
274
275	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
276	if (pin == kpad_pupd_spec[i].pin){
277	if (select == GPIO_PULL_DOWN)
278	GPIO_SET_BITS((1L << kpad_pupd_spec[i].bit), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].set);
279	else
280	GPIO_SET_BITS((1L << kpad_pupd_spec[i].bit), &reg->kpad_ctrl[kpad_pupd_spec[i].reg].rst);
281	return RSUCCESS;
282	}
283	}
284
285	/for special eint pupd/
286	if(((pin >= GPIO46) && (pin <= GPIO49)) \|\| (pin == GPIO142)) {
287	for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
288	if (pin == eint_pupd_spec[i].pin){
289	if (select == GPIO_PULL_DOWN)
290	GPIO_SET_BITS((1L << eint_pupd_spec[i].bit), &reg->eint_ctrl[eint_pupd_spec[i].reg].set);
291	else
292	GPIO_SET_BITS((1L << eint_pupd_spec[i].bit), &reg->eint_ctrl[eint_pupd_spec[i].reg].rst);
293	return RSUCCESS;
294	}
295	}
296	}
297
298
299	/* msdc IO */
300	if (((pin >= GPIO85)&&(pin <= GPIO90))\|\|((pin >= GPIO121)&&(pin <= GPIO126))){
301	for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
302	for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
303	if (pin == msdc_pupd_spec[i][j].pin){
304	if (select == GPIO_PULL_DOWN){
305	if (i == 0) {
306	GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].set);
307	} else if (i == 1) {
308	GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].set);
309	}
310	}else{
311	if (i == 0) {
312	GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
313	} else if (i == 1) {
314	GPIO_SET_BITS((1L << msdc_pupd_spec[i][j].bit), &reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
315	}
316	}
317	return RSUCCESS;
318	}
319	}
320	}
321	}
322
323	if ((select == GPIO_PULL_UP) &&
324	(((pin >= GPIO75)&&(pin <= GPIO78))\|\|((pin >= GPIO57)&&(pin <= GPIO58))\|\|((pin >= GPIO138)&&(pin <= GPIO141)))){
325	return -ERINVAL;
326	}else{
327	pos = pin / MAX_GPIO_REG_BITS;
328	bit = pin % MAX_GPIO_REG_BITS;
329
330	if (select == GPIO_PULL_DOWN)
331	GPIO_SET_BITS((1L << bit), &reg->pullsel[pos].rst);
332	else
333	GPIO_SET_BITS((1L << bit), &reg->pullsel[pos].set);
334	}
335	return RSUCCESS;
336	}
337	/---------------------------------------------------------------------------/
338	int mt_get_gpio_pull_select_base(unsigned long pin)
339	{
340	unsigned long pos=0;
341	unsigned long bit=0;
342	unsigned long data=0;
343	unsigned long i,j;
344	GPIO_REGS *reg = gpio_reg;
345
346	/for special kpad pupd/
347	for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++){
348	if (pin == kpad_pupd_spec[i].pin){
349	data = GPIO_RD32(&reg->kpad_ctrl[kpad_pupd_spec[i].reg].val);
350	return (((data & (1L << kpad_pupd_spec[i].bit)) != 0)? 0: 1);
351	}
352	}
353
354	/for special eint pupd/
355	if(((pin >= GPIO46) && (pin <= GPIO49)) \|\| (pin == GPIO142)) {
356	for(i = 0; i < sizeof(eint_pupd_spec)/sizeof(eint_pupd_spec[0]); i++){
357	if (pin == eint_pupd_spec[i].pin){
358	data = GPIO_RD32(&reg->eint_ctrl[eint_pupd_spec[i].reg].val);
359	return (((data & (1L << eint_pupd_spec[i].bit)) != 0)? 0: 1);
360	}
361	}
362	}
363
364	/* msdc IO */
365	if (((pin >= GPIO85)&&(pin <= GPIO90))\|\|((pin >= GPIO121)&&(pin <= GPIO126))){
366	for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++){
367	for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++){
368	if (pin == msdc_pupd_spec[i][j].pin){
369	if (i == 0) {
370	data = GPIO_RD32(&reg->msdc1_ctrl[msdc_pupd_spec[i][j].reg].val);
371	} else if (i == 1) {
372	data = GPIO_RD32(&reg->msdc2_ctrl[msdc_pupd_spec[i][j].reg].val);
373	}
374
375	return (((data & (1L << msdc_pupd_spec[i][j].bit)) != 0)? 0: 1);
376	}
377	}
378	}
379	}
380
381
382	pos = pin / MAX_GPIO_REG_BITS;
383	bit = pin % MAX_GPIO_REG_BITS;
384
385	data = GPIO_RD32(&reg->pullsel[pos].val);
386
387	return (((data & (1L << bit)) != 0)? 1: 0);
388	}
389	/---------------------------------------------------------------------------/
390	int mt_set_gpio_inversion_base(unsigned long pin, unsigned long enable)
391	{/*FIX-ME
392	unsigned long pos;
393	unsigned long bit;
394	unsigned long data;
395	unsigned long mask;
396	GPIO_REGS *reg = gpio_reg;
397
398	//GPIO44~GPIO49 is special pin for sim
399	if((pin >= 44) && (pin <= 46)){
400	data = GPIO_RD32(GPIO_BASE+ 0X990);
401	mask = (1L << 1) - 1;
402	//pos = pin / 4;
403	bit = pin % 4;
404	data &= ~(mask << (bit));
405	data \|= (enable << (bit));
406
407	GPIO_WR32(GPIO_BASE+ 0X990, data);
408	}else if((pin >= 47) && (pin <= 49)){
409	pin -= 3;
410	data = GPIO_RD32(GPIO_BASE+ 0X9B0);
411	mask = (1L << 1) - 1;
412	//pos = pin / 4;
413	bit = pin % 4;
414	data &= ~(mask << (bit));
415	data \|= (enable << (bit));
416
417	GPIO_WR32(GPIO_BASE+ 0X9B0, data);
418	}else{
419	pos = pin / MAX_GPIO_REG_BITS;
420	bit = pin % MAX_GPIO_REG_BITS;
421
422	if (enable == GPIO_DATA_UNINV)
423	GPIO_SET_BITS((1L << bit), &reg->dinv[pos].rst);
424	else
425	GPIO_SET_BITS((1L << bit), &reg->dinv[pos].set);
426	*/
427	return RSUCCESS;
428	}
429	/---------------------------------------------------------------------------/
430	int mt_get_gpio_inversion_base(unsigned long pin)
431	{/*FIX-ME
432	unsigned long pos;
433	unsigned long bit;
434	unsigned long data;
435	GPIO_REGS *reg = gpio_reg;
436
437	//GPIO44~GPIO49 is special pin for sim
438	if((pin >= 44) && (pin <= 46)){
439	data = GPIO_RD32(GPIO_BASE+ 0X990);
440	bit = (pin % 4);
441	}else if((pin >= 47) && (pin <= 49)){
442	pin -= 3;
443	data = GPIO_RD32(GPIO_BASE+ 0X9B0);
444	bit = (pin % 4);
445	}else{
446	pos = pin / MAX_GPIO_REG_BITS;
447	bit = pin % MAX_GPIO_REG_BITS;
448
449	data = GPIO_RD32(&reg->dinv[pos].val);
450	}
451	return (((data & (1L << bit)) != 0)? 1: 0); */
452	return 0;//FIX-ME
453	}
454	/---------------------------------------------------------------------------/
455	int mt_set_gpio_out_base(unsigned long pin, unsigned long output)
456	{
457	unsigned long pos;
458	unsigned long bit;
459	GPIO_REGS *reg = gpio_reg;
460
461	pos = pin / MAX_GPIO_REG_BITS;
462	bit = pin % MAX_GPIO_REG_BITS;
463
464	if (output == GPIO_OUT_ZERO)
465	GPIO_SET_BITS((1L << bit), &reg->dout[pos].rst);
466	else
467	GPIO_SET_BITS((1L << bit), &reg->dout[pos].set);
468	return RSUCCESS;
469	}
470	/---------------------------------------------------------------------------/
471	int mt_get_gpio_out_base(unsigned long pin)
472	{
473	unsigned long pos;
474	unsigned long bit;
475	unsigned long data;
476	GPIO_REGS *reg = gpio_reg;
477
478	pos = pin / MAX_GPIO_REG_BITS;
479	bit = pin % MAX_GPIO_REG_BITS;
480
481	data = GPIO_RD32(&reg->dout[pos].val);
482	return (((data & (1L << bit)) != 0)? 1: 0);
483	}
484	/---------------------------------------------------------------------------/
485	int mt_get_gpio_in_base(unsigned long pin)
486	{
487	unsigned long pos;
488	unsigned long bit;
489	unsigned long data;
490	GPIO_REGS *reg = gpio_reg;
491
492	pos = pin / MAX_GPIO_REG_BITS;
493	bit = pin % MAX_GPIO_REG_BITS;
494
495	data = GPIO_RD32(&reg->din[pos].val);
496	return (((data & (1L << bit)) != 0)? 1: 0);
497	}
498	/---------------------------------------------------------------------------/
499	int mt_set_gpio_mode_base(unsigned long pin, unsigned long mode)
500	{
501	unsigned long pos;
502	unsigned long bit;
503	unsigned long data;
504	unsigned long mask = (1L << GPIO_MODE_BITS) - 1;
505	GPIO_REGS *reg = gpio_reg;
506
507	pos = pin / MAX_GPIO_MODE_PER_REG;
508	bit = pin % MAX_GPIO_MODE_PER_REG;
509
510	data = GPIO_RD32(&reg->mode[pos].val);
511
512	data &= ~(mask << (GPIO_MODE_BITS*bit));
513	data \|= (mode << (GPIO_MODE_BITS*bit));
514
515	GPIO_WR32(&reg->mode[pos].val, data);
516
517	return RSUCCESS;
518	}
519	/---------------------------------------------------------------------------/
520	int mt_get_gpio_mode_base(unsigned long pin)
521	{
522	unsigned long pos;
523	unsigned long bit;
524	unsigned long data;
525	unsigned long mask = (1L << GPIO_MODE_BITS) - 1;
526	GPIO_REGS *reg = gpio_reg;
527
528	pos = pin / MAX_GPIO_MODE_PER_REG;
529	bit = pin % MAX_GPIO_MODE_PER_REG;
530
531	data = GPIO_RD32(&reg->mode[pos].val);
532
533	return ((data >> (GPIO_MODE_BITS*bit)) & mask);
534	}
535	/---------------------------------------------------------------------------/
536	/---------------------------------------------------------------------------/
537	/---------------------------------------------------------------------------/
538	#ifdef CONFIG_PM
539	/---------------------------------------------------------------------------/
540	void mt_gpio_suspend(void)
541	{
542	/* compatible with HAL */
543	}
544	/---------------------------------------------------------------------------/
545	void mt_gpio_resume(void)
546	{
547	/* compatible with HAL */
548	}
549	/---------------------------------------------------------------------------/
550	#endif /CONFIG_PM/
551	/---------------------------------------------------------------------------/
552
553	/---------------------------------------------------------------------------/
554	int mt_set_gpio_smt_base(unsigned long pin, unsigned long enable)
555	{
556	/* compatible with HAL */
557	return RSUCCESS;
558	}
559
560	/---------------------------------------------------------------------------/
561	int mt_get_gpio_smt_base(unsigned long pin)
562	{
563	/* compatible with HAL */
564	return RSUCCESS;
565	}