projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fa3eb70 S |
1 | #ifndef __MT_EMI_MPU_H |
| 2 | #define __MT_EMI_MPU_H | |
| 3 | ||
| 4 | #define EMI_MPUA (EMI_BASE+0x0160) | |
| 5 | #define EMI_MPUB (EMI_BASE+0x0168) | |
| 6 | #define EMI_MPUC (EMI_BASE+0x0170) | |
| 7 | #define EMI_MPUD (EMI_BASE+0x0178) | |
| 8 | #define EMI_MPUE (EMI_BASE+0x0180) | |
| 9 | #define EMI_MPUF (EMI_BASE+0x0188) | |
| 10 | #define EMI_MPUG (EMI_BASE+0x0190) | |
| 11 | #define EMI_MPUH (EMI_BASE+0x0198) | |
| 12 | #define EMI_MPUI (EMI_BASE+0x01A0) | |
| 13 | #define EMI_MPUJ (EMI_BASE+0x01A8) | |
| 14 | #define EMI_MPUK (EMI_BASE+0x01B0) | |
| 15 | #define EMI_MPUL (EMI_BASE+0x01B8) | |
| 16 | #define EMI_MPUM (EMI_BASE+0x01C0) | |
| 17 | #define EMI_MPUN (EMI_BASE+0x01C8) | |
| 18 | #define EMI_MPUO (EMI_BASE+0x01D0) | |
| 19 | #define EMI_MPUP (EMI_BASE+0x01D8) | |
| 20 | #define EMI_MPUQ (EMI_BASE+0x01E0) | |
| 21 | #define EMI_MPUR (EMI_BASE+0x01E8) | |
| 22 | #define EMI_MPUS (EMI_BASE+0x01F0) | |
| 23 | #define EMI_MPUT (EMI_BASE+0x01F8) | |
| 24 | #define EMI_MPUU (EMI_BASE+0x0200) | |
| 25 | #define EMI_MPUY (EMI_BASE+0x0220) | |
| 26 | #define EMI_CHKER (EMI_BASE + 0x5F0) | |
| 27 | #define EMI_CHKER_ADR (EMI_BASE + 0x5F8) | |
| 28 | ||
| 29 | #define NO_PROTECTION 0 | |
| 30 | #define SEC_RW 1 | |
| 31 | #define SEC_RW_NSEC_R 2 | |
| 32 | #define SEC_RW_NSEC_W 3 | |
| 33 | #define SEC_R_NSEC_R 4 | |
| 34 | #define FORBIDDEN 5 | |
| 35 | ||
| 36 | #define EN_MPU_STR "ON" | |
| 37 | #define DIS_MPU_STR "OFF" | |
| 38 | ||
| 39 | ||
| 40 | /*EMI memory protection align 64K*/ | |
| 41 | #define EMI_MPU_ALIGNMENT 0x10000 | |
| 42 | #define OOR_VIO 0x00000200 | |
| 43 | #define EMI_PHY_OFFSET 0x80000000 | |
| 44 | ||
| 45 | enum | |
| 46 | { | |
| 47 | /* apmcu */ | |
| 48 | MST_ID_APMCU_0, MST_ID_APMCU_1, MST_ID_APMCU_2, MST_ID_APMCU_3, MST_ID_APMCU_4, | |
| 49 | /* MM */ | |
| 50 | MST_ID_MM_0, MST_ID_MM_1, MST_ID_MM_2, MST_ID_MM_3, MST_ID_MM_4, MST_ID_MM_5, MST_ID_MM_6, | |
| 51 | /* Periperal */ | |
| 52 | MST_ID_PERI_0, MST_ID_PERI_1, MST_ID_PERI_2, MST_ID_PERI_3, MST_ID_PERI_4, MST_ID_PERI_5, MST_ID_PERI_6, MST_ID_PERI_7, MST_ID_PERI_8, | |
| 53 | MST_ID_PERI_9, MST_ID_PERI_10, MST_ID_PERI_11, MST_ID_PERI_12, MST_ID_PERI_13, | |
| 54 | /* Modem */ | |
| 55 | MST_ID_MDMCU_0, MST_ID_MDMCU_1, MST_ID_MDMCU_2, | |
| 56 | /* Modem HW (2G/3G) */ | |
| 57 | MST_ID_MDHW_0, MST_ID_MDHW_1, MST_ID_MDHW_2, MST_ID_MDHW_3, MST_ID_MDHW_4, MST_ID_MDHW_5, MST_ID_MDHW_6, MST_ID_MDHW_7, | |
| 58 | MST_INVALID, | |
| 59 | NR_MST, | |
| 60 | }; | |
| 61 | ||
| 62 | enum | |
| 63 | { | |
| 64 | AXI_ADR_CHK_EN = 0, | |
| 65 | AXI_LOCK_CHK_EN, | |
| 66 | AXI_NON_ALIGN_CHK_EN, | |
| 67 | AXI_NON_ALIGN_CHK_MST = 4, | |
| 68 | AXI_VIO_CLR = 8, | |
| 69 | AXI_VIO_ID = 16, | |
| 70 | AXI_VIO_WR = 27, | |
| 71 | AXI_ADR_VIO, | |
| 72 | AXI_LOCK_ISSUE, | |
| 73 | AXI_NON_ALIGN_ISSUE | |
| 74 | }; | |
| 75 | ||
| 76 | enum | |
| 77 | { | |
| 78 | MASTER_APMCU = 0, | |
| 79 | MASTER_MM, | |
| 80 | MASTER_PERI, | |
| 81 | MASTER_MDMCU, | |
| 82 | MASTER_MDHW, | |
| 83 | MASTER_ALL = 7 | |
| 84 | }; | |
| 85 | ||
| 86 | typedef void (*emi_mpu_notifier)(u32 addr, int wr_vio); | |
| 87 | ||
| 88 | #define SET_ACCESS_PERMISSON(d3, d2, d1, d0) (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0)) | |
| 89 | ||
| 90 | extern int emi_mpu_set_region_protection(unsigned int start_addr, unsigned int end_addr, int region, unsigned int access_permission); | |
| 91 | extern int emi_mpu_notifier_register(int master, emi_mpu_notifier notifider); | |
| 92 | ||
| 93 | #endif /* !__MT_EMI_MPU_H */ |