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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / eccci / port_cfg.c
CommitLineData
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S		 1#include "port_cfg.h"
2
3#define TAG "cfg"
4// Port mapping
5extern struct ccci_port_ops char_port_ops;
6extern struct ccci_port_ops net_port_ops;
7extern struct ccci_port_ops kernel_port_ops;
8extern struct ccci_port_ops ipc_port_ack_ops;
9extern struct ccci_port_ops ipc_kern_port_ops;
10#ifdef CONFIG_MTK_ENABLE_MD1
11static struct ccci_port md1_ccci_ports[] = {
12// char port, notes ccci_monitor must be first
13{CCCI_MONITOR_CH, CCCI_MONITOR_CH, 0xFF, 0xFF, 0xFF, 0xFF, 4, &char_port_ops, 0, "ccci_monitor", },
14{CCCI_PCM_TX, CCCI_PCM_RX, 0, 0, 0xFF, 0xFF, 4, &char_port_ops, 1, "ccci_aud", },
15{CCCI_UART1_TX, CCCI_UART1_RX, 1, 1, 3, 3, 0, &char_port_ops, 2, "ccci_md_log_ctrl", },
16{CCCI_UART2_TX, CCCI_UART2_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 3, "ttyC0", },
17{CCCI_FS_TX, CCCI_FS_RX, 1, 1, 1, 1, 4, &char_port_ops, 4, "ccci_fs", },
18{CCCI_IPC_UART_TX, CCCI_IPC_UART_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 5, "ttyC2", },
19{CCCI_ICUSB_TX, CCCI_ICUSB_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 6, "ttyC3", },
20{CCCI_MD_LOG_TX, CCCI_MD_LOG_RX, 2, 2, 2, 2, 8, &char_port_ops, 7, "ttyC1", },
21{CCCI_IMSV_UL, CCCI_IMSV_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 8, "ccci_imsv", },
22{CCCI_IMSC_UL, CCCI_IMSC_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 9, "ccci_imsc", },
23{CCCI_IMSA_UL, CCCI_IMSA_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 10, "ccci_imsa", },
24{CCCI_IMSDC_UL, CCCI_IMSDC_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 11, "ccci_imsdc", },
25{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 12, "ccci_ioctl0", },
26{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 13, "ccci_ioctl1", },
27{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 14, "ccci_ioctl2", },
28{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 15, "ccci_ioctl3", },
29{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 16, "ccci_ioctl4", },
30{CCCI_IT_TX, CCCI_IT_RX, 0, 0, 0xFF, 0xFF, 4, &char_port_ops, 17, "ccci_it", },
31{CCCI_LB_IT_TX, CCCI_LB_IT_RX, 0, 0, 0xFF, 0xFF, 0, &char_port_ops, 18, "ccci_lb_it", },
32{CCCI_RPC_TX, CCCI_RPC_RX, 1, 1, 1, 1, 4, &char_port_ops, 19, "ccci_rpc", },
33// IPC char port minor= minor idx + CCCI_IPC_MINOR_BASE(100)
34{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 0, "ccci_ipc_1220_0", },
35{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 2, "ccci_ipc_2", },
36//IPC kernel port
37{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &ipc_kern_port_ops, 3, "ccci_ipc_3", },
38{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 4, "ccci_ipc_4", },
39
40// sys port
41{CCCI_CONTROL_TX, CCCI_CONTROL_RX, 0, 0, 0, 0, 0, &kernel_port_ops, 0, "ccci_ctrl", },
42{CCCI_SYSTEM_TX, CCCI_SYSTEM_RX, 0, 0, 0xFF, 0xFF, 0, &kernel_port_ops, 0, "ccci_sys", },
43{CCCI_STATUS_TX, CCCI_STATUS_RX, 0, 0, 0, 0, 0, &kernel_port_ops, 0, "ccci_poll", },
44// network port
45{CCCI_CCMNI1_TX, CCCI_CCMNI1_RX, 3, 3, 0xF4, 0xFF, 8, &net_port_ops, 0, "ccmni0", },
46{CCCI_CCMNI2_TX, CCCI_CCMNI2_RX, 3, 4, 0xF4, 0xFF, 8, &net_port_ops, 0, "ccmni1", },
47{CCCI_CCMNI3_TX, CCCI_CCMNI3_RX, 5, 5, 0xFF, 0xFF, 8, &net_port_ops, 0, "ccmni2", },
48};
49#endif
50
51#ifdef CONFIG_MTK_ENABLE_MD2
52static struct ccci_port md2_ccci_ports[] = {
53// char port, notes ccci_monitor must be first
54{CCCI_MONITOR_CH, CCCI_MONITOR_CH, 0xFF, 0xFF, 0xFF, 0xFF, 4, &char_port_ops, 0, "ccci2_monitor", },
55{CCCI_PCM_TX, CCCI_PCM_RX, 0, 0, 0xFF, 0xFF, 4, &char_port_ops, 1, "ccci2_aud", },
56{CCCI_UART1_TX, CCCI_UART1_RX, 1, 1, 3, 3, 0, &char_port_ops, 2, "ccci2_md_log_ctrl", },
57{CCCI_UART2_TX, CCCI_UART2_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 3, "ccci2_tty0", },
58{CCCI_FS_TX, CCCI_FS_RX, 1, 1, 1, 1, 4, &char_port_ops, 4, "ccci2_fs", },
59{CCCI_IPC_UART_TX, CCCI_IPC_UART_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 5, "ccci2_tty2", },
60{CCCI_ICUSB_TX, CCCI_ICUSB_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 6, "ccci2_tty3", },
61{CCCI_MD_LOG_TX, CCCI_MD_LOG_RX, 2, 2, 2, 2, 8, &char_port_ops, 7, "ccci2_tty1", },
62{CCCI_IMSV_UL, CCCI_IMSV_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 8, "ccci2_imsv", },
63{CCCI_IMSC_UL, CCCI_IMSC_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 9, "ccci2_imsc", },
64{CCCI_IMSA_UL, CCCI_IMSA_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 10, "ccci2_imsa", },
65{CCCI_IMSDC_UL, CCCI_IMSDC_DL, 6, 6, 0xFF, 0xFF, 0, &char_port_ops, 11, "ccci2_imsdc", },
66{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 12, "ccci2_ioctl0", },
67{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 13, "ccci2_ioctl1", },
68{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 14, "ccci2_ioctl2", },
69{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 15, "ccci2_ioctl3", },
70{CCCI_DUMMY_CH, CCCI_DUMMY_CH, 0xFF, 0xFF, 0xFF, 0xFF, 0, &char_port_ops, 16, "ccci2_ioctl4", },
71{CCCI_IT_TX, CCCI_IT_RX, 0, 0, 0xFF, 0xFF, 4, &char_port_ops, 17, "ccci2_it", },
72{CCCI_LB_IT_TX, CCCI_LB_IT_RX, 0, 0, 0xFF, 0xFF, 0, &char_port_ops, 18, "ccci2_lb_it", },
73{CCCI_RPC_TX, CCCI_RPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 19, "ccci2_rpc", },
74// IPC char port minor= minor idx + CCCI_IPC_MINOR_BASE(100)
75{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 0, "ccci2_ipc_0", },
76{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 2, "ccci2_ipc_2", },
77//IPC kernel port
78{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &ipc_kern_port_ops, 3, "ccci2_ipc_3", },
79{CCCI_IPC_TX, CCCI_IPC_RX, 1, 1, 0xFF, 0xFF, 0, &char_port_ops, 4, "ccci2_ipc_4", },
80
81// sys port
82{CCCI_CONTROL_TX, CCCI_CONTROL_RX, 0, 0, 0, 0, 0, &kernel_port_ops, 0, "ccci2_ctrl", },
83{CCCI_SYSTEM_TX, CCCI_SYSTEM_RX, 0, 0, 0xFF, 0xFF, 0, &kernel_port_ops, 0, "ccci2_sys", },
84{CCCI_STATUS_TX, CCCI_STATUS_RX, 0, 0, 0, 0, 0, &kernel_port_ops, 0, "ccci_poll", },
85// network port
86{CCCI_CCMNI1_TX, CCCI_CCMNI1_RX, 3, 3, 0xF4, 0xFF, 8, &net_port_ops, 0, "cc2mni0", },
87{CCCI_CCMNI2_TX, CCCI_CCMNI2_RX, 3, 4, 0xF4, 0xFF, 8, &net_port_ops, 0, "cc2mni1", },
88{CCCI_CCMNI3_TX, CCCI_CCMNI3_RX, 5, 5, 0xFF, 0xFF, 8, &net_port_ops, 0, "cc2mni2", },
89};
90
91#endif
92
93int md_port_cfg(struct ccci_modem *md)
94{
95 switch(md->index)
96 {
97#ifdef CONFIG_MTK_ENABLE_MD1
98 case MD_SYS1:
99 md->ports = md1_ccci_ports;
100 md->port_number = ARRAY_SIZE(md1_ccci_ports);
101 break;
102#endif
103#ifdef CONFIG_MTK_ENABLE_MD2
104 case MD_SYS2:
105 md->ports = md2_ccci_ports;
106 md->port_number = ARRAY_SIZE(md2_ccci_ports);
107 break;
108#endif
109 default:
110 md->ports = NULL;
111 md->port_number =0;
112 CCCI_ERR_MSG(md->index, TAG, "md_port_cfg:no md enable\n");
113 return -1;
114 }
115 return 0;
116}
117
kernel source for telekom puls (alcatel/mediatek)