projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 6fa3eb70 S |
1 | #ifndef __DDP_DRV_H__ |
| 2 | #define __DDP_DRV_H__ | |
| 3 | #include <linux/ioctl.h> | |
| 4 | #include "ddp_hal.h" | |
| 5 | #include "ddp_aal.h" | |
| 6 | ||
| 7 | typedef enum DISP_MODULE_ENUM_ | |
| 8 | { | |
| 9 | DISP_MODULE_OVL, | |
| 10 | DISP_MODULE_COLOR, | |
| 11 | DISP_MODULE_BLS, | |
| 12 | DISP_MODULE_WDMA, | |
| 13 | DISP_MODULE_RDMA0, | |
| 14 | DISP_MODULE_RDMA1, //5 | |
| 15 | DISP_MODULE_DPI0, | |
| 16 | DISP_MODULE_DPI1, | |
| 17 | DISP_MODULE_DBI, | |
| 18 | DISP_MODULE_DSI_CMD, | |
| 19 | DISP_MODULE_DSI_VDO, //10 | |
| 20 | DISP_MODULE_CONFIG, | |
| 21 | DISP_MODULE_MUTEX, | |
| 22 | DISP_MODULE_CMDQ, | |
| 23 | DISP_MODULE_G2D, //20 | |
| 24 | DISP_MODULE_SMI, // For interrupt handling | |
| 25 | DISP_MODULE_MDP_ROT, | |
| 26 | DISP_MODULE_MDP_SCL, | |
| 27 | DISP_MODULE_MDP_WDMA, | |
| 28 | DISP_MODULE_MAX | |
| 29 | } DISP_MODULE_ENUM; | |
| 30 | ||
| 31 | ||
| 32 | typedef struct | |
| 33 | { | |
| 34 | unsigned int reg; | |
| 35 | unsigned int val; | |
| 36 | unsigned int mask; | |
| 37 | } DISP_WRITE_REG; | |
| 38 | ||
| 39 | typedef struct | |
| 40 | { | |
| 41 | unsigned int reg; | |
| 42 | unsigned int val; | |
| 43 | unsigned int mask; | |
| 44 | } DISP_READ_REG; | |
| 45 | ||
| 46 | typedef struct | |
| 47 | { | |
| 48 | unsigned int count; | |
| 49 | unsigned int *reg; | |
| 50 | unsigned int *mask; | |
| 51 | unsigned int *val; | |
| 52 | } DISP_READ_REG_TABLE; | |
| 53 | ||
| 54 | ||
| 55 | #if 0 | |
| 56 | typedef enum | |
| 57 | { | |
| 58 | DDP_YUYV , | |
| 59 | DDP_UYVY , | |
| 60 | DDP_YVYU , | |
| 61 | DDP_VYUY , | |
| 62 | ||
| 63 | DDP_YUV444 , | |
| 64 | ||
| 65 | DDP_RGB565 , // 14 | |
| 66 | DDP_RGB888 , // 15 | |
| 67 | DDP_ARGB8888 , // 16 | |
| 68 | DDP_ABGR8888 , // 17 | |
| 69 | ||
| 70 | DDP_RGBA8888, | |
| 71 | DDP_BGRA8888, | |
| 72 | ||
| 73 | DDP_PARGB8888 , | |
| 74 | DDP_XARGB8888 , | |
| 75 | DDP_NONE_FMT | |
| 76 | } DDP_OVL_FORMAT; | |
| 77 | #endif | |
| 78 | ||
| 79 | ||
| 80 | /* | |
| 81 | * CMDQ sec address metadata: | |
| 82 | * replase (_d)th instruciton to sec_addr, sec_addr = hadnle_sec_base_addr(baseHandle, isMva) + offset(_b) | |
| 83 | */ | |
| 84 | typedef struct | |
| 85 | { | |
| 86 | uint32_t instrIndex; // _d, index of instruction, which will be replace instruciton value in secure world | |
| 87 | uint32_t baseHandle; // _h, secure handle | |
| 88 | uint32_t offset; // _b, buffser offset to secure handle | |
| 89 | bool isMVA; // true, if address has to config as mva | |
| 90 | uint32_t size; // buffer size | |
| 91 | uint32_t port; // hw port | |
| 92 | } DISP_SEC_ADDR_METADATA; | |
| 93 | ||
| 94 | /* | |
| 95 | * CMDQ sec port metadata: | |
| 96 | * config HW port to sec/non-sec, useMva or not | |
| 97 | */ | |
| 98 | typedef struct | |
| 99 | { | |
| 100 | uint32_t port; | |
| 101 | bool useMVA; // true, if HW engine acccess mva, not PA | |
| 102 | }DISP_SEC_PORT_METADATA; | |
| 103 | ||
| 104 | ||
| 105 | typedef struct DISP_EXEC_COMMAND | |
| 106 | { | |
| 107 | int taskID; | |
| 108 | uint32_t scenario; | |
| 109 | uint32_t priority; | |
| 110 | uint32_t engineFlag; | |
| 111 | uint32_t *pFrameBaseSW; | |
| 112 | uint32_t *pTileBaseSW; | |
| 113 | uint32_t blockSize; | |
| 114 | } DISP_EXEC_COMMAND; | |
| 115 | ||
| 116 | typedef struct DISP_EXEC_SEC_METADATA | |
| 117 | { | |
| 118 | uint32_t addrListLength; | |
| 119 | uint32_t portListLength; | |
| 120 | void* addrList; | |
| 121 | void* portList; | |
| 122 | ||
| 123 | // discarded! | |
| 124 | // the following will be phased out latter | |
| 125 | uint32_t totalSecureFd; | |
| 126 | uint32_t *pSecureFdIndex; | |
| 127 | uint32_t *pSecurePortList; | |
| 128 | uint32_t *pSecureSizeList; | |
| 129 | }DISP_EXEC_SEC_METADATA; | |
| 130 | ||
| 131 | typedef struct DISP_EXEC_SEC_COMMAND | |
| 132 | { | |
| 133 | struct DISP_EXEC_COMMAND command; | |
| 134 | struct DISP_EXEC_SEC_METADATA metadata; | |
| 135 | } DISP_EXEC_SEC_COMMAND; | |
| 136 | ||
| 137 | typedef struct | |
| 138 | { | |
| 139 | int layer; | |
| 140 | ||
| 141 | unsigned int addr; | |
| 142 | DpColorFormat fmt; | |
| 143 | ||
| 144 | int x; | |
| 145 | int y; | |
| 146 | int w; | |
| 147 | int h; // clip region | |
| 148 | int pitch; | |
| 149 | } DISP_OVL_INFO; | |
| 150 | ||
| 151 | ||
| 152 | //PQ | |
| 153 | #define COLOR_TUNING_INDEX 19 | |
| 154 | #define THSHP_TUNING_INDEX 12 | |
| 155 | #define THSHP_PARAM_MAX 52 | |
| 156 | ||
| 157 | ||
| 158 | #define PARTIAL_Y_SIZE 28 | |
| 159 | #define PQ_HUE_ADJ_PHASE_CNT 4 | |
| 160 | #define PQ_SAT_ADJ_PHASE_CNT 4 | |
| 161 | #define PQ_PARTIALS_CONTROL 5 | |
| 162 | #define PURP_TONE_SIZE 3 | |
| 163 | #define SKIN_TONE_SIZE 8 //(-6) | |
| 164 | #define GRASS_TONE_SIZE 6 //(-2) | |
| 165 | #define SKY_TONE_SIZE 3 | |
| 166 | ||
| 167 | typedef struct { | |
| 168 | unsigned long u4SHPGain;// 0 : min , 9 : max. | |
| 169 | unsigned long u4SatGain;// 0 : min , 9 : max. | |
| 170 | unsigned long u4HueAdj[PQ_HUE_ADJ_PHASE_CNT]; | |
| 171 | unsigned long u4SatAdj[PQ_SAT_ADJ_PHASE_CNT]; | |
| 172 | } DISP_PQ_PARAM; | |
| 173 | ||
| 174 | typedef struct{ | |
| 175 | ||
| 176 | unsigned char GLOBAL_SAT [COLOR_TUNING_INDEX]; | |
| 177 | unsigned char PURP_TONE_S [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][PURP_TONE_SIZE]; | |
| 178 | unsigned char SKIN_TONE_S [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][SKIN_TONE_SIZE]; | |
| 179 | unsigned char GRASS_TONE_S [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][GRASS_TONE_SIZE]; | |
| 180 | unsigned char SKY_TONE_S [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][SKY_TONE_SIZE]; | |
| 181 | unsigned char PURP_TONE_H [COLOR_TUNING_INDEX][PURP_TONE_SIZE]; | |
| 182 | unsigned char SKIN_TONE_H [COLOR_TUNING_INDEX][SKIN_TONE_SIZE]; | |
| 183 | unsigned char GRASS_TONE_H [COLOR_TUNING_INDEX][GRASS_TONE_SIZE]; | |
| 184 | unsigned char SKY_TONE_H [COLOR_TUNING_INDEX][SKY_TONE_SIZE]; | |
| 185 | ||
| 186 | } DISPLAY_PQ_T; | |
| 187 | ||
| 188 | typedef struct{ | |
| 189 | ||
| 190 | unsigned long entry[3][257]; | |
| 191 | ||
| 192 | } DISPLAY_GAMMA_T; | |
| 193 | ||
| 194 | typedef struct{ | |
| 195 | ||
| 196 | unsigned int entry[THSHP_TUNING_INDEX][THSHP_PARAM_MAX]; | |
| 197 | ||
| 198 | } DISPLAY_TDSHP_T; | |
| 199 | ||
| 200 | ||
| 201 | #define PWM_LUT_ENTRY 33 | |
| 202 | #define PWM_LUT_ENTRY_BIT 12 | |
| 203 | typedef struct{ | |
| 204 | unsigned long entry[PWM_LUT_ENTRY]; | |
| 205 | } DISPLAY_PWM_T; | |
| 206 | ||
| 207 | ||
| 208 | typedef enum | |
| 209 | { | |
| 210 | DISP_INTERLACE_FORMAT_NONE, | |
| 211 | DISP_INTERLACE_FORMAT_TOP_FIELD, | |
| 212 | DISP_INTERLACE_FORMAT_BOTTOM_FIELD | |
| 213 | }DISP_INTERLACE_FORMAT; | |
| 214 | ||
| 215 | #if 0 | |
| 216 | typedef enum | |
| 217 | { | |
| 218 | DISP_COLOR_FORMAT_YUV_420_3P , // 0 | |
| 219 | DISP_COLOR_FORMAT_YUV_420_2P_YUYV , | |
| 220 | DISP_COLOR_FORMAT_YUV_420_2P_UYVY , | |
| 221 | DISP_COLOR_FORMAT_YUV_420_2P_YVYU , | |
| 222 | DISP_COLOR_FORMAT_YUV_420_2P_VYUY , | |
| 223 | DISP_COLOR_FORMAT_YUV_420_2P_ISP_BLK , // 5 | |
| 224 | DISP_COLOR_FORMAT_YUV_420_2P_VDO_BLK , | |
| 225 | DISP_COLOR_FORMAT_YUV_422_3P , | |
| 226 | DISP_COLOR_FORMAT_YUV_422_2P , | |
| 227 | DISP_COLOR_FORMAT_YUV_422_I , | |
| 228 | DISP_COLOR_FORMAT_YUV_422_I_BLK , // 10 | |
| 229 | DISP_COLOR_FORMAT_YUV_444_3P , | |
| 230 | DISP_COLOR_FORMAT_YUV_444_2P , | |
| 231 | DISP_COLOR_FORMAT_YUV_444_1P , | |
| 232 | ||
| 233 | DISP_COLOR_FORMAT_RGB565 , // 14 | |
| 234 | DISP_COLOR_FORMAT_RGB888 , // 15 | |
| 235 | DISP_COLOR_FORMAT_ARGB8888 , // 16 | |
| 236 | DISP_COLOR_FORMAT_ABGR8888 , // 17 | |
| 237 | ||
| 238 | DISP_COLOR_FORMAT_RGBA8888, | |
| 239 | DISP_COLOR_FORMAT_BGRA8888, | |
| 240 | ||
| 241 | DISP_COLOR_FORMAT_PARGB8888 , | |
| 242 | DISP_COLOR_FORMAT_XARGB8888 , | |
| 243 | ||
| 244 | DISP_COLOR_FORMAT_MTKYUV, | |
| 245 | DISP_COLOR_FORMAT_YUV_420_3P_YVU | |
| 246 | }DISP_COLOR_FORMAT; | |
| 247 | #endif | |
| 248 | ||
| 249 | struct disp_mva_map | |
| 250 | { | |
| 251 | DISP_MODULE_ENUM module; | |
| 252 | unsigned int cache_coherent; | |
| 253 | unsigned int addr; | |
| 254 | unsigned int size; | |
| 255 | }; | |
| 256 | ||
| 257 | ||
| 258 | ||
| 259 | #define DISP_IOCTL_MAGIC 'x' | |
| 260 | ||
| 261 | #define DISP_IOCTL_WRITE_REG _IOW (DISP_IOCTL_MAGIC, 1, DISP_WRITE_REG) | |
| 262 | #define DISP_IOCTL_READ_REG _IOWR (DISP_IOCTL_MAGIC, 2, DISP_READ_REG) | |
| 263 | #define DISP_IOCTL_WAIT_IRQ _IOR (DISP_IOCTL_MAGIC, 3, disp_wait_irq_struct) | |
| 264 | #define DISP_IOCTL_DUMP_REG _IOR (DISP_IOCTL_MAGIC, 4, int) | |
| 265 | #define DISP_IOCTL_LOCK_THREAD _IOR (DISP_IOCTL_MAGIC, 5, int) | |
| 266 | #define DISP_IOCTL_UNLOCK_THREAD _IOR (DISP_IOCTL_MAGIC, 6, int) | |
| 267 | #define DISP_IOCTL_MARK_CMQ _IOR (DISP_IOCTL_MAGIC, 7, int) | |
| 268 | #define DISP_IOCTL_WAIT_CMQ _IOR (DISP_IOCTL_MAGIC, 8, int) | |
| 269 | #define DISP_IOCTL_SYNC_REG _IOR (DISP_IOCTL_MAGIC, 9, int) | |
| 270 | ||
| 271 | #define DISP_IOCTL_LOCK_MUTEX _IOW (DISP_IOCTL_MAGIC, 20, int) | |
| 272 | #define DISP_IOCTL_UNLOCK_MUTEX _IOR (DISP_IOCTL_MAGIC, 21, int) | |
| 273 | ||
| 274 | #define DISP_IOCTL_LOCK_RESOURCE _IOW (DISP_IOCTL_MAGIC, 25, int) | |
| 275 | #define DISP_IOCTL_UNLOCK_RESOURCE _IOR (DISP_IOCTL_MAGIC, 26, int) | |
| 276 | ||
| 277 | #define DISP_IOCTL_SET_INTR _IOR (DISP_IOCTL_MAGIC, 10, int) | |
| 278 | #define DISP_IOCTL_TEST_PATH _IOR (DISP_IOCTL_MAGIC, 11, int) | |
| 279 | ||
| 280 | #define DISP_IOCTL_CLOCK_ON _IOR (DISP_IOCTL_MAGIC, 12, int) | |
| 281 | #define DISP_IOCTL_CLOCK_OFF _IOR (DISP_IOCTL_MAGIC, 13, int) | |
| 282 | ||
| 283 | #define DISP_IOCTL_RUN_DPF _IOW (DISP_IOCTL_MAGIC, 30, int) | |
| 284 | #define DISP_IOCTL_CHECK_OVL _IOR (DISP_IOCTL_MAGIC, 31, int) | |
| 285 | #define DISP_IOCTL_GET_OVL _IOWR (DISP_IOCTL_MAGIC, 32, DISP_OVL_INFO) | |
| 286 | ||
| 287 | #define DISP_IOCTL_EXEC_COMMAND _IOW (DISP_IOCTL_MAGIC, 33, DISP_EXEC_COMMAND) | |
| 288 | #define DISP_IOCTL_RESOURCE_REQUIRE _IOR (DISP_IOCTL_MAGIC, 34, int) | |
| 289 | #define DISP_IOCTL_EXEC_COMMAND_SECURE _IOW (DISP_IOCTL_MAGIC, 35, DISP_EXEC_SEC_COMMAND) | |
| 290 | #define DISP_IOCTL_CMDQ_SEC_TEST _IOR (DISP_IOCTL_MAGIC, 36, int) | |
| 291 | ||
| 292 | ||
| 293 | ||
| 294 | //Add for AAL control - S | |
| 295 | //0 : disable AAL event, 1 : enable AAL event | |
| 296 | #define DISP_IOCTL_AAL_EVENTCTL _IOW (DISP_IOCTL_MAGIC, 15 , int) | |
| 297 | //Get AAL statistics data. | |
| 298 | #define DISP_IOCTL_GET_AALSTATISTICS _IOR (DISP_IOCTL_MAGIC, 16 , DISP_AAL_STATISTICS) | |
| 299 | //Update AAL setting | |
| 300 | #define DISP_IOCTL_SET_AALPARAM _IOW (DISP_IOCTL_MAGIC, 17 , DISP_AAL_PARAM) | |
| 301 | //Update PQ setting | |
| 302 | #define DISP_IOCTL_SET_PQPARAM _IOW (DISP_IOCTL_MAGIC, 18 , DISP_PQ_PARAM) | |
| 303 | #define DISP_IOCTL_SET_PQINDEX _IOW (DISP_IOCTL_MAGIC, 19 , DISPLAY_PQ_T) | |
| 304 | #define DISP_IOCTL_SET_GAMMALUT _IOW (DISP_IOCTL_MAGIC, 20 , DISPLAY_GAMMA_T) | |
| 305 | //Update BLS setting | |
| 306 | #define DISP_IOCTL_SET_PWMLUT _IOW (DISP_IOCTL_MAGIC, 22 , DISPLAY_PWM_T) | |
| 307 | ||
| 308 | //Add for AAL control - E | |
| 309 | /*----------------------------------------------------------------------------- | |
| 310 | DDP Kernel Mode API (for Kernel Trap) | |
| 311 | -----------------------------------------------------------------------------*/ | |
| 312 | //DDPK Bitblit | |
| 313 | //#define DISP_IOCTL_G_WAIT_REQUEST _IOR (DISP_IOCTL_MAGIC , 40 , DDPIOCTL_DdpkBitbltConfig) | |
| 314 | //#define DISP_IOCTL_T_INFORM_DONE _IOW (DISP_IOCTL_MAGIC , 41 , DDPIOCTL_DdpkBitbltInformDone) | |
| 315 | ||
| 316 | #define DISP_IOCTL_SET_CLKON _IOW (DISP_IOCTL_MAGIC, 50 , DISP_MODULE_ENUM) | |
| 317 | #define DISP_IOCTL_SET_CLKOFF _IOW (DISP_IOCTL_MAGIC, 51 , DISP_MODULE_ENUM) | |
| 318 | ||
| 319 | //Get PQ setting | |
| 320 | #define DISP_IOCTL_GET_PQPARAM _IOR (DISP_IOCTL_MAGIC, 52 , DISP_PQ_PARAM) | |
| 321 | #define DISP_IOCTL_SET_TDSHPINDEX _IOW (DISP_IOCTL_MAGIC, 53 , DISPLAY_TDSHP_T) | |
| 322 | #define DISP_IOCTL_GET_TDSHPINDEX _IOR (DISP_IOCTL_MAGIC, 54 , DISPLAY_TDSHP_T) | |
| 323 | #define DISP_IOCTL_MUTEX_CONTROL _IOW (DISP_IOCTL_MAGIC, 55 , int) | |
| 324 | #define DISP_IOCTL_GET_LCMINDEX _IOR (DISP_IOCTL_MAGIC, 56 , int) | |
| 325 | #define DISP_IOCTL_SET_PQ_CAM_PARAM _IOW (DISP_IOCTL_MAGIC, 57 , DISP_PQ_PARAM) | |
| 326 | #define DISP_IOCTL_GET_PQ_CAM_PARAM _IOR (DISP_IOCTL_MAGIC, 58 , DISP_PQ_PARAM) | |
| 327 | #define DISP_IOCTL_SET_PQ_GAL_PARAM _IOW (DISP_IOCTL_MAGIC, 59 , DISP_PQ_PARAM) | |
| 328 | #define DISP_IOCTL_GET_PQ_GAL_PARAM _IOR (DISP_IOCTL_MAGIC, 60 , DISP_PQ_PARAM) | |
| 329 | ||
| 330 | #define DISP_IOCTL_READ_REG_TABLE _IOWR (DISP_IOCTL_MAGIC, 61, DISP_READ_REG_TABLE) | |
| 331 | ||
| 332 | #define DISP_SECURE_MVA_MAP _IOW (DISP_IOCTL_MAGIC, 80 , struct disp_mva_map) | |
| 333 | #define DISP_SECURE_MVA_UNMAP _IOW (DISP_IOCTL_MAGIC, 81 , struct disp_mva_map) | |
| 334 | ||
| 335 | #define DISP_SECURE_SET_MODE_BITBLT _IOW (DISP_IOCTL_MAGIC, 82 , enum DpSecure) | |
| 336 | #define DISP_SECURE_SET_MODE_OVL_MEM_OUT _IOW (DISP_IOCTL_MAGIC, 83 , enum DpSecure) | |
| 337 | ||
| 338 | ||
| 339 | // secure video path implementation: the handle value | |
| 340 | #define DISP_IOCTL_SET_TPLAY_HANDLE _IOW (DISP_IOCTL_MAGIC, 200, unsigned int) | |
| 341 | ||
| 342 | typedef struct | |
| 343 | { | |
| 344 | DISP_MODULE_ENUM module; | |
| 345 | unsigned int timeout_ms; //timeout, unit is ms | |
| 346 | } disp_wait_irq_struct; | |
| 347 | ||
| 348 | #ifdef __KERNEL__ | |
| 349 | typedef void (*DDP_IRQ_CALLBACK)(unsigned int param); | |
| 350 | ||
| 351 | //------------------------------------------------------- | |
| 352 | // functions | |
| 353 | //------------------------------------------------------- | |
| 354 | void disp_aal_lock(void); | |
| 355 | void disp_aal_unlock(void); | |
| 356 | int disp_register_irq(DISP_MODULE_ENUM module, DDP_IRQ_CALLBACK cb); | |
| 357 | int disp_unregister_irq(DISP_MODULE_ENUM module, DDP_IRQ_CALLBACK cb); | |
| 358 | void cmdq_ion_flush(void); | |
| 359 | ||
| 360 | int disp_dump_reg(DISP_MODULE_ENUM module); | |
| 361 | void disp_print_reg(DISP_MODULE_ENUM module); | |
| 362 | int disp_clock_check(void); | |
| 363 | ||
| 364 | int disp_color_set_pq_param(void* arg); | |
| 365 | ||
| 366 | int disp_module_clock_on(DISP_MODULE_ENUM module, char* caller_name); | |
| 367 | int disp_module_clock_off(DISP_MODULE_ENUM module, char* caller_name); | |
| 368 | void disp_register_rdma1_irq(void); | |
| 369 | void disp_unregister_rdma1_irq(void); | |
| 370 | ||
| 371 | #endif | |
| 372 | ||
| 373 | #endif |