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[media] tvaudio: don't use thread for TA8874Z
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / tvaudio.c
CommitLineData
1da177e4 1/*
b4ab114c 2 * Driver for simple i2c audio chips.
1da177e4
LT		 3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
b4ab114c
MCC		 10 * Copyright(c) 2005-2008 Mauro Carvalho Chehab
11 * - Some cleanups, code fixes, etc
12 * - Convert it to V4L2 API
13 *
1da177e4
LT		 14 * This code is placed under the terms of the GNU General Public License
15 *
16 * OPTIONS:
17 * debug - set to 1 if you'd like to see debug messages
18 *
19 */
20
1da177e4 21#include <linux/module.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/timer.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
7f6adeaf 29#include <linux/videodev2.h>
1da177e4 30#include <linux/i2c.h>
1da177e4 31#include <linux/init.h>
bc282879 32#include <linux/kthread.h>
7dfb7103 33#include <linux/freezer.h>
1da177e4 34
8bf2f8e7 35#include <media/tvaudio.h>
64f70e7e 36#include <media/v4l2-device.h>
74cab31c 37#include <media/v4l2-chip-ident.h>
1da177e4 38
7c9b5048 39#include <media/i2c-addr.h>
1da177e4
LT		 40
41/* ---------------------------------------------------------------------- */
42/* insmod args */
43
ff699e6b 44static int debug; /* insmod parameter */
1da177e4
LT		 45module_param(debug, int, 0644);
46
47MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
48MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
49MODULE_LICENSE("GPL");
50
51#define UNSET (-1U)
18fc59e2 52
1da177e4
LT		 53/* ---------------------------------------------------------------------- */
54/* our structs */
55
4c6c390e 56#define MAXREGS 256
1da177e4
LT		 57
58struct CHIPSTATE;
59typedef int (*getvalue)(int);
60typedef int (*checkit)(struct CHIPSTATE*);
61typedef int (*initialize)(struct CHIPSTATE*);
62typedef int (*getmode)(struct CHIPSTATE*);
63typedef void (*setmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 64
65/* i2c command */
66typedef struct AUDIOCMD {
67 int count; /* # of bytes to send */
68 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
69} audiocmd;
70
71/* chip description */
72struct CHIPDESC {
73 char *name; /* chip name */
1da177e4
LT		 74 int addr_lo, addr_hi; /* i2c address range */
75 int registers; /* # of registers */
76
77 int *insmodopt;
78 checkit checkit;
79 initialize initialize;
80 int flags;
81#define CHIP_HAS_VOLUME 1
82#define CHIP_HAS_BASSTREBLE 2
83#define CHIP_HAS_INPUTSEL 4
dd03e970 84#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 85
86 /* various i2c command sequences */
87 audiocmd init;
88
89 /* which register has which value */
90 int leftreg,rightreg,treblereg,bassreg;
91
92 /* initialize with (defaults to 65535/65535/32768/32768 */
93 int leftinit,rightinit,trebleinit,bassinit;
94
95 /* functions to convert the values (v4l -> chip) */
96 getvalue volfunc,treblefunc,bassfunc;
97
98 /* get/set mode */
99 getmode getmode;
100 setmode setmode;
101
1da177e4
LT		 102 /* input switch register + values for v4l inputs */
103 int inputreg;
8bf2f8e7 104 int inputmap[4];
1da177e4
LT		 105 int inputmute;
106 int inputmask;
107};
1da177e4
LT		 108
109/* current state of the chip */
110struct CHIPSTATE {
64f70e7e 111 struct v4l2_subdev sd;
1da177e4 112
81cb5c4f
MCC		 113 /* chip-specific description - should point to
114 an entry at CHIPDESC table */
115 struct CHIPDESC *desc;
1da177e4
LT		 116
117 /* shadow register set */
118 audiocmd shadow;
119
120 /* current settings */
8bf2f8e7 121 __u16 left,right,treble,bass,muted,mode;
1da177e4 122 int prevmode;
8a854284 123 int radio;
8bf2f8e7 124 int input;
1da177e4
LT		 125
126 /* thread */
bc282879 127 struct task_struct *thread;
1da177e4 128 struct timer_list wt;
8a4b275f 129 int audmode;
1da177e4
LT		 130};
131
64f70e7e
HV		 132static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
133{
134 return container_of(sd, struct CHIPSTATE, sd);
135}
136
1da177e4 137
1da177e4
LT		 138/* ---------------------------------------------------------------------- */
139/* i2c I/O functions */
140
141static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
142{
64f70e7e
HV		 143 struct v4l2_subdev *sd = &chip->sd;
144 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 145 unsigned char buffer[2];
146
49426437 147 if (subaddr < 0) {
64f70e7e 148 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
1da177e4
LT		 149 chip->shadow.bytes[1] = val;
150 buffer[0] = val;
64f70e7e
HV		 151 if (1 != i2c_master_send(c, buffer, 1)) {
152 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
1da177e4
LT		 153 return -1;
154 }
155 } else {
49426437 156 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 157 v4l2_info(sd,
49426437
MCC		 158 "Tried to access a non-existent register: %d\n",
159 subaddr);
160 return -EINVAL;
161 }
162
64f70e7e
HV		 163 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
164 subaddr, val);
1da177e4
LT		 165 chip->shadow.bytes[subaddr+1] = val;
166 buffer[0] = subaddr;
167 buffer[1] = val;
64f70e7e
HV		 168 if (2 != i2c_master_send(c, buffer, 2)) {
169 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
170 subaddr, val);
1da177e4
LT		 171 return -1;
172 }
173 }
174 return 0;
175}
176
49426437
MCC		 177static int chip_write_masked(struct CHIPSTATE *chip,
178 int subaddr, int val, int mask)
1da177e4 179{
64f70e7e
HV		 180 struct v4l2_subdev *sd = &chip->sd;
181
1da177e4 182 if (mask != 0) {
49426437 183 if (subaddr < 0) {
1da177e4
LT		 184 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
185 } else {
49426437 186 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 187 v4l2_info(sd,
49426437
MCC		 188 "Tried to access a non-existent register: %d\n",
189 subaddr);
190 return -EINVAL;
191 }
192
1da177e4
LT		 193 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
194 }
195 }
196 return chip_write(chip, subaddr, val);
197}
198
199static int chip_read(struct CHIPSTATE *chip)
200{
64f70e7e
HV		 201 struct v4l2_subdev *sd = &chip->sd;
202 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 203 unsigned char buffer;
204
64f70e7e
HV		 205 if (1 != i2c_master_recv(c, &buffer, 1)) {
206 v4l2_warn(sd, "I/O error (read)\n");
1da177e4
LT		 207 return -1;
208 }
64f70e7e 209 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
1da177e4
LT		 210 return buffer;
211}
212
213static int chip_read2(struct CHIPSTATE *chip, int subaddr)
214{
64f70e7e
HV		 215 struct v4l2_subdev *sd = &chip->sd;
216 struct i2c_client *c = v4l2_get_subdevdata(sd);
18fc59e2
MCC		 217 unsigned char write[1];
218 unsigned char read[1];
219 struct i2c_msg msgs[2] = {
64f70e7e
HV		 220 { c->addr, 0, 1, write },
221 { c->addr, I2C_M_RD, 1, read }
18fc59e2 222 };
64f70e7e 223
18fc59e2 224 write[0] = subaddr;
1da177e4 225
64f70e7e
HV		 226 if (2 != i2c_transfer(c->adapter, msgs, 2)) {
227 v4l2_warn(sd, "I/O error (read2)\n");
1da177e4
LT		 228 return -1;
229 }
64f70e7e
HV		 230 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
231 subaddr, read[0]);
1da177e4
LT		 232 return read[0];
233}
234
235static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
236{
64f70e7e
HV		 237 struct v4l2_subdev *sd = &chip->sd;
238 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 239 int i;
240
241 if (0 == cmd->count)
242 return 0;
243
49426437 244 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 245 v4l2_info(sd,
49426437
MCC		 246 "Tried to access a non-existent register range: %d to %d\n",
247 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
248 return -EINVAL;
249 }
250
251 /* FIXME: it seems that the shadow bytes are wrong bellow !*/
252
1da177e4 253 /* update our shadow register set; print bytes if (debug > 0) */
64f70e7e
HV		 254 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
255 name, cmd->bytes[0]);
1da177e4 256 for (i = 1; i < cmd->count; i++) {
18fc59e2 257 if (debug)
64f70e7e 258 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
1da177e4
LT		 259 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
260 }
18fc59e2 261 if (debug)
64f70e7e 262 printk(KERN_CONT "\n");
1da177e4
LT		 263
264 /* send data to the chip */
64f70e7e
HV		 265 if (cmd->count != i2c_master_send(c, cmd->bytes, cmd->count)) {
266 v4l2_warn(sd, "I/O error (%s)\n", name);
1da177e4
LT		 267 return -1;
268 }
269 return 0;
270}
271
272/* ---------------------------------------------------------------------- */
273/* kernel thread for doing i2c stuff asyncronly
274 * right now it is used only to check the audio mode (mono/stereo/whatever)
275 * some time after switching to another TV channel, then turn on stereo
276 * if available, ...
277 */
278
279static void chip_thread_wake(unsigned long data)
280{
18fc59e2 281 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 282 wake_up_process(chip->thread);
1da177e4
LT		 283}
284
285static int chip_thread(void *data)
286{
18fc59e2 287 struct CHIPSTATE *chip = data;
81cb5c4f 288 struct CHIPDESC *desc = chip->desc;
64f70e7e 289 struct v4l2_subdev *sd = &chip->sd;
dd03e970 290 int mode;
1da177e4 291
64f70e7e 292 v4l2_dbg(1, debug, sd, "thread started\n");
83144186 293 set_freezable();
1da177e4 294 for (;;) {
bc282879
CLG		 295 set_current_state(TASK_INTERRUPTIBLE);
296 if (!kthread_should_stop())
1da177e4 297 schedule();
bc282879 298 set_current_state(TASK_RUNNING);
5e50e7a9 299 try_to_freeze();
bc282879 300 if (kthread_should_stop())
1da177e4 301 break;
64f70e7e 302 v4l2_dbg(1, debug, sd, "thread wakeup\n");
1da177e4
LT		 303
304 /* don't do anything for radio or if mode != auto */
8a854284 305 if (chip->radio || chip->mode != 0)
1da177e4
LT		 306 continue;
307
308 /* have a look what's going on */
dd03e970
MCC		 309 mode = desc->getmode(chip);
310 if (mode == chip->prevmode)
311 continue;
312
313 /* chip detected a new audio mode - set it */
64f70e7e 314 v4l2_dbg(1, debug, sd, "thread checkmode\n");
dd03e970
MCC		 315
316 chip->prevmode = mode;
317
318 if (mode & V4L2_TUNER_MODE_STEREO)
319 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
320 if (mode & V4L2_TUNER_MODE_LANG1_LANG2)
321 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
322 else if (mode & V4L2_TUNER_MODE_LANG1)
323 desc->setmode(chip, V4L2_TUNER_MODE_LANG1);
324 else if (mode & V4L2_TUNER_MODE_LANG2)
325 desc->setmode(chip, V4L2_TUNER_MODE_LANG2);
326 else
327 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1da177e4
LT		 328
329 /* schedule next check */
09df5cbe 330 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 331 }
332
64f70e7e 333 v4l2_dbg(1, debug, sd, "thread exiting\n");
1da177e4
LT		 334 return 0;
335}
336
1da177e4
LT		 337/* ---------------------------------------------------------------------- */
338/* audio chip descriptions - defines+functions for tda9840 */
339
340#define TDA9840_SW 0x00
341#define TDA9840_LVADJ 0x02
342#define TDA9840_STADJ 0x03
343#define TDA9840_TEST 0x04
344
345#define TDA9840_MONO 0x10
346#define TDA9840_STEREO 0x2a
347#define TDA9840_DUALA 0x12
348#define TDA9840_DUALB 0x1e
349#define TDA9840_DUALAB 0x1a
350#define TDA9840_DUALBA 0x16
351#define TDA9840_EXTERNAL 0x7a
352
353#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
354#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
355#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
356
357#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
358#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
359
360static int tda9840_getmode(struct CHIPSTATE *chip)
361{
64f70e7e 362 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 363 int val, mode;
364
365 val = chip_read(chip);
dc3d75da 366 mode = V4L2_TUNER_MODE_MONO;
1da177e4 367 if (val & TDA9840_DS_DUAL)
dc3d75da 368 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 369 if (val & TDA9840_ST_STEREO)
dc3d75da 370 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 371
64f70e7e 372 v4l2_dbg(1, debug, sd, "tda9840_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 373 val, mode);
1da177e4
LT		 374 return mode;
375}
376
377static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
378{
379 int update = 1;
380 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
381
382 switch (mode) {
dc3d75da 383 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 384 t |= TDA9840_MONO;
385 break;
dc3d75da 386 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 387 t |= TDA9840_STEREO;
388 break;
dc3d75da 389 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 390 t |= TDA9840_DUALA;
391 break;
dc3d75da 392 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 393 t |= TDA9840_DUALB;
394 break;
395 default:
396 update = 0;
397 }
398
399 if (update)
400 chip_write(chip, TDA9840_SW, t);
401}
402
94f9e56e
HV		 403static int tda9840_checkit(struct CHIPSTATE *chip)
404{
405 int rc;
406 rc = chip_read(chip);
407 /* lower 5 bits should be 0 */
408 return ((rc & 0x1f) == 0) ? 1 : 0;
409}
410
1da177e4
LT		 411/* ---------------------------------------------------------------------- */
412/* audio chip descriptions - defines+functions for tda985x */
413
414/* subaddresses for TDA9855 */
415#define TDA9855_VR 0x00 /* Volume, right */
416#define TDA9855_VL 0x01 /* Volume, left */
417#define TDA9855_BA 0x02 /* Bass */
418#define TDA9855_TR 0x03 /* Treble */
419#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
420
421/* subaddresses for TDA9850 */
422#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
423
424/* subaddesses for both chips */
425#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
426#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
427#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
428#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
429#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
430#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
431
432/* Masks for bits in TDA9855 subaddresses */
433/* 0x00 - VR in TDA9855 */
434/* 0x01 - VL in TDA9855 */
435/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
436 * in 1dB steps - mute is 0x27 */
437
438
439/* 0x02 - BA in TDA9855 */
440/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
441 * in .5dB steps - 0 is 0x0E */
442
443
444/* 0x03 - TR in TDA9855 */
445/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
446 * in 3dB steps - 0 is 0x7 */
447
448/* Masks for bits in both chips' subaddresses */
449/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
450/* Unique to TDA9855: */
451/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
452 * in 3dB steps - mute is 0x0 */
453
454/* Unique to TDA9850: */
455/* lower 4 bits control stereo noise threshold, over which stereo turns off
456 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
457
458
459/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
460/* Unique to TDA9855: */
461#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
462#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
463#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
464#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
465 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 466 * of line in and line out, only the
467 * interesting ones are defined */
1da177e4
LT		 468#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
469#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
470
471/* Unique to TDA9850: */
472/* lower 4 bits contol SAP noise threshold, over which SAP turns off
473 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
474
475
476/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
477/* Common to TDA9855 and TDA9850: */
478#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
479#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
480#define TDA985x_MONO 0 /* Forces Mono output */
481#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
482
483/* Unique to TDA9855: */
484#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
485#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
486#define TDA9855_LINEAR 0 /* Linear Stereo */
487#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
488#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
489#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
490#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
491
492/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
493/* Common to both TDA9855 and TDA9850: */
494/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
495 * in .5dB steps - 0dB is 0x7 */
496
497/* 0x08, 0x09 - A1 and A2 (read/write) */
498/* Common to both TDA9855 and TDA9850: */
499/* lower 5 bites are wideband and spectral expander alignment
500 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
501#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
502#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
503#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
504
505/* 0x0a - A3 */
506/* Common to both TDA9855 and TDA9850: */
507/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
508 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
509#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
510
511static int tda9855_volume(int val) { return val/0x2e8+0x27; }
512static int tda9855_bass(int val) { return val/0xccc+0x06; }
513static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
514
515static int tda985x_getmode(struct CHIPSTATE *chip)
516{
517 int mode;
518
519 mode = ((TDA985x_STP | TDA985x_SAPP) &
520 chip_read(chip)) >> 4;
521 /* Add mono mode regardless of SAP and stereo */
522 /* Allows forced mono */
dc3d75da 523 return mode | V4L2_TUNER_MODE_MONO;
1da177e4
LT		 524}
525
526static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
527{
528 int update = 1;
529 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
530
531 switch (mode) {
dc3d75da 532 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 533 c6 |= TDA985x_MONO;
534 break;
dc3d75da 535 case V4L2_TUNER_MODE_STEREO:
00fb1850 536 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 537 c6 |= TDA985x_STEREO;
538 break;
00fb1850 539 case V4L2_TUNER_MODE_SAP:
1da177e4
LT		 540 c6 |= TDA985x_SAP;
541 break;
542 default:
543 update = 0;
544 }
545 if (update)
546 chip_write(chip,TDA985x_C6,c6);
547}
548
549
550/* ---------------------------------------------------------------------- */
551/* audio chip descriptions - defines+functions for tda9873h */
552
553/* Subaddresses for TDA9873H */
554
555#define TDA9873_SW 0x00 /* Switching */
556#define TDA9873_AD 0x01 /* Adjust */
557#define TDA9873_PT 0x02 /* Port */
558
559/* Subaddress 0x00: Switching Data
560 * B7..B0:
561 *
562 * B1, B0: Input source selection
563 * 0, 0 internal
564 * 1, 0 external stereo
565 * 0, 1 external mono
566 */
567#define TDA9873_INP_MASK 3
568#define TDA9873_INTERNAL 0
569#define TDA9873_EXT_STEREO 2
570#define TDA9873_EXT_MONO 1
571
572/* B3, B2: output signal select
573 * B4 : transmission mode
574 * 0, 0, 1 Mono
575 * 1, 0, 0 Stereo
576 * 1, 1, 1 Stereo (reversed channel)
577 * 0, 0, 0 Dual AB
578 * 0, 0, 1 Dual AA
579 * 0, 1, 0 Dual BB
580 * 0, 1, 1 Dual BA
581 */
582
583#define TDA9873_TR_MASK (7 << 2)
584#define TDA9873_TR_MONO 4
585#define TDA9873_TR_STEREO 1 << 4
d59a14e2 586#define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
1da177e4
LT		 587#define TDA9873_TR_DUALA 1 << 2
588#define TDA9873_TR_DUALB 1 << 3
589
590/* output level controls
591 * B5: output level switch (0 = reduced gain, 1 = normal gain)
592 * B6: mute (1 = muted)
593 * B7: auto-mute (1 = auto-mute enabled)
594 */
595
596#define TDA9873_GAIN_NORMAL 1 << 5
597#define TDA9873_MUTE 1 << 6
598#define TDA9873_AUTOMUTE 1 << 7
599
600/* Subaddress 0x01: Adjust/standard */
601
602/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
603 * Recommended value is +0 dB
604 */
605
606#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
607
608/* Bits C6..C4 control FM stantard
609 * C6, C5, C4
610 * 0, 0, 0 B/G (PAL FM)
611 * 0, 0, 1 M
612 * 0, 1, 0 D/K(1)
613 * 0, 1, 1 D/K(2)
614 * 1, 0, 0 D/K(3)
615 * 1, 0, 1 I
616 */
617#define TDA9873_BG 0
618#define TDA9873_M 1
619#define TDA9873_DK1 2
620#define TDA9873_DK2 3
621#define TDA9873_DK3 4
622#define TDA9873_I 5
623
624/* C7 controls identification response time (1=fast/0=normal)
625 */
626#define TDA9873_IDR_NORM 0
627#define TDA9873_IDR_FAST 1 << 7
628
629
630/* Subaddress 0x02: Port data */
631
632/* E1, E0 free programmable ports P1/P2
633 0, 0 both ports low
634 0, 1 P1 high
635 1, 0 P2 high
636 1, 1 both ports high
637*/
638
639#define TDA9873_PORTS 3
640
641/* E2: test port */
642#define TDA9873_TST_PORT 1 << 2
643
644/* E5..E3 control mono output channel (together with transmission mode bit B4)
645 *
646 * E5 E4 E3 B4 OUTM
647 * 0 0 0 0 mono
648 * 0 0 1 0 DUAL B
649 * 0 1 0 1 mono (from stereo decoder)
650 */
651#define TDA9873_MOUT_MONO 0
652#define TDA9873_MOUT_FMONO 0
653#define TDA9873_MOUT_DUALA 0
654#define TDA9873_MOUT_DUALB 1 << 3
655#define TDA9873_MOUT_ST 1 << 4
d59a14e2 656#define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
1da177e4 657#define TDA9873_MOUT_EXTL 1 << 5
d59a14e2
DG		 658#define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
659#define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
660#define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
1da177e4
LT		 661
662/* Status bits: (chip read) */
663#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
664#define TDA9873_STEREO 2 /* Stereo sound is identified */
665#define TDA9873_DUAL 4 /* Dual sound is identified */
666
667static int tda9873_getmode(struct CHIPSTATE *chip)
668{
64f70e7e 669 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 670 int val,mode;
671
672 val = chip_read(chip);
dc3d75da 673 mode = V4L2_TUNER_MODE_MONO;
1da177e4 674 if (val & TDA9873_STEREO)
dc3d75da 675 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 676 if (val & TDA9873_DUAL)
dc3d75da 677 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
64f70e7e 678 v4l2_dbg(1, debug, sd, "tda9873_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 679 val, mode);
1da177e4
LT		 680 return mode;
681}
682
683static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
684{
64f70e7e 685 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 686 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
687 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
688
689 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
64f70e7e 690 v4l2_dbg(1, debug, sd, "tda9873_setmode(): external input\n");
1da177e4
LT		 691 return;
692 }
693
64f70e7e
HV		 694 v4l2_dbg(1, debug, sd, "tda9873_setmode(): chip->shadow.bytes[%d] = %d\n", TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
695 v4l2_dbg(1, debug, sd, "tda9873_setmode(): sw_data = %d\n", sw_data);
1da177e4
LT		 696
697 switch (mode) {
dc3d75da 698 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 699 sw_data |= TDA9873_TR_MONO;
700 break;
dc3d75da 701 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 702 sw_data |= TDA9873_TR_STEREO;
703 break;
dc3d75da 704 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 705 sw_data |= TDA9873_TR_DUALA;
706 break;
dc3d75da 707 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 708 sw_data |= TDA9873_TR_DUALB;
709 break;
710 default:
711 chip->mode = 0;
712 return;
713 }
714
715 chip_write(chip, TDA9873_SW, sw_data);
64f70e7e 716 v4l2_dbg(1, debug, sd, "tda9873_setmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 717 mode, sw_data);
718}
719
720static int tda9873_checkit(struct CHIPSTATE *chip)
721{
722 int rc;
723
724 if (-1 == (rc = chip_read2(chip,254)))
725 return 0;
726 return (rc & ~0x1f) == 0x80;
727}
728
729
730/* ---------------------------------------------------------------------- */
731/* audio chip description - defines+functions for tda9874h and tda9874a */
732/* Dariusz Kowalewski <darekk@automex.pl> */
733
734/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
735#define TDA9874A_AGCGR 0x00 /* AGC gain */
736#define TDA9874A_GCONR 0x01 /* general config */
737#define TDA9874A_MSR 0x02 /* monitor select */
738#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
739#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
740#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
741#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
742#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
743#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
744#define TDA9874A_DCR 0x09 /* demodulator config */
745#define TDA9874A_FMER 0x0a /* FM de-emphasis */
746#define TDA9874A_FMMR 0x0b /* FM dematrix */
747#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
748#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
749#define TDA9874A_NCONR 0x0e /* NICAM config */
750#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
751#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
752#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
753#define TDA9874A_AMCONR 0x12 /* audio mute control */
754#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
755#define TDA9874A_AOSR 0x14 /* analog output select */
756#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
757#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
758#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
759#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
760#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
761
762/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
763#define TDA9874A_DSR 0x00 /* device status */
764#define TDA9874A_NSR 0x01 /* NICAM status */
765#define TDA9874A_NECR 0x02 /* NICAM error count */
766#define TDA9874A_DR1 0x03 /* add. data LSB */
767#define TDA9874A_DR2 0x04 /* add. data MSB */
768#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
769#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
770#define TDA9874A_SIFLR 0x07 /* SIF level */
771#define TDA9874A_TR2 252 /* test reg. 2 */
772#define TDA9874A_TR1 253 /* test reg. 1 */
773#define TDA9874A_DIC 254 /* device id. code */
774#define TDA9874A_SIC 255 /* software id. code */
775
776
777static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
778static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
779static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
780static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
781static int tda9874a_dic = -1; /* device id. code */
782
783/* insmod options for tda9874a */
784static unsigned int tda9874a_SIF = UNSET;
785static unsigned int tda9874a_AMSEL = UNSET;
786static unsigned int tda9874a_STD = UNSET;
787module_param(tda9874a_SIF, int, 0444);
788module_param(tda9874a_AMSEL, int, 0444);
789module_param(tda9874a_STD, int, 0444);
790
791/*
792 * initialization table for tda9874 decoder:
793 * - carrier 1 freq. registers (3 bytes)
794 * - carrier 2 freq. registers (3 bytes)
795 * - demudulator config register
796 * - FM de-emphasis register (slow identification mode)
797 * Note: frequency registers must be written in single i2c transfer.
798 */
799static struct tda9874a_MODES {
800 char *name;
801 audiocmd cmd;
802} tda9874a_modelist[9] = {
04e6f990 803 { "A2, B/G", /* default */
1da177e4
LT		 804 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
805 { "A2, M (Korea)",
806 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
807 { "A2, D/K (1)",
808 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
809 { "A2, D/K (2)",
810 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
811 { "A2, D/K (3)",
812 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
813 { "NICAM, I",
814 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
815 { "NICAM, B/G",
816 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 817 { "NICAM, D/K",
1da177e4
LT		 818 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
819 { "NICAM, L",
820 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
821};
822
823static int tda9874a_setup(struct CHIPSTATE *chip)
824{
64f70e7e
HV		 825 struct v4l2_subdev *sd = &chip->sd;
826
1da177e4
LT		 827 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
828 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
829 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
830 if(tda9874a_dic == 0x11) {
831 chip_write(chip, TDA9874A_FMMR, 0x80);
832 } else { /* dic == 0x07 */
833 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
834 chip_write(chip, TDA9874A_FMMR, 0x00);
835 }
836 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
837 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
838 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
839 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
840 /* Note: If signal quality is poor you may want to change NICAM */
841 /* error limit registers (NLELR and NUELR) to some greater values. */
842 /* Then the sound would remain stereo, but won't be so clear. */
843 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
844 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
845
846 if(tda9874a_dic == 0x11) {
847 chip_write(chip, TDA9874A_AMCONR, 0xf9);
848 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
849 chip_write(chip, TDA9874A_AOSR, 0x80);
850 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
851 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
852 } else { /* dic == 0x07 */
853 chip_write(chip, TDA9874A_AMCONR, 0xfb);
854 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 855 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 856 }
64f70e7e 857 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 858 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
859 return 1;
860}
861
862static int tda9874a_getmode(struct CHIPSTATE *chip)
863{
64f70e7e 864 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 865 int dsr,nsr,mode;
866 int necr; /* just for debugging */
867
dc3d75da 868 mode = V4L2_TUNER_MODE_MONO;
1da177e4
LT		 869
870 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
871 return mode;
872 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
873 return mode;
874 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
875 return mode;
876
877 /* need to store dsr/nsr somewhere */
878 chip->shadow.bytes[MAXREGS-2] = dsr;
879 chip->shadow.bytes[MAXREGS-1] = nsr;
880
881 if(tda9874a_mode) {
882 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
883 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
884 * that sound has (temporarily) switched from NICAM to
885 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
886 * error count. So in fact there is no stereo in this case :-(
dc3d75da 887 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 888 * external 4052 multiplexer in audio_hook().
889 */
1da177e4 890 if(nsr & 0x02) /* NSR.S/MB=1 */
dc3d75da 891 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 892 if(nsr & 0x01) /* NSR.D/SB=1 */
dc3d75da 893 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 894 } else {
895 if(dsr & 0x02) /* DSR.IDSTE=1 */
dc3d75da 896 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 897 if(dsr & 0x04) /* DSR.IDDUA=1 */
dc3d75da 898 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 899 }
900
64f70e7e 901 v4l2_dbg(1, debug, sd, "tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 902 dsr, nsr, necr, mode);
903 return mode;
904}
905
906static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
907{
64f70e7e
HV		 908 struct v4l2_subdev *sd = &chip->sd;
909
1da177e4
LT		 910 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
911 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
64f70e7e 912 if (tda9874a_mode) {
1da177e4
LT		 913 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
914 tda9874a_NCONR &= 0xfe; /* enable */
915 else
916 tda9874a_NCONR |= 0x01; /* disable */
917 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
918 }
919
920 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
921 * and has auto-select function for audio output (AOSR register).
922 * Old TDA9874H doesn't support these features.
923 * TDA9874A also has additional mono output pin (OUTM), which
924 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
925 */
926 if(tda9874a_dic == 0x11) {
927 int aosr = 0x80;
928 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
929
930 switch(mode) {
dc3d75da
MCC		 931 case V4L2_TUNER_MODE_MONO:
932 case V4L2_TUNER_MODE_STEREO:
1da177e4 933 break;
dc3d75da 934 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 935 aosr = 0x80; /* auto-select, dual A/A */
936 mdacosr = (tda9874a_mode) ? 0x82:0x80;
937 break;
dc3d75da 938 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 939 aosr = 0xa0; /* auto-select, dual B/B */
940 mdacosr = (tda9874a_mode) ? 0x83:0x81;
941 break;
942 default:
943 chip->mode = 0;
944 return;
945 }
946 chip_write(chip, TDA9874A_AOSR, aosr);
947 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
948
64f70e7e 949 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 950 mode, aosr, mdacosr);
951
952 } else { /* dic == 0x07 */
953 int fmmr,aosr;
954
955 switch(mode) {
dc3d75da 956 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 957 fmmr = 0x00; /* mono */
958 aosr = 0x10; /* A/A */
959 break;
dc3d75da 960 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 961 if(tda9874a_mode) {
962 fmmr = 0x00;
963 aosr = 0x00; /* handled by NICAM auto-mute */
964 } else {
965 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
966 aosr = 0x00;
967 }
968 break;
dc3d75da 969 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 970 fmmr = 0x02; /* dual */
971 aosr = 0x10; /* dual A/A */
972 break;
dc3d75da 973 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 974 fmmr = 0x02; /* dual */
975 aosr = 0x20; /* dual B/B */
976 break;
977 default:
978 chip->mode = 0;
979 return;
980 }
981 chip_write(chip, TDA9874A_FMMR, fmmr);
982 chip_write(chip, TDA9874A_AOSR, aosr);
983
64f70e7e 984 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 985 mode, fmmr, aosr);
986 }
987}
988
989static int tda9874a_checkit(struct CHIPSTATE *chip)
990{
64f70e7e 991 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 992 int dic,sic; /* device id. and software id. codes */
993
994 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
995 return 0;
996 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
997 return 0;
998
64f70e7e 999 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 1000
1001 if((dic == 0x11)||(dic == 0x07)) {
64f70e7e 1002 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1da177e4
LT		 1003 tda9874a_dic = dic; /* remember device id. */
1004 return 1;
1005 }
1006 return 0; /* not found */
1007}
1008
1009static int tda9874a_initialize(struct CHIPSTATE *chip)
1010{
1011 if (tda9874a_SIF > 2)
1012 tda9874a_SIF = 1;
04e6f990 1013 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 1014 tda9874a_STD = 0;
1015 if(tda9874a_AMSEL > 1)
1016 tda9874a_AMSEL = 0;
1017
1018 if(tda9874a_SIF == 1)
1019 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
1020 else
1021 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
1022
1023 tda9874a_ESP = tda9874a_STD;
1024 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1025
1026 if(tda9874a_AMSEL == 0)
1027 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
1028 else
1029 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
1030
1031 tda9874a_setup(chip);
1032 return 0;
1033}
1034
411674fd
HV		 1035/* ---------------------------------------------------------------------- */
1036/* audio chip description - defines+functions for tda9875 */
1037/* The TDA9875 is made by Philips Semiconductor
1038 * http://www.semiconductors.philips.com
1039 * TDA9875: I2C-bus controlled DSP audio processor, FM demodulator
1040 *
1041 */
1042
1043/* subaddresses for TDA9875 */
1044#define TDA9875_MUT 0x12 /*General mute (value --> 0b11001100*/
1045#define TDA9875_CFG 0x01 /* Config register (value --> 0b00000000 */
1046#define TDA9875_DACOS 0x13 /*DAC i/o select (ADC) 0b0000100*/
1047#define TDA9875_LOSR 0x16 /*Line output select regirter 0b0100 0001*/
1048
1049#define TDA9875_CH1V 0x0c /*Channel 1 volume (mute)*/
1050#define TDA9875_CH2V 0x0d /*Channel 2 volume (mute)*/
1051#define TDA9875_SC1 0x14 /*SCART 1 in (mono)*/
1052#define TDA9875_SC2 0x15 /*SCART 2 in (mono)*/
1053
1054#define TDA9875_ADCIS 0x17 /*ADC input select (mono) 0b0110 000*/
1055#define TDA9875_AER 0x19 /*Audio effect (AVL+Pseudo) 0b0000 0110*/
1056#define TDA9875_MCS 0x18 /*Main channel select (DAC) 0b0000100*/
1057#define TDA9875_MVL 0x1a /* Main volume gauche */
1058#define TDA9875_MVR 0x1b /* Main volume droite */
1059#define TDA9875_MBA 0x1d /* Main Basse */
1060#define TDA9875_MTR 0x1e /* Main treble */
25985edc
LDM		 1061#define TDA9875_ACS 0x1f /* Auxiliary channel select (FM) 0b0000000*/
1062#define TDA9875_AVL 0x20 /* Auxiliary volume gauche */
1063#define TDA9875_AVR 0x21 /* Auxiliary volume droite */
1064#define TDA9875_ABA 0x22 /* Auxiliary Basse */
1065#define TDA9875_ATR 0x23 /* Auxiliary treble */
411674fd
HV		 1066
1067#define TDA9875_MSR 0x02 /* Monitor select register */
1068#define TDA9875_C1MSB 0x03 /* Carrier 1 (FM) frequency register MSB */
1069#define TDA9875_C1MIB 0x04 /* Carrier 1 (FM) frequency register (16-8]b */
1070#define TDA9875_C1LSB 0x05 /* Carrier 1 (FM) frequency register LSB */
1071#define TDA9875_C2MSB 0x06 /* Carrier 2 (nicam) frequency register MSB */
1072#define TDA9875_C2MIB 0x07 /* Carrier 2 (nicam) frequency register (16-8]b */
1073#define TDA9875_C2LSB 0x08 /* Carrier 2 (nicam) frequency register LSB */
1074#define TDA9875_DCR 0x09 /* Demodulateur configuration regirter*/
1075#define TDA9875_DEEM 0x0a /* FM de-emphasis regirter*/
1076#define TDA9875_FMAT 0x0b /* FM Matrix regirter*/
1077
1078/* values */
1079#define TDA9875_MUTE_ON 0xff /* general mute */
1080#define TDA9875_MUTE_OFF 0xcc /* general no mute */
1081
1082static int tda9875_initialize(struct CHIPSTATE *chip)
1083{
1084 chip_write(chip, TDA9875_CFG, 0xd0); /*reg de config 0 (reset)*/
1085 chip_write(chip, TDA9875_MSR, 0x03); /* Monitor 0b00000XXX*/
1086 chip_write(chip, TDA9875_C1MSB, 0x00); /*Car1(FM) MSB XMHz*/
1087 chip_write(chip, TDA9875_C1MIB, 0x00); /*Car1(FM) MIB XMHz*/
1088 chip_write(chip, TDA9875_C1LSB, 0x00); /*Car1(FM) LSB XMHz*/
1089 chip_write(chip, TDA9875_C2MSB, 0x00); /*Car2(NICAM) MSB XMHz*/
1090 chip_write(chip, TDA9875_C2MIB, 0x00); /*Car2(NICAM) MIB XMHz*/
1091 chip_write(chip, TDA9875_C2LSB, 0x00); /*Car2(NICAM) LSB XMHz*/
1092 chip_write(chip, TDA9875_DCR, 0x00); /*Demod config 0x00*/
1093 chip_write(chip, TDA9875_DEEM, 0x44); /*DE-Emph 0b0100 0100*/
1094 chip_write(chip, TDA9875_FMAT, 0x00); /*FM Matrix reg 0x00*/
1095 chip_write(chip, TDA9875_SC1, 0x00); /* SCART 1 (SC1)*/
1096 chip_write(chip, TDA9875_SC2, 0x01); /* SCART 2 (sc2)*/
1097
1098 chip_write(chip, TDA9875_CH1V, 0x10); /* Channel volume 1 mute*/
1099 chip_write(chip, TDA9875_CH2V, 0x10); /* Channel volume 2 mute */
1100 chip_write(chip, TDA9875_DACOS, 0x02); /* sig DAC i/o(in:nicam)*/
1101 chip_write(chip, TDA9875_ADCIS, 0x6f); /* sig ADC input(in:mono)*/
1102 chip_write(chip, TDA9875_LOSR, 0x00); /* line out (in:mono)*/
1103 chip_write(chip, TDA9875_AER, 0x00); /*06 Effect (AVL+PSEUDO) */
1104 chip_write(chip, TDA9875_MCS, 0x44); /* Main ch select (DAC) */
1105 chip_write(chip, TDA9875_MVL, 0x03); /* Vol Main left 10dB */
1106 chip_write(chip, TDA9875_MVR, 0x03); /* Vol Main right 10dB*/
1107 chip_write(chip, TDA9875_MBA, 0x00); /* Main Bass Main 0dB*/
1108 chip_write(chip, TDA9875_MTR, 0x00); /* Main Treble Main 0dB*/
1109 chip_write(chip, TDA9875_ACS, 0x44); /* Aux chan select (dac)*/
1110 chip_write(chip, TDA9875_AVL, 0x00); /* Vol Aux left 0dB*/
1111 chip_write(chip, TDA9875_AVR, 0x00); /* Vol Aux right 0dB*/
1112 chip_write(chip, TDA9875_ABA, 0x00); /* Aux Bass Main 0dB*/
1113 chip_write(chip, TDA9875_ATR, 0x00); /* Aux Aigus Main 0dB*/
1114
1115 chip_write(chip, TDA9875_MUT, 0xcc); /* General mute */
1116 return 0;
1117}
1118
1119static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1120static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1121static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1122
1123/* ----------------------------------------------------------------------- */
1124
1125
1126/* *********************** *
1127 * i2c interface functions *
1128 * *********************** */
1129
1130static int tda9875_checkit(struct CHIPSTATE *chip)
1131{
1132 struct v4l2_subdev *sd = &chip->sd;
1133 int dic, rev;
1134
1135 dic = chip_read2(chip, 254);
1136 rev = chip_read2(chip, 255);
1137
1138 if (dic == 0 || dic == 2) { /* tda9875 and tda9875A */
1139 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1140 dic == 0 ? "" : "A", rev);
1141 return 1;
1142 }
1143 return 0;
1144}
1da177e4
LT		 1145
1146/* ---------------------------------------------------------------------- */
1147/* audio chip descriptions - defines+functions for tea6420 */
1148
1149#define TEA6300_VL 0x00 /* volume left */
1150#define TEA6300_VR 0x01 /* volume right */
1151#define TEA6300_BA 0x02 /* bass */
1152#define TEA6300_TR 0x03 /* treble */
1153#define TEA6300_FA 0x04 /* fader control */
1154#define TEA6300_S 0x05 /* switch register */
f2421ca3 1155 /* values for those registers: */
1da177e4
LT		 1156#define TEA6300_S_SA 0x01 /* stereo A input */
1157#define TEA6300_S_SB 0x02 /* stereo B */
1158#define TEA6300_S_SC 0x04 /* stereo C */
1159#define TEA6300_S_GMU 0x80 /* general mute */
1160
1161#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1162#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1163#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1164#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1165#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1166#define TEA6320_BA 0x05 /* bass (0-4) */
1167#define TEA6320_TR 0x06 /* treble (0-4) */
1168#define TEA6320_S 0x07 /* switch register */
f2421ca3 1169 /* values for those registers: */
1da177e4
LT		 1170#define TEA6320_S_SA 0x07 /* stereo A input */
1171#define TEA6320_S_SB 0x06 /* stereo B */
1172#define TEA6320_S_SC 0x05 /* stereo C */
1173#define TEA6320_S_SD 0x04 /* stereo D */
1174#define TEA6320_S_GMU 0x80 /* general mute */
1175
1176#define TEA6420_S_SA 0x00 /* stereo A input */
1177#define TEA6420_S_SB 0x01 /* stereo B */
1178#define TEA6420_S_SC 0x02 /* stereo C */
1179#define TEA6420_S_SD 0x03 /* stereo D */
1180#define TEA6420_S_SE 0x04 /* stereo E */
1181#define TEA6420_S_GMU 0x05 /* general mute */
1182
1183static int tea6300_shift10(int val) { return val >> 10; }
1184static int tea6300_shift12(int val) { return val >> 12; }
1185
1186/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1187/* 0x0c mirror those immediately higher) */
1188static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1189static int tea6320_shift11(int val) { return val >> 11; }
1190static int tea6320_initialize(struct CHIPSTATE * chip)
1191{
1192 chip_write(chip, TEA6320_FFR, 0x3f);
1193 chip_write(chip, TEA6320_FFL, 0x3f);
1194 chip_write(chip, TEA6320_FRR, 0x3f);
1195 chip_write(chip, TEA6320_FRL, 0x3f);
1196
1197 return 0;
1198}
1199
1200
1201/* ---------------------------------------------------------------------- */
1202/* audio chip descriptions - defines+functions for tda8425 */
1203
1204#define TDA8425_VL 0x00 /* volume left */
1205#define TDA8425_VR 0x01 /* volume right */
1206#define TDA8425_BA 0x02 /* bass */
1207#define TDA8425_TR 0x03 /* treble */
1208#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1209 /* values for those registers: */
1da177e4
LT		 1210#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1211#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1212#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1213#define TDA8425_S1_MU 0x20 /* mute bit */
1214#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1215#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1216#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1217#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1218#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1219#define TDA8425_S1_ML 0x06 /* language selector */
1220#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1221#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1222#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1223#define TDA8425_S1_IS 0x01 /* channel selector */
1224
1225
1226static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1227static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1228
1da177e4
LT		 1229static void tda8425_setmode(struct CHIPSTATE *chip, int mode)
1230{
1231 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1232
f952848d
DG		 1233 switch (mode) {
1234 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1235 s1 |= TDA8425_S1_ML_SOUND_A;
1236 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d
DG		 1237 break;
1238 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1239 s1 |= TDA8425_S1_ML_SOUND_B;
1240 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d
DG		 1241 break;
1242 case V4L2_TUNER_MODE_MONO:
1da177e4 1243 s1 |= TDA8425_S1_ML_STEREO;
f952848d
DG		 1244 s1 |= TDA8425_S1_STEREO_MONO;
1245 break;
1246 case V4L2_TUNER_MODE_STEREO:
1247 s1 |= TDA8425_S1_ML_STEREO;
1248 s1 |= TDA8425_S1_STEREO_SPATIAL;
1249 break;
1250 default:
1251 return;
1da177e4
LT		 1252 }
1253 chip_write(chip,TDA8425_S1,s1);
1254}
1255
1256
1257/* ---------------------------------------------------------------------- */
1258/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1259
1260/* the registers of 16C54, I2C sub address. */
1261#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1262#define PIC16C54_REG_MISC 0x02
1263
1264/* bit definition of the RESET register, I2C data. */
1265#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1266 /* code of remote controller */
1da177e4
LT		 1267#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1268#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1269#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1270#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1271#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1272#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1273#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1274
1275/* ---------------------------------------------------------------------- */
1276/* audio chip descriptions - defines+functions for TA8874Z */
1277
18fc59e2 1278/* write 1st byte */
1da177e4
LT		 1279#define TA8874Z_LED_STE 0x80
1280#define TA8874Z_LED_BIL 0x40
1281#define TA8874Z_LED_EXT 0x20
1282#define TA8874Z_MONO_SET 0x10
1283#define TA8874Z_MUTE 0x08
1284#define TA8874Z_F_MONO 0x04
1285#define TA8874Z_MODE_SUB 0x02
1286#define TA8874Z_MODE_MAIN 0x01
1287
18fc59e2
MCC		 1288/* write 2nd byte */
1289/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1290#define TA8874Z_SEPARATION 0x3f
1291#define TA8874Z_SEPARATION_DEFAULT 0x10
1292
18fc59e2 1293/* read */
1da177e4
LT		 1294#define TA8874Z_B1 0x80
1295#define TA8874Z_B0 0x40
1296#define TA8874Z_CHAG_FLAG 0x20
1297
18fc59e2
MCC		 1298/*
1299 * B1 B0
1300 * mono L H
1301 * stereo L L
1302 * BIL H L
1303 */
1da177e4
LT		 1304static int ta8874z_getmode(struct CHIPSTATE *chip)
1305{
1306 int val, mode;
1307
1308 val = chip_read(chip);
dc3d75da 1309 mode = V4L2_TUNER_MODE_MONO;
1da177e4 1310 if (val & TA8874Z_B1){
dc3d75da 1311 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 1312 }else if (!(val & TA8874Z_B0)){
dc3d75da 1313 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 1314 }
08e14054 1315 /* v4l_dbg(1, debug, chip->c, "ta8874z_getmode(): raw chip read: 0x%02x, return: 0x%02x\n", val, mode); */
1da177e4
LT		 1316 return mode;
1317}
1318
1319static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1320static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1321static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1322static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1323
1324static void ta8874z_setmode(struct CHIPSTATE *chip, int mode)
1325{
64f70e7e 1326 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1327 int update = 1;
1328 audiocmd *t = NULL;
64f70e7e
HV		 1329
1330 v4l2_dbg(1, debug, sd, "ta8874z_setmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1331
1332 switch(mode){
dc3d75da 1333 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1334 t = &ta8874z_mono;
1335 break;
dc3d75da 1336 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1337 t = &ta8874z_stereo;
1338 break;
dc3d75da 1339 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1340 t = &ta8874z_main;
1341 break;
dc3d75da 1342 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1343 t = &ta8874z_sub;
1344 break;
1345 default:
1346 update = 0;
1347 }
1348
1349 if(update)
1350 chip_cmd(chip, "TA8874Z", t);
1351}
1352
1353static int ta8874z_checkit(struct CHIPSTATE *chip)
1354{
1355 int rc;
1356 rc = chip_read(chip);
1357 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1358}
1359
1360/* ---------------------------------------------------------------------- */
1361/* audio chip descriptions - struct CHIPDESC */
1362
1363/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1364static int tda8425 = 1;
1365static int tda9840 = 1;
1366static int tda9850 = 1;
1367static int tda9855 = 1;
1368static int tda9873 = 1;
1369static int tda9874a = 1;
411674fd 1370static int tda9875 = 1;
ff699e6b
DSL		 1371static int tea6300; /* default 0 - address clash with msp34xx */
1372static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1373static int tea6420 = 1;
1374static int pic16c54 = 1;
ff699e6b 1375static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1376
1377module_param(tda8425, int, 0444);
1378module_param(tda9840, int, 0444);
1379module_param(tda9850, int, 0444);
1380module_param(tda9855, int, 0444);
1381module_param(tda9873, int, 0444);
1382module_param(tda9874a, int, 0444);
411674fd 1383module_param(tda9875, int, 0444);
1da177e4
LT		 1384module_param(tea6300, int, 0444);
1385module_param(tea6320, int, 0444);
1386module_param(tea6420, int, 0444);
1387module_param(pic16c54, int, 0444);
1388module_param(ta8874z, int, 0444);
1389
1390static struct CHIPDESC chiplist[] = {
1391 {
1392 .name = "tda9840",
1da177e4 1393 .insmodopt = &tda9840,
09df1c16
MCC		 1394 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1395 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1396 .registers = 5,
dd03e970 1397 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1398
af1a9951 1399 /* callbacks */
94f9e56e 1400 .checkit = tda9840_checkit,
1da177e4
LT		 1401 .getmode = tda9840_getmode,
1402 .setmode = tda9840_setmode,
1da177e4 1403
4ac97914 1404 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1405 /* ,TDA9840_SW, TDA9840_MONO */} }
1406 },
1407 {
1408 .name = "tda9873h",
1da177e4 1409 .insmodopt = &tda9873,
09df1c16
MCC		 1410 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1411 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1412 .registers = 3,
dd03e970 1413 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1414
af1a9951
MCC		 1415 /* callbacks */
1416 .checkit = tda9873_checkit,
1da177e4
LT		 1417 .getmode = tda9873_getmode,
1418 .setmode = tda9873_setmode,
1da177e4
LT		 1419
1420 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1421 .inputreg = TDA9873_SW,
1422 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1423 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1424 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1425
1426 },
1427 {
1428 .name = "tda9874h/a",
1da177e4 1429 .insmodopt = &tda9874a,
09df1c16
MCC		 1430 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1431 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1432 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1433
af1a9951
MCC		 1434 /* callbacks */
1435 .initialize = tda9874a_initialize,
1436 .checkit = tda9874a_checkit,
1da177e4
LT		 1437 .getmode = tda9874a_getmode,
1438 .setmode = tda9874a_setmode,
1da177e4 1439 },
411674fd
HV		 1440 {
1441 .name = "tda9875",
1442 .insmodopt = &tda9875,
1443 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1444 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1445 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1446
1447 /* callbacks */
1448 .initialize = tda9875_initialize,
1449 .checkit = tda9875_checkit,
1450 .volfunc = tda9875_volume,
1451 .bassfunc = tda9875_bass,
1452 .treblefunc = tda9875_treble,
1453 .leftreg = TDA9875_MVL,
1454 .rightreg = TDA9875_MVR,
1455 .bassreg = TDA9875_MBA,
1456 .treblereg = TDA9875_MTR,
1457 .leftinit = 58880,
1458 .rightinit = 58880,
1459 },
1da177e4
LT		 1460 {
1461 .name = "tda9850",
1da177e4 1462 .insmodopt = &tda9850,
09df1c16
MCC		 1463 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1464 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1465 .registers = 11,
1466
1467 .getmode = tda985x_getmode,
1468 .setmode = tda985x_setmode,
1469
1470 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1471 },
1472 {
1473 .name = "tda9855",
1da177e4 1474 .insmodopt = &tda9855,
09df1c16
MCC		 1475 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1476 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1477 .registers = 11,
1478 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1479
1480 .leftreg = TDA9855_VL,
1481 .rightreg = TDA9855_VR,
1482 .bassreg = TDA9855_BA,
1483 .treblereg = TDA9855_TR,
af1a9951
MCC		 1484
1485 /* callbacks */
1da177e4
LT		 1486 .volfunc = tda9855_volume,
1487 .bassfunc = tda9855_bass,
1488 .treblefunc = tda9855_treble,
1da177e4
LT		 1489 .getmode = tda985x_getmode,
1490 .setmode = tda985x_setmode,
1491
1492 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1493 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1494 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1495 0x07, 0x10, 0x10, 0x03 }}
1496 },
1497 {
1498 .name = "tea6300",
1da177e4 1499 .insmodopt = &tea6300,
09df1c16
MCC		 1500 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1501 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1502 .registers = 6,
1503 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1504
1505 .leftreg = TEA6300_VR,
1506 .rightreg = TEA6300_VL,
1507 .bassreg = TEA6300_BA,
1508 .treblereg = TEA6300_TR,
af1a9951
MCC		 1509
1510 /* callbacks */
1da177e4
LT		 1511 .volfunc = tea6300_shift10,
1512 .bassfunc = tea6300_shift12,
1513 .treblefunc = tea6300_shift12,
1514
1515 .inputreg = TEA6300_S,
1516 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1517 .inputmute = TEA6300_S_GMU,
1518 },
1519 {
1520 .name = "tea6320",
1da177e4 1521 .insmodopt = &tea6320,
09df1c16
MCC		 1522 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1523 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1524 .registers = 8,
1525 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1526
1527 .leftreg = TEA6320_V,
1528 .rightreg = TEA6320_V,
1529 .bassreg = TEA6320_BA,
1530 .treblereg = TEA6320_TR,
af1a9951
MCC		 1531
1532 /* callbacks */
1533 .initialize = tea6320_initialize,
1da177e4
LT		 1534 .volfunc = tea6320_volume,
1535 .bassfunc = tea6320_shift11,
1536 .treblefunc = tea6320_shift11,
1537
1538 .inputreg = TEA6320_S,
1539 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1540 .inputmute = TEA6300_S_GMU,
1541 },
1542 {
1543 .name = "tea6420",
1da177e4 1544 .insmodopt = &tea6420,
09df1c16
MCC		 1545 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1546 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1547 .registers = 1,
1548 .flags = CHIP_HAS_INPUTSEL,
1549
1550 .inputreg = -1,
1551 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1552 .inputmute = TEA6300_S_GMU,
1553 },
1554 {
1555 .name = "tda8425",
1da177e4 1556 .insmodopt = &tda8425,
09df1c16
MCC		 1557 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1558 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1559 .registers = 9,
1560 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1561
1562 .leftreg = TDA8425_VL,
1563 .rightreg = TDA8425_VR,
1564 .bassreg = TDA8425_BA,
1565 .treblereg = TDA8425_TR,
af1a9951
MCC		 1566
1567 /* callbacks */
1da177e4
LT		 1568 .volfunc = tda8425_shift10,
1569 .bassfunc = tda8425_shift12,
1570 .treblefunc = tda8425_shift12,
af1a9951 1571 .setmode = tda8425_setmode,
1da177e4
LT		 1572
1573 .inputreg = TDA8425_S1,
1574 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1575 .inputmute = TDA8425_S1_OFF,
1576
1da177e4
LT		 1577 },
1578 {
1579 .name = "pic16c54 (PV951)",
1da177e4 1580 .insmodopt = &pic16c54,
09df1c16
MCC		 1581 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1582 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1583 .registers = 2,
1584 .flags = CHIP_HAS_INPUTSEL,
1585
1586 .inputreg = PIC16C54_REG_MISC,
1587 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1588 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1589 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1590 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1591 .inputmute = PIC16C54_MISC_SND_MUTE,
1592 },
1593 {
1594 .name = "ta8874z",
1da177e4
LT		 1595 .checkit = ta8874z_checkit,
1596 .insmodopt = &ta8874z,
09df1c16
MCC		 1597 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1598 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4
LT		 1599 .registers = 2,
1600
af1a9951 1601 /* callbacks */
1da177e4
LT		 1602 .getmode = ta8874z_getmode,
1603 .setmode = ta8874z_setmode,
1da177e4 1604
4ac97914 1605 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1606 },
1607 { .name = NULL } /* EOF */
1608};
1609
1610
1611/* ---------------------------------------------------------------------- */
1da177e4 1612
64f70e7e 1613static int tvaudio_g_ctrl(struct v4l2_subdev *sd,
dc3d75da
MCC		 1614 struct v4l2_control *ctrl)
1615{
64f70e7e 1616 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1617 struct CHIPDESC *desc = chip->desc;
dc3d75da
MCC		 1618
1619 switch (ctrl->id) {
1620 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1621 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1622 break;
dc3d75da
MCC		 1623 ctrl->value=chip->muted;
1624 return 0;
1625 case V4L2_CID_AUDIO_VOLUME:
18c0ecf1 1626 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1627 break;
1628 ctrl->value = max(chip->left,chip->right);
1629 return 0;
1630 case V4L2_CID_AUDIO_BALANCE:
1631 {
1632 int volume;
18c0ecf1 1633 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1634 break;
1635 volume = max(chip->left,chip->right);
1636 if (volume)
1637 ctrl->value=(32768*min(chip->left,chip->right))/volume;
1638 else
1639 ctrl->value=32768;
1640 return 0;
1641 }
1642 case V4L2_CID_AUDIO_BASS:
01a1a3cc 1643 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
dc3d75da
MCC		 1644 break;
1645 ctrl->value = chip->bass;
1646 return 0;
1647 case V4L2_CID_AUDIO_TREBLE:
01a1a3cc
MCC		 1648 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1649 break;
dc3d75da
MCC		 1650 ctrl->value = chip->treble;
1651 return 0;
1652 }
1653 return -EINVAL;
1654}
1655
64f70e7e 1656static int tvaudio_s_ctrl(struct v4l2_subdev *sd,
dc3d75da 1657 struct v4l2_control *ctrl)
8bf2f8e7 1658{
64f70e7e 1659 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1660 struct CHIPDESC *desc = chip->desc;
8bf2f8e7
HV		 1661
1662 switch (ctrl->id) {
1663 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1664 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1665 break;
1666
8bf2f8e7
HV		 1667 if (ctrl->value < 0 || ctrl->value >= 2)
1668 return -ERANGE;
1669 chip->muted = ctrl->value;
1670 if (chip->muted)
1671 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1672 else
1673 chip_write_masked(chip,desc->inputreg,
1674 desc->inputmap[chip->input],desc->inputmask);
dc3d75da
MCC		 1675 return 0;
1676 case V4L2_CID_AUDIO_VOLUME:
1677 {
1678 int volume,balance;
1679
18c0ecf1 1680 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1681 break;
1682
1683 volume = max(chip->left,chip->right);
1684 if (volume)
1685 balance=(32768*min(chip->left,chip->right))/volume;
1686 else
1687 balance=32768;
1688
1689 volume=ctrl->value;
1690 chip->left = (min(65536 - balance,32768) * volume) / 32768;
1691 chip->right = (min(balance,volume *(__u16)32768)) / 32768;
1692
1693 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1694 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1695
1696 return 0;
8bf2f8e7 1697 }
dc3d75da
MCC		 1698 case V4L2_CID_AUDIO_BALANCE:
1699 {
1700 int volume, balance;
88af8304 1701
18c0ecf1 1702 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1703 break;
1704
88af8304 1705 volume = max(chip->left, chip->right);
dc3d75da 1706 balance = ctrl->value;
88af8304
HV		 1707 chip->left = (min(65536 - balance, 32768) * volume) / 32768;
1708 chip->right = (min(balance, volume * (__u16)32768)) / 32768;
dc3d75da 1709
88af8304
HV		 1710 chip_write(chip, desc->leftreg, desc->volfunc(chip->left));
1711 chip_write(chip, desc->rightreg, desc->volfunc(chip->right));
dc3d75da
MCC		 1712
1713 return 0;
1714 }
1715 case V4L2_CID_AUDIO_BASS:
01a1a3cc 1716 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
dc3d75da
MCC		 1717 break;
1718 chip->bass = ctrl->value;
1719 chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass));
1720
1721 return 0;
1722 case V4L2_CID_AUDIO_TREBLE:
01a1a3cc
MCC		 1723 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1724 break;
dc3d75da
MCC		 1725 chip->treble = ctrl->value;
1726 chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
1727
1728 return 0;
1729 }
1730 return -EINVAL;
8bf2f8e7
HV		 1731}
1732
1733
1da177e4
LT		 1734/* ---------------------------------------------------------------------- */
1735/* video4linux interface */
1736
64f70e7e 1737static int tvaudio_s_radio(struct v4l2_subdev *sd)
1da177e4 1738{
64f70e7e 1739 struct CHIPSTATE *chip = to_state(sd);
1da177e4 1740
64f70e7e 1741 chip->radio = 1;
64f70e7e
HV		 1742 /* del_timer(&chip->wt); */
1743 return 0;
1744}
1745
1746static int tvaudio_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
1747{
1748 struct CHIPSTATE *chip = to_state(sd);
1749 struct CHIPDESC *desc = chip->desc;
1750
1751 switch (qc->id) {
1752 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1753 if (desc->flags & CHIP_HAS_INPUTSEL)
1754 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1755 break;
64f70e7e 1756 case V4L2_CID_AUDIO_VOLUME:
10afbef1
HV		 1757 if (desc->flags & CHIP_HAS_VOLUME)
1758 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 58880);
1759 break;
64f70e7e 1760 case V4L2_CID_AUDIO_BALANCE:
10afbef1
HV		 1761 if (desc->flags & CHIP_HAS_VOLUME)
1762 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
64f70e7e
HV		 1763 break;
1764 case V4L2_CID_AUDIO_BASS:
1765 case V4L2_CID_AUDIO_TREBLE:
10afbef1
HV		 1766 if (desc->flags & CHIP_HAS_BASSTREBLE)
1767 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
64f70e7e
HV		 1768 break;
1769 default:
10afbef1 1770 break;
c6241b6c 1771 }
10afbef1 1772 return -EINVAL;
64f70e7e
HV		 1773}
1774
5325b427
HV		 1775static int tvaudio_s_routing(struct v4l2_subdev *sd,
1776 u32 input, u32 output, u32 config)
64f70e7e
HV		 1777{
1778 struct CHIPSTATE *chip = to_state(sd);
1779 struct CHIPDESC *desc = chip->desc;
1da177e4 1780
5fa7b9f3
HV		 1781 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1782 return 0;
5325b427 1783 if (input >= 4)
64f70e7e
HV		 1784 return -EINVAL;
1785 /* There are four inputs: tuner, radio, extern and intern. */
5325b427 1786 chip->input = input;
64f70e7e
HV		 1787 if (chip->muted)
1788 return 0;
1789 chip_write_masked(chip, desc->inputreg,
1790 desc->inputmap[chip->input], desc->inputmask);
1791 return 0;
1792}
1793
1794static int tvaudio_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1795{
1796 struct CHIPSTATE *chip = to_state(sd);
1797 struct CHIPDESC *desc = chip->desc;
1798 int mode = 0;
1799
5fa7b9f3
HV		 1800 if (!desc->setmode)
1801 return 0;
64f70e7e
HV		 1802 if (chip->radio)
1803 return 0;
5fa7b9f3 1804
64f70e7e
HV		 1805 switch (vt->audmode) {
1806 case V4L2_TUNER_MODE_MONO:
1807 case V4L2_TUNER_MODE_STEREO:
1808 case V4L2_TUNER_MODE_LANG1:
1809 case V4L2_TUNER_MODE_LANG2:
1810 mode = vt->audmode;
1811 break;
1812 case V4L2_TUNER_MODE_LANG1_LANG2:
1813 mode = V4L2_TUNER_MODE_STEREO;
1814 break;
1815 default:
1816 return -EINVAL;
1817 }
1818 chip->audmode = vt->audmode;
1819
5fa7b9f3 1820 if (mode) {
1da177e4 1821 /* del_timer(&chip->wt); */
64f70e7e
HV		 1822 chip->mode = mode;
1823 desc->setmode(chip, mode);
1da177e4 1824 }
64f70e7e
HV		 1825 return 0;
1826}
8bf2f8e7 1827
64f70e7e
HV		 1828static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1829{
1830 struct CHIPSTATE *chip = to_state(sd);
1831 struct CHIPDESC *desc = chip->desc;
1832 int mode = V4L2_TUNER_MODE_MONO;
2474ed44 1833
5fa7b9f3
HV		 1834 if (!desc->getmode)
1835 return 0;
64f70e7e
HV		 1836 if (chip->radio)
1837 return 0;
5fa7b9f3 1838
64f70e7e
HV		 1839 vt->audmode = chip->audmode;
1840 vt->rxsubchans = 0;
1841 vt->capability = V4L2_TUNER_CAP_STEREO |
1842 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1843
5fa7b9f3 1844 mode = desc->getmode(chip);
64f70e7e
HV		 1845
1846 if (mode & V4L2_TUNER_MODE_MONO)
1847 vt->rxsubchans |= V4L2_TUNER_SUB_MONO;
1848 if (mode & V4L2_TUNER_MODE_STEREO)
1849 vt->rxsubchans |= V4L2_TUNER_SUB_STEREO;
1850 /* Note: for SAP it should be mono/lang2 or stereo/lang2.
1851 When this module is converted fully to v4l2, then this
1852 should change for those chips that can detect SAP. */
1853 if (mode & V4L2_TUNER_MODE_LANG1)
1854 vt->rxsubchans = V4L2_TUNER_SUB_LANG1 |
1855 V4L2_TUNER_SUB_LANG2;
1856 return 0;
1857}
1858
1859static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1860{
1861 struct CHIPSTATE *chip = to_state(sd);
1862
1863 chip->radio = 0;
1864 return 0;
1865}
1866
1867static int tvaudio_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1868{
1869 struct CHIPSTATE *chip = to_state(sd);
1870 struct CHIPDESC *desc = chip->desc;
1871
1872 chip->mode = 0; /* automatic */
1873
1874 /* For chips that provide getmode and setmode, and doesn't
1875 automatically follows the stereo carrier, a kthread is
1876 created to set the audio standard. In this case, when then
1877 the video channel is changed, tvaudio starts on MONO mode.
1878 After waiting for 2 seconds, the kernel thread is called,
1879 to follow whatever audio standard is pointed by the
1880 audio carrier.
1881 */
1882 if (chip->thread) {
1883 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1884 if (chip->prevmode != V4L2_TUNER_MODE_MONO)
1885 chip->prevmode = -1; /* reset previous mode */
1886 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
2474ed44 1887 }
64f70e7e
HV		 1888 return 0;
1889}
2474ed44 1890
aecde8b5 1891static int tvaudio_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
64f70e7e
HV		 1892{
1893 struct i2c_client *client = v4l2_get_subdevdata(sd);
1894
1895 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVAUDIO, 0);
1896}
1897
64f70e7e
HV		 1898/* ----------------------------------------------------------------------- */
1899
1900static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
1901 .g_chip_ident = tvaudio_g_chip_ident,
1902 .queryctrl = tvaudio_queryctrl,
1903 .g_ctrl = tvaudio_g_ctrl,
1904 .s_ctrl = tvaudio_s_ctrl,
f41737ec 1905 .s_std = tvaudio_s_std,
64f70e7e
HV		 1906};
1907
1908static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1909 .s_radio = tvaudio_s_radio,
1910 .s_frequency = tvaudio_s_frequency,
64f70e7e 1911 .s_tuner = tvaudio_s_tuner,
e6a1a08f 1912 .g_tuner = tvaudio_g_tuner,
64f70e7e
HV		 1913};
1914
1915static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1916 .s_routing = tvaudio_s_routing,
1917};
1918
1919static const struct v4l2_subdev_ops tvaudio_ops = {
1920 .core = &tvaudio_core_ops,
1921 .tuner = &tvaudio_tuner_ops,
1922 .audio = &tvaudio_audio_ops,
1923};
1924
1925/* ----------------------------------------------------------------------- */
1926
1927
1928/* i2c registration */
1929
1930static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1931{
1932 struct CHIPSTATE *chip;
1933 struct CHIPDESC *desc;
1934 struct v4l2_subdev *sd;
1935
1936 if (debug) {
1937 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1938 printk(KERN_INFO "tvaudio: known chips: ");
1939 for (desc = chiplist; desc->name != NULL; desc++)
1940 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1941 printk("\n");
2474ed44 1942 }
1da177e4 1943
64f70e7e
HV		 1944 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1945 if (!chip)
1946 return -ENOMEM;
1947 sd = &chip->sd;
1948 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
8a854284 1949
64f70e7e
HV		 1950 /* find description for the chip */
1951 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1952 for (desc = chiplist; desc->name != NULL; desc++) {
1953 if (0 == *(desc->insmodopt))
1954 continue;
1955 if (client->addr < desc->addr_lo ||
1956 client->addr > desc->addr_hi)
1957 continue;
1958 if (desc->checkit && !desc->checkit(chip))
1959 continue;
1da177e4
LT		 1960 break;
1961 }
64f70e7e
HV		 1962 if (desc->name == NULL) {
1963 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1964 kfree(chip);
1965 return -EIO;
1966 }
1967 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1968 if (desc->flags) {
1969 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1970 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1971 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1972 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1973 }
8a854284 1974
64f70e7e
HV		 1975 /* fill required data structures */
1976 if (!id)
1977 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1978 chip->desc = desc;
1979 chip->shadow.count = desc->registers+1;
1980 chip->prevmode = -1;
1981 chip->audmode = V4L2_TUNER_MODE_LANG1;
8a854284 1982
64f70e7e
HV		 1983 /* initialization */
1984 if (desc->initialize != NULL)
1985 desc->initialize(chip);
1986 else
1987 chip_cmd(chip, "init", &desc->init);
8a854284 1988
64f70e7e
HV		 1989 if (desc->flags & CHIP_HAS_VOLUME) {
1990 if (!desc->volfunc) {
1991 /* This shouldn't be happen. Warn user, but keep working
1992 without volume controls
1993 */
1994 v4l2_info(sd, "volume callback undefined!\n");
1995 desc->flags &= ~CHIP_HAS_VOLUME;
1996 } else {
1997 chip->left = desc->leftinit ? desc->leftinit : 65535;
1998 chip->right = desc->rightinit ? desc->rightinit : 65535;
1999 chip_write(chip, desc->leftreg,
2000 desc->volfunc(chip->left));
2001 chip_write(chip, desc->rightreg,
2002 desc->volfunc(chip->right));
2003 }
8a854284 2004 }
64f70e7e
HV		 2005 if (desc->flags & CHIP_HAS_BASSTREBLE) {
2006 if (!desc->bassfunc || !desc->treblefunc) {
2007 /* This shouldn't be happen. Warn user, but keep working
2008 without bass/treble controls
2009 */
2010 v4l2_info(sd, "bass/treble callbacks undefined!\n");
2011 desc->flags &= ~CHIP_HAS_BASSTREBLE;
2012 } else {
2013 chip->treble = desc->trebleinit ?
2014 desc->trebleinit : 32768;
2015 chip->bass = desc->bassinit ?
2016 desc->bassinit : 32768;
2017 chip_write(chip, desc->bassreg,
2018 desc->bassfunc(chip->bass));
2019 chip_write(chip, desc->treblereg,
2020 desc->treblefunc(chip->treble));
1da177e4 2021 }
64f70e7e 2022 }
74cab31c 2023
64f70e7e 2024 chip->thread = NULL;
e4129a9c 2025 init_timer(&chip->wt);
64f70e7e
HV		 2026 if (desc->flags & CHIP_NEED_CHECKMODE) {
2027 if (!desc->getmode || !desc->setmode) {
2028 /* This shouldn't be happen. Warn user, but keep working
2029 without kthread
2030 */
2031 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2032 return 0;
2033 }
2034 /* start async thread */
64f70e7e
HV		 2035 chip->wt.function = chip_thread_wake;
2036 chip->wt.data = (unsigned long)chip;
2037 chip->thread = kthread_run(chip_thread, chip, client->name);
2038 if (IS_ERR(chip->thread)) {
2039 v4l2_warn(sd, "failed to create kthread\n");
2040 chip->thread = NULL;
2041 }
1da177e4
LT		 2042 }
2043 return 0;
2044}
2045
64f70e7e
HV		 2046static int tvaudio_remove(struct i2c_client *client)
2047{
2048 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2049 struct CHIPSTATE *chip = to_state(sd);
2050
2051 del_timer_sync(&chip->wt);
2052 if (chip->thread) {
2053 /* shutdown async thread */
2054 kthread_stop(chip->thread);
2055 chip->thread = NULL;
2056 }
2057
2058 v4l2_device_unregister_subdev(sd);
2059 kfree(chip);
2060 return 0;
2061}
2062
ae429083
JD		 2063/* This driver supports many devices and the idea is to let the driver
2064 detect which device is present. So rather than listing all supported
2065 devices here, we pretend to support a single, fake device type. */
64f70e7e 2066static const struct i2c_device_id tvaudio_id[] = {
ae429083
JD		 2067 { "tvaudio", 0 },
2068 { }
2069};
64f70e7e 2070MODULE_DEVICE_TABLE(i2c, tvaudio_id);
ae429083 2071
7a004d13
HV		 2072static struct i2c_driver tvaudio_driver = {
2073 .driver = {
2074 .owner = THIS_MODULE,
2075 .name = "tvaudio",
2076 },
2077 .probe = tvaudio_probe,
2078 .remove = tvaudio_remove,
2079 .id_table = tvaudio_id,
08e14054 2080};
7a004d13 2081
c6e8d86f 2082module_i2c_driver(tvaudio_driver);
kernel source for telekom puls (alcatel/mediatek)