[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / icside.c

/*
 * Copyright (c) 1996-2004 Russell King.
 *
 * Please note that this platform does not support 32-bit IDE IO.
 */

#include <linux/string.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/errno.h>
#include <linux/ide.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/scatterlist.h>
#include <linux/io.h>

#include <asm/dma.h>
#include <asm/ecard.h>

#define DRV_NAME "icside"

#define ICS_IDENT_OFFSET		0x2280

#define ICS_ARCIN_V5_INTRSTAT		0x0000
#define ICS_ARCIN_V5_INTROFFSET		0x0004
#define ICS_ARCIN_V5_IDEOFFSET		0x2800
#define ICS_ARCIN_V5_IDEALTOFFSET	0x2b80
#define ICS_ARCIN_V5_IDESTEPPING	6

#define ICS_ARCIN_V6_IDEOFFSET_1	0x2000
#define ICS_ARCIN_V6_INTROFFSET_1	0x2200
#define ICS_ARCIN_V6_INTRSTAT_1		0x2290
#define ICS_ARCIN_V6_IDEALTOFFSET_1	0x2380
#define ICS_ARCIN_V6_IDEOFFSET_2	0x3000
#define ICS_ARCIN_V6_INTROFFSET_2	0x3200
#define ICS_ARCIN_V6_INTRSTAT_2		0x3290
#define ICS_ARCIN_V6_IDEALTOFFSET_2	0x3380
#define ICS_ARCIN_V6_IDESTEPPING	6

struct cardinfo {
	unsigned int dataoffset;
	unsigned int ctrloffset;
	unsigned int stepping;
};

static struct cardinfo icside_cardinfo_v5 = {
	.dataoffset	= ICS_ARCIN_V5_IDEOFFSET,
	.ctrloffset	= ICS_ARCIN_V5_IDEALTOFFSET,
	.stepping	= ICS_ARCIN_V5_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_1 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_1,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_1,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_2 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_2,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_2,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

struct icside_state {
	unsigned int channel;
	unsigned int enabled;
	void __iomem *irq_port;
	void __iomem *ioc_base;
	unsigned int sel;
	unsigned int type;
	struct ide_host *host;
};

#define ICS_TYPE_A3IN	0
#define ICS_TYPE_A3USER	1
#define ICS_TYPE_V6	3
#define ICS_TYPE_V5	15
#define ICS_TYPE_NOTYPE	((unsigned int)-1)

/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

static const expansioncard_ops_t icside_ops_arcin_v5 = {
	.irqenable	= icside_irqenable_arcin_v5,
	.irqdisable	= icside_irqdisable_arcin_v5,
};


/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;
	void __iomem *base = state->irq_port;

	state->enabled = 1;

	switch (state->channel) {
	case 0:
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
		readb(base + ICS_ARCIN_V6_INTROFFSET_2);
		break;
	case 1:
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
		readb(base + ICS_ARCIN_V6_INTROFFSET_1);
		break;
	}
}

/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	state->enabled = 0;

	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int icside_irqpending_arcin_v6(struct expansion_card *ec)
{
	struct icside_state *state = ec->irq_data;

	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
	       readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}

static const expansioncard_ops_t icside_ops_arcin_v6 = {
	.irqenable	= icside_irqenable_arcin_v6,
	.irqdisable	= icside_irqdisable_arcin_v6,
	.irqpending	= icside_irqpending_arcin_v6,
};

/*
 * Handle routing of interrupts.  This is called before
 * we write the command to the drive.
 */
static void icside_maskproc(ide_drive_t *drive, int mask)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned long flags;

	local_irq_save(flags);

	state->channel = hwif->channel;

	if (state->enabled && !mask) {
		switch (hwif->channel) {
		case 0:
			writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
			readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
			break;
		case 1:
			writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
			readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
			break;
		}
	} else {
		readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
		readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	}

	local_irq_restore(flags);
}

static const struct ide_port_ops icside_v6_no_dma_port_ops = {
	.maskproc		= icside_maskproc,
};

#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */

/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *	Type	Active		Recovery	Cycle
 *	A	250 (250)	312 (550)	562 (800)
 *	B	187		250		437
 *	C	125 (125)	125 (375)	250 (500)
 *	D	62		125		187
 *
 * (figures in brackets are actual measured timings)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *			Read	Write
 *  	Mode	Active	-- Recovery --	Cycle	IOMD type
 *	MW0	215	50	215	480	A
 *	MW1	80	50	50	150	C
 *	MW2	70	25	25	120	C
 */
static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
{
	int cycle_time, use_dma_info = 0;

	switch (xfer_mode) {
	case XFER_MW_DMA_2:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_1:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_0:
		cycle_time = 480;
		break;

	case XFER_SW_DMA_2:
	case XFER_SW_DMA_1:
	case XFER_SW_DMA_0:
		cycle_time = 480;
		break;
	}

	/*
	 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	 * take care to note the values in the ID...
	 */
	if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
		cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];

	drive->drive_data = cycle_time;

	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
		ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
}

static const struct ide_port_ops icside_v6_port_ops = {
	.set_dma_mode		= icside_set_dma_mode,
	.maskproc		= icside_maskproc,
};

static void icside_dma_host_set(ide_drive_t *drive, int on)
{
}

static int icside_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	drive->waiting_for_dma = 0;

	disable_dma(ec->dma);

	/* Teardown mappings after DMA has completed. */
	ide_destroy_dmatable(drive);

	return get_dma_residue(ec->dma) != 0;
}

static void icside_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	/* We can not enable DMA on both channels simultaneously. */
	BUG_ON(dma_channel_active(ec->dma));
	enable_dma(ec->dma);
}

static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned int dma_mode;

	if (cmd->tf_flags & IDE_TFLAG_WRITE)
		dma_mode = DMA_MODE_WRITE;
	else
		dma_mode = DMA_MODE_READ;

	/*
	 * We can not enable DMA on both channels.
	 */
	BUG_ON(dma_channel_active(ec->dma));

	/*
	 * Ensure that we have the right interrupt routed.
	 */
	icside_maskproc(drive, 0);

	/*
	 * Route the DMA signals to the correct interface.
	 */
	writeb(state->sel | hwif->channel, state->ioc_base);

	/*
	 * Select the correct timing for this drive.
	 */
	set_dma_speed(ec->dma, drive->drive_data);

	/*
	 * Tell the DMA engine about the SG table and
	 * data direction.
	 */
	set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
	set_dma_mode(ec->dma, dma_mode);

	drive->waiting_for_dma = 1;

	return 0;
}

static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
{
	/* issue cmd to drive */
	ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
}

static int icside_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);

	return readb(state->irq_port +
		     (hwif->channel ?
			ICS_ARCIN_V6_INTRSTAT_2 :
			ICS_ARCIN_V6_INTRSTAT_1)) & 1;
}

static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	hwif->dmatable_cpu	= NULL;
	hwif->dmatable_dma	= 0;

	return 0;
}

static const struct ide_dma_ops icside_v6_dma_ops = {
	.dma_host_set		= icside_dma_host_set,
	.dma_setup		= icside_dma_setup,
	.dma_exec_cmd		= icside_dma_exec_cmd,
	.dma_start		= icside_dma_start,
	.dma_end		= icside_dma_end,
	.dma_test_irq		= icside_dma_test_irq,
	.dma_timeout		= ide_dma_timeout,
	.dma_lost_irq		= ide_dma_lost_irq,
};
#else
#define icside_v6_dma_ops NULL
#endif

static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	return -EOPNOTSUPP;
}

static void icside_setup_ports(hw_regs_t *hw, void __iomem *base,
			       struct cardinfo *info, struct expansion_card *ec)
{
	unsigned long port = (unsigned long)base + info->dataoffset;

	hw->io_ports.data_addr	 = port;
	hw->io_ports.error_addr	 = port + (1 << info->stepping);
	hw->io_ports.nsect_addr	 = port + (2 << info->stepping);
	hw->io_ports.lbal_addr	 = port + (3 << info->stepping);
	hw->io_ports.lbam_addr	 = port + (4 << info->stepping);
	hw->io_ports.lbah_addr	 = port + (5 << info->stepping);
	hw->io_ports.device_addr = port + (6 << info->stepping);
	hw->io_ports.status_addr = port + (7 << info->stepping);
	hw->io_ports.ctl_addr	 = (unsigned long)base + info->ctrloffset;

	hw->irq = ec->irq;
	hw->dev = &ec->dev;
	hw->chipset = ide_acorn;
}

static const struct ide_port_info icside_v5_port_info = {
	.host_flags		= IDE_HFLAG_NO_DMA,
};

static int __devinit
icside_register_v5(struct icside_state *state, struct expansion_card *ec)
{
	void __iomem *base;
	struct ide_host *host;
	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
	int ret;

	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
	if (!base)
		return -ENOMEM;

	state->irq_port = base;

	ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
	ec->irqmask  = 1;

	ecard_setirq(ec, &icside_ops_arcin_v5, state);

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v5(ec, 0);

	icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);

	host = ide_host_alloc(&icside_v5_port_info, hws);
	if (host == NULL)
		return -ENODEV;

	state->host = host;

	ecard_set_drvdata(ec, state);

	ret = ide_host_register(host, &icside_v5_port_info, hws);
	if (ret)
		goto err_free;

	return 0;
err_free:
	ide_host_free(host);
	ecard_set_drvdata(ec, NULL);
	return ret;
}

static const struct ide_port_info icside_v6_port_info __initdata = {
	.init_dma		= icside_dma_off_init,
	.port_ops		= &icside_v6_no_dma_port_ops,
	.dma_ops		= &icside_v6_dma_ops,
	.host_flags		= IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
	.mwdma_mask		= ATA_MWDMA2,
	.swdma_mask		= ATA_SWDMA2,
};

static int __devinit
icside_register_v6(struct icside_state *state, struct expansion_card *ec)
{
	void __iomem *ioc_base, *easi_base;
	struct ide_host *host;
	unsigned int sel = 0;
	int ret;
	hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL };
	struct ide_port_info d = icside_v6_port_info;

	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (!ioc_base) {
		ret = -ENOMEM;
		goto out;
	}

	easi_base = ioc_base;

	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
		easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
		if (!easi_base) {
			ret = -ENOMEM;
			goto out;
		}

		/*
		 * Enable access to the EASI region.
		 */
		sel = 1 << 5;
	}

	writeb(sel, ioc_base);

	ecard_setirq(ec, &icside_ops_arcin_v6, state);

	state->irq_port   = easi_base;
	state->ioc_base   = ioc_base;
	state->sel	  = sel;

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v6(ec, 0);

	icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
	icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);

	host = ide_host_alloc(&d, hws);
	if (host == NULL)
		return -ENODEV;

	state->host = host;

	ecard_set_drvdata(ec, state);

	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
		d.init_dma = icside_dma_init;
		d.port_ops = &icside_v6_port_ops;
		d.dma_ops = NULL;
	}

	ret = ide_host_register(host, &d, hws);
	if (ret)
		goto err_free;

	return 0;
err_free:
	ide_host_free(host);
	if (d.dma_ops)
		free_dma(ec->dma);
	ecard_set_drvdata(ec, NULL);
out:
	return ret;
}

static int __devinit
icside_probe(struct expansion_card *ec, const struct ecard_id *id)
{
	struct icside_state *state;
	void __iomem *idmem;
	int ret;

	ret = ecard_request_resources(ec);
	if (ret)
		goto out;

	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
	if (!state) {
		ret = -ENOMEM;
		goto release;
	}

	state->type	= ICS_TYPE_NOTYPE;

	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (idmem) {
		unsigned int type;

		type = readb(idmem + ICS_IDENT_OFFSET) & 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
		ecardm_iounmap(ec, idmem);

		state->type = type;
	}

	switch (state->type) {
	case ICS_TYPE_A3IN:
		dev_warn(&ec->dev, "A3IN unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_A3USER:
		dev_warn(&ec->dev, "A3USER unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_V5:
		ret = icside_register_v5(state, ec);
		break;

	case ICS_TYPE_V6:
		ret = icside_register_v6(state, ec);
		break;

	default:
		dev_warn(&ec->dev, "unknown interface type\n");
		ret = -ENODEV;
		break;
	}

	if (ret == 0)
		goto out;

	kfree(state);
 release:
	ecard_release_resources(ec);
 out:
	return ret;
}

static void __devexit icside_remove(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);

	switch (state->type) {
	case ICS_TYPE_V5:
		/* FIXME: tell IDE to stop using the interface */

		/* Disable interrupts */
		icside_irqdisable_arcin_v5(ec, 0);
		break;

	case ICS_TYPE_V6:
		/* FIXME: tell IDE to stop using the interface */
		if (ec->dma != NO_DMA)
			free_dma(ec->dma);

		/* Disable interrupts */
		icside_irqdisable_arcin_v6(ec, 0);

		/* Reset the ROM pointer/EASI selection */
		writeb(0, state->ioc_base);
		break;
	}

	ecard_set_drvdata(ec, NULL);

	kfree(state);
	ecard_release_resources(ec);
}

static void icside_shutdown(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned long flags;

	/*
	 * Disable interrupts from this card.  We need to do
	 * this before disabling EASI since we may be accessing
	 * this register via that region.
	 */
	local_irq_save(flags);
	ec->ops->irqdisable(ec, 0);
	local_irq_restore(flags);

	/*
	 * Reset the ROM pointer so that we can read the ROM
	 * after a soft reboot.  This also disables access to
	 * the IDE taskfile via the EASI region.
	 */
	if (state->ioc_base)
		writeb(0, state->ioc_base);
}

static const struct ecard_id icside_ids[] = {
	{ MANU_ICS,  PROD_ICS_IDE  },
	{ MANU_ICS2, PROD_ICS2_IDE },
	{ 0xffff, 0xffff }
};

static struct ecard_driver icside_driver = {
	.probe		= icside_probe,
	.remove		= __devexit_p(icside_remove),
	.shutdown	= icside_shutdown,
	.id_table	= icside_ids,
	.drv = {
		.name	= "icside",
	},
};

static int __init icside_init(void)
{
	return ecard_register_driver(&icside_driver);
}

static void __exit icside_exit(void)
{
	ecard_remove_driver(&icside_driver);
}

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS IDE driver");

module_init(icside_init);
module_exit(icside_exit);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (c) 1996-2004 Russell King.
	3	*
	4	* Please note that this platform does not support 32-bit IDE IO.
	5	*/
	6
1da177e4 LT	7	#include <linux/string.h>
	8	#include <linux/module.h>
	9	#include <linux/ioport.h>
	10	#include <linux/slab.h>
	11	#include <linux/blkdev.h>
	12	#include <linux/errno.h>
1da177e4 LT	13	#include <linux/ide.h>
	14	#include <linux/dma-mapping.h>
	15	#include <linux/device.h>
	16	#include <linux/init.h>
	17	#include <linux/scatterlist.h>
ba5b55d0	18	#include <linux/io.h>
1da177e4 LT	19
	20	#include <asm/dma.h>
	21	#include <asm/ecard.h>
1da177e4	22
67717e22 BZ	23	#define DRV_NAME "icside"
67717e22 BZ	24
1da177e4 LT	25	#define ICS_IDENT_OFFSET 0x2280
	26
	27	#define ICS_ARCIN_V5_INTRSTAT 0x0000
	28	#define ICS_ARCIN_V5_INTROFFSET 0x0004
	29	#define ICS_ARCIN_V5_IDEOFFSET 0x2800
	30	#define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
	31	#define ICS_ARCIN_V5_IDESTEPPING 6
	32
	33	#define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
	34	#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
	35	#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
	36	#define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
	37	#define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
	38	#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
	39	#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
	40	#define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
	41	#define ICS_ARCIN_V6_IDESTEPPING 6
	42
	43	struct cardinfo {
	44	unsigned int dataoffset;
	45	unsigned int ctrloffset;
	46	unsigned int stepping;
	47	};
	48
	49	static struct cardinfo icside_cardinfo_v5 = {
	50	.dataoffset = ICS_ARCIN_V5_IDEOFFSET,
	51	.ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
	52	.stepping = ICS_ARCIN_V5_IDESTEPPING,
	53	};
	54
	55	static struct cardinfo icside_cardinfo_v6_1 = {
	56	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
	57	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
	58	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	59	};
	60
	61	static struct cardinfo icside_cardinfo_v6_2 = {
	62	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
	63	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
	64	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	65	};
	66
	67	struct icside_state {
	68	unsigned int channel;
	69	unsigned int enabled;
	70	void __iomem *irq_port;
	71	void __iomem *ioc_base;
26839f09	72	unsigned int sel;
1da177e4	73	unsigned int type;
48c3c107	74	struct ide_host *host;
1da177e4 LT	75	};
	76
	77	#define ICS_TYPE_A3IN 0
	78	#define ICS_TYPE_A3USER 1
	79	#define ICS_TYPE_V6 3
	80	#define ICS_TYPE_V5 15
	81	#define ICS_TYPE_NOTYPE ((unsigned int)-1)
	82
	83	/* ---------------- Version 5 PCB Support Functions --------------------- */
	84	/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	85	* Purpose : enable interrupts from card
	86	*/
	87	static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	88	{
	89	struct icside_state *state = ec->irq_data;
	90
	91	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	92	}
	93
	94	/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	95	* Purpose : disable interrupts from card
	96	*/
	97	static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	98	{
	99	struct icside_state *state = ec->irq_data;
	100
	101	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	102	}
	103
	104	static const expansioncard_ops_t icside_ops_arcin_v5 = {
	105	.irqenable = icside_irqenable_arcin_v5,
	106	.irqdisable = icside_irqdisable_arcin_v5,
	107	};
	108
	109
	110	/* ---------------- Version 6 PCB Support Functions --------------------- */
	111	/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	112	* Purpose : enable interrupts from card
	113	*/
	114	static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	115	{
	116	struct icside_state *state = ec->irq_data;
	117	void __iomem *base = state->irq_port;
	118
	119	state->enabled = 1;
	120
	121	switch (state->channel) {
	122	case 0:
	123	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	124	readb(base + ICS_ARCIN_V6_INTROFFSET_2);
	125	break;
	126	case 1:
	127	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
	128	readb(base + ICS_ARCIN_V6_INTROFFSET_1);
	129	break;
	130	}
	131	}
	132
	133	/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	134	* Purpose : disable interrupts from card
	135	*/
	136	static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	137	{
	138	struct icside_state *state = ec->irq_data;
139
140	state->enabled = 0;
141
142	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
143	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
144	}
145
146	/* Prototype: icside_irqprobe(struct expansion_card *ec)
147	* Purpose : detect an active interrupt from card
148	*/
149	static int icside_irqpending_arcin_v6(struct expansion_card *ec)
150	{
151	struct icside_state *state = ec->irq_data;
152
153	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|
154	readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
155	}
156
157	static const expansioncard_ops_t icside_ops_arcin_v6 = {
158	.irqenable = icside_irqenable_arcin_v6,
159	.irqdisable = icside_irqdisable_arcin_v6,
160	.irqpending = icside_irqpending_arcin_v6,
161	};
162
163	/*
164	* Handle routing of interrupts. This is called before
165	* we write the command to the drive.
166	*/
167	static void icside_maskproc(ide_drive_t *drive, int mask)
168	{
898ec223	169	ide_hwif_t *hwif = drive->hwif;
26839f09 BZ	170	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09 BZ	171	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	172	unsigned long flags;
	173
	174	local_irq_save(flags);
	175
	176	state->channel = hwif->channel;
	177
	178	if (state->enabled && !mask) {
	179	switch (hwif->channel) {
	180	case 0:
	181	writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	182	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	183	break;
	184	case 1:
	185	writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	186	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	187	break;
	188	}
	189	} else {
	190	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	191	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	192	}
	193
	194	local_irq_restore(flags);
	195	}
	196
ac95beed BZ	197	static const struct ide_port_ops icside_v6_no_dma_port_ops = {
	198	.maskproc = icside_maskproc,
	199	};
	200
1da177e4	201	#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
1da177e4 LT	202	/*
	203	* SG-DMA support.
	204	*
	205	* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
	206	* There is only one DMA controller per card, which means that only
	207	* one drive can be accessed at one time. NOTE! We do not enforce that
	208	* here, but we rely on the main IDE driver spotting that both
	209	* interfaces use the same IRQ, which should guarantee this.
	210	*/
	211
1da177e4 LT	212	/*
	213	* Configure the IOMD to give the appropriate timings for the transfer
	214	* mode being requested. We take the advice of the ATA standards, and
	215	* calculate the cycle time based on the transfer mode, and the EIDE
	216	* MW DMA specs that the drive provides in the IDENTIFY command.
	217	*
	218	* We have the following IOMD DMA modes to choose from:
	219	*
	220	* Type Active Recovery Cycle
	221	* A 250 (250) 312 (550) 562 (800)
	222	* B 187 250 437
	223	* C 125 (125) 125 (375) 250 (500)
	224	* D 62 125 187
	225	*
	226	* (figures in brackets are actual measured timings)
	227	*
	228	* However, we also need to take care of the read/write active and
	229	* recovery timings:
	230	*
	231	* Read Write
	232	* Mode Active -- Recovery -- Cycle IOMD type
	233	* MW0 215 50 215 480 A
	234	* MW1 80 50 50 150 C
	235	* MW2 70 25 25 120 C
	236	*/
88b2b32b	237	static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
1da177e4	238	{
f44ae58a	239	int cycle_time, use_dma_info = 0;
1da177e4	240
1da177e4 LT	241	switch (xfer_mode) {
	242	case XFER_MW_DMA_2:
	243	cycle_time = 250;
	244	use_dma_info = 1;
	245	break;
	246
	247	case XFER_MW_DMA_1:
	248	cycle_time = 250;
	249	use_dma_info = 1;
	250	break;
	251
	252	case XFER_MW_DMA_0:
	253	cycle_time = 480;
	254	break;
	255
	256	case XFER_SW_DMA_2:
	257	case XFER_SW_DMA_1:
	258	case XFER_SW_DMA_0:
	259	cycle_time = 480;
	260	break;
	261	}
	262
	263	/*
	264	* If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	265	* take care to note the values in the ID...
	266	*/
4dde4492 BZ	267	if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
4dde4492 BZ	268	cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
1da177e4 LT	269
	270	drive->drive_data = cycle_time;
	271
1da177e4 LT	272	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
1da177e4 LT	273	ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
1da177e4 LT	274	}
1da177e4 LT	275
ac95beed BZ	276	static const struct ide_port_ops icside_v6_port_ops = {
	277	.set_dma_mode = icside_set_dma_mode,
	278	.maskproc = icside_maskproc,
	279	};
	280
15ce926a	281	static void icside_dma_host_set(ide_drive_t *drive, int on)
1da177e4	282	{
1da177e4 LT	283	}
1da177e4 LT	284
1da177e4 LT	285	static int icside_dma_end(ide_drive_t *drive)
1da177e4 LT	286	{
898ec223	287	ide_hwif_t *hwif = drive->hwif;
f8341c1c	288	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	289
	290	drive->waiting_for_dma = 0;
	291
f8341c1c	292	disable_dma(ec->dma);
1da177e4 LT	293
1da177e4 LT	294	/* Teardown mappings after DMA has completed. */
062f9f02	295	ide_destroy_dmatable(drive);
1da177e4	296
f8341c1c	297	return get_dma_residue(ec->dma) != 0;
1da177e4 LT	298	}
	299
	300	static void icside_dma_start(ide_drive_t *drive)
	301	{
898ec223	302	ide_hwif_t *hwif = drive->hwif;
f8341c1c	303	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	304
1da177e4 LT	305	/* We can not enable DMA on both channels simultaneously. */
f8341c1c BZ	306	BUG_ON(dma_channel_active(ec->dma));
f8341c1c BZ	307	enable_dma(ec->dma);
1da177e4 LT	308	}
1da177e4 LT	309
22981694	310	static int icside_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
1da177e4	311	{
898ec223	312	ide_hwif_t *hwif = drive->hwif;
f8341c1c	313	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09	314	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	315	unsigned int dma_mode;
1da177e4 LT	316
22981694	317	if (cmd->tf_flags & IDE_TFLAG_WRITE)
1da177e4 LT	318	dma_mode = DMA_MODE_WRITE;
	319	else
	320	dma_mode = DMA_MODE_READ;
	321
	322	/*
	323	* We can not enable DMA on both channels.
	324	*/
f8341c1c	325	BUG_ON(dma_channel_active(ec->dma));
1da177e4	326
1da177e4 LT	327	/*
	328	* Ensure that we have the right interrupt routed.
	329	*/
	330	icside_maskproc(drive, 0);
	331
	332	/*
	333	* Route the DMA signals to the correct interface.
	334	*/
26839f09	335	writeb(state->sel \| hwif->channel, state->ioc_base);
1da177e4 LT	336
	337	/*
	338	* Select the correct timing for this drive.
	339	*/
f8341c1c	340	set_dma_speed(ec->dma, drive->drive_data);
1da177e4 LT	341
	342	/*
	343	* Tell the DMA engine about the SG table and
	344	* data direction.
	345	*/
22981694	346	set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
f8341c1c	347	set_dma_mode(ec->dma, dma_mode);
1da177e4 LT	348
	349	drive->waiting_for_dma = 1;
	350
	351	return 0;
	352	}
	353
	354	static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
	355	{
	356	/* issue cmd to drive */
	357	ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
	358	}
	359
	360	static int icside_dma_test_irq(ide_drive_t *drive)
	361	{
898ec223	362	ide_hwif_t *hwif = drive->hwif;
26839f09 BZ	363	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09 BZ	364	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	365
	366	return readb(state->irq_port +
	367	(hwif->channel ?
	368	ICS_ARCIN_V6_INTRSTAT_2 :
	369	ICS_ARCIN_V6_INTRSTAT_1)) & 1;
	370	}
	371
91432f48	372	static int icside_dma_init(ide_hwif_t hwif, const struct ide_port_info d)
1da177e4	373	{
1da177e4 LT	374	hwif->dmatable_cpu = NULL;
1da177e4 LT	375	hwif->dmatable_dma = 0;
1da177e4	376
91432f48	377	return 0;
1da177e4	378	}
5e37bdc0	379
f37afdac	380	static const struct ide_dma_ops icside_v6_dma_ops = {
5e37bdc0 BZ	381	.dma_host_set = icside_dma_host_set,
	382	.dma_setup = icside_dma_setup,
	383	.dma_exec_cmd = icside_dma_exec_cmd,
	384	.dma_start = icside_dma_start,
	385	.dma_end = icside_dma_end,
	386	.dma_test_irq = icside_dma_test_irq,
ffa15a69	387	.dma_timeout = ide_dma_timeout,
de23ec9c	388	.dma_lost_irq = ide_dma_lost_irq,
5e37bdc0 BZ	389	};
	390	#else
	391	#define icside_v6_dma_ops NULL
1da177e4 LT	392	#endif
1da177e4 LT	393
91432f48 BZ	394	static int icside_dma_off_init(ide_hwif_t hwif, const struct ide_port_info d)
	395	{
	396	return -EOPNOTSUPP;
	397	}
	398
b25afdf1 BZ	399	static void icside_setup_ports(hw_regs_t hw, void __iomem base,
b25afdf1 BZ	400	struct cardinfo info, struct expansion_card ec)
1da177e4 LT	401	{
1da177e4 LT	402	unsigned long port = (unsigned long)base + info->dataoffset;
1da177e4	403
b25afdf1 BZ	404	hw->io_ports.data_addr = port;
	405	hw->io_ports.error_addr = port + (1 << info->stepping);
	406	hw->io_ports.nsect_addr = port + (2 << info->stepping);
	407	hw->io_ports.lbal_addr = port + (3 << info->stepping);
	408	hw->io_ports.lbam_addr = port + (4 << info->stepping);
	409	hw->io_ports.lbah_addr = port + (5 << info->stepping);
	410	hw->io_ports.device_addr = port + (6 << info->stepping);
	411	hw->io_ports.status_addr = port + (7 << info->stepping);
	412	hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
	413
	414	hw->irq = ec->irq;
	415	hw->dev = &ec->dev;
	416	hw->chipset = ide_acorn;
1da177e4 LT	417	}
1da177e4 LT	418
33050ec7 BZ	419	static const struct ide_port_info icside_v5_port_info = {
	420	.host_flags = IDE_HFLAG_NO_DMA,
	421	};
	422
d16d7667	423	static int __devinit
1da177e4 LT	424	icside_register_v5(struct icside_state state, struct expansion_card ec)
1da177e4 LT	425	{
1da177e4	426	void __iomem *base;
48c3c107	427	struct ide_host *host;
c97c6aca	428	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
8a69580e	429	int ret;
1da177e4	430
10bdaaa0	431	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
1da177e4 LT	432	if (!base)
	433	return -ENOMEM;
	434
	435	state->irq_port = base;
	436
	437	ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	438	ec->irqmask = 1;
c7b87f3d RK	439
c7b87f3d RK	440	ecard_setirq(ec, &icside_ops_arcin_v5, state);
1da177e4 LT	441
	442	/*
	443	* Be on the safe side - disable interrupts
	444	*/
	445	icside_irqdisable_arcin_v5(ec, 0);
	446
b25afdf1 BZ	447	icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
b25afdf1 BZ	448
33050ec7	449	host = ide_host_alloc(&icside_v5_port_info, hws);
48c3c107	450	if (host == NULL)
1da177e4	451	return -ENODEV;
1da177e4	452
48c3c107	453	state->host = host;
1da177e4	454
26839f09 BZ	455	ecard_set_drvdata(ec, state);
26839f09 BZ	456
33050ec7	457	ret = ide_host_register(host, &icside_v5_port_info, hws);
8a69580e BZ	458	if (ret)
8a69580e BZ	459	goto err_free;
1da177e4 LT	460
1da177e4 LT	461	return 0;
8a69580e BZ	462	err_free:
	463	ide_host_free(host);
	464	ecard_set_drvdata(ec, NULL);
	465	return ret;
1da177e4 LT	466	}
1da177e4 LT	467
c413b9b9	468	static const struct ide_port_info icside_v6_port_info __initdata = {
91432f48	469	.init_dma = icside_dma_off_init,
ac95beed	470	.port_ops = &icside_v6_no_dma_port_ops,
5e37bdc0	471	.dma_ops = &icside_v6_dma_ops,
c5dd43ec	472	.host_flags = IDE_HFLAG_SERIALIZE \| IDE_HFLAG_MMIO,
c413b9b9 BZ	473	.mwdma_mask = ATA_MWDMA2,
	474	.swdma_mask = ATA_SWDMA2,
	475	};
	476
d16d7667	477	static int __devinit
1da177e4 LT	478	icside_register_v6(struct icside_state state, struct expansion_card ec)
1da177e4 LT	479	{
1da177e4	480	void __iomem ioc_base, easi_base;
48c3c107	481	struct ide_host *host;
1da177e4 LT	482	unsigned int sel = 0;
1da177e4 LT	483	int ret;
c97c6aca	484	hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL };
c413b9b9	485	struct ide_port_info d = icside_v6_port_info;
1da177e4	486
10bdaaa0	487	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	488	if (!ioc_base) {
	489	ret = -ENOMEM;
	490	goto out;
	491	}
	492
	493	easi_base = ioc_base;
	494
	495	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
10bdaaa0	496	easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
1da177e4 LT	497	if (!easi_base) {
1da177e4 LT	498	ret = -ENOMEM;
10bdaaa0	499	goto out;
1da177e4 LT	500	}
	501
	502	/*
	503	* Enable access to the EASI region.
	504	*/
	505	sel = 1 << 5;
	506	}
	507
	508	writeb(sel, ioc_base);
	509
c7b87f3d	510	ecard_setirq(ec, &icside_ops_arcin_v6, state);
1da177e4 LT	511
	512	state->irq_port = easi_base;
	513	state->ioc_base = ioc_base;
26839f09	514	state->sel = sel;
1da177e4 LT	515
	516	/*
	517	* Be on the safe side - disable interrupts
	518	*/
	519	icside_irqdisable_arcin_v6(ec, 0);
	520
b25afdf1 BZ	521	icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
	522	icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
	523
48c3c107 BZ	524	host = ide_host_alloc(&d, hws);
48c3c107 BZ	525	if (host == NULL)
b25afdf1	526	return -ENODEV;
1da177e4	527
48c3c107	528	state->host = host;
1da177e4	529
26839f09	530	ecard_set_drvdata(ec, state);
1da177e4	531
67717e22	532	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
91432f48	533	d.init_dma = icside_dma_init;
9c391bae	534	d.port_ops = &icside_v6_port_ops;
5e37bdc0	535	d.dma_ops = NULL;
91432f48	536	}
1da177e4	537
d224b626	538	ret = ide_host_register(host, &d, hws);
8a69580e BZ	539	if (ret)
8a69580e BZ	540	goto err_free;
1da177e4 LT	541
1da177e4 LT	542	return 0;
8a69580e BZ	543	err_free:
	544	ide_host_free(host);
	545	if (d.dma_ops)
	546	free_dma(ec->dma);
	547	ecard_set_drvdata(ec, NULL);
	548	out:
1da177e4 LT	549	return ret;
	550	}
	551
	552	static int __devinit
	553	icside_probe(struct expansion_card ec, const struct ecard_id id)
	554	{
	555	struct icside_state *state;
	556	void __iomem *idmem;
	557	int ret;
	558
	559	ret = ecard_request_resources(ec);
	560	if (ret)
	561	goto out;
	562
cc60d8ba	563	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
1da177e4 LT	564	if (!state) {
	565	ret = -ENOMEM;
	566	goto release;
	567	}
	568
1da177e4	569	state->type = ICS_TYPE_NOTYPE;
1da177e4	570
10bdaaa0	571	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	572	if (idmem) {
	573	unsigned int type;
	574
	575	type = readb(idmem + ICS_IDENT_OFFSET) & 1;
	576	type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
	577	type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
	578	type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
10bdaaa0	579	ecardm_iounmap(ec, idmem);
1da177e4 LT	580
	581	state->type = type;
	582	}
	583
	584	switch (state->type) {
	585	case ICS_TYPE_A3IN:
	586	dev_warn(&ec->dev, "A3IN unsupported\n");
	587	ret = -ENODEV;
	588	break;
	589
	590	case ICS_TYPE_A3USER:
	591	dev_warn(&ec->dev, "A3USER unsupported\n");
	592	ret = -ENODEV;
	593	break;
	594
	595	case ICS_TYPE_V5:
	596	ret = icside_register_v5(state, ec);
	597	break;
	598
	599	case ICS_TYPE_V6:
	600	ret = icside_register_v6(state, ec);
	601	break;
	602
	603	default:
	604	dev_warn(&ec->dev, "unknown interface type\n");
	605	ret = -ENODEV;
	606	break;
	607	}
	608
26839f09	609	if (ret == 0)
1da177e4	610	goto out;
1da177e4 LT	611
	612	kfree(state);
	613	release:
	614	ecard_release_resources(ec);
	615	out:
	616	return ret;
	617	}
	618
	619	static void __devexit icside_remove(struct expansion_card *ec)
	620	{
	621	struct icside_state *state = ecard_get_drvdata(ec);
	622
	623	switch (state->type) {
	624	case ICS_TYPE_V5:
	625	/* FIXME: tell IDE to stop using the interface */
	626
	627	/* Disable interrupts */
	628	icside_irqdisable_arcin_v5(ec, 0);
	629	break;
	630
	631	case ICS_TYPE_V6:
	632	/* FIXME: tell IDE to stop using the interface */
	633	if (ec->dma != NO_DMA)
	634	free_dma(ec->dma);
	635
	636	/* Disable interrupts */
	637	icside_irqdisable_arcin_v6(ec, 0);
	638
	639	/* Reset the ROM pointer/EASI selection */
	640	writeb(0, state->ioc_base);
	641	break;
	642	}
	643
	644	ecard_set_drvdata(ec, NULL);
1da177e4	645
1da177e4 LT	646	kfree(state);
	647	ecard_release_resources(ec);
	648	}
	649
	650	static void icside_shutdown(struct expansion_card *ec)
	651	{
	652	struct icside_state *state = ecard_get_drvdata(ec);
	653	unsigned long flags;
	654
	655	/*
	656	* Disable interrupts from this card. We need to do
	657	* this before disabling EASI since we may be accessing
	658	* this register via that region.
	659	*/
	660	local_irq_save(flags);
	661	ec->ops->irqdisable(ec, 0);
	662	local_irq_restore(flags);
	663
	664	/*
	665	* Reset the ROM pointer so that we can read the ROM
	666	* after a soft reboot. This also disables access to
	667	* the IDE taskfile via the EASI region.
	668	*/
	669	if (state->ioc_base)
	670	writeb(0, state->ioc_base);
	671	}
	672
	673	static const struct ecard_id icside_ids[] = {
	674	{ MANU_ICS, PROD_ICS_IDE },
	675	{ MANU_ICS2, PROD_ICS2_IDE },
	676	{ 0xffff, 0xffff }
	677	};
	678
	679	static struct ecard_driver icside_driver = {
	680	.probe = icside_probe,
	681	.remove = __devexit_p(icside_remove),
	682	.shutdown = icside_shutdown,
	683	.id_table = icside_ids,
	684	.drv = {
	685	.name = "icside",
	686	},
	687	};
	688
	689	static int __init icside_init(void)
	690	{
	691	return ecard_register_driver(&icside_driver);
	692	}
	693
1137fb67	694	static void __exit icside_exit(void)
8e27cb11	695	{
1137fb67	696	ecard_remove_driver(&icside_driver);
8e27cb11 BZ	697	}
8e27cb11 BZ	698
1da177e4 LT	699	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	700	MODULE_LICENSE("GPL");
	701	MODULE_DESCRIPTION("ICS IDE driver");
	702
	703	module_init(icside_init);
8e27cb11	704	module_exit(icside_exit);