Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <ttm/ttm_bo_api.h> | |
33 | #include <ttm/ttm_bo_driver.h> | |
34 | #include <ttm/ttm_placement.h> | |
35 | #include <ttm/ttm_module.h> | |
8d7cddcd | 36 | #include <ttm/ttm_page_alloc.h> |
771fe6b9 JG |
37 | #include <drm/drmP.h> |
38 | #include <drm/radeon_drm.h> | |
fa8a1238 | 39 | #include <linux/seq_file.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
771fe6b9 JG |
41 | #include "radeon_reg.h" |
42 | #include "radeon.h" | |
43 | ||
44 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
45 | ||
fa8a1238 DA |
46 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
47 | ||
771fe6b9 JG |
48 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
49 | { | |
50 | struct radeon_mman *mman; | |
51 | struct radeon_device *rdev; | |
52 | ||
53 | mman = container_of(bdev, struct radeon_mman, bdev); | |
54 | rdev = container_of(mman, struct radeon_device, mman); | |
55 | return rdev; | |
56 | } | |
57 | ||
58 | ||
59 | /* | |
60 | * Global memory. | |
61 | */ | |
ba4420c2 | 62 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
771fe6b9 JG |
63 | { |
64 | return ttm_mem_global_init(ref->object); | |
65 | } | |
66 | ||
ba4420c2 | 67 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
771fe6b9 JG |
68 | { |
69 | ttm_mem_global_release(ref->object); | |
70 | } | |
71 | ||
72 | static int radeon_ttm_global_init(struct radeon_device *rdev) | |
73 | { | |
ba4420c2 | 74 | struct drm_global_reference *global_ref; |
771fe6b9 JG |
75 | int r; |
76 | ||
77 | rdev->mman.mem_global_referenced = false; | |
78 | global_ref = &rdev->mman.mem_global_ref; | |
ba4420c2 | 79 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
771fe6b9 JG |
80 | global_ref->size = sizeof(struct ttm_mem_global); |
81 | global_ref->init = &radeon_ttm_mem_global_init; | |
82 | global_ref->release = &radeon_ttm_mem_global_release; | |
ba4420c2 | 83 | r = drm_global_item_ref(global_ref); |
771fe6b9 | 84 | if (r != 0) { |
a987fcaa TH |
85 | DRM_ERROR("Failed setting up TTM memory accounting " |
86 | "subsystem.\n"); | |
771fe6b9 JG |
87 | return r; |
88 | } | |
a987fcaa TH |
89 | |
90 | rdev->mman.bo_global_ref.mem_glob = | |
91 | rdev->mman.mem_global_ref.object; | |
92 | global_ref = &rdev->mman.bo_global_ref.ref; | |
ba4420c2 | 93 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
7f5f4db2 | 94 | global_ref->size = sizeof(struct ttm_bo_global); |
a987fcaa TH |
95 | global_ref->init = &ttm_bo_global_init; |
96 | global_ref->release = &ttm_bo_global_release; | |
ba4420c2 | 97 | r = drm_global_item_ref(global_ref); |
a987fcaa TH |
98 | if (r != 0) { |
99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | |
ba4420c2 | 100 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
a987fcaa TH |
101 | return r; |
102 | } | |
103 | ||
771fe6b9 JG |
104 | rdev->mman.mem_global_referenced = true; |
105 | return 0; | |
106 | } | |
107 | ||
108 | static void radeon_ttm_global_fini(struct radeon_device *rdev) | |
109 | { | |
110 | if (rdev->mman.mem_global_referenced) { | |
ba4420c2 DA |
111 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
112 | drm_global_item_unref(&rdev->mman.mem_global_ref); | |
771fe6b9 JG |
113 | rdev->mman.mem_global_referenced = false; |
114 | } | |
115 | } | |
116 | ||
771fe6b9 JG |
117 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
118 | { | |
119 | return 0; | |
120 | } | |
121 | ||
122 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
123 | struct ttm_mem_type_manager *man) | |
124 | { | |
125 | struct radeon_device *rdev; | |
126 | ||
127 | rdev = radeon_get_rdev(bdev); | |
128 | ||
129 | switch (type) { | |
130 | case TTM_PL_SYSTEM: | |
131 | /* System memory */ | |
132 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
133 | man->available_caching = TTM_PL_MASK_CACHING; | |
134 | man->default_caching = TTM_PL_FLAG_CACHED; | |
135 | break; | |
136 | case TTM_PL_TT: | |
d961db75 | 137 | man->func = &ttm_bo_manager_func; |
d594e46a | 138 | man->gpu_offset = rdev->mc.gtt_start; |
771fe6b9 JG |
139 | man->available_caching = TTM_PL_MASK_CACHING; |
140 | man->default_caching = TTM_PL_FLAG_CACHED; | |
55c93278 | 141 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
771fe6b9 JG |
142 | #if __OS_HAS_AGP |
143 | if (rdev->flags & RADEON_IS_AGP) { | |
144 | if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { | |
145 | DRM_ERROR("AGP is not enabled for memory type %u\n", | |
146 | (unsigned)type); | |
147 | return -EINVAL; | |
148 | } | |
55c93278 | 149 | if (!rdev->ddev->agp->cant_use_aperture) |
0a2d50e3 | 150 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
771fe6b9 JG |
151 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
152 | TTM_PL_FLAG_WC; | |
153 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 | 154 | } |
0c321c79 | 155 | #endif |
771fe6b9 JG |
156 | break; |
157 | case TTM_PL_VRAM: | |
158 | /* "On-card" video ram */ | |
d961db75 | 159 | man->func = &ttm_bo_manager_func; |
d594e46a | 160 | man->gpu_offset = rdev->mc.vram_start; |
771fe6b9 | 161 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
771fe6b9 JG |
162 | TTM_MEMTYPE_FLAG_MAPPABLE; |
163 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
164 | man->default_caching = TTM_PL_FLAG_WC; | |
771fe6b9 JG |
165 | break; |
166 | default: | |
167 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
168 | return -EINVAL; | |
169 | } | |
170 | return 0; | |
171 | } | |
172 | ||
312ea8da JG |
173 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
174 | struct ttm_placement *placement) | |
771fe6b9 | 175 | { |
d03d8589 JG |
176 | struct radeon_bo *rbo; |
177 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
178 | ||
179 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { | |
180 | placement->fpfn = 0; | |
181 | placement->lpfn = 0; | |
182 | placement->placement = &placements; | |
183 | placement->busy_placement = &placements; | |
184 | placement->num_placement = 1; | |
185 | placement->num_busy_placement = 1; | |
186 | return; | |
187 | } | |
188 | rbo = container_of(bo, struct radeon_bo, tbo); | |
771fe6b9 | 189 | switch (bo->mem.mem_type) { |
312ea8da | 190 | case TTM_PL_VRAM: |
e32eb50d | 191 | if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) |
9270eb1b DA |
192 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
193 | else | |
194 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); | |
312ea8da JG |
195 | break; |
196 | case TTM_PL_TT: | |
771fe6b9 | 197 | default: |
312ea8da | 198 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
771fe6b9 | 199 | } |
eaa5fd1a | 200 | *placement = rbo->placement; |
771fe6b9 JG |
201 | } |
202 | ||
203 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static void radeon_move_null(struct ttm_buffer_object *bo, | |
209 | struct ttm_mem_reg *new_mem) | |
210 | { | |
211 | struct ttm_mem_reg *old_mem = &bo->mem; | |
212 | ||
213 | BUG_ON(old_mem->mm_node != NULL); | |
214 | *old_mem = *new_mem; | |
215 | new_mem->mm_node = NULL; | |
216 | } | |
217 | ||
218 | static int radeon_move_blit(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
219 | bool evict, int no_wait_reserve, bool no_wait_gpu, |
220 | struct ttm_mem_reg *new_mem, | |
221 | struct ttm_mem_reg *old_mem) | |
771fe6b9 JG |
222 | { |
223 | struct radeon_device *rdev; | |
224 | uint64_t old_start, new_start; | |
876dc9f3 | 225 | struct radeon_fence *fence; |
7c0d409d | 226 | struct radeon_semaphore *sem = NULL; |
876dc9f3 | 227 | int r, ridx; |
771fe6b9 JG |
228 | |
229 | rdev = radeon_get_rdev(bo->bdev); | |
876dc9f3 | 230 | ridx = radeon_copy_ring_index(rdev); |
d961db75 BS |
231 | old_start = old_mem->start << PAGE_SHIFT; |
232 | new_start = new_mem->start << PAGE_SHIFT; | |
771fe6b9 JG |
233 | |
234 | switch (old_mem->mem_type) { | |
235 | case TTM_PL_VRAM: | |
d594e46a | 236 | old_start += rdev->mc.vram_start; |
771fe6b9 JG |
237 | break; |
238 | case TTM_PL_TT: | |
d594e46a | 239 | old_start += rdev->mc.gtt_start; |
771fe6b9 JG |
240 | break; |
241 | default: | |
242 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
243 | return -EINVAL; | |
244 | } | |
245 | switch (new_mem->mem_type) { | |
246 | case TTM_PL_VRAM: | |
d594e46a | 247 | new_start += rdev->mc.vram_start; |
771fe6b9 JG |
248 | break; |
249 | case TTM_PL_TT: | |
d594e46a | 250 | new_start += rdev->mc.gtt_start; |
771fe6b9 JG |
251 | break; |
252 | default: | |
253 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
254 | return -EINVAL; | |
255 | } | |
876dc9f3 | 256 | if (!rdev->ring[ridx].ready) { |
3000bf39 | 257 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
771fe6b9 JG |
258 | return -EINVAL; |
259 | } | |
003cefe0 AD |
260 | |
261 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); | |
262 | ||
3000bf39 | 263 | /* sync other rings */ |
876dc9f3 CK |
264 | fence = bo->sync_obj; |
265 | if (fence && fence->ring != ridx | |
266 | && !radeon_fence_signaled(fence)) { | |
8f676c4c | 267 | bool sync_to_ring[RADEON_NUM_RINGS] = { }; |
876dc9f3 | 268 | sync_to_ring[fence->ring] = true; |
3000bf39 | 269 | |
7c0d409d | 270 | r = radeon_semaphore_create(rdev, &sem); |
8f676c4c | 271 | if (r) { |
8f676c4c CK |
272 | return r; |
273 | } | |
3000bf39 | 274 | |
876dc9f3 | 275 | r = radeon_semaphore_sync_rings(rdev, sem, sync_to_ring, ridx); |
8f676c4c | 276 | if (r) { |
7c0d409d | 277 | radeon_semaphore_free(rdev, sem, NULL); |
8f676c4c | 278 | return r; |
3000bf39 AD |
279 | } |
280 | } | |
281 | ||
876dc9f3 | 282 | fence = NULL; |
003cefe0 AD |
283 | r = radeon_copy(rdev, old_start, new_start, |
284 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ | |
876dc9f3 | 285 | &fence); |
771fe6b9 JG |
286 | /* FIXME: handle copy error */ |
287 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL, | |
9d87fa21 | 288 | evict, no_wait_reserve, no_wait_gpu, new_mem); |
7c0d409d | 289 | radeon_semaphore_free(rdev, sem, fence); |
771fe6b9 JG |
290 | radeon_fence_unref(&fence); |
291 | return r; | |
292 | } | |
293 | ||
294 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
295 | bool evict, bool interruptible, |
296 | bool no_wait_reserve, bool no_wait_gpu, | |
771fe6b9 JG |
297 | struct ttm_mem_reg *new_mem) |
298 | { | |
299 | struct radeon_device *rdev; | |
300 | struct ttm_mem_reg *old_mem = &bo->mem; | |
301 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
302 | u32 placements; |
303 | struct ttm_placement placement; | |
771fe6b9 JG |
304 | int r; |
305 | ||
306 | rdev = radeon_get_rdev(bo->bdev); | |
307 | tmp_mem = *new_mem; | |
308 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
309 | placement.fpfn = 0; |
310 | placement.lpfn = 0; | |
311 | placement.num_placement = 1; | |
312 | placement.placement = &placements; | |
313 | placement.num_busy_placement = 1; | |
314 | placement.busy_placement = &placements; | |
315 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
316 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
9d87fa21 | 317 | interruptible, no_wait_reserve, no_wait_gpu); |
771fe6b9 JG |
318 | if (unlikely(r)) { |
319 | return r; | |
320 | } | |
df67bed9 DA |
321 | |
322 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
323 | if (unlikely(r)) { | |
324 | goto out_cleanup; | |
325 | } | |
326 | ||
771fe6b9 JG |
327 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
328 | if (unlikely(r)) { | |
329 | goto out_cleanup; | |
330 | } | |
9d87fa21 | 331 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem); |
771fe6b9 JG |
332 | if (unlikely(r)) { |
333 | goto out_cleanup; | |
334 | } | |
9d87fa21 | 335 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 | 336 | out_cleanup: |
42311ff9 | 337 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
338 | return r; |
339 | } | |
340 | ||
341 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
342 | bool evict, bool interruptible, |
343 | bool no_wait_reserve, bool no_wait_gpu, | |
771fe6b9 JG |
344 | struct ttm_mem_reg *new_mem) |
345 | { | |
346 | struct radeon_device *rdev; | |
347 | struct ttm_mem_reg *old_mem = &bo->mem; | |
348 | struct ttm_mem_reg tmp_mem; | |
312ea8da JG |
349 | struct ttm_placement placement; |
350 | u32 placements; | |
771fe6b9 JG |
351 | int r; |
352 | ||
353 | rdev = radeon_get_rdev(bo->bdev); | |
354 | tmp_mem = *new_mem; | |
355 | tmp_mem.mm_node = NULL; | |
312ea8da JG |
356 | placement.fpfn = 0; |
357 | placement.lpfn = 0; | |
358 | placement.num_placement = 1; | |
359 | placement.placement = &placements; | |
360 | placement.num_busy_placement = 1; | |
361 | placement.busy_placement = &placements; | |
362 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
9d87fa21 | 363 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu); |
771fe6b9 JG |
364 | if (unlikely(r)) { |
365 | return r; | |
366 | } | |
9d87fa21 | 367 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem); |
771fe6b9 JG |
368 | if (unlikely(r)) { |
369 | goto out_cleanup; | |
370 | } | |
9d87fa21 | 371 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
771fe6b9 JG |
372 | if (unlikely(r)) { |
373 | goto out_cleanup; | |
374 | } | |
375 | out_cleanup: | |
42311ff9 | 376 | ttm_bo_mem_put(bo, &tmp_mem); |
771fe6b9 JG |
377 | return r; |
378 | } | |
379 | ||
380 | static int radeon_bo_move(struct ttm_buffer_object *bo, | |
9d87fa21 JG |
381 | bool evict, bool interruptible, |
382 | bool no_wait_reserve, bool no_wait_gpu, | |
383 | struct ttm_mem_reg *new_mem) | |
771fe6b9 JG |
384 | { |
385 | struct radeon_device *rdev; | |
386 | struct ttm_mem_reg *old_mem = &bo->mem; | |
387 | int r; | |
388 | ||
389 | rdev = radeon_get_rdev(bo->bdev); | |
390 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { | |
391 | radeon_move_null(bo, new_mem); | |
392 | return 0; | |
393 | } | |
394 | if ((old_mem->mem_type == TTM_PL_TT && | |
395 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
396 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
397 | new_mem->mem_type == TTM_PL_TT)) { | |
af901ca1 | 398 | /* bind is enough */ |
771fe6b9 JG |
399 | radeon_move_null(bo, new_mem); |
400 | return 0; | |
401 | } | |
27cd7769 AD |
402 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
403 | rdev->asic->copy.copy == NULL) { | |
771fe6b9 | 404 | /* use memcpy */ |
1ab2e105 | 405 | goto memcpy; |
771fe6b9 JG |
406 | } |
407 | ||
408 | if (old_mem->mem_type == TTM_PL_VRAM && | |
409 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
1ab2e105 | 410 | r = radeon_move_vram_ram(bo, evict, interruptible, |
9d87fa21 | 411 | no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 JG |
412 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
413 | new_mem->mem_type == TTM_PL_VRAM) { | |
1ab2e105 | 414 | r = radeon_move_ram_vram(bo, evict, interruptible, |
9d87fa21 | 415 | no_wait_reserve, no_wait_gpu, new_mem); |
771fe6b9 | 416 | } else { |
9d87fa21 | 417 | r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
771fe6b9 | 418 | } |
1ab2e105 MD |
419 | |
420 | if (r) { | |
421 | memcpy: | |
9d87fa21 | 422 | r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
1ab2e105 | 423 | } |
771fe6b9 JG |
424 | return r; |
425 | } | |
426 | ||
0a2d50e3 JG |
427 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
428 | { | |
429 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
430 | struct radeon_device *rdev = radeon_get_rdev(bdev); | |
431 | ||
432 | mem->bus.addr = NULL; | |
433 | mem->bus.offset = 0; | |
434 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
435 | mem->bus.base = 0; | |
436 | mem->bus.is_iomem = false; | |
437 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
438 | return -EINVAL; | |
439 | switch (mem->mem_type) { | |
440 | case TTM_PL_SYSTEM: | |
441 | /* system memory */ | |
442 | return 0; | |
443 | case TTM_PL_TT: | |
444 | #if __OS_HAS_AGP | |
445 | if (rdev->flags & RADEON_IS_AGP) { | |
446 | /* RADEON_IS_AGP is set only if AGP is active */ | |
d961db75 | 447 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 | 448 | mem->bus.base = rdev->mc.agp_base; |
365048ff | 449 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
0a2d50e3 JG |
450 | } |
451 | #endif | |
452 | break; | |
453 | case TTM_PL_VRAM: | |
d961db75 | 454 | mem->bus.offset = mem->start << PAGE_SHIFT; |
0a2d50e3 JG |
455 | /* check if it's visible */ |
456 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) | |
457 | return -EINVAL; | |
458 | mem->bus.base = rdev->mc.aper_base; | |
459 | mem->bus.is_iomem = true; | |
ffb57c4b JE |
460 | #ifdef __alpha__ |
461 | /* | |
462 | * Alpha: use bus.addr to hold the ioremap() return, | |
463 | * so we can modify bus.base below. | |
464 | */ | |
465 | if (mem->placement & TTM_PL_FLAG_WC) | |
466 | mem->bus.addr = | |
467 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
468 | mem->bus.size); | |
469 | else | |
470 | mem->bus.addr = | |
471 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
472 | mem->bus.size); | |
473 | ||
474 | /* | |
475 | * Alpha: Use just the bus offset plus | |
476 | * the hose/domain memory base for bus.base. | |
477 | * It then can be used to build PTEs for VRAM | |
478 | * access, as done in ttm_bo_vm_fault(). | |
479 | */ | |
480 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
481 | rdev->ddev->hose->dense_mem_base; | |
482 | #endif | |
0a2d50e3 JG |
483 | break; |
484 | default: | |
485 | return -EINVAL; | |
486 | } | |
487 | return 0; | |
488 | } | |
489 | ||
490 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
491 | { | |
492 | } | |
493 | ||
771fe6b9 JG |
494 | static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg, |
495 | bool lazy, bool interruptible) | |
496 | { | |
497 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); | |
498 | } | |
499 | ||
500 | static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg) | |
501 | { | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static void radeon_sync_obj_unref(void **sync_obj) | |
506 | { | |
507 | radeon_fence_unref((struct radeon_fence **)sync_obj); | |
508 | } | |
509 | ||
510 | static void *radeon_sync_obj_ref(void *sync_obj) | |
511 | { | |
512 | return radeon_fence_ref((struct radeon_fence *)sync_obj); | |
513 | } | |
514 | ||
515 | static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg) | |
516 | { | |
517 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); | |
518 | } | |
519 | ||
649bf3ca JG |
520 | /* |
521 | * TTM backend functions. | |
522 | */ | |
523 | struct radeon_ttm_tt { | |
8e7e7052 | 524 | struct ttm_dma_tt ttm; |
649bf3ca JG |
525 | struct radeon_device *rdev; |
526 | u64 offset; | |
527 | }; | |
528 | ||
529 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, | |
530 | struct ttm_mem_reg *bo_mem) | |
531 | { | |
8e7e7052 | 532 | struct radeon_ttm_tt *gtt = (void*)ttm; |
649bf3ca JG |
533 | int r; |
534 | ||
649bf3ca JG |
535 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
536 | if (!ttm->num_pages) { | |
537 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
538 | ttm->num_pages, bo_mem, ttm); | |
539 | } | |
540 | r = radeon_gart_bind(gtt->rdev, gtt->offset, | |
8e7e7052 | 541 | ttm->num_pages, ttm->pages, gtt->ttm.dma_address); |
649bf3ca JG |
542 | if (r) { |
543 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
544 | ttm->num_pages, (unsigned)gtt->offset); | |
545 | return r; | |
546 | } | |
547 | return 0; | |
548 | } | |
549 | ||
550 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) | |
551 | { | |
8e7e7052 | 552 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 553 | |
649bf3ca JG |
554 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
555 | return 0; | |
556 | } | |
557 | ||
558 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) | |
559 | { | |
8e7e7052 | 560 | struct radeon_ttm_tt *gtt = (void *)ttm; |
649bf3ca | 561 | |
8e7e7052 | 562 | ttm_dma_tt_fini(>t->ttm); |
649bf3ca JG |
563 | kfree(gtt); |
564 | } | |
565 | ||
566 | static struct ttm_backend_func radeon_backend_func = { | |
567 | .bind = &radeon_ttm_backend_bind, | |
568 | .unbind = &radeon_ttm_backend_unbind, | |
569 | .destroy = &radeon_ttm_backend_destroy, | |
570 | }; | |
571 | ||
572 | struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, | |
573 | unsigned long size, uint32_t page_flags, | |
574 | struct page *dummy_read_page) | |
575 | { | |
576 | struct radeon_device *rdev; | |
577 | struct radeon_ttm_tt *gtt; | |
578 | ||
579 | rdev = radeon_get_rdev(bdev); | |
580 | #if __OS_HAS_AGP | |
581 | if (rdev->flags & RADEON_IS_AGP) { | |
582 | return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, | |
583 | size, page_flags, dummy_read_page); | |
584 | } | |
585 | #endif | |
586 | ||
587 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); | |
588 | if (gtt == NULL) { | |
589 | return NULL; | |
590 | } | |
8e7e7052 | 591 | gtt->ttm.ttm.func = &radeon_backend_func; |
649bf3ca | 592 | gtt->rdev = rdev; |
8e7e7052 JG |
593 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { |
594 | kfree(gtt); | |
649bf3ca JG |
595 | return NULL; |
596 | } | |
8e7e7052 | 597 | return >t->ttm.ttm; |
649bf3ca JG |
598 | } |
599 | ||
c52494f6 KRW |
600 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm) |
601 | { | |
602 | struct radeon_device *rdev; | |
8e7e7052 | 603 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 KRW |
604 | unsigned i; |
605 | int r; | |
40f5cf99 | 606 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
c52494f6 KRW |
607 | |
608 | if (ttm->state != tt_unpopulated) | |
609 | return 0; | |
610 | ||
40f5cf99 AD |
611 | if (slave && ttm->sg) { |
612 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
613 | gtt->ttm.dma_address, ttm->num_pages); | |
614 | ttm->state = tt_unbound; | |
615 | return 0; | |
616 | } | |
617 | ||
c52494f6 | 618 | rdev = radeon_get_rdev(ttm->bdev); |
dea7e0ac JG |
619 | #if __OS_HAS_AGP |
620 | if (rdev->flags & RADEON_IS_AGP) { | |
621 | return ttm_agp_tt_populate(ttm); | |
622 | } | |
623 | #endif | |
c52494f6 KRW |
624 | |
625 | #ifdef CONFIG_SWIOTLB | |
626 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 627 | return ttm_dma_populate(>t->ttm, rdev->dev); |
c52494f6 KRW |
628 | } |
629 | #endif | |
630 | ||
631 | r = ttm_pool_populate(ttm); | |
632 | if (r) { | |
633 | return r; | |
634 | } | |
635 | ||
636 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
637 | gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], |
638 | 0, PAGE_SIZE, | |
639 | PCI_DMA_BIDIRECTIONAL); | |
640 | if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { | |
c52494f6 | 641 | while (--i) { |
8e7e7052 | 642 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
c52494f6 | 643 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
8e7e7052 | 644 | gtt->ttm.dma_address[i] = 0; |
c52494f6 KRW |
645 | } |
646 | ttm_pool_unpopulate(ttm); | |
647 | return -EFAULT; | |
648 | } | |
649 | } | |
650 | return 0; | |
651 | } | |
652 | ||
653 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
654 | { | |
655 | struct radeon_device *rdev; | |
8e7e7052 | 656 | struct radeon_ttm_tt *gtt = (void *)ttm; |
c52494f6 | 657 | unsigned i; |
40f5cf99 AD |
658 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
659 | ||
660 | if (slave) | |
661 | return; | |
c52494f6 KRW |
662 | |
663 | rdev = radeon_get_rdev(ttm->bdev); | |
dea7e0ac JG |
664 | #if __OS_HAS_AGP |
665 | if (rdev->flags & RADEON_IS_AGP) { | |
666 | ttm_agp_tt_unpopulate(ttm); | |
667 | return; | |
668 | } | |
669 | #endif | |
c52494f6 KRW |
670 | |
671 | #ifdef CONFIG_SWIOTLB | |
672 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 673 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
c52494f6 KRW |
674 | return; |
675 | } | |
676 | #endif | |
677 | ||
678 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
679 | if (gtt->ttm.dma_address[i]) { |
680 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], | |
c52494f6 KRW |
681 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
682 | } | |
683 | } | |
684 | ||
685 | ttm_pool_unpopulate(ttm); | |
686 | } | |
649bf3ca | 687 | |
771fe6b9 | 688 | static struct ttm_bo_driver radeon_bo_driver = { |
649bf3ca | 689 | .ttm_tt_create = &radeon_ttm_tt_create, |
c52494f6 KRW |
690 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
691 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, | |
771fe6b9 JG |
692 | .invalidate_caches = &radeon_invalidate_caches, |
693 | .init_mem_type = &radeon_init_mem_type, | |
694 | .evict_flags = &radeon_evict_flags, | |
695 | .move = &radeon_bo_move, | |
696 | .verify_access = &radeon_verify_access, | |
697 | .sync_obj_signaled = &radeon_sync_obj_signaled, | |
698 | .sync_obj_wait = &radeon_sync_obj_wait, | |
699 | .sync_obj_flush = &radeon_sync_obj_flush, | |
700 | .sync_obj_unref = &radeon_sync_obj_unref, | |
701 | .sync_obj_ref = &radeon_sync_obj_ref, | |
e024e110 DA |
702 | .move_notify = &radeon_bo_move_notify, |
703 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, | |
0a2d50e3 JG |
704 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
705 | .io_mem_free = &radeon_ttm_io_mem_free, | |
771fe6b9 JG |
706 | }; |
707 | ||
708 | int radeon_ttm_init(struct radeon_device *rdev) | |
709 | { | |
710 | int r; | |
711 | ||
712 | r = radeon_ttm_global_init(rdev); | |
713 | if (r) { | |
714 | return r; | |
715 | } | |
716 | /* No others user of address space so set it to 0 */ | |
717 | r = ttm_bo_device_init(&rdev->mman.bdev, | |
a987fcaa | 718 | rdev->mman.bo_global_ref.ref.object, |
ad49f501 DA |
719 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
720 | rdev->need_dma32); | |
771fe6b9 JG |
721 | if (r) { |
722 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
723 | return r; | |
724 | } | |
0a0c7596 | 725 | rdev->mman.initialized = true; |
4c788679 | 726 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
312ea8da | 727 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
771fe6b9 JG |
728 | if (r) { |
729 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
730 | return r; | |
731 | } | |
441921d5 | 732 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
40f5cf99 AD |
733 | RADEON_GEM_DOMAIN_VRAM, |
734 | NULL, &rdev->stollen_vga_memory); | |
771fe6b9 JG |
735 | if (r) { |
736 | return r; | |
737 | } | |
4c788679 JG |
738 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
739 | if (r) | |
740 | return r; | |
741 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); | |
742 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
771fe6b9 | 743 | if (r) { |
4c788679 | 744 | radeon_bo_unref(&rdev->stollen_vga_memory); |
771fe6b9 JG |
745 | return r; |
746 | } | |
747 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | |
3ce0a23d | 748 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); |
4c788679 | 749 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
312ea8da | 750 | rdev->mc.gtt_size >> PAGE_SHIFT); |
771fe6b9 JG |
751 | if (r) { |
752 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
753 | return r; | |
754 | } | |
755 | DRM_INFO("radeon: %uM of GTT memory ready.\n", | |
3ce0a23d | 756 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
771fe6b9 JG |
757 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
758 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
759 | } | |
fa8a1238 DA |
760 | |
761 | r = radeon_ttm_debugfs_init(rdev); | |
762 | if (r) { | |
763 | DRM_ERROR("Failed to init debugfs\n"); | |
764 | return r; | |
765 | } | |
771fe6b9 JG |
766 | return 0; |
767 | } | |
768 | ||
769 | void radeon_ttm_fini(struct radeon_device *rdev) | |
770 | { | |
4c788679 JG |
771 | int r; |
772 | ||
0a0c7596 JG |
773 | if (!rdev->mman.initialized) |
774 | return; | |
771fe6b9 | 775 | if (rdev->stollen_vga_memory) { |
4c788679 JG |
776 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
777 | if (r == 0) { | |
778 | radeon_bo_unpin(rdev->stollen_vga_memory); | |
779 | radeon_bo_unreserve(rdev->stollen_vga_memory); | |
780 | } | |
781 | radeon_bo_unref(&rdev->stollen_vga_memory); | |
771fe6b9 JG |
782 | } |
783 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
784 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); | |
785 | ttm_bo_device_release(&rdev->mman.bdev); | |
786 | radeon_gart_fini(rdev); | |
787 | radeon_ttm_global_fini(rdev); | |
0a0c7596 | 788 | rdev->mman.initialized = false; |
771fe6b9 JG |
789 | DRM_INFO("radeon: ttm finalized\n"); |
790 | } | |
791 | ||
53595338 DA |
792 | /* this should only be called at bootup or when userspace |
793 | * isn't running */ | |
794 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) | |
795 | { | |
796 | struct ttm_mem_type_manager *man; | |
797 | ||
798 | if (!rdev->mman.initialized) | |
799 | return; | |
800 | ||
801 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; | |
802 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
803 | man->size = size >> PAGE_SHIFT; | |
804 | } | |
805 | ||
771fe6b9 | 806 | static struct vm_operations_struct radeon_ttm_vm_ops; |
f0f37e2f | 807 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
771fe6b9 JG |
808 | |
809 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
810 | { | |
811 | struct ttm_buffer_object *bo; | |
5876dd24 | 812 | struct radeon_device *rdev; |
771fe6b9 JG |
813 | int r; |
814 | ||
5876dd24 | 815 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
771fe6b9 JG |
816 | if (bo == NULL) { |
817 | return VM_FAULT_NOPAGE; | |
818 | } | |
5876dd24 MG |
819 | rdev = radeon_get_rdev(bo->bdev); |
820 | mutex_lock(&rdev->vram_mutex); | |
771fe6b9 | 821 | r = ttm_vm_ops->fault(vma, vmf); |
5876dd24 | 822 | mutex_unlock(&rdev->vram_mutex); |
771fe6b9 JG |
823 | return r; |
824 | } | |
825 | ||
826 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) | |
827 | { | |
828 | struct drm_file *file_priv; | |
829 | struct radeon_device *rdev; | |
830 | int r; | |
831 | ||
832 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { | |
833 | return drm_mmap(filp, vma); | |
834 | } | |
835 | ||
40b3be3f | 836 | file_priv = filp->private_data; |
771fe6b9 JG |
837 | rdev = file_priv->minor->dev->dev_private; |
838 | if (rdev == NULL) { | |
839 | return -EINVAL; | |
840 | } | |
841 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); | |
842 | if (unlikely(r != 0)) { | |
843 | return r; | |
844 | } | |
845 | if (unlikely(ttm_vm_ops == NULL)) { | |
846 | ttm_vm_ops = vma->vm_ops; | |
847 | radeon_ttm_vm_ops = *ttm_vm_ops; | |
848 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; | |
849 | } | |
850 | vma->vm_ops = &radeon_ttm_vm_ops; | |
851 | return 0; | |
852 | } | |
853 | ||
854 | ||
fa8a1238 DA |
855 | #define RADEON_DEBUGFS_MEM_TYPES 2 |
856 | ||
fa8a1238 DA |
857 | #if defined(CONFIG_DEBUG_FS) |
858 | static int radeon_mm_dump_table(struct seq_file *m, void *data) | |
859 | { | |
860 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
861 | struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; | |
862 | struct drm_device *dev = node->minor->dev; | |
863 | struct radeon_device *rdev = dev->dev_private; | |
864 | int ret; | |
865 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; | |
866 | ||
867 | spin_lock(&glob->lru_lock); | |
868 | ret = drm_mm_dump_table(m, mm); | |
869 | spin_unlock(&glob->lru_lock); | |
870 | return ret; | |
871 | } | |
872 | #endif | |
873 | ||
874 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |
875 | { | |
f4e45d02 | 876 | #if defined(CONFIG_DEBUG_FS) |
c52494f6 KRW |
877 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; |
878 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; | |
fa8a1238 DA |
879 | unsigned i; |
880 | ||
fa8a1238 DA |
881 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { |
882 | if (i == 0) | |
883 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); | |
884 | else | |
885 | sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); | |
886 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
887 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; | |
888 | radeon_mem_types_list[i].driver_features = 0; | |
889 | if (i == 0) | |
16f9fdcb | 890 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; |
fa8a1238 | 891 | else |
16f9fdcb | 892 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; |
fa8a1238 DA |
893 | |
894 | } | |
8d7cddcd PN |
895 | /* Add ttm page pool to debugfs */ |
896 | sprintf(radeon_mem_types_names[i], "ttm_page_pool"); | |
897 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
898 | radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; | |
899 | radeon_mem_types_list[i].driver_features = 0; | |
c52494f6 KRW |
900 | radeon_mem_types_list[i++].data = NULL; |
901 | #ifdef CONFIG_SWIOTLB | |
902 | if (swiotlb_nr_tbl()) { | |
903 | sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); | |
904 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; | |
905 | radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; | |
906 | radeon_mem_types_list[i].driver_features = 0; | |
907 | radeon_mem_types_list[i++].data = NULL; | |
908 | } | |
909 | #endif | |
910 | return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); | |
fa8a1238 DA |
911 | |
912 | #endif | |
913 | return 0; | |
914 | } |