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wifi: update bcmdhd.1.579.77.41.1.cn from ampak[3/3]
[GitHub/LineageOS/G12/android_hardware_amlogic_kernel-modules_dhd-driver.git] / bcmdhd.1.579.77.41.1.cn / dhd_sdio.c
CommitLineData
010c3a89
RC		 1/*
2 * DHD Bus Module for SDIO
3 *
4 * Copyright (C) 1999-2017, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 *
25 * <<Broadcom-WL-IPTag/Open:>>
26 *
27 * $Id: dhd_sdio.c 705650 2017-06-19 03:00:50Z $
28 */
29
30#include <typedefs.h>
31#include <osl.h>
32#include <bcmsdh.h>
33
34#ifdef BCMEMBEDIMAGE
35#include BCMEMBEDIMAGE
36#endif /* BCMEMBEDIMAGE */
37
38#include <bcmdefs.h>
39#include <bcmutils.h>
40#include <bcmendian.h>
41#include <bcmdevs.h>
42
43#include <siutils.h>
44#include <hndpmu.h>
45#include <hndsoc.h>
46#include <bcmsdpcm.h>
47#include <hnd_armtrap.h>
48#include <hnd_cons.h>
49#include <sbchipc.h>
50#include <sbhnddma.h>
51
52#include <sdio.h>
53#include <sbsdio.h>
54#include <sbsdpcmdev.h>
55#include <bcmsdpcm.h>
56#include <bcmsdbus.h>
57
58#include <ethernet.h>
59#include <802.1d.h>
60#include <802.11.h>
61
62#include <dngl_stats.h>
63#include <dhd.h>
64#include <dhd_bus.h>
65#include <dhd_proto.h>
66#include <dhd_dbg.h>
67#include <dhdioctl.h>
68#include <sdiovar.h>
69#include <dhd_config.h>
70
71#ifdef PROP_TXSTATUS
72#include <dhd_wlfc.h>
73#endif
74#ifdef DHDTCPACK_SUPPRESS
75#include <dhd_ip.h>
76#endif /* DHDTCPACK_SUPPRESS */
77
78#ifdef BT_OVER_SDIO
79#include <dhd_bt_interface.h>
80#endif /* BT_OVER_SDIO */
81
82bool dhd_mp_halting(dhd_pub_t *dhdp);
83extern void bcmsdh_waitfor_iodrain(void *sdh);
84extern void bcmsdh_reject_ioreqs(void *sdh, bool reject);
85extern bool bcmsdh_fatal_error(void *sdh);
86static int dhdsdio_suspend(void *context);
87static int dhdsdio_resume(void *context);
88
89
90#ifndef DHDSDIO_MEM_DUMP_FNAME
91#define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
92#endif
93
94#define QLEN (1024) /* bulk rx and tx queue lengths */
95#define FCHI (QLEN - 10)
96#define FCLOW (FCHI / 2)
97#define PRIOMASK 7
98
99#define F0_BLOCK_SIZE 32
100#define TXRETRIES 2 /* # of retries for tx frames */
101#define READ_FRM_CNT_RETRIES 3
102#ifndef DHD_RXBOUND
103#define DHD_RXBOUND 50 /* Default for max rx frames in one scheduling */
104#endif
105
106#ifndef DHD_TXBOUND
107#define DHD_TXBOUND 20 /* Default for max tx frames in one scheduling */
108#endif
109
110#define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
111
112#define MEMBLOCK 2048 /* Block size used for downloading of dongle image */
113#define MAX_MEMBLOCK (32 * 1024) /* Block size used for downloading of dongle image */
114
115#define MAX_DATA_BUF (64 * 1024) /* Must be large enough to hold biggest possible glom */
07d6b24a 116#define MAX_MEM_BUF 4096
010c3a89
RC		 117
118#ifndef DHD_FIRSTREAD
119#define DHD_FIRSTREAD 32
120#endif
121#if !ISPOWEROF2(DHD_FIRSTREAD)
122#error DHD_FIRSTREAD is not a power of 2!
123#endif
124
125/* Total length of frame header for dongle protocol */
126#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
127#define SDPCM_HDRLEN_TXGLOM (SDPCM_HDRLEN + SDPCM_HWEXT_LEN)
128#define MAX_TX_PKTCHAIN_CNT SDPCM_MAXGLOM_SIZE
129
130#ifdef SDTEST
131#define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
132#else
133#define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
134#endif
135
136/* Space for header read, limit for data packets */
137#ifndef MAX_HDR_READ
138#define MAX_HDR_READ 32
139#endif
140#if !ISPOWEROF2(MAX_HDR_READ)
141#error MAX_HDR_READ is not a power of 2!
142#endif
143
144#define MAX_RX_DATASZ 2048
145
146/* Maximum milliseconds to wait for F2 to come up */
147#define DHD_WAIT_F2RDY 3000
148
149/* Maximum usec to wait for HTAVAIL to come up */
150#define DHD_WAIT_HTAVAIL 10000
151
152/* Bump up limit on waiting for HT to account for first startup;
153 * if the image is doing a CRC calculation before programming the PMU
154 * for HT availability, it could take a couple hundred ms more, so
155 * max out at a 1 second (1000000us).
156 */
157#if (PMU_MAX_TRANSITION_DLY <= 1000000)
158#undef PMU_MAX_TRANSITION_DLY
159#define PMU_MAX_TRANSITION_DLY 1000000
160#endif
161
162/* hooks for limiting threshold custom tx num in rx processing */
163#define DEFAULT_TXINRX_THRES 0
164#ifndef CUSTOM_TXINRX_THRES
165#define CUSTOM_TXINRX_THRES DEFAULT_TXINRX_THRES
166#endif
167
168/* Value for ChipClockCSR during initial setup */
169#define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ)
170#define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
171
172/* Flags for SDH calls */
173#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
174
175/* Packet free applicable unconditionally for sdio and sdspi. Conditional if
176 * bufpool was present for gspi bus.
177 */
178#define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
179 PKTFREE(bus->dhd->osh, pkt, FALSE);
180DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
181
182#ifdef PKT_STATICS
183pkt_statics_t tx_statics = {0};
184#endif
185
010c3a89
RC		 186#ifdef SUPPORT_MULTIPLE_BOARD_REV_FROM_HW
187extern unsigned int system_hw_rev;
188#endif /* SUPPORT_MULTIPLE_BOARD_REV_FROM_HW */
189
190/* Device console log buffer state */
191#define CONSOLE_LINE_MAX 192
192#define CONSOLE_BUFFER_MAX 2024
193typedef struct dhd_console {
194 uint count; /* Poll interval msec counter */
195 uint log_addr; /* Log struct address (fixed) */
196 hnd_log_t log; /* Log struct (host copy) */
197 uint bufsize; /* Size of log buffer */
198 uint8 *buf; /* Log buffer (host copy) */
199 uint last; /* Last buffer read index */
200} dhd_console_t;
201
202#define REMAP_ENAB(bus) ((bus)->remap)
203#define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
204#define KSO_ENAB(bus) ((bus)->kso)
205#define SR_ENAB(bus) ((bus)->_srenab)
206#define SLPAUTO_ENAB(bus) ((SR_ENAB(bus)) && ((bus)->_slpauto))
207
208#define MIN_RSRC_SR 0x3
209#define CORE_CAPEXT_ADDR_OFFSET (0x64c)
210#define CORE_CAPEXT_SR_SUPPORTED_MASK (1 << 1)
211#define RCTL_MACPHY_DISABLE_MASK (1 << 26)
212#define RCTL_LOGIC_DISABLE_MASK (1 << 27)
213
214#define OOB_WAKEUP_ENAB(bus) ((bus)->_oobwakeup)
215#define GPIO_DEV_SRSTATE 16 /* Host gpio17 mapped to device gpio0 SR state */
216#define GPIO_DEV_SRSTATE_TIMEOUT 320000 /* 320ms */
217#define GPIO_DEV_WAKEUP 17 /* Host gpio17 mapped to device gpio1 wakeup */
218#define CC_CHIPCTRL2_GPIO1_WAKEUP (1 << 0)
219#define CC_CHIPCTRL3_SR_ENG_ENABLE (1 << 2)
220#define OVERFLOW_BLKSZ512_WM 96
221#define OVERFLOW_BLKSZ512_MES 80
222
223#define CC_PMUCC3 (0x3)
224
225#ifdef DHD_UCODE_DOWNLOAD
226/* Ucode host download related macros */
227#define UCODE_DOWNLOAD_REQUEST 0xCAFECAFE
228#define UCODE_DOWNLOAD_COMPLETE 0xABCDABCD
229#endif /* DHD_UCODE_DOWNLOAD */
230
231#if defined(BT_OVER_SDIO)
232#define BTMEM_OFFSET 0x19000000
233/* BIT0 => WLAN Power UP and BIT1=> WLAN Wake */
234#define BT2WLAN_PWRUP_WAKE 0x03
235#define BT2WLAN_PWRUP_ADDR 0x640894 /* This address is specific to 43012B0 */
236
237#define BTFW_MAX_STR_LEN 600
238#define BTFW_DOWNLOAD_BLK_SIZE (BTFW_MAX_STR_LEN/2 + 8)
239
240#define BTFW_ADDR_MODE_UNKNOWN 0
241#define BTFW_ADDR_MODE_EXTENDED 1
242#define BTFW_ADDR_MODE_SEGMENT 2
243#define BTFW_ADDR_MODE_LINEAR32 3
244
245#define BTFW_HEX_LINE_TYPE_DATA 0
246#define BTFW_HEX_LINE_TYPE_END_OF_DATA 1
247#define BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS 2
248#define BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS 4
249#define BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS 5
250
251#endif /* defined (BT_OVER_SDIO) */
252
253/* Private data for SDIO bus interaction */
254typedef struct dhd_bus {
255 dhd_pub_t *dhd;
256
257 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
258 si_t *sih; /* Handle for SI calls */
259 char *vars; /* Variables (from CIS and/or other) */
260 uint varsz; /* Size of variables buffer */
261 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
262
263 sdpcmd_regs_t *regs; /* Registers for SDIO core */
264 uint sdpcmrev; /* SDIO core revision */
265 uint armrev; /* CPU core revision */
266 uint ramrev; /* SOCRAM core revision */
267 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
268 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
269 uint32 srmemsize; /* Size of SRMEM */
270
271 uint32 bus; /* gSPI or SDIO bus */
272 uint32 bus_num; /* bus number */
273 uint32 slot_num; /* slot ID */
274 uint32 hostintmask; /* Copy of Host Interrupt Mask */
275 uint32 intstatus; /* Intstatus bits (events) pending */
276 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
277 bool fcstate; /* State of dongle flow-control */
278
279 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
280 char *fw_path; /* module_param: path to firmware image */
281 char *nv_path; /* module_param: path to nvram vars file */
282
283 uint blocksize; /* Block size of SDIO transfers */
284 uint roundup; /* Max roundup limit */
285
286 struct pktq txq; /* Queue length used for flow-control */
287 uint8 flowcontrol; /* per prio flow control bitmask */
288 uint8 tx_seq; /* Transmit sequence number (next) */
289 uint8 tx_max; /* Maximum transmit sequence allowed */
290
291 uint8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
292 uint8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
293 uint16 nextlen; /* Next Read Len from last header */
294 uint8 rx_seq; /* Receive sequence number (expected) */
295 bool rxskip; /* Skip receive (awaiting NAK ACK) */
296
297 void *glomd; /* Packet containing glomming descriptor */
298 void *glom; /* Packet chain for glommed superframe */
299 uint glomerr; /* Glom packet read errors */
300
301 uint8 *rxbuf; /* Buffer for receiving control packets */
302 uint rxblen; /* Allocated length of rxbuf */
303 uint8 *rxctl; /* Aligned pointer into rxbuf */
304 uint8 *databuf; /* Buffer for receiving big glom packet */
305 uint8 *dataptr; /* Aligned pointer into databuf */
306 uint rxlen; /* Length of valid data in buffer */
307
308 uint8 sdpcm_ver; /* Bus protocol reported by dongle */
309
310 bool intr; /* Use interrupts */
311 bool poll; /* Use polling */
312 bool ipend; /* Device interrupt is pending */
313 bool intdis; /* Interrupts disabled by isr */
314 uint intrcount; /* Count of device interrupt callbacks */
315 uint lastintrs; /* Count as of last watchdog timer */
316 uint spurious; /* Count of spurious interrupts */
317 uint pollrate; /* Ticks between device polls */
318 uint polltick; /* Tick counter */
319 uint pollcnt; /* Count of active polls */
320
321 dhd_console_t console; /* Console output polling support */
322 uint console_addr; /* Console address from shared struct */
323
324 uint regfails; /* Count of R_REG/W_REG failures */
325
326 uint clkstate; /* State of sd and backplane clock(s) */
327 bool activity; /* Activity flag for clock down */
328 int32 idletime; /* Control for activity timeout */
329 int32 idlecount; /* Activity timeout counter */
330 int32 idleclock; /* How to set bus driver when idle */
331 int32 sd_divisor; /* Speed control to bus driver */
332 int32 sd_mode; /* Mode control to bus driver */
333 int32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
334 bool use_rxchain; /* If dhd should use PKT chains */
335 bool sleeping; /* Is SDIO bus sleeping? */
336#if defined(SUPPORT_P2P_GO_PS)
337 wait_queue_head_t bus_sleep;
338#endif /* LINUX && SUPPORT_P2P_GO_PS */
dfb0f3ae
RC		 339 bool ctrl_wait;
340 wait_queue_head_t ctrl_tx_wait;
010c3a89
RC		 341 uint rxflow_mode; /* Rx flow control mode */
342 bool rxflow; /* Is rx flow control on */
343 uint prev_rxlim_hit; /* Is prev rx limit exceeded (per dpc schedule) */
344 bool alp_only; /* Don't use HT clock (ALP only) */
345 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
346 bool usebufpool;
347 int32 txinrx_thres; /* num of in-queued pkts */
348 int32 dotxinrx; /* tx first in dhdsdio_readframes */
349#ifdef SDTEST
350 /* external loopback */
351 bool ext_loop;
352 uint8 loopid;
353
354 /* pktgen configuration */
355 uint pktgen_freq; /* Ticks between bursts */
356 uint pktgen_count; /* Packets to send each burst */
357 uint pktgen_print; /* Bursts between count displays */
358 uint pktgen_total; /* Stop after this many */
359 uint pktgen_minlen; /* Minimum packet data len */
360 uint pktgen_maxlen; /* Maximum packet data len */
361 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
362 uint pktgen_stop; /* Number of tx failures causing stop */
363
364 /* active pktgen fields */
365 uint pktgen_tick; /* Tick counter for bursts */
366 uint pktgen_ptick; /* Burst counter for printing */
367 uint pktgen_sent; /* Number of test packets generated */
368 uint pktgen_rcvd; /* Number of test packets received */
369 uint pktgen_prev_time; /* Time at which previous stats where printed */
370 uint pktgen_prev_sent; /* Number of test packets generated when
371 * previous stats were printed
372 */
373 uint pktgen_prev_rcvd; /* Number of test packets received when
374 * previous stats were printed
375 */
376 uint pktgen_fail; /* Number of failed send attempts */
377 uint16 pktgen_len; /* Length of next packet to send */
378#define PKTGEN_RCV_IDLE (0)
379#define PKTGEN_RCV_ONGOING (1)
380 uint16 pktgen_rcv_state; /* receive state */
381 uint pktgen_rcvd_rcvsession; /* test pkts rcvd per rcv session. */
382#endif /* SDTEST */
383
384 /* Some additional counters */
385 uint tx_sderrs; /* Count of tx attempts with sd errors */
386 uint fcqueued; /* Tx packets that got queued */
387 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
388 uint rx_toolong; /* Receive frames too long to receive */
389 uint rxc_errors; /* SDIO errors when reading control frames */
390 uint rx_hdrfail; /* SDIO errors on header reads */
391 uint rx_badhdr; /* Bad received headers (roosync?) */
392 uint rx_badseq; /* Mismatched rx sequence number */
393 uint fc_rcvd; /* Number of flow-control events received */
394 uint fc_xoff; /* Number which turned on flow-control */
395 uint fc_xon; /* Number which turned off flow-control */
396 uint rxglomfail; /* Failed deglom attempts */
397 uint rxglomframes; /* Number of glom frames (superframes) */
398 uint rxglompkts; /* Number of packets from glom frames */
399 uint f2rxhdrs; /* Number of header reads */
400 uint f2rxdata; /* Number of frame data reads */
401 uint f2txdata; /* Number of f2 frame writes */
402 uint f1regdata; /* Number of f1 register accesses */
403 wake_counts_t wake_counts; /* Wake up counter */
404#ifdef DHDENABLE_TAILPAD
405 uint tx_tailpad_chain; /* Number of tail padding by chaining pad_pkt */
406 uint tx_tailpad_pktget; /* Number of tail padding by new PKTGET */
407#endif /* DHDENABLE_TAILPAD */
408 uint8 *ctrl_frame_buf;
409 uint32 ctrl_frame_len;
410 bool ctrl_frame_stat;
411 uint32 rxint_mode; /* rx interrupt mode */
412 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
413 * Available with socram rev 16
414 * Remap region not DMA-able
415 */
416 bool kso;
417 bool _slpauto;
418 bool _oobwakeup;
419 bool _srenab;
420 bool readframes;
421 bool reqbussleep;
422 uint32 resetinstr;
423 uint32 dongle_ram_base;
424
425 void *glom_pkt_arr[SDPCM_MAXGLOM_SIZE]; /* Array of pkts for glomming */
426 uint32 txglom_cnt; /* Number of pkts in the glom array */
427 uint32 txglom_total_len; /* Total length of pkts in glom array */
428 bool txglom_enable; /* Flag to indicate whether tx glom is enabled/disabled */
429 uint32 txglomsize; /* Glom size limitation */
430#ifdef DHDENABLE_TAILPAD
431 void *pad_pkt;
432#endif /* DHDENABLE_TAILPAD */
433 uint32 dongle_trap_addr; /* device trap addr location in device memory */
434#if defined(BT_OVER_SDIO)
435 char *btfw_path; /* module_param: path to BT firmware image */
436 uint32 bt_use_count; /* Counter that tracks whether BT is using the bus */
437#endif /* defined (BT_OVER_SDIO) */
438 uint txglomframes; /* Number of tx glom frames (superframes) */
439 uint txglompkts; /* Number of packets from tx glom frames */
07d6b24a 440 uint8 *membuf; /* Buffer for receiving big glom packet */
010c3a89
RC		 441} dhd_bus_t;
442
443
444/*
445 * Whenever DHD_IDLE_IMMEDIATE condition is handled, we have to now check if
446 * BT is active too. Instead of adding #ifdef code in all the places, we thought
447 * of adding one macro check as part of the if condition that checks for DHD_IDLE_IMMEDIATE
448 * In case of non BT over SDIO builds, this macro will always return TRUE. In case
449 * of the builds where BT_OVER_SDIO is enabled, it will expand to a condition check
450 * that checks if bt_use_count is zero. So this macro will return equate to 1 if
451 * bt_use_count is 0, indicating that there are no active users and if bt_use_count
452 * is non zero it would return 0 there by preventing the caller from executing the
453 * sleep calls.
454 */
455#ifdef BT_OVER_SDIO
456#define NO_OTHER_ACTIVE_BUS_USER(bus) (bus->bt_use_count == 0)
457#else
458#define NO_OTHER_ACTIVE_BUS_USER(bus) (1)
459#endif /* BT_OVER_SDIO */
460
461/* clkstate */
462#define CLK_NONE 0
463#define CLK_SDONLY 1
464#define CLK_PENDING 2 /* Not used yet */
465#define CLK_AVAIL 3
466
467#define DHD_NOPMU(dhd) (FALSE)
468
469#if defined(BCMSDIOH_STD)
470#define BLK_64_MAXTXGLOM 20
471#endif /* BCMSDIOH_STD */
472
473#ifdef DHD_DEBUG
474static int qcount[NUMPRIO];
475static int tx_packets[NUMPRIO];
476#endif /* DHD_DEBUG */
477
478/* Deferred transmit */
479const uint dhd_deferred_tx = 1;
480
481extern uint dhd_watchdog_ms;
482extern uint sd_f1_blocksize;
483
484
485#if defined(BT_OVER_SDIO)
486extern dhd_pub_t *g_dhd_pub;
487#endif /* (BT_OVER_SDIO) */
488extern void dhd_os_wd_timer(void *bus, uint wdtick);
489int dhd_enableOOB(dhd_pub_t *dhd, bool sleep);
490
491
492/* Tx/Rx bounds */
493uint dhd_txbound;
494uint dhd_rxbound;
495uint dhd_txminmax = DHD_TXMINMAX;
496
497/* override the RAM size if possible */
498#define DONGLE_MIN_RAMSIZE (128 *1024)
499int dhd_dongle_ramsize;
500
501uint dhd_doflow = TRUE;
502uint dhd_dpcpoll = FALSE;
503
504module_param(dhd_doflow, uint, 0644);
505module_param(dhd_dpcpoll, uint, 0644);
506
507static bool dhd_alignctl;
508
509static bool sd1idle;
510
511static bool retrydata;
512#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
513
514static uint watermark = 8;
515static uint mesbusyctrl = 0;
516static const uint firstread = DHD_FIRSTREAD;
517
518/* Retry count for register access failures */
519static const uint retry_limit = 2;
520
521/* Force even SD lengths (some host controllers mess up on odd bytes) */
522static bool forcealign;
523
524#define ALIGNMENT 4
525
526#if (defined(OOB_INTR_ONLY) && defined(HW_OOB)) || defined(FORCE_WOWLAN)
527extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
528#endif
529
530#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
531#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
532#endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
533#define PKTALIGN(osh, p, len, align) \
534 do { \
535 uintptr datalign; \
536 datalign = (uintptr)PKTDATA((osh), (p)); \
537 datalign = ROUNDUP(datalign, (align)) - datalign; \
538 ASSERT(datalign < (align)); \
539 ASSERT(PKTLEN((osh), (p)) >= ((len) + datalign)); \
540 if (datalign) \
541 PKTPULL((osh), (p), (uint)datalign); \
542 PKTSETLEN((osh), (p), (len)); \
543 } while (0)
544
545/* Limit on rounding up frames */
546static const uint max_roundup = 512;
547
548/* Try doing readahead */
549static bool dhd_readahead;
550
551#if defined(BCMSDIOH_TXGLOM_EXT)
552bool
553dhdsdio_is_dataok(dhd_bus_t *bus) {
554 return (((uint8)(bus->tx_max - bus->tx_seq) - bus->dhd->conf->tx_max_offset > 1) && \
555 (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0));
556}
557
558uint8
559dhdsdio_get_databufcnt(dhd_bus_t *bus) {
560 return ((uint8)(bus->tx_max - bus->tx_seq) - 1 - bus->dhd->conf->tx_max_offset);
561}
562#endif
563
564/* To check if there's window offered */
565#if defined(BCMSDIOH_TXGLOM_EXT)
566#define DATAOK(bus) dhdsdio_is_dataok(bus)
567#else
568#define DATAOK(bus) \
569 (((uint8)(bus->tx_max - bus->tx_seq) > 1) && \
570 (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
571#endif
572
573/* To check if there's window offered for ctrl frame */
574#define TXCTLOK(bus) \
575 (((uint8)(bus->tx_max - bus->tx_seq) != 0) && \
576 (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
577
578/* Number of pkts available in dongle for data RX */
579#if defined(BCMSDIOH_TXGLOM_EXT)
580#define DATABUFCNT(bus) dhdsdio_get_databufcnt(bus)
581#else
582#define DATABUFCNT(bus) \
583 ((uint8)(bus->tx_max - bus->tx_seq) - 1)
584#endif
585
586/* Macros to get register read/write status */
587/* NOTE: these assume a local dhdsdio_bus_t *bus! */
588#define R_SDREG(regvar, regaddr, retryvar) \
589do { \
590 retryvar = 0; \
591 do { \
592 regvar = R_REG(bus->dhd->osh, regaddr); \
593 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
594 if (retryvar) { \
595 bus->regfails += (retryvar-1); \
596 if (retryvar > retry_limit) { \
597 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
598 __FUNCTION__, __LINE__)); \
599 regvar = 0; \
600 } \
601 } \
602} while (0)
603
604#define W_SDREG(regval, regaddr, retryvar) \
605do { \
606 retryvar = 0; \
607 do { \
608 W_REG(bus->dhd->osh, regaddr, regval); \
609 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
610 if (retryvar) { \
611 bus->regfails += (retryvar-1); \
612 if (retryvar > retry_limit) \
613 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
614 __FUNCTION__, __LINE__)); \
615 } \
616} while (0)
617
618#define BUS_WAKE(bus) \
619 do { \
620 bus->idlecount = 0; \
621 if ((bus)->sleeping) \
622 dhdsdio_bussleep((bus), FALSE); \
623 } while (0);
624
625/*
626 * pktavail interrupts from dongle to host can be managed in 3 different ways
627 * whenever there is a packet available in dongle to transmit to host.
628 *
629 * Mode 0: Dongle writes the software host mailbox and host is interrupted.
630 * Mode 1: (sdiod core rev >= 4)
631 * Device sets a new bit in the intstatus whenever there is a packet
632 * available in fifo. Host can't clear this specific status bit until all the
633 * packets are read from the FIFO. No need to ack dongle intstatus.
634 * Mode 2: (sdiod core rev >= 4)
635 * Device sets a bit in the intstatus, and host acks this by writing
636 * one to this bit. Dongle won't generate anymore packet interrupts
637 * until host reads all the packets from the dongle and reads a zero to
638 * figure that there are no more packets. No need to disable host ints.
639 * Need to ack the intstatus.
640 */
641
642#define SDIO_DEVICE_HMB_RXINT 0 /* default old way */
643#define SDIO_DEVICE_RXDATAINT_MODE_0 1 /* from sdiod rev 4 */
644#define SDIO_DEVICE_RXDATAINT_MODE_1 2 /* from sdiod rev 4 */
645
646
647#define FRAME_AVAIL_MASK(bus) \
648 ((bus->rxint_mode == SDIO_DEVICE_HMB_RXINT) ? I_HMB_FRAME_IND : I_XMTDATA_AVAIL)
649
650#define DHD_BUS SDIO_BUS
651
652#define PKT_AVAILABLE(bus, intstatus) ((intstatus) & (FRAME_AVAIL_MASK(bus)))
653
654#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
655
656#define GSPI_PR55150_BAILOUT
657
658#ifdef SDTEST
659static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
660static void dhdsdio_sdtest_set(dhd_bus_t *bus, uint count);
661#endif
662
663static int dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size);
664#ifdef DHD_DEBUG
665static int dhd_serialconsole(dhd_bus_t *bus, bool get, bool enable, int *bcmerror);
666#endif /* DHD_DEBUG */
667
668#if defined(DHD_FW_COREDUMP)
669static int dhdsdio_mem_dump(dhd_bus_t *bus);
670#endif /* DHD_FW_COREDUMP */
671static int dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap);
672static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
673
674static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
675static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
676static void dhdsdio_disconnect(void *ptr);
677static bool dhdsdio_chipmatch(uint16 chipid);
678static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
679 void * regsva, uint16 devid);
680static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
681static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
682static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation,
683 bool reset_flag);
684
685static void dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size);
686static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
687 uint8 *buf, uint nbytes,
688 void *pkt, bcmsdh_cmplt_fn_t complete, void *handle);
689static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
690 uint8 *buf, uint nbytes,
691 void *pkt, bcmsdh_cmplt_fn_t complete, void *handle, int max_retry);
692static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt);
693static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq,
694 int prev_chain_total_len, bool last_chained_pkt,
695 int *pad_pkt_len, void **new_pkt
696#if defined(BCMSDIOH_TXGLOM_EXT)
91a2c117 697 , int first_frame
010c3a89
RC		 698#endif
699);
700static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt);
701
702static int dhdsdio_download_firmware(dhd_bus_t *bus, osl_t *osh, void *sdh);
703static int _dhdsdio_download_firmware(dhd_bus_t *bus);
704
705#ifdef DHD_UCODE_DOWNLOAD
706static int dhdsdio_download_ucode_file(struct dhd_bus *bus, char *ucode_path);
707#endif /* DHD_UCODE_DOWNLOAD */
708static int dhdsdio_download_code_file(dhd_bus_t *bus, char *image_path);
709static int dhdsdio_download_nvram(dhd_bus_t *bus);
710#ifdef BCMEMBEDIMAGE
711static int dhdsdio_download_code_array(dhd_bus_t *bus);
712#endif
713static int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep);
714static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok);
715static uint8 dhdsdio_sleepcsr_get(dhd_bus_t *bus);
716static bool dhdsdio_dpc(dhd_bus_t *bus);
717static int dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len);
718static int dhdsdio_set_sdmode(dhd_bus_t *bus, int32 sd_mode);
719static int dhdsdio_sdclk(dhd_bus_t *bus, bool on);
720static void dhdsdio_advertise_bus_cleanup(dhd_pub_t *dhdp);
ccd15baf 721static void dhdsdio_advertise_bus_remove(dhd_pub_t *dhdp);
010c3a89
RC		 722#ifdef SUPPORT_MULTIPLE_BOARD_REV_FROM_DT
723int dhd_get_system_rev(void);
724#endif /* SUPPORT_MULTIPLE_BOARD_REV_FROM_DT */
725
726#ifdef WLMEDIA_HTSF
727#include <htsf.h>
728extern uint32 dhd_get_htsf(void *dhd, int ifidx);
729#endif /* WLMEDIA_HTSF */
730
731#if defined(BT_OVER_SDIO)
732static int extract_hex_field(char * line, uint16 start_pos, uint16 num_chars, uint16 * value);
733static int read_more_btbytes(struct dhd_bus *bus, void * file, char *line, int * addr_mode,
734 uint16 * hi_addr, uint32 * dest_addr, uint8 *data_bytes, uint32 * num_bytes);
735static int dhdsdio_download_btfw(struct dhd_bus *bus, osl_t *osh, void *sdh);
736static int _dhdsdio_download_btfw(struct dhd_bus *bus);
737#endif /* defined (BT_OVER_SDIO) */
738
739#ifdef DHD_ULP
740#include <dhd_ulp.h>
741static int dhd_bus_ulp_reinit_fw(dhd_bus_t *bus);
742#endif /* DHD_ULP */
743
744#ifdef DHD_WAKE_STATUS
745int bcmsdh_get_total_wake(bcmsdh_info_t *bcmsdh);
746int bcmsdh_set_get_wake(bcmsdh_info_t *bcmsdh, int flag);
747#endif /* DHD_WAKE_STATUS */
748
749static void
750dhdsdio_tune_fifoparam(struct dhd_bus *bus)
751{
752 int err;
753 uint8 devctl, wm, mes;
754
755 if (bus->sih->buscorerev >= 15) {
756 /* See .ppt in PR for these recommended values */
757 if (bus->blocksize == 512) {
758 wm = OVERFLOW_BLKSZ512_WM;
759 mes = OVERFLOW_BLKSZ512_MES;
760 } else {
761 mes = bus->blocksize/4;
762 wm = bus->blocksize/4;
763 }
764
765 watermark = wm;
766 mesbusyctrl = mes;
767 } else {
768 DHD_INFO(("skip fifotune: SdioRev(%d) is lower than minimal requested ver\n",
769 bus->sih->buscorerev));
770 return;
771 }
772
773 /* Update watermark */
774 if (wm > 0) {
775 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, wm, &err);
776
777 devctl = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
778 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
779 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
780 }
781
782 /* Update MES */
783 if (mes > 0) {
784 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL,
785 (mes | SBSDIO_MESBUSYCTRL_ENAB), &err);
786 }
787
788 DHD_INFO(("Apply overflow WAR: 0x%02x 0x%02x 0x%02x\n",
789 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err),
790 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, &err),
791 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL, &err)));
792}
793
794static void
795dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size)
796{
797 int32 min_size = DONGLE_MIN_RAMSIZE;
798 /* Restrict the ramsize to user specified limit */
799 DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
800 dhd_dongle_ramsize, min_size));
801 if ((dhd_dongle_ramsize > min_size) &&
802 (dhd_dongle_ramsize < (int32)bus->orig_ramsize))
803 bus->ramsize = dhd_dongle_ramsize;
804}
805
806static int
807dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address)
808{
809 int err = 0;
810 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
811 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
812 if (!err)
813 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
814 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
815 if (!err)
816 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
817 (address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
818 return err;
819}
820
821
822#ifdef USE_OOB_GPIO1
823static int
824dhdsdio_oobwakeup_init(dhd_bus_t *bus)
825{
826 uint32 val, addr, data;
827
828 bcmsdh_gpioouten(bus->sdh, GPIO_DEV_WAKEUP);
829
830 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
831 data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
832
833 /* Set device for gpio1 wakeup */
834 bcmsdh_reg_write(bus->sdh, addr, 4, 2);
835 val = bcmsdh_reg_read(bus->sdh, data, 4);
836 val |= CC_CHIPCTRL2_GPIO1_WAKEUP;
837 bcmsdh_reg_write(bus->sdh, data, 4, val);
838
839 bus->_oobwakeup = TRUE;
840
841 return 0;
842}
843#endif /* USE_OOB_GPIO1 */
844
845/*
846 * Query if FW is in SR mode
847 */
848static bool
849dhdsdio_sr_cap(dhd_bus_t *bus)
850{
851 bool cap = FALSE;
852 uint32 core_capext, addr, data;
853
854 if (bus->sih->chip == BCM43430_CHIP_ID ||
855 bus->sih->chip == BCM43018_CHIP_ID) {
856 /* check if fw initialized sr engine */
857 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, sr_control1);
858 if (bcmsdh_reg_read(bus->sdh, addr, 4) != 0)
859 cap = TRUE;
860
861 return cap;
862 }
863 if (bus->sih->chip == BCM4324_CHIP_ID) {
864 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
865 data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
866 bcmsdh_reg_write(bus->sdh, addr, 4, 3);
867 core_capext = bcmsdh_reg_read(bus->sdh, data, 4);
868 } else if ((bus->sih->chip == BCM4330_CHIP_ID) ||
869 (bus->sih->chip == BCM43362_CHIP_ID) ||
870 (BCM4347_CHIP(bus->sih->chip))) {
871 core_capext = FALSE;
872 } else if ((bus->sih->chip == BCM4335_CHIP_ID) ||
873 (bus->sih->chip == BCM4339_CHIP_ID) ||
874 (bus->sih->chip == BCM43349_CHIP_ID) ||
875 BCM4345_CHIP(bus->sih->chip) ||
876 (bus->sih->chip == BCM4354_CHIP_ID) ||
877 (bus->sih->chip == BCM4358_CHIP_ID) ||
878 (bus->sih->chip == BCM43569_CHIP_ID) ||
879 (bus->sih->chip == BCM4371_CHIP_ID) ||
880 (BCM4349_CHIP(bus->sih->chip)) ||
881 (bus->sih->chip == BCM4350_CHIP_ID) ||
dfb0f3ae
RC		 882 (bus->sih->chip == BCM43012_CHIP_ID) ||
883 (bus->sih->chip == BCM4362_CHIP_ID)) {
010c3a89
RC		 884 core_capext = TRUE;
885 } else {
886 core_capext = bcmsdh_reg_read(bus->sdh,
887 si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, core_cap_ext)),
888 4);
889 core_capext = (core_capext & CORE_CAPEXT_SR_SUPPORTED_MASK);
890 }
891 if (!(core_capext))
892 return FALSE;
893
894 if (bus->sih->chip == BCM4324_CHIP_ID) {
895 /* FIX: Should change to query SR control register instead */
896 cap = TRUE;
897 } else if ((bus->sih->chip == BCM4335_CHIP_ID) ||
898 (bus->sih->chip == BCM4339_CHIP_ID) ||
899 (bus->sih->chip == BCM43349_CHIP_ID) ||
900 BCM4345_CHIP(bus->sih->chip) ||
901 (bus->sih->chip == BCM4354_CHIP_ID) ||
902 (bus->sih->chip == BCM4358_CHIP_ID) ||
903 (bus->sih->chip == BCM43569_CHIP_ID) ||
904 (bus->sih->chip == BCM4371_CHIP_ID) ||
905 (bus->sih->chip == BCM4350_CHIP_ID)) {
906 uint32 enabval = 0;
907 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
908 data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
909 bcmsdh_reg_write(bus->sdh, addr, 4, CC_PMUCC3);
910 enabval = bcmsdh_reg_read(bus->sdh, data, 4);
911
912 if ((bus->sih->chip == BCM4350_CHIP_ID) ||
913 BCM4345_CHIP(bus->sih->chip) ||
914 (bus->sih->chip == BCM4354_CHIP_ID) ||
915 (bus->sih->chip == BCM4358_CHIP_ID) ||
916 (bus->sih->chip == BCM43569_CHIP_ID) ||
917 (bus->sih->chip == BCM4371_CHIP_ID))
918 enabval &= CC_CHIPCTRL3_SR_ENG_ENABLE;
919
920 if (enabval)
921 cap = TRUE;
922 } else {
923 data = bcmsdh_reg_read(bus->sdh,
924 si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, retention_ctl)),
925 4);
926 if ((data & (RCTL_MACPHY_DISABLE_MASK | RCTL_LOGIC_DISABLE_MASK)) == 0)
927 cap = TRUE;
928 }
929
930 return cap;
931}
932
933static int
934dhdsdio_srwar_init(dhd_bus_t *bus)
935{
936 bcmsdh_gpio_init(bus->sdh);
937
938#ifdef USE_OOB_GPIO1
939 dhdsdio_oobwakeup_init(bus);
940#endif
941
942
943 return 0;
944}
945
946static int
947dhdsdio_sr_init(dhd_bus_t *bus)
948{
949 uint8 val;
950 int err = 0;
951
952 if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2))
953 dhdsdio_srwar_init(bus);
954
955
956 if (bus->sih->chip == BCM43012_CHIP_ID) {
957 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
958 val |= 1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
959 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL,
960 1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT, &err);
961 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
962 } else {
963 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
964 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
965 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL,
966 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT, &err);
967 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL);
968 }
969
970#ifdef USE_CMD14
971 /* Add CMD14 Support */
972 dhdsdio_devcap_set(bus,
973 (SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT));
974#endif /* USE_CMD14 */
975
976 if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
977 CHIPID(bus->sih->chip) == BCM43018_CHIP_ID ||
978 CHIPID(bus->sih->chip) == BCM4339_CHIP_ID ||
dfb0f3ae
RC		 979 CHIPID(bus->sih->chip) == BCM43012_CHIP_ID ||
980 CHIPID(bus->sih->chip) == BCM4362_CHIP_ID)
010c3a89
RC		 981 dhdsdio_devcap_set(bus, SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC);
982
983 if (bus->sih->chip == BCM43012_CHIP_ID) {
984 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
985 SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_HT_AVAIL_REQ, &err);
986 } else {
987 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
988 SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_FORCE_HT, &err);
989 }
990 bus->_slpauto = dhd_slpauto ? TRUE : FALSE;
991
992 bus->_srenab = TRUE;
993
994 return 0;
995}
996
997/*
998 * FIX: Be sure KSO bit is enabled
999 * Currently, it's defaulting to 0 which should be 1.
1000 */
1001static int
1002dhdsdio_clk_kso_init(dhd_bus_t *bus)
1003{
1004 uint8 val;
1005 int err = 0;
1006
1007 /* set flag */
1008 bus->kso = TRUE;
1009
1010 /*
1011 * Enable KeepSdioOn (KSO) bit for normal operation
1012 * Default is 0 (4334A0) so set it. Fixed in B0.
1013 */
1014 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, NULL);
1015 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
1016 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
1017 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, val, &err);
1018 if (err)
1019 DHD_ERROR(("%s: SBSDIO_FUNC1_SLEEPCSR err: 0x%x\n", __FUNCTION__, err));
1020 }
1021
1022 return 0;
1023}
1024
1025#define KSO_DBG(x)
1026#define KSO_WAIT_US 50
1027#define KSO_WAIT_MS 1
1028#define KSO_SLEEP_RETRY_COUNT 20
1029#define KSO_WAKE_RETRY_COUNT 100
1030#define ERROR_BCME_NODEVICE_MAX 1
1031
1032#define DEFAULT_MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
1033#ifndef CUSTOM_MAX_KSO_ATTEMPTS
1034#define CUSTOM_MAX_KSO_ATTEMPTS DEFAULT_MAX_KSO_ATTEMPTS
1035#endif
1036
1037static int
1038dhdsdio_clk_kso_enab(dhd_bus_t *bus, bool on)
1039{
1040 uint8 wr_val = 0, rd_val, cmp_val, bmask;
1041 int err = 0;
1042 int try_cnt = 0;
91a2c117 1043
010c3a89
RC		 1044 KSO_DBG(("%s> op:%s\n", __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR")));
1045
1046 wr_val |= (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
1047
1048 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
1049
1050
1051 /* In case of 43012 chip, the chip could go down immediately after KSO bit is cleared.
1052 * So the further reads of KSO register could fail. Thereby just bailing out immediately
1053 * after clearing KSO bit, to avoid polling of KSO bit.
1054 */
1055 if ((!on) && (bus->sih->chip == BCM43012_CHIP_ID)) {
1056 return err;
1057 }
1058
1059 if (on) {
1060 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
1061 bmask = cmp_val;
1062
1063 OSL_SLEEP(3);
1064
1065 } else {
1066 /* Put device to sleep, turn off KSO */
1067 cmp_val = 0;
1068 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
1069 }
1070
1071 do {
1072 rd_val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err);
1073 if (((rd_val & bmask) == cmp_val) && !err)
1074 break;
1075
1076 KSO_DBG(("%s> KSO wr/rd retry:%d, ERR:%x \n", __FUNCTION__, try_cnt, err));
1077
1078 if (((try_cnt + 1) % KSO_SLEEP_RETRY_COUNT) == 0) {
1079 OSL_SLEEP(KSO_WAIT_MS);
1080 } else
1081 OSL_DELAY(KSO_WAIT_US);
1082
1083 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
1084 } while (try_cnt++ < CUSTOM_MAX_KSO_ATTEMPTS);
1085
1086
1087 if (try_cnt > 2)
1088 KSO_DBG(("%s> op:%s, try_cnt:%d, rd_val:%x, ERR:%x \n",
1089 __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err));
1090
1091 if (try_cnt > CUSTOM_MAX_KSO_ATTEMPTS) {
1092 DHD_ERROR(("%s> op:%s, ERROR: try_cnt:%d, rd_val:%x, ERR:%x \n",
1093 __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err));
1094 }
1095
1096 return err;
1097}
1098
1099static int
1100dhdsdio_clk_kso_iovar(dhd_bus_t *bus, bool on)
1101{
1102 int err = 0;
1103
1104 if (on == FALSE) {
1105
1106 BUS_WAKE(bus);
1107 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1108
1109 DHD_ERROR(("%s: KSO disable clk: 0x%x\n", __FUNCTION__,
1110 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
1111 SBSDIO_FUNC1_CHIPCLKCSR, &err)));
1112 dhdsdio_clk_kso_enab(bus, FALSE);
1113 } else {
1114 DHD_ERROR(("%s: KSO enable\n", __FUNCTION__));
1115
1116 /* Make sure we have SD bus access */
1117 if (bus->clkstate == CLK_NONE) {
1118 DHD_ERROR(("%s: Request SD clk\n", __FUNCTION__));
1119 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
1120 }
1121
1122 dhdsdio_clk_kso_enab(bus, TRUE);
1123
1124 DHD_ERROR(("%s: sleepcsr: 0x%x\n", __FUNCTION__,
1125 dhdsdio_sleepcsr_get(bus)));
1126 }
1127
1128 bus->kso = on;
1129 BCM_REFERENCE(err);
1130
1131 return 0;
1132}
1133
1134static uint8
1135dhdsdio_sleepcsr_get(dhd_bus_t *bus)
1136{
1137 int err = 0;
1138 uint8 val = 0;
1139
1140 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err);
1141 if (err)
1142 DHD_TRACE(("Failed to read SLEEPCSR: %d\n", err));
1143
1144 return val;
1145}
1146
1147uint8
1148dhdsdio_devcap_get(dhd_bus_t *bus)
1149{
1150 return bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, NULL);
1151}
1152
1153static int
1154dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap)
1155{
1156 int err = 0;
1157
1158 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, cap, &err);
1159 if (err)
1160 DHD_ERROR(("%s: devcap set err: 0x%x\n", __FUNCTION__, err));
1161
1162 return 0;
1163}
1164
1165static int
1166dhdsdio_clk_devsleep_iovar(dhd_bus_t *bus, bool on)
1167{
1168 int err = 0, retry;
1169 uint8 val;
1170
1171 retry = 0;
1172 if (on == TRUE) {
1173 /* Enter Sleep */
1174
1175 /* Be sure we request clk before going to sleep
1176 * so we can wake-up with clk request already set
1177 * else device can go back to sleep immediately
1178 */
1179 if (!SLPAUTO_ENAB(bus))
1180 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1181 else {
1182 val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
1183 if ((val & SBSDIO_CSR_MASK) == 0) {
1184 DHD_ERROR(("%s: No clock before enter sleep:0x%x\n",
1185 __FUNCTION__, val));
1186
1187 /* Reset clock request */
1188 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1189 SBSDIO_ALP_AVAIL_REQ, &err);
1190 DHD_ERROR(("%s: clock before sleep:0x%x\n", __FUNCTION__,
1191 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
1192 SBSDIO_FUNC1_CHIPCLKCSR, &err)));
1193 }
1194 }
1195
1196 DHD_TRACE(("%s: clk before sleep: 0x%x\n", __FUNCTION__,
1197 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
1198 SBSDIO_FUNC1_CHIPCLKCSR, &err)));
1199#ifdef USE_CMD14
1200 err = bcmsdh_sleep(bus->sdh, TRUE);
1201#else
1202 if ((SLPAUTO_ENAB(bus)) && (bus->idleclock == DHD_IDLE_STOP)) {
1203 if (sd1idle) {
1204 /* Change to SD1 mode */
1205 dhdsdio_set_sdmode(bus, 1);
1206 }
1207 }
1208
1209 err = dhdsdio_clk_kso_enab(bus, FALSE);
1210 if (OOB_WAKEUP_ENAB(bus))
1211 {
1212 err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, FALSE); /* GPIO_1 is off */
1213 }
1214#endif /* USE_CMD14 */
1215
1216 if ((SLPAUTO_ENAB(bus)) && (bus->idleclock != DHD_IDLE_ACTIVE)) {
1217 DHD_TRACE(("%s: Turnoff SD clk\n", __FUNCTION__));
1218 /* Now remove the SD clock */
1219 err = dhdsdio_sdclk(bus, FALSE);
1220 }
1221 } else {
1222 /* Exit Sleep */
1223 /* Make sure we have SD bus access */
1224 if (bus->clkstate == CLK_NONE) {
1225 DHD_TRACE(("%s: Request SD clk\n", __FUNCTION__));
1226 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
1227 }
1228
1229 if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2)) {
1230 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
1231 (bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) != TRUE),
1232 GPIO_DEV_SRSTATE_TIMEOUT);
1233
1234 if (bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) == FALSE) {
1235 DHD_ERROR(("ERROR: GPIO_DEV_SRSTATE still low!\n"));
1236 }
1237 }
1238#ifdef USE_CMD14
1239 err = bcmsdh_sleep(bus->sdh, FALSE);
1240 if (SLPAUTO_ENAB(bus) && (err != 0)) {
1241 OSL_DELAY(10000);
1242 DHD_TRACE(("%s: Resync device sleep\n", __FUNCTION__));
1243
1244 /* Toggle sleep to resync with host and device */
1245 err = bcmsdh_sleep(bus->sdh, TRUE);
1246 OSL_DELAY(10000);
1247 err = bcmsdh_sleep(bus->sdh, FALSE);
1248
1249 if (err) {
1250 OSL_DELAY(10000);
1251 DHD_ERROR(("%s: CMD14 exit failed again!\n", __FUNCTION__));
1252
1253 /* Toggle sleep to resync with host and device */
1254 err = bcmsdh_sleep(bus->sdh, TRUE);
1255 OSL_DELAY(10000);
1256 err = bcmsdh_sleep(bus->sdh, FALSE);
1257 if (err) {
1258 DHD_ERROR(("%s: CMD14 exit failed twice!\n", __FUNCTION__));
1259 DHD_ERROR(("%s: FATAL: Device non-response!\n",
1260 __FUNCTION__));
1261 err = 0;
1262 }
1263 }
1264 }
1265#else
1266 if (OOB_WAKEUP_ENAB(bus))
1267 {
1268 err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, TRUE); /* GPIO_1 is on */
1269 }
1270 do {
1271 err = dhdsdio_clk_kso_enab(bus, TRUE);
1272 if (err)
1273 OSL_SLEEP(10);
1274 } while ((err != 0) && (++retry < 3));
1275
1276 if (err != 0) {
1277 DHD_ERROR(("ERROR: kso set failed retry: %d\n", retry));
1278#ifndef BT_OVER_SDIO
1279 err = 0; /* continue anyway */
1280#endif /* BT_OVER_SDIO */
1281 }
1282
1283 if ((SLPAUTO_ENAB(bus)) && (bus->idleclock == DHD_IDLE_STOP)) {
1284 dhdsdio_set_sdmode(bus, bus->sd_mode);
1285 }
1286#endif /* !USE_CMD14 */
1287
1288 if (err == 0) {
1289 uint8 csr;
1290
1291 /* Wait for device ready during transition to wake-up */
1292 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
1293 (((csr = dhdsdio_sleepcsr_get(bus)) &
1294 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK) !=
1295 (SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)), (20000));
1296
1297 DHD_TRACE(("%s: ExitSleep sleepcsr: 0x%x\n", __FUNCTION__, csr));
1298
1299 if (!(csr & SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)) {
1300 DHD_ERROR(("%s:ERROR: ExitSleep device NOT Ready! 0x%x\n",
1301 __FUNCTION__, csr));
1302 err = BCME_NODEVICE;
1303 }
1304
1305 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
1306 (((csr = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
1307 SBSDIO_FUNC1_CHIPCLKCSR, &err)) & SBSDIO_HT_AVAIL) !=
1308 (SBSDIO_HT_AVAIL)), (DHD_WAIT_HTAVAIL));
1309
1310 DHD_TRACE(("%s: SBSDIO_FUNC1_CHIPCLKCSR : 0x%x\n", __FUNCTION__, csr));
1311 if (!err && ((csr & SBSDIO_HT_AVAIL) != SBSDIO_HT_AVAIL)) {
1312 DHD_ERROR(("%s:ERROR: device NOT Ready! 0x%x\n",
1313 __FUNCTION__, csr));
1314 err = BCME_NODEVICE;
1315 }
1316 }
1317 }
1318
1319 /* Update if successful */
1320 if (err == 0)
1321 bus->kso = on ? FALSE : TRUE;
1322 else {
1323 DHD_ERROR(("%s: Sleep request failed: kso:%d on:%d err:%d\n",
1324 __FUNCTION__, bus->kso, on, err));
1325 if (!on && retry > 2)
1326 bus->kso = FALSE;
1327 }
1328
1329 return err;
1330}
1331
1332/* Turn backplane clock on or off */
1333static int
1334dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
1335{
1336#define HT_AVAIL_ERROR_MAX 10
1337 static int ht_avail_error = 0;
1338 int err;
1339 uint8 clkctl, clkreq, devctl;
1340 bcmsdh_info_t *sdh;
1341
1342 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1343
1344 clkctl = 0;
1345 sdh = bus->sdh;
1346
1347
1348 if (!KSO_ENAB(bus))
1349 return BCME_OK;
1350
1351 if (SLPAUTO_ENAB(bus)) {
1352 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
1353 return BCME_OK;
1354 }
1355
1356 if (on) {
1357 /* Request HT Avail */
1358 clkreq = bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
1359
1360
1361
1362 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
1363 if (err) {
1364 ht_avail_error++;
1365 if (ht_avail_error < HT_AVAIL_ERROR_MAX) {
1366 DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
1367 }
1368
1369#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
1370 else if (ht_avail_error == HT_AVAIL_ERROR_MAX) {
1371 bus->dhd->hang_reason = HANG_REASON_HT_AVAIL_ERROR;
1372 dhd_os_send_hang_message(bus->dhd);
1373 }
1374#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */
1375 return BCME_ERROR;
1376 } else {
1377 ht_avail_error = 0;
1378 }
1379
1380
1381 /* Check current status */
1382 clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
1383 if (err) {
1384 DHD_ERROR(("%s: HT Avail read error: %d\n", __FUNCTION__, err));
1385 return BCME_ERROR;
1386 }
1387
1388#if !defined(OOB_INTR_ONLY)
1389 /* Go to pending and await interrupt if appropriate */
1390 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
1391 /* Allow only clock-available interrupt */
1392 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
1393 if (err) {
1394 DHD_ERROR(("%s: Devctl access error setting CA: %d\n",
1395 __FUNCTION__, err));
1396 return BCME_ERROR;
1397 }
1398
1399 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
1400 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
1401 DHD_INFO(("CLKCTL: set PENDING\n"));
1402 bus->clkstate = CLK_PENDING;
1403 return BCME_OK;
1404 } else
1405#endif /* !defined (OOB_INTR_ONLY) */
1406 {
1407 if (bus->clkstate == CLK_PENDING) {
1408 /* Cancel CA-only interrupt filter */
1409 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
1410 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1411 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
1412 }
1413 }
1414
1415 /* Otherwise, wait here (polling) for HT Avail */
1416 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1417 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
1418 ((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1419 SBSDIO_FUNC1_CHIPCLKCSR, &err)),
1420 !SBSDIO_CLKAV(clkctl, bus->alp_only)), PMU_MAX_TRANSITION_DLY);
1421 }
1422 if (err) {
1423 DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
1424 return BCME_ERROR;
1425 }
1426 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1427 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
1428 __FUNCTION__, PMU_MAX_TRANSITION_DLY, clkctl));
1429 return BCME_ERROR;
1430 }
1431
1432 /* Mark clock available */
1433 bus->clkstate = CLK_AVAIL;
1434 DHD_INFO(("CLKCTL: turned ON\n"));
1435
1436#if defined(DHD_DEBUG)
1437 if (bus->alp_only == TRUE) {
1438#if !defined(BCMLXSDMMC)
1439 if (!SBSDIO_ALPONLY(clkctl)) {
1440 DHD_ERROR(("%s: HT Clock, when ALP Only\n", __FUNCTION__));
1441 }
1442#endif /* !defined(BCMLXSDMMC) */
1443 } else {
1444 if (SBSDIO_ALPONLY(clkctl)) {
1445 DHD_ERROR(("%s: HT Clock should be on.\n", __FUNCTION__));
1446 }
1447 }
1448#endif /* defined (DHD_DEBUG) */
1449
1450 bus->activity = TRUE;
1451#ifdef DHD_USE_IDLECOUNT
1452 bus->idlecount = 0;
1453#endif /* DHD_USE_IDLECOUNT */
1454 } else {
1455 clkreq = 0;
1456
1457 if (bus->clkstate == CLK_PENDING) {
1458 /* Cancel CA-only interrupt filter */
1459 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
1460 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1461 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
1462 }
1463
1464 bus->clkstate = CLK_SDONLY;
1465 if (!SR_ENAB(bus)) {
1466 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
1467 DHD_INFO(("CLKCTL: turned OFF\n"));
1468 if (err) {
1469 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
1470 __FUNCTION__, err));
1471 return BCME_ERROR;
1472 }
1473 }
1474 }
1475 return BCME_OK;
1476}
1477
1478/* Change SD1/SD4 bus mode */
1479static int
1480dhdsdio_set_sdmode(dhd_bus_t *bus, int32 sd_mode)
1481{
1482 int err;
1483
1484 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
1485 &sd_mode, sizeof(sd_mode), TRUE);
1486 if (err) {
1487 DHD_ERROR(("%s: error changing sd_mode: %d\n",
1488 __FUNCTION__, err));
1489 return BCME_ERROR;
1490 }
1491 return BCME_OK;
1492}
1493
1494/* Change idle/active SD state */
1495static int
1496dhdsdio_sdclk(dhd_bus_t *bus, bool on)
1497{
1498 int err;
1499 int32 iovalue;
1500
1501 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1502
1503 if (on) {
1504 if (bus->idleclock == DHD_IDLE_STOP) {
1505 /* Turn on clock and restore mode */
1506 iovalue = 1;
1507 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
1508 &iovalue, sizeof(iovalue), TRUE);
1509 if (err) {
1510 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
1511 __FUNCTION__, err));
1512 return BCME_ERROR;
1513 }
1514
1515 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
1516 /* Restore clock speed */
1517 iovalue = bus->sd_divisor;
1518 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
1519 &iovalue, sizeof(iovalue), TRUE);
1520 if (err) {
1521 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
1522 __FUNCTION__, err));
1523 return BCME_ERROR;
1524 }
1525 }
1526 bus->clkstate = CLK_SDONLY;
1527 } else {
1528 /* Stop or slow the SD clock itself */
1529 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
1530 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
1531 __FUNCTION__, bus->sd_divisor, bus->sd_mode));
1532 return BCME_ERROR;
1533 }
1534 if (bus->idleclock == DHD_IDLE_STOP) {
1535 iovalue = 0;
1536 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
1537 &iovalue, sizeof(iovalue), TRUE);
1538 if (err) {
1539 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
1540 __FUNCTION__, err));
1541 return BCME_ERROR;
1542 }
1543 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
1544 /* Set divisor to idle value */
1545 iovalue = bus->idleclock;
1546 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
1547 &iovalue, sizeof(iovalue), TRUE);
1548 if (err) {
1549 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
1550 __FUNCTION__, err));
1551 return BCME_ERROR;
1552 }
1553 }
1554 bus->clkstate = CLK_NONE;
1555 }
1556
1557 return BCME_OK;
1558}
1559
1560/* Transition SD and backplane clock readiness */
1561static int
1562dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
1563{
1564 int ret = BCME_OK;
1565#ifdef DHD_DEBUG
1566 uint oldstate = bus->clkstate;
1567#endif /* DHD_DEBUG */
1568
1569 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1570
1571 /* Early exit if we're already there */
1572 if (bus->clkstate == target) {
1573 if (target == CLK_AVAIL) {
1574 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1575 bus->activity = TRUE;
1576#ifdef DHD_USE_IDLECOUNT
1577 bus->idlecount = 0;
1578#endif /* DHD_USE_IDLECOUNT */
1579 }
1580 return ret;
1581 }
1582
1583 switch (target) {
1584 case CLK_AVAIL:
1585 /* Make sure SD clock is available */
1586 if (bus->clkstate == CLK_NONE)
1587 dhdsdio_sdclk(bus, TRUE);
1588 /* Now request HT Avail on the backplane */
1589 ret = dhdsdio_htclk(bus, TRUE, pendok);
1590 if (ret == BCME_OK) {
1591 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1592 bus->activity = TRUE;
1593#ifdef DHD_USE_IDLECOUNT
1594 bus->idlecount = 0;
1595#endif /* DHD_USE_IDLECOUNT */
1596 }
1597 break;
1598
1599 case CLK_SDONLY:
1600
1601#ifdef BT_OVER_SDIO
1602 /*
1603 * If the request is to switch off Back plane clock,
1604 * confirm that BT is inactive before doing so.
1605 * If this call had come from Non Watchdog context any way
1606 * the Watchdog would switch off the clock again when
1607 * nothing is to be done & Bt has finished using the bus.
1608 */
1609 if (bus->bt_use_count != 0) {
1610 DHD_INFO(("%s(): Req CLK_SDONLY, BT is active %d not switching off \r\n",
1611 __FUNCTION__, bus->bt_use_count));
1612 ret = BCME_OK;
1613 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1614 break;
1615 }
1616
1617 DHD_INFO(("%s(): Request CLK_NONE BT is NOT active switching off \r\n",
1618 __FUNCTION__));
1619#endif /* BT_OVER_SDIO */
1620
1621 /* Remove HT request, or bring up SD clock */
1622 if (bus->clkstate == CLK_NONE)
1623 ret = dhdsdio_sdclk(bus, TRUE);
1624 else if (bus->clkstate == CLK_AVAIL)
1625 ret = dhdsdio_htclk(bus, FALSE, FALSE);
1626 else
1627 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
1628 bus->clkstate, target));
1629 if (ret == BCME_OK) {
1630 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1631 }
1632 break;
1633
1634 case CLK_NONE:
1635
1636#ifdef BT_OVER_SDIO
1637 /*
1638 * If the request is to switch off Back plane clock,
1639 * confirm that BT is inactive before doing so.
1640 * If this call had come from Non Watchdog context any way
1641 * the Watchdog would switch off the clock again when
1642 * nothing is to be done & Bt has finished using the bus.
1643 */
1644 if (bus->bt_use_count != 0) {
1645 DHD_INFO(("%s(): Request CLK_NONE BT is active %d not switching off \r\n",
1646 __FUNCTION__, bus->bt_use_count));
1647 ret = BCME_OK;
1648 break;
1649 }
1650
1651 DHD_INFO(("%s(): Request CLK_NONE BT is NOT active switching off \r\n",
1652 __FUNCTION__));
1653#endif /* BT_OVER_SDIO */
1654
1655 /* Make sure to remove HT request */
1656 if (bus->clkstate == CLK_AVAIL)
1657 ret = dhdsdio_htclk(bus, FALSE, FALSE);
1658 /* Now remove the SD clock */
1659 ret = dhdsdio_sdclk(bus, FALSE);
1660#ifdef DHD_DEBUG
1661 if (dhd_console_ms == 0)
1662#endif /* DHD_DEBUG */
1663 if (bus->poll == 0)
1664 dhd_os_wd_timer(bus->dhd, 0);
1665 break;
1666 }
1667#ifdef DHD_DEBUG
1668 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1669#endif /* DHD_DEBUG */
1670
1671 return ret;
1672}
1673
1674static int
1675dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
1676{
1677 int err = 0;
1678 bcmsdh_info_t *sdh = bus->sdh;
1679 sdpcmd_regs_t *regs = bus->regs;
1680 uint retries = 0;
1681
1682 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
1683 (sleep ? "SLEEP" : "WAKE"),
1684 (bus->sleeping ? "SLEEP" : "WAKE")));
1685
1686 if (bus->dhd->hang_was_sent)
1687 return BCME_ERROR;
1688
1689 /* Done if we're already in the requested state */
1690 if (sleep == bus->sleeping)
1691 return BCME_OK;
1692
1693 /* Going to sleep: set the alarm and turn off the lights... */
1694 if (sleep) {
1695 /* Don't sleep if something is pending */
1696#ifdef DHD_USE_IDLECOUNT
1697 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq) || bus->readframes ||
1698 bus->ctrl_frame_stat)
1699#else
1700 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1701#endif /* DHD_USE_IDLECOUNT */
1702 return BCME_BUSY;
1703
1704#ifdef BT_OVER_SDIO
1705 /*
1706 * The following is the assumption based on which the hook is placed.
1707 * From WLAN driver, either from the active contexts OR from the Watchdog contexts
1708 * we will be attempting to Go to Sleep. AT that moment if we see that BT is still
1709 * actively using the bus, we will return BCME_BUSY from here, but the bus->sleeping
1710 * state would not have changed. So the caller can then schedule the Watchdog again
1711 * which will come and attempt to sleep at a later point.
1712 *
1713 * In case if BT is the only one and is the last user, we don't switch off the clock
1714 * immediately, we allow the WLAN to decide when to sleep i.e from the watchdog.
1715 * Now if the watchdog becomes active and attempts to switch off the clock and if
1716 * another WLAN context is active they are any way serialized with sdlock.
1717 */
1718 if (bus->bt_use_count != 0) {
1719 DHD_INFO(("%s(): Cannot sleep BT is active \r\n", __FUNCTION__));
1720 return BCME_BUSY;
1721 }
1722#endif /* !BT_OVER_SDIO */
1723
1724
1725 if (!SLPAUTO_ENAB(bus)) {
1726 /* Disable SDIO interrupts (no longer interested) */
1727 bcmsdh_intr_disable(bus->sdh);
1728
1729 /* Make sure the controller has the bus up */
1730 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1731
1732 /* Tell device to start using OOB wakeup */
1733 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1734 if (retries > retry_limit)
1735 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1736
1737 /* Turn off our contribution to the HT clock request */
1738 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
1739
1740 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1741 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1742
1743 /* Isolate the bus */
1744 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
1745 SBSDIO_DEVCTL_PADS_ISO, NULL);
1746 } else {
1747 /* Leave interrupts enabled since device can exit sleep and
1748 * interrupt host
1749 */
1750 err = dhdsdio_clk_devsleep_iovar(bus, TRUE /* sleep */);
1751 }
1752
1753 /* Change state */
1754 bus->sleeping = TRUE;
1755#if defined(SUPPORT_P2P_GO_PS)
1756 wake_up(&bus->bus_sleep);
1757#endif /* LINUX && SUPPORT_P2P_GO_PS */
1758 } else {
1759 /* Waking up: bus power up is ok, set local state */
1760
1761 if (!SLPAUTO_ENAB(bus)) {
1762 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, &err);
1763
1764 /* Force pad isolation off if possible (in case power never toggled) */
1765 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0, NULL);
1766
1767
1768 /* Make sure the controller has the bus up */
1769 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1770
1771 /* Send misc interrupt to indicate OOB not needed */
1772 W_SDREG(0, &regs->tosbmailboxdata, retries);
1773 if (retries <= retry_limit)
1774 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1775
1776 if (retries > retry_limit)
1777 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1778
1779 /* Make sure we have SD bus access */
1780 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
1781
1782 /* Enable interrupts again */
1783 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1784 bus->intdis = FALSE;
1785 bcmsdh_intr_enable(bus->sdh);
1786 }
1787 } else {
1788 err = dhdsdio_clk_devsleep_iovar(bus, FALSE /* wake */);
1789#ifdef BT_OVER_SDIO
1790 if (err < 0) {
1791 struct net_device *net = NULL;
1792 dhd_pub_t *dhd = bus->dhd;
1793 net = dhd_idx2net(dhd, 0);
1794 if (net != NULL) {
1795 DHD_ERROR(("<<<<<< WIFI HANG by KSO Enabled failure\n"));
1796 dhd_os_sdunlock(dhd);
1797 net_os_send_hang_message(net);
1798 dhd_os_sdlock(dhd);
1799 } else {
1800 DHD_ERROR(("<<<<< WIFI HANG Fail because net is NULL\n"));
1801 }
1802 }
1803#endif /* BT_OVER_SDIO */
1804 }
1805
1806 if (err == 0) {
1807 /* Change state */
1808 bus->sleeping = FALSE;
1809 }
1810 }
1811
1812 return err;
1813}
1814
1815#ifdef BT_OVER_SDIO
1816/*
1817 * Call this function to Get the Clock running.
1818 * Assumes that the caller holds the sdlock.
1819 * bus - Pointer to the dhd_bus handle
1820 * can_wait - TRUE if the caller can wait until the clock becomes ready
1821 * FALSE if the caller cannot wait
1822 */
1823int __dhdsdio_clk_enable(struct dhd_bus *bus, bus_owner_t owner, int can_wait)
1824{
1825 int ret = BCME_ERROR;
1826
1827 BCM_REFERENCE(owner);
1828
1829 bus->bt_use_count++;
1830
1831 /*
1832 * We can call BUS_WAKE, clkctl multiple times, both of the items
1833 * have states and if its already ON, no new configuration is done
1834 */
1835
1836 /* Wake up the Dongle FW from SR */
1837 BUS_WAKE(bus);
1838
1839 /*
1840 * Make sure back plane ht clk is on
1841 * CLK_AVAIL - Turn On both SD & HT clock
1842 */
1843 ret = dhdsdio_clkctl(bus, CLK_AVAIL, can_wait);
1844
1845 DHD_INFO(("%s():bt_use_count %d \r\n", __FUNCTION__,
1846 bus->bt_use_count));
1847 return ret;
1848}
1849
1850/*
1851 * Call this function to relinquish the Clock.
1852 * Assumes that the caller holds the sdlock.
1853 * bus - Pointer to the dhd_bus handle
1854 * can_wait - TRUE if the caller can wait until the clock becomes ready
1855 * FALSE if the caller cannot wait
1856 */
1857int __dhdsdio_clk_disable(struct dhd_bus *bus, bus_owner_t owner, int can_wait)
1858{
1859 int ret = BCME_ERROR;
1860
1861 BCM_REFERENCE(owner);
1862 BCM_REFERENCE(can_wait);
1863
1864 if (bus->bt_use_count == 0) {
1865 DHD_ERROR(("%s(): Clocks are already turned off \r\n",
1866 __FUNCTION__));
1867 return ret;
1868 }
1869
1870 bus->bt_use_count--;
1871
1872 /*
1873 * When the SDIO Bus is shared between BT & WLAN, we turn Off the clock
1874 * once the last user has relinqushed the same. But there are two schemes
1875 * in that too. We consider WLAN as the bus master (even if its not
1876 * active). Even when the WLAN is OFF the DHD Watchdog is active.
1877 * So this Bus Watchdog is the context whill put the Bus to sleep.
1878 * Refer dhd_bus_watchdog function
1879 */
1880
1881 ret = BCME_OK;
1882 DHD_INFO(("%s():bt_use_count %d \r\n", __FUNCTION__,
1883 bus->bt_use_count));
1884 return ret;
1885}
1886
1887void dhdsdio_reset_bt_use_count(struct dhd_bus *bus)
1888{
1889 /* reset bt use count */
1890 bus->bt_use_count = 0;
1891}
1892#endif /* BT_OVER_SDIO */
1893
1894int dhdsdio_func_blocksize(dhd_pub_t *dhd, int function_num, int block_size)
1895{
1896 int func_blk_size = function_num;
1897 int bcmerr = 0;
1898 int result;
1899
1900 bcmerr = dhd_bus_iovar_op(dhd, "sd_blocksize", &func_blk_size,
1901 sizeof(int), &result, sizeof(int), IOV_GET);
1902
1903 if (bcmerr != BCME_OK) {
1904 DHD_ERROR(("%s: Get F%d Block size error\n", __FUNCTION__, function_num));
1905 return BCME_ERROR;
1906 }
1907
1908 if (result != block_size) {
1909 DHD_ERROR(("%s: F%d Block size set from %d to %d\n",
1910 __FUNCTION__, function_num, result, block_size));
1911 func_blk_size = function_num << 16 | block_size;
1912 bcmerr = dhd_bus_iovar_op(dhd, "sd_blocksize", NULL,
1913 0, &func_blk_size, sizeof(int32), IOV_SET);
1914 if (bcmerr != BCME_OK) {
1915 DHD_ERROR(("%s: Set F2 Block size error\n", __FUNCTION__));
1916 return BCME_ERROR;
1917 }
1918 }
1919
1920 return BCME_OK;
1921}
1922
1923#if defined(OOB_INTR_ONLY) || defined(FORCE_WOWLAN)
1924void
1925dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
1926{
1927#if defined(HW_OOB) || defined(FORCE_WOWLAN)
1928 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1929#else
1930 sdpcmd_regs_t *regs = bus->regs;
1931 uint retries = 0;
1932
1933 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1934 if (enable == TRUE) {
1935
1936 /* Tell device to start using OOB wakeup */
1937 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1938 if (retries > retry_limit)
1939 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1940
1941 } else {
1942 /* Send misc interrupt to indicate OOB not needed */
1943 W_SDREG(0, &regs->tosbmailboxdata, retries);
1944 if (retries <= retry_limit)
1945 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1946 }
1947
1948 /* Turn off our contribution to the HT clock request */
1949 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
1950#endif /* !defined(HW_OOB) */
1951}
1952#endif
1953
1954int
1955dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1956{
1957 int ret = BCME_ERROR;
1958 osl_t *osh;
1959 uint datalen, prec;
1960
1961 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1962
1963 osh = bus->dhd->osh;
1964 datalen = PKTLEN(osh, pkt);
1965
1966#ifdef SDTEST
1967 /* Push the test header if doing loopback */
1968 if (bus->ext_loop) {
1969 uint8* data;
1970 PKTPUSH(osh, pkt, SDPCM_TEST_HDRLEN);
1971 data = PKTDATA(osh, pkt);
1972 *data++ = SDPCM_TEST_ECHOREQ;
1973 *data++ = (uint8)bus->loopid++;
1974 *data++ = (datalen >> 0);
1975 *data++ = (datalen >> 8);
1976 datalen += SDPCM_TEST_HDRLEN;
1977 }
1978#else /* SDTEST */
1979 BCM_REFERENCE(datalen);
1980#endif /* SDTEST */
1981
1982 prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
1983
dfb0f3ae
RC		 1984 /* move from dhdsdio_sendfromq(), try to orphan skb early */
1985 if (bus->dhd->conf->orphan_move)
1986 PKTORPHAN(pkt, bus->dhd->conf->tsq);
1987
010c3a89
RC		 1988 /* Check for existing queue, current flow-control, pending event, or pending clock */
1989 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq) || bus->dpc_sched ||
1990 (!DATAOK(bus)) || (bus->flowcontrol & NBITVAL(prec)) ||
1991 (bus->clkstate != CLK_AVAIL)) {
1992 bool deq_ret;
dfb0f3ae 1993 int pkq_len = 0;
010c3a89
RC		 1994
1995 DHD_TRACE(("%s: deferring pktq len %d\n", __FUNCTION__, pktq_len(&bus->txq)));
1996 bus->fcqueued++;
1997
1998 /* Priority based enq */
1999 dhd_os_sdlock_txq(bus->dhd);
2000 deq_ret = dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec);
2001 dhd_os_sdunlock_txq(bus->dhd);
2002
2003 if (!deq_ret) {
2004#ifdef PROP_TXSTATUS
2005 if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt)) == 0)
2006#endif /* PROP_TXSTATUS */
2007 {
2008#ifdef DHDTCPACK_SUPPRESS
2009 if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) {
2010 DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using\n",
2011 __FUNCTION__, __LINE__));
2012 dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF);
2013 }
2014#endif /* DHDTCPACK_SUPPRESS */
2015 dhd_txcomplete(bus->dhd, pkt, FALSE);
2016 PKTFREE(osh, pkt, TRUE);
2017 }
2018 ret = BCME_NORESOURCE;
2019 } else
2020 ret = BCME_OK;
2021
dfb0f3ae
RC		 2022 if (dhd_doflow) {
2023 dhd_os_sdlock_txq(bus->dhd);
2024 pkq_len = pktq_len(&bus->txq);
2025 dhd_os_sdunlock_txq(bus->dhd);
2026 }
2027 if (dhd_doflow && pkq_len >= FCHI) {
010c3a89
RC		 2028 bool wlfc_enabled = FALSE;
2029#ifdef PROP_TXSTATUS
2030 wlfc_enabled = (dhd_wlfc_flowcontrol(bus->dhd, ON, FALSE) !=
2031 WLFC_UNSUPPORTED);
2032#endif
2033 if (!wlfc_enabled && dhd_doflow) {
2034 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
2035 }
2036 }
2037
2038#ifdef DHD_DEBUG
2039 dhd_os_sdlock_txq(bus->dhd);
2040 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2041 qcount[prec] = pktq_plen(&bus->txq, prec);
2042 dhd_os_sdunlock_txq(bus->dhd);
2043#endif
2044
2045 /* Schedule DPC if needed to send queued packet(s) */
2046 if (dhd_deferred_tx && !bus->dpc_sched) {
2047 if (bus->dhd->conf->deferred_tx_len) {
2048 if(dhd_os_wd_timer_enabled(bus->dhd) == FALSE) {
2049 bus->dpc_sched = TRUE;
2050 dhd_sched_dpc(bus->dhd);
2051 }
2052 if(pktq_len(&bus->txq) >= bus->dhd->conf->deferred_tx_len &&
2053 dhd_os_wd_timer_enabled(bus->dhd) == FALSE) {
2054 bus->dpc_sched = TRUE;
2055 dhd_sched_dpc(bus->dhd);
2056 }
2057 } else {
2058 bus->dpc_sched = TRUE;
2059 dhd_sched_dpc(bus->dhd);
2060 }
2061 }
2062 } else {
2063 int chan = SDPCM_DATA_CHANNEL;
2064
2065#ifdef SDTEST
2066 chan = (bus->ext_loop ? SDPCM_TEST_CHANNEL : SDPCM_DATA_CHANNEL);
2067#endif
2068 /* Lock: we're about to use shared data/code (and SDIO) */
2069 dhd_os_sdlock(bus->dhd);
2070
2071 /* Otherwise, send it now */
2072 BUS_WAKE(bus);
2073 /* Make sure back plane ht clk is on, no pending allowed */
2074 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
2075
2076 ret = dhdsdio_txpkt(bus, chan, &pkt, 1, TRUE);
2077
2078 if (ret != BCME_OK)
2079 bus->dhd->tx_errors++;
2080 else
2081 bus->dhd->dstats.tx_bytes += datalen;
2082
2083 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
2084 NO_OTHER_ACTIVE_BUS_USER(bus)) {
2085 bus->activity = FALSE;
2086 dhdsdio_bussleep(bus, TRUE);
2087 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
2088 }
2089
2090 dhd_os_sdunlock(bus->dhd);
2091 }
2092
2093 return ret;
2094}
2095
2096/* align packet data pointer and packet length to n-byte boundary, process packet headers,
2097 * a new packet may be allocated if there is not enough head and/or tail from for padding.
2098 * the caller is responsible for updating the glom size in the head packet (when glom is
2099 * used)
2100 *
2101 * pad_pkt_len: returns the length of extra padding needed from the padding packet, this parameter
2102 * is taken in tx glom mode only
2103 *
2104 * new_pkt: out, pointer of the new packet allocated due to insufficient head room for alignment
2105 * padding, NULL if not needed, the caller is responsible for freeing the new packet
2106 *
2107 * return: positive value - length of the packet, including head and tail padding
2108 * negative value - errors
2109 */
2110static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq,
2111 int prev_chain_total_len, bool last_chained_pkt,
2112 int *pad_pkt_len, void **new_pkt
2113#if defined(BCMSDIOH_TXGLOM_EXT)
2114 , int first_frame
2115#endif
2116)
2117{
2118 osl_t *osh;
2119 uint8 *frame;
2120 int pkt_len;
2121 int modulo;
2122 int head_padding;
2123 int tail_padding = 0;
2124 uint32 swheader;
2125 uint32 swhdr_offset;
2126 bool alloc_new_pkt = FALSE;
2127 uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
2128#ifdef PKT_STATICS
2129 uint16 len;
2130#endif
2131
2132 *new_pkt = NULL;
2133 osh = bus->dhd->osh;
2134
2135#ifdef DHDTCPACK_SUPPRESS
2136 if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) {
2137 DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n",
2138 __FUNCTION__, __LINE__));
2139 dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF);
2140 }
2141#endif /* DHDTCPACK_SUPPRESS */
2142
2143 /* Add space for the SDPCM hardware/software headers */
2144 PKTPUSH(osh, pkt, sdpcm_hdrlen);
2145 ASSERT(ISALIGNED((uintptr)PKTDATA(osh, pkt), 2));
2146
2147 frame = (uint8*)PKTDATA(osh, pkt);
2148 pkt_len = (uint16)PKTLEN(osh, pkt);
2149
2150#ifdef WLMEDIA_HTSF
2151 frame = (uint8*)PKTDATA(osh, pkt);
2152 if (PKTLEN(osh, pkt) >= 100) {
2153 htsf_ts = (htsfts_t*) (frame + HTSF_HOSTOFFSET + 12);
2154 if (htsf_ts->magic == HTSFMAGIC) {
2155 htsf_ts->c20 = get_cycles();
2156 htsf_ts->t20 = dhd_get_htsf(bus->dhd->info, 0);
2157 }
2158 }
2159#endif /* WLMEDIA_HTSF */
2160#ifdef PKT_STATICS
2161 len = (uint16)PKTLEN(osh, pkt);
2162 switch(chan) {
2163 case SDPCM_CONTROL_CHANNEL:
2164 tx_statics.ctrl_count++;
2165 tx_statics.ctrl_size += len;
2166 break;
2167 case SDPCM_DATA_CHANNEL:
2168 tx_statics.data_count++;
2169 tx_statics.data_size += len;
2170 break;
2171 case SDPCM_GLOM_CHANNEL:
2172 tx_statics.glom_count++;
2173 tx_statics.glom_size += len;
2174 break;
2175 case SDPCM_EVENT_CHANNEL:
2176 tx_statics.event_count++;
2177 tx_statics.event_size += len;
2178 break;
2179 case SDPCM_TEST_CHANNEL:
2180 tx_statics.test_count++;
2181 tx_statics.test_size += len;
2182 break;
2183
2184 default:
2185 break;
2186 }
2187#endif /* PKT_STATICS */
2188#ifdef DHD_DEBUG
2189 if (PKTPRIO(pkt) < ARRAYSIZE(tx_packets))
2190 tx_packets[PKTPRIO(pkt)]++;
2191#endif /* DHD_DEBUG */
2192
2193 /* align the data pointer, allocate a new packet if there is not enough space (new
2194 * packet data pointer will be aligned thus no padding will be needed)
2195 */
2196 head_padding = (uintptr)frame % DHD_SDALIGN;
2197 if (PKTHEADROOM(osh, pkt) < head_padding) {
2198 head_padding = 0;
2199 alloc_new_pkt = TRUE;
2200 } else {
2201 uint cur_chain_total_len;
2202 int chain_tail_padding = 0;
2203
2204 /* All packets need to be aligned by DHD_SDALIGN */
2205 modulo = (pkt_len + head_padding) % DHD_SDALIGN;
2206 tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0;
2207
2208 /* Total pkt chain length needs to be aligned by block size,
2209 * unless it is a single pkt chain with total length less than one block size,
2210 * which we prefer sending by byte mode.
2211 *
2212 * Do the chain alignment here if
2213 * 1. This is the last pkt of the chain of multiple pkts or a single pkt.
2214 * 2-1. This chain is of multiple pkts, or
2215 * 2-2. This is a single pkt whose size is longer than one block size.
2216 */
2217 cur_chain_total_len = prev_chain_total_len +
2218 (head_padding + pkt_len + tail_padding);
2219 if (last_chained_pkt && bus->blocksize != 0 &&
2220 (cur_chain_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) {
2221 modulo = cur_chain_total_len % bus->blocksize;
2222 chain_tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0;
2223 }
2224
2225#ifdef DHDENABLE_TAILPAD
2226 if (PKTTAILROOM(osh, pkt) < tail_padding) {
2227 /* We don't have tail room to align by DHD_SDALIGN */
2228 alloc_new_pkt = TRUE;
2229 bus->tx_tailpad_pktget++;
2230 } else if (PKTTAILROOM(osh, pkt) < tail_padding + chain_tail_padding) {
2231 /* We have tail room for tail_padding of this pkt itself, but not for
2232 * total pkt chain alignment by block size.
2233 * Use the padding packet to avoid memory copy if applicable,
2234 * otherwise, just allocate a new pkt.
2235 */
2236 if (bus->pad_pkt) {
2237 *pad_pkt_len = chain_tail_padding;
2238 bus->tx_tailpad_chain++;
2239 } else {
2240 alloc_new_pkt = TRUE;
2241 bus->tx_tailpad_pktget++;
2242 }
2243 } else
2244 /* This last pkt's tailroom is sufficient to hold both tail_padding
2245 * of the pkt itself and chain_tail_padding of total pkt chain
2246 */
2247#endif /* DHDENABLE_TAILPAD */
2248 tail_padding += chain_tail_padding;
2249 }
2250
2251 DHD_INFO(("%s sdhdr len + orig_pkt_len %d h_pad %d t_pad %d pad_pkt_len %d\n",
2252 __FUNCTION__, pkt_len, head_padding, tail_padding, *pad_pkt_len));
2253
2254 if (alloc_new_pkt) {
2255 void *tmp_pkt;
2256 int newpkt_size;
2257 int cur_total_len;
2258
2259 ASSERT(*pad_pkt_len == 0);
2260
2261 DHD_INFO(("%s allocating new packet for padding\n", __FUNCTION__));
2262
2263 /* head pointer is aligned now, no padding needed */
2264 head_padding = 0;
2265
2266 /* update the tail padding as it depends on the head padding, since a new packet is
2267 * allocated, the head padding is non longer needed and packet length is chagned
2268 */
2269
2270 cur_total_len = prev_chain_total_len + pkt_len;
2271 if (last_chained_pkt && bus->blocksize != 0 &&
2272 (cur_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) {
2273 modulo = cur_total_len % bus->blocksize;
2274 tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0;
2275 } else {
2276 modulo = pkt_len % DHD_SDALIGN;
2277 tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0;
2278 }
2279
2280 newpkt_size = PKTLEN(osh, pkt) + bus->blocksize + DHD_SDALIGN;
2281 bus->dhd->tx_realloc++;
2282 tmp_pkt = PKTGET(osh, newpkt_size, TRUE);
2283 if (tmp_pkt == NULL) {
2284 DHD_ERROR(("failed to alloc new %d byte packet\n", newpkt_size));
2285 return BCME_NOMEM;
2286 }
2287 PKTALIGN(osh, tmp_pkt, PKTLEN(osh, pkt), DHD_SDALIGN);
2288 bcopy(PKTDATA(osh, pkt), PKTDATA(osh, tmp_pkt), PKTLEN(osh, pkt));
2289 *new_pkt = tmp_pkt;
2290 pkt = tmp_pkt;
2291 }
2292
2293 if (head_padding)
2294 PKTPUSH(osh, pkt, head_padding);
2295
2296 frame = (uint8*)PKTDATA(osh, pkt);
2297 bzero(frame, head_padding + sdpcm_hdrlen);
2298 pkt_len = (uint16)PKTLEN(osh, pkt);
2299
2300 /* the header has the followming format
2301 * 4-byte HW frame tag: length, ~length (for glom this is the total length)
2302 *
2303 * 8-byte HW extesion flags (glom mode only) as the following:
2304 * 2-byte packet length, excluding HW tag and padding
2305 * 2-byte frame channel and frame flags (e.g. next frame following)
2306 * 2-byte header length
2307 * 2-byte tail padding size
2308 *
2309 * 8-byte SW frame tags as the following
2310 * 4-byte flags: host tx seq, channel, data offset
2311 * 4-byte flags: TBD
2312 */
2313
2314 swhdr_offset = SDPCM_FRAMETAG_LEN;
2315
2316 /* hardware frame tag:
2317 *
2318 * in tx-glom mode, dongle only checks the hardware frame tag in the first
2319 * packet and sees it as the total lenght of the glom (including tail padding),
2320 * for each packet in the glom, the packet length needs to be updated, (see
2321 * below PKTSETLEN)
2322 *
2323 * in non tx-glom mode, PKTLEN still need to include tail padding as to be
2324 * referred to in sdioh_request_buffer(). The tail length will be excluded in
2325 * dhdsdio_txpkt_postprocess().
2326 */
2327#if defined(BCMSDIOH_TXGLOM_EXT)
2328 if (bus->dhd->conf->txglom_bucket_size)
2329 tail_padding = 0;
2330#endif
2331 *(uint16*)frame = (uint16)htol16(pkt_len);
2332 *(((uint16*)frame) + 1) = (uint16)htol16(~pkt_len);
2333 pkt_len += tail_padding;
2334
2335 /* hardware extesion flags */
2336 if (bus->txglom_enable) {
2337 uint32 hwheader1;
2338 uint32 hwheader2;
2339#ifdef BCMSDIOH_TXGLOM_EXT
2340 uint32 act_len = pkt_len - tail_padding;
2341 uint32 real_pad = 0;
2342 if(bus->dhd->conf->txglom_ext && !last_chained_pkt) {
2343 tail_padding = 0;
2344 if(first_frame == 0) {
2345 // first pkt, add pad to bucket size - recv offset
2346 pkt_len = bus->dhd->conf->txglom_bucket_size - TXGLOM_RECV_OFFSET;
2347 } else {
2348 // add pad to bucket size
2349 pkt_len = bus->dhd->conf->txglom_bucket_size;
2350 }
2351 swhdr_offset += SDPCM_HWEXT_LEN;
2352 hwheader1 = (act_len - SDPCM_FRAMETAG_LEN) | (last_chained_pkt << 24);
2353 hwheader2 = (pkt_len - act_len) << 16;
2354 htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
2355 htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
2356 real_pad = pkt_len - act_len;
2357
2358 if (PKTTAILROOM(osh, pkt) < real_pad) {
2359 DHD_INFO(("%s : insufficient tailroom %d for %d real_pad\n",
2360 __func__, (int)PKTTAILROOM(osh, pkt), real_pad));
2361 if (PKTPADTAILROOM(osh, pkt, real_pad)) {
2362 DHD_ERROR(("CHK1: padding error size %d\n", real_pad));
2363 } else
2364 frame = (uint8 *)PKTDATA(osh, pkt);
2365 }
2366 } else
2367#endif
2368 {
2369 swhdr_offset += SDPCM_HWEXT_LEN;
2370 hwheader1 = (pkt_len - SDPCM_FRAMETAG_LEN - tail_padding) |
2371 (last_chained_pkt << 24);
2372 hwheader2 = (tail_padding) << 16;
2373 htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
2374 htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
2375 }
2376 }
2377 PKTSETLEN((osh), (pkt), (pkt_len));
2378
2379 /* software frame tags */
2380 swheader = ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
2381 | (txseq % SDPCM_SEQUENCE_WRAP) |
2382 (((head_padding + sdpcm_hdrlen) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2383 htol32_ua_store(swheader, frame + swhdr_offset);
2384 htol32_ua_store(0, frame + swhdr_offset + sizeof(swheader));
2385
2386 return pkt_len;
2387}
2388
2389static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt)
2390{
2391 osl_t *osh;
2392 uint8 *frame;
2393 int data_offset;
2394 int tail_padding;
2395 int swhdr_offset = SDPCM_FRAMETAG_LEN + (bus->txglom_enable ? SDPCM_HWEXT_LEN : 0);
2396
2397 (void)osh;
2398 osh = bus->dhd->osh;
2399
2400 /* restore pkt buffer pointer, but keeps the header pushed by dhd_prot_hdrpush */
2401 frame = (uint8*)PKTDATA(osh, pkt);
2402
2403 DHD_INFO(("%s PKTLEN before postprocess %d",
2404 __FUNCTION__, PKTLEN(osh, pkt)));
2405
2406 /* PKTLEN still includes tail_padding, so exclude it.
2407 * We shall have head_padding + original pkt_len for PKTLEN afterwards.
2408 */
2409 if (bus->txglom_enable) {
2410 /* txglom pkts have tail_padding length in HW ext header */
2411 tail_padding = ltoh32_ua(frame + SDPCM_FRAMETAG_LEN + 4) >> 16;
2412 PKTSETLEN(osh, pkt, PKTLEN(osh, pkt) - tail_padding);
2413 DHD_INFO((" txglom pkt: tail_padding %d PKTLEN %d\n",
2414 tail_padding, PKTLEN(osh, pkt)));
2415 } else {
2416 /* non-txglom pkts have head_padding + original pkt length in HW frame tag.
2417 * We cannot refer to this field for txglom pkts as the first pkt of the chain will
2418 * have the field for the total length of the chain.
2419 */
2420 PKTSETLEN(osh, pkt, *(uint16*)frame);
2421 DHD_INFO((" non-txglom pkt: HW frame tag len %d after PKTLEN %d\n",
2422 *(uint16*)frame, PKTLEN(osh, pkt)));
2423 }
2424
2425 data_offset = ltoh32_ua(frame + swhdr_offset);
2426 data_offset = (data_offset & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT;
2427 /* Get rid of sdpcm header + head_padding */
2428 PKTPULL(osh, pkt, data_offset);
2429
2430 DHD_INFO(("%s data_offset %d, PKTLEN %d\n",
2431 __FUNCTION__, data_offset, PKTLEN(osh, pkt)));
2432
2433 return BCME_OK;
2434}
2435
2436static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt)
2437{
2438 int i;
2439 int ret = 0;
2440 osl_t *osh;
2441 bcmsdh_info_t *sdh;
2442 void *pkt = NULL;
2443 void *pkt_chain;
2444 int total_len = 0;
2445 void *head_pkt = NULL;
2446 void *prev_pkt = NULL;
2447 int pad_pkt_len = 0;
2448 int new_pkt_num = 0;
2449 void *new_pkts[MAX_TX_PKTCHAIN_CNT];
2450 bool wlfc_enabled = FALSE;
2451
2452 if (bus->dhd->dongle_reset)
2453 return BCME_NOTREADY;
2454
2455 if (num_pkt <= 0)
2456 return BCME_BADARG;
2457
2458 sdh = bus->sdh;
2459 osh = bus->dhd->osh;
2460 /* init new_pkts[0] to make some compiler happy, not necessary as we check new_pkt_num */
2461 new_pkts[0] = NULL;
2462
2463 for (i = 0; i < num_pkt; i++) {
2464 int pkt_len;
2465 bool last_pkt;
2466 void *new_pkt = NULL;
2467
2468 pkt = pkts[i];
2469 ASSERT(pkt);
2470 last_pkt = (i == num_pkt - 1);
2471 pkt_len = dhdsdio_txpkt_preprocess(bus, pkt, chan, bus->tx_seq + i,
2472 total_len, last_pkt, &pad_pkt_len, &new_pkt
2473#if defined(BCMSDIOH_TXGLOM_EXT)
2474 , i
2475#endif
2476 );
2477 if (pkt_len <= 0)
2478 goto done;
2479 if (new_pkt) {
2480 pkt = new_pkt;
2481 new_pkts[new_pkt_num++] = new_pkt;
2482 }
2483 total_len += pkt_len;
2484
2485 PKTSETNEXT(osh, pkt, NULL);
2486 /* insert the packet into the list */
2487 head_pkt ? PKTSETNEXT(osh, prev_pkt, pkt) : (head_pkt = pkt);
2488 prev_pkt = pkt;
2489
2490 }
2491
2492 /* Update the HW frame tag (total length) in the first pkt of the glom */
2493 if (bus->txglom_enable) {
2494 uint8 *frame;
2495
2496 total_len += pad_pkt_len;
2497 frame = (uint8*)PKTDATA(osh, head_pkt);
2498 *(uint16*)frame = (uint16)htol16(total_len);
2499 *(((uint16*)frame) + 1) = (uint16)htol16(~total_len);
2500
2501 }
2502
2503#ifdef DHDENABLE_TAILPAD
2504 /* if a padding packet if needed, insert it to the end of the link list */
2505 if (pad_pkt_len) {
2506 PKTSETLEN(osh, bus->pad_pkt, pad_pkt_len);
2507 PKTSETNEXT(osh, pkt, bus->pad_pkt);
2508 }
2509#endif /* DHDENABLE_TAILPAD */
2510
2511 /* dhd_bcmsdh_send_buf ignores the buffer pointer if he packet
2512 * parameter is not NULL, for non packet chian we pass NULL pkt pointer
2513 * so it will take the aligned length and buffer pointer.
2514 */
2515 pkt_chain = PKTNEXT(osh, head_pkt) ? head_pkt : NULL;
2516 ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
2517 PKTDATA(osh, head_pkt), total_len, pkt_chain, NULL, NULL, TXRETRIES);
2518 if (ret == BCME_OK)
2519 bus->tx_seq = (bus->tx_seq + num_pkt) % SDPCM_SEQUENCE_WRAP;
2520
2521 /* if a padding packet was needed, remove it from the link list as it not a data pkt */
2522 if (pad_pkt_len && pkt)
2523 PKTSETNEXT(osh, pkt, NULL);
2524
2525done:
2526 pkt = head_pkt;
2527 while (pkt) {
2528 void *pkt_next = PKTNEXT(osh, pkt);
2529 PKTSETNEXT(osh, pkt, NULL);
2530 dhdsdio_txpkt_postprocess(bus, pkt);
2531 pkt = pkt_next;
2532 }
2533
2534 /* new packets might be allocated due to insufficient room for padding, but we
2535 * still have to indicate the original packets to upper layer
2536 */
2537 for (i = 0; i < num_pkt; i++) {
2538 pkt = pkts[i];
2539 wlfc_enabled = FALSE;
2540#ifdef PROP_TXSTATUS
2541 if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt))) {
2542 wlfc_enabled = (dhd_wlfc_txcomplete(bus->dhd, pkt, ret == 0) !=
2543 WLFC_UNSUPPORTED);
2544 }
2545#endif /* PROP_TXSTATUS */
2546 if (!wlfc_enabled) {
2547 PKTSETNEXT(osh, pkt, NULL);
2548 dhd_txcomplete(bus->dhd, pkt, ret != 0);
2549 if (free_pkt)
2550 PKTFREE(osh, pkt, TRUE);
2551 }
2552 }
2553
2554 for (i = 0; i < new_pkt_num; i++)
2555 PKTFREE(osh, new_pkts[i], TRUE);
2556
2557 return ret;
2558}
2559
2560static uint
2561dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
2562{
2563 uint cnt = 0;
2564 uint8 tx_prec_map;
2565 uint16 txpktqlen = 0;
2566 uint32 intstatus = 0;
2567 uint retries = 0;
2568 osl_t *osh;
2569 uint datalen = 0;
2570 dhd_pub_t *dhd = bus->dhd;
2571 sdpcmd_regs_t *regs = bus->regs;
2572#ifdef DHD_LOSSLESS_ROAMING
2573 uint8 *pktdata;
2574 struct ether_header *eh;
2575#endif /* DHD_LOSSLESS_ROAMING */
2576
2577 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2578
2579 if (!KSO_ENAB(bus)) {
2580 DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
2581 return BCME_NODEVICE;
2582 }
2583
2584 osh = dhd->osh;
2585 tx_prec_map = ~bus->flowcontrol;
2586#ifdef DHD_LOSSLESS_ROAMING
2587 tx_prec_map &= dhd->dequeue_prec_map;
2588#endif /* DHD_LOSSLESS_ROAMING */
2589 for (cnt = 0; (cnt < maxframes) && DATAOK(bus);) {
2590 int i;
2591 int num_pkt = 1;
2592 void *pkts[MAX_TX_PKTCHAIN_CNT];
2593 int prec_out;
2594
2595 dhd_os_sdlock_txq(bus->dhd);
2596 if (bus->txglom_enable) {
2597 uint32 glomlimit = (uint32)bus->txglomsize;
2598#if defined(BCMSDIOH_STD)
2599 if (bus->blocksize == 64) {
2600 glomlimit = MIN((uint32)bus->txglomsize, BLK_64_MAXTXGLOM);
2601 }
2602#endif /* BCMSDIOH_STD */
2603 num_pkt = MIN((uint32)DATABUFCNT(bus), glomlimit);
2604 num_pkt = MIN(num_pkt, ARRAYSIZE(pkts));
2605 }
2606 num_pkt = MIN(num_pkt, pktq_mlen(&bus->txq, tx_prec_map));
2607 for (i = 0; i < num_pkt; i++) {
2608 pkts[i] = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2609 if (!pkts[i]) {
2610 DHD_ERROR(("%s: pktq_mlen non-zero when no pkt\n",
2611 __FUNCTION__));
2612 ASSERT(0);
2613 break;
2614 }
2615#ifdef DHD_LOSSLESS_ROAMING
2616 pktdata = (uint8 *)PKTDATA(osh, pkts[i]);
2617#ifdef BDC
2618 /* Skip BDC header */
2619 pktdata += BDC_HEADER_LEN + ((struct bdc_header *)pktdata)->dataOffset;
2620#endif
2621 eh = (struct ether_header *)pktdata;
2622 if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
2623 uint8 prio = (uint8)PKTPRIO(pkts[i]);
2624
2625 /* Restore to original priority for 802.1X packet */
2626 if (prio == PRIO_8021D_NC) {
2627 PKTSETPRIO(pkts[i], dhd->prio_8021x);
2628 }
2629 }
2630#endif /* DHD_LOSSLESS_ROAMING */
dfb0f3ae
RC		 2631 if (!bus->dhd->conf->orphan_move)
2632 PKTORPHAN(pkts[i], bus->dhd->conf->tsq);
010c3a89
RC		 2633 datalen += PKTLEN(osh, pkts[i]);
2634 }
2635 dhd_os_sdunlock_txq(bus->dhd);
2636
2637 if (i == 0)
2638 break;
2639 if (dhdsdio_txpkt(bus, SDPCM_DATA_CHANNEL, pkts, i, TRUE) != BCME_OK)
2640 dhd->tx_errors++;
2641 else {
2642 dhd->dstats.tx_bytes += datalen;
2643 bus->txglomframes++;
2644 bus->txglompkts += num_pkt;
2645 }
2646 cnt += i;
2647#ifdef PKT_STATICS
2648 if (num_pkt) {
2649 tx_statics.glom_cnt[num_pkt-1]++;
2650 if (num_pkt > tx_statics.glom_max)
2651 tx_statics.glom_max = num_pkt;
2652 }
2653#endif
2654
2655 /* In poll mode, need to check for other events */
2656 if (!bus->intr && cnt)
2657 {
2658 /* Check device status, signal pending interrupt */
2659 R_SDREG(intstatus, &regs->intstatus, retries);
2660 bus->f2txdata++;
2661 if (bcmsdh_regfail(bus->sdh))
2662 break;
2663 if (intstatus & bus->hostintmask)
2664 bus->ipend = TRUE;
2665 }
2666
2667 }
2668
dfb0f3ae
RC		 2669 if (dhd_doflow) {
2670 dhd_os_sdlock_txq(bus->dhd);
2671 txpktqlen = pktq_len(&bus->txq);
2672 dhd_os_sdunlock_txq(bus->dhd);
2673 }
010c3a89
RC		 2674
2675 /* Do flow-control if needed */
2676 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) && (txpktqlen < FCLOW)) {
2677 bool wlfc_enabled = FALSE;
2678#ifdef PROP_TXSTATUS
2679 wlfc_enabled = (dhd_wlfc_flowcontrol(dhd, OFF, TRUE) != WLFC_UNSUPPORTED);
2680#endif
2681 if (!wlfc_enabled && dhd_doflow && dhd->txoff) {
2682 dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
2683 }
2684 }
2685
2686 return cnt;
2687}
2688
2689static void
2690dhdsdio_sendpendctl(dhd_bus_t *bus)
2691{
2692 bcmsdh_info_t *sdh = bus->sdh;
2693 int ret;
2694 uint8* frame_seq = bus->ctrl_frame_buf + SDPCM_FRAMETAG_LEN;
2695
2696 if (bus->txglom_enable)
2697 frame_seq += SDPCM_HWEXT_LEN;
2698
2699 if (*frame_seq != bus->tx_seq) {
2700 DHD_INFO(("%s IOCTL frame seq lag detected!"
2701 " frm_seq:%d != bus->tx_seq:%d, corrected\n",
2702 __FUNCTION__, *frame_seq, bus->tx_seq));
2703 *frame_seq = bus->tx_seq;
2704 }
2705
2706 ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
2707 (uint8 *)bus->ctrl_frame_buf, (uint32)bus->ctrl_frame_len,
2708 NULL, NULL, NULL, 1);
2709 if (ret == BCME_OK)
2710 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2711
2712 bus->ctrl_frame_stat = FALSE;
2713 dhd_wait_event_wakeup(bus->dhd);
2714}
2715
2716int
2717dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen)
2718{
2719 static int err_nodevice = 0;
2720 uint8 *frame;
2721 uint16 len;
2722 uint32 swheader;
2723 uint8 doff = 0;
2724 int ret = -1;
2725 uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
2726
2727 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2728
2729 if (bus->dhd->dongle_reset)
2730 return -EIO;
2731
2732 /* Back the pointer to make a room for bus header */
2733 frame = msg - sdpcm_hdrlen;
2734 len = (msglen += sdpcm_hdrlen);
2735
2736 /* Add alignment padding (optional for ctl frames) */
2737 if (dhd_alignctl) {
2738 if ((doff = ((uintptr)frame % DHD_SDALIGN))) {
2739 frame -= doff;
2740 len += doff;
2741 msglen += doff;
2742 bzero(frame, doff + sdpcm_hdrlen);
2743 }
2744 ASSERT(doff < DHD_SDALIGN);
2745 }
2746 doff += sdpcm_hdrlen;
2747
2748 /* Round send length to next SDIO block */
2749 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2750 uint16 pad = bus->blocksize - (len % bus->blocksize);
2751 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2752 len += pad;
2753 } else if (len % DHD_SDALIGN) {
2754 len += DHD_SDALIGN - (len % DHD_SDALIGN);
2755 }
2756
2757 /* Satisfy length-alignment requirements */
2758 if (forcealign && (len & (ALIGNMENT - 1)))
2759 len = ROUNDUP(len, ALIGNMENT);
2760
2761 ASSERT(ISALIGNED((uintptr)frame, 2));
2762
2763
2764 /* Need to lock here to protect txseq and SDIO tx calls */
dfb0f3ae
RC		 2765 if (bus->dhd->conf->txctl_tmo_fix > 0 && !TXCTLOK(bus)) {
2766 bus->ctrl_wait = TRUE;
2767 wait_event_interruptible_timeout(bus->ctrl_tx_wait, TXCTLOK(bus),
2768 msecs_to_jiffies(bus->dhd->conf->txctl_tmo_fix));
2769 bus->ctrl_wait = FALSE;
ccd15baf 2770 }
dfb0f3ae 2771 dhd_os_sdlock(bus->dhd);
010c3a89
RC		 2772
2773 BUS_WAKE(bus);
2774
2775 /* Make sure backplane clock is on */
2776 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2777
2778 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2779 *(uint16*)frame = htol16((uint16)msglen);
2780 *(((uint16*)frame) + 1) = htol16(~msglen);
2781
2782 if (bus->txglom_enable) {
2783 uint32 hwheader1, hwheader2;
2784 /* Software tag: channel, sequence number, data offset */
2785 swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
2786 | bus->tx_seq
2787 | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2788 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN + SDPCM_HWEXT_LEN);
2789 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN
2790 + SDPCM_HWEXT_LEN + sizeof(swheader));
2791
2792 hwheader1 = (msglen - SDPCM_FRAMETAG_LEN) | (1 << 24);
2793 hwheader2 = (len - (msglen)) << 16;
2794 htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN);
2795 htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4);
2796
2797 *(uint16*)frame = htol16(len);
2798 *(((uint16*)frame) + 1) = htol16(~(len));
2799 } else {
2800 /* Software tag: channel, sequence number, data offset */
2801 swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
2802 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2803 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
2804 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2805 }
2806
2807#ifdef DHD_ULP
2808 dhd_ulp_set_path(bus->dhd, DHD_ULP_TX_CTRL);
2809
2810 if (!TXCTLOK(bus) || !dhd_ulp_f2_ready(bus->dhd, bus->sdh))
2811#else
2812 if (!TXCTLOK(bus))
2813#endif
2814 {
2815 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2816 __FUNCTION__, bus->tx_max, bus->tx_seq));
2817 bus->ctrl_frame_stat = TRUE;
2818 /* Send from dpc */
2819 bus->ctrl_frame_buf = frame;
2820 bus->ctrl_frame_len = len;
2821
2822 if (!bus->dpc_sched) {
2823 bus->dpc_sched = TRUE;
2824 dhd_sched_dpc(bus->dhd);
2825 }
2826 if (bus->ctrl_frame_stat) {
2827 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
2828 }
2829
2830 if (bus->ctrl_frame_stat == FALSE) {
2831 DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __FUNCTION__));
2832 ret = 0;
2833 } else {
2834 bus->dhd->txcnt_timeout++;
2835 if (!bus->dhd->hang_was_sent) {
2836#ifdef CUSTOMER_HW4_DEBUG
2837 uint32 status, retry = 0;
2838 R_SDREG(status, &bus->regs->intstatus, retry);
2839 DHD_TRACE_HW4(("%s: txcnt_timeout, INT status=0x%08X\n",
2840 __FUNCTION__, status));
2841 DHD_TRACE_HW4(("%s : tx_max : %d, tx_seq : %d, clkstate : %d \n",
2842 __FUNCTION__, bus->tx_max, bus->tx_seq, bus->clkstate));
2843#endif /* CUSTOMER_HW4_DEBUG */
2844 DHD_ERROR(("%s: ctrl_frame_stat == TRUE txcnt_timeout=%d\n",
2845 __FUNCTION__, bus->dhd->txcnt_timeout));
2846 }
2847#ifdef DHD_FW_COREDUMP
2848 /* Collect socram dump */
2849 if (bus->dhd->memdump_enabled) {
2850 /* collect core dump */
2851 bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT_TX;
2852 dhd_os_sdunlock(bus->dhd);
2853 dhd_bus_mem_dump(bus->dhd);
2854 dhd_os_sdlock(bus->dhd);
2855 }
2856#endif /* DHD_FW_COREDUMP */
2857 ret = -1;
2858 bus->ctrl_frame_stat = FALSE;
2859 goto done;
2860 }
2861 }
2862
2863 bus->dhd->txcnt_timeout = 0;
2864 bus->ctrl_frame_stat = TRUE;
2865
2866 if (ret == -1) {
2867#ifdef DHD_DEBUG
2868 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
2869 prhex("Tx Frame", frame, len);
2870 } else if (DHD_HDRS_ON()) {
2871 prhex("TxHdr", frame, MIN(len, 16));
2872 }
2873#endif
2874#ifdef PKT_STATICS
2875 tx_statics.ctrl_count++;
2876 tx_statics.ctrl_size += len;
2877#endif
2878 ret = dhd_bcmsdh_send_buffer(bus, frame, len);
2879 }
2880 bus->ctrl_frame_stat = FALSE;
2881#ifdef DHD_ULP
2882 dhd_ulp_enable_cached_sbwad(bus->dhd, bus->sdh);
2883#endif /* DHD_ULP */
2884
2885done:
2886 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
2887 NO_OTHER_ACTIVE_BUS_USER(bus)) {
2888 bus->activity = FALSE;
2889 dhdsdio_bussleep(bus, TRUE);
2890 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
2891 }
2892
2893 dhd_os_sdunlock(bus->dhd);
2894
2895 if (ret)
2896 bus->dhd->tx_ctlerrs++;
2897 else
2898 bus->dhd->tx_ctlpkts++;
2899
2900 if (bus->dhd->txcnt_timeout >= MAX_CNTL_TX_TIMEOUT) {
2901 return -ETIMEDOUT;
2902 }
2903
2904 if (ret == BCME_NODEVICE)
2905 err_nodevice++;
2906 else
2907 err_nodevice = 0;
2908
2909 return ret ? err_nodevice >= ERROR_BCME_NODEVICE_MAX ? -ETIMEDOUT : -EIO : 0;
2910}
2911
2912int
2913dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen)
2914{
2915 int timeleft;
2916 uint rxlen = 0;
91a2c117 2917 static uint cnt = 0;
010c3a89
RC		 2918
2919 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2920
2921 if (bus->dhd->dongle_reset)
2922 return -EIO;
2923
2924 /* Wait until control frame is available */
91a2c117 2925 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, false);
010c3a89
RC		 2926
2927 dhd_os_sdlock(bus->dhd);
2928 rxlen = bus->rxlen;
2929 bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
2930 bus->rxlen = 0;
2931 dhd_os_sdunlock(bus->dhd);
2932
91a2c117
RC		 2933 if (bus->dhd->conf->ctrl_resched > 0 && !rxlen && timeleft == 0) {
2934 cnt++;
2935 if (cnt <= bus->dhd->conf->ctrl_resched) {
2936 uint32 status, retry = 0;
2937 R_SDREG(status, &bus->regs->intstatus, retry);
2938 if ((status & I_HMB_HOST_INT) || PKT_AVAILABLE(bus, status)) {
2939 DHD_ERROR(("%s: reschedule dhd_dpc, cnt=%d, status=0x%x\n",
2940 __FUNCTION__, cnt, status));
2941 bus->ipend = TRUE;
2942 bus->dpc_sched = TRUE;
2943 dhd_sched_dpc(bus->dhd);
2944
2945 /* Wait until control frame is available */
2946 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, true);
2947
2948 dhd_os_sdlock(bus->dhd);
2949 rxlen = bus->rxlen;
2950 bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
2951 bus->rxlen = 0;
2952 dhd_os_sdunlock(bus->dhd);
2953 }
2954 }
2955 } else {
2956 cnt = 0;
2957 }
2958
010c3a89
RC		 2959 if (rxlen) {
2960 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
2961 __FUNCTION__, rxlen, msglen));
2962 } else {
2963 if (timeleft == 0) {
2964#ifdef DHD_DEBUG
2965 uint32 status, retry = 0;
2966 R_SDREG(status, &bus->regs->intstatus, retry);
2967 DHD_ERROR(("%s: resumed on timeout, INT status=0x%08X\n",
2968 __FUNCTION__, status));
2969#else
2970 DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__));
2971#endif /* DHD_DEBUG */
2972 if (!bus->dhd->dongle_trap_occured) {
2973#ifdef DHD_FW_COREDUMP
2974 bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT;
2975#endif /* DHD_FW_COREDUMP */
2976 dhd_os_sdlock(bus->dhd);
2977 dhdsdio_checkdied(bus, NULL, 0);
2978 dhd_os_sdunlock(bus->dhd);
2979 }
2980 } else {
2981 DHD_CTL(("%s: resumed for unknown reason?\n", __FUNCTION__));
2982 if (!bus->dhd->dongle_trap_occured) {
2983#ifdef DHD_FW_COREDUMP
2984 bus->dhd->memdump_type = DUMP_TYPE_RESUMED_UNKNOWN;
2985#endif /* DHD_FW_COREDUMP */
2986 dhd_os_sdlock(bus->dhd);
2987 dhdsdio_checkdied(bus, NULL, 0);
2988 dhd_os_sdunlock(bus->dhd);
2989 }
2990 }
2991#ifdef DHD_FW_COREDUMP
2992 /* Dump the ram image */
2993 if (bus->dhd->memdump_enabled && !bus->dhd->dongle_trap_occured)
2994 dhdsdio_mem_dump(bus);
2995#endif /* DHD_FW_COREDUMP */
2996 }
2997 if (timeleft == 0) {
2998 if (rxlen == 0)
2999 bus->dhd->rxcnt_timeout++;
3000 DHD_ERROR(("%s: rxcnt_timeout=%d, rxlen=%d\n", __FUNCTION__,
3001 bus->dhd->rxcnt_timeout, rxlen));
3002#ifdef DHD_FW_COREDUMP
3003 /* collect socram dump */
3004 if (bus->dhd->memdump_enabled) {
3005 bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT_RX;
3006 dhd_bus_mem_dump(bus->dhd);
3007 }
3008#endif /* DHD_FW_COREDUMP */
3009 } else {
3010 bus->dhd->rxcnt_timeout = 0;
3011 }
3012
3013 if (rxlen)
3014 bus->dhd->rx_ctlpkts++;
3015 else
3016 bus->dhd->rx_ctlerrs++;
3017
3018 if (bus->dhd->rxcnt_timeout >= MAX_CNTL_RX_TIMEOUT) {
3019 return -ETIMEDOUT;
3020 }
3021
3022
3023 if (bus->dhd->dongle_trap_occured)
3024 return -EREMOTEIO;
3025
3026 return rxlen ? (int)rxlen : -EIO;
3027}
3028
3029/* IOVar table */
3030enum {
3031 IOV_INTR = 1,
3032 IOV_POLLRATE,
3033 IOV_SDREG,
3034 IOV_SBREG,
3035 IOV_SDCIS,
3036 IOV_RAMSIZE,
3037 IOV_RAMSTART,
3038#ifdef DHD_DEBUG
3039 IOV_CHECKDIED,
3040 IOV_SERIALCONS,
3041#endif /* DHD_DEBUG */
3042 IOV_SET_DOWNLOAD_STATE,
3043 IOV_SOCRAM_STATE,
3044 IOV_FORCEEVEN,
3045 IOV_SDIOD_DRIVE,
3046 IOV_READAHEAD,
3047 IOV_SDRXCHAIN,
3048 IOV_ALIGNCTL,
3049 IOV_SDALIGN,
3050 IOV_DEVRESET,
3051 IOV_CPU,
3052#if defined(USE_SDIOFIFO_IOVAR)
3053 IOV_WATERMARK,
3054 IOV_MESBUSYCTRL,
3055#endif /* USE_SDIOFIFO_IOVAR */
3056#ifdef SDTEST
3057 IOV_PKTGEN,
3058 IOV_EXTLOOP,
3059#endif /* SDTEST */
3060 IOV_SPROM,
3061 IOV_TXBOUND,
3062 IOV_RXBOUND,
3063 IOV_TXMINMAX,
3064 IOV_IDLETIME,
3065 IOV_IDLECLOCK,
3066 IOV_SD1IDLE,
3067 IOV_SLEEP,
3068 IOV_DONGLEISOLATION,
3069 IOV_KSO,
3070 IOV_DEVSLEEP,
3071 IOV_DEVCAP,
3072 IOV_VARS,
3073#ifdef SOFTAP
3074 IOV_FWPATH,
3075#endif
3076 IOV_TXGLOMSIZE,
3077 IOV_TXGLOMMODE,
3078 IOV_HANGREPORT,
3079 IOV_TXINRX_THRES,
3080 IOV_SDIO_SUSPEND
3081};
3082
3083const bcm_iovar_t dhdsdio_iovars[] = {
3084 {"intr", IOV_INTR, 0, 0, IOVT_BOOL, 0 },
3085 {"sleep", IOV_SLEEP, 0, 0, IOVT_BOOL, 0 },
3086 {"pollrate", IOV_POLLRATE, 0, 0, IOVT_UINT32, 0 },
3087 {"idletime", IOV_IDLETIME, 0, 0, IOVT_INT32, 0 },
3088 {"idleclock", IOV_IDLECLOCK, 0, 0, IOVT_INT32, 0 },
3089 {"sd1idle", IOV_SD1IDLE, 0, 0, IOVT_BOOL, 0 },
3090 {"ramsize", IOV_RAMSIZE, 0, 0, IOVT_UINT32, 0 },
3091 {"ramstart", IOV_RAMSTART, 0, 0, IOVT_UINT32, 0 },
3092 {"dwnldstate", IOV_SET_DOWNLOAD_STATE, 0, 0, IOVT_BOOL, 0 },
3093 {"socram_state", IOV_SOCRAM_STATE, 0, 0, IOVT_BOOL, 0 },
3094 {"vars", IOV_VARS, 0, 0, IOVT_BUFFER, 0 },
3095 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, 0, IOVT_UINT32, 0 },
3096 {"readahead", IOV_READAHEAD, 0, 0, IOVT_BOOL, 0 },
3097 {"sdrxchain", IOV_SDRXCHAIN, 0, 0, IOVT_BOOL, 0 },
3098 {"alignctl", IOV_ALIGNCTL, 0, 0, IOVT_BOOL, 0 },
3099 {"sdalign", IOV_SDALIGN, 0, 0, IOVT_BOOL, 0 },
3100 {"devreset", IOV_DEVRESET, 0, 0, IOVT_BOOL, 0 },
3101#ifdef DHD_DEBUG
3102 {"sdreg", IOV_SDREG, 0, 0, IOVT_BUFFER, sizeof(sdreg_t) },
3103 {"sbreg", IOV_SBREG, 0, 0, IOVT_BUFFER, sizeof(sdreg_t) },
3104 {"sd_cis", IOV_SDCIS, 0, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN },
3105 {"forcealign", IOV_FORCEEVEN, 0, 0, IOVT_BOOL, 0 },
3106 {"txbound", IOV_TXBOUND, 0, 0, IOVT_UINT32, 0 },
3107 {"rxbound", IOV_RXBOUND, 0, 0, IOVT_UINT32, 0 },
3108 {"txminmax", IOV_TXMINMAX, 0, 0, IOVT_UINT32, 0 },
3109 {"cpu", IOV_CPU, 0, 0, IOVT_BOOL, 0 },
3110#ifdef DHD_DEBUG
3111 {"checkdied", IOV_CHECKDIED, 0, 0, IOVT_BUFFER, 0 },
3112 {"serial", IOV_SERIALCONS, 0, 0, IOVT_UINT32, 0 },
3113#endif /* DHD_DEBUG */
3114#endif /* DHD_DEBUG */
3115#ifdef SDTEST
3116 {"extloop", IOV_EXTLOOP, 0, 0, IOVT_BOOL, 0 },
3117 {"pktgen", IOV_PKTGEN, 0, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t) },
3118#endif /* SDTEST */
3119#if defined(USE_SDIOFIFO_IOVAR)
3120 {"watermark", IOV_WATERMARK, 0, 0, IOVT_UINT32, 0 },
3121 {"mesbusyctrl", IOV_MESBUSYCTRL, 0, 0, IOVT_UINT32, 0 },
3122#endif /* USE_SDIOFIFO_IOVAR */
3123 {"devcap", IOV_DEVCAP, 0, 0, IOVT_UINT32, 0 },
3124 {"dngl_isolation", IOV_DONGLEISOLATION, 0, 0, IOVT_UINT32, 0 },
3125 {"kso", IOV_KSO, 0, 0, IOVT_UINT32, 0 },
3126 {"devsleep", IOV_DEVSLEEP, 0, 0, IOVT_UINT32, 0 },
3127#ifdef SOFTAP
3128 {"fwpath", IOV_FWPATH, 0, 0, IOVT_BUFFER, 0 },
3129#endif
3130 {"txglomsize", IOV_TXGLOMSIZE, 0, 0, IOVT_UINT32, 0 },
3131 {"fw_hang_report", IOV_HANGREPORT, 0, 0, IOVT_BOOL, 0 },
3132 {"txinrx_thres", IOV_TXINRX_THRES, 0, 0, IOVT_INT32, 0 },
3133 {"sdio_suspend", IOV_SDIO_SUSPEND, 0, 0, IOVT_UINT32, 0 },
3134 {NULL, 0, 0, 0, 0, 0 }
3135};
3136
3137static void
3138dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
3139{
3140 uint q1, q2;
3141
3142 if (!div) {
3143 bcm_bprintf(strbuf, "%s N/A", desc);
3144 } else {
3145 q1 = num / div;
3146 q2 = (100 * (num - (q1 * div))) / div;
3147 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
3148 }
3149}
3150
3151void
3152dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
3153{
3154 dhd_bus_t *bus = dhdp->bus;
3155#if defined(DHD_WAKE_STATUS) && defined(DHD_WAKE_EVENT_STATUS)
3156 int i;
3157#endif
3158
3159 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
3160 bcm_bprintf(strbuf, "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
3161 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
3162 bcm_bprintf(strbuf, "fcstate %d qlen %u tx_seq %d, max %d, rxskip %d rxlen %u rx_seq %d\n",
3163 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max, bus->rxskip,
3164 bus->rxlen, bus->rx_seq);
3165 bcm_bprintf(strbuf, "intr %d intrcount %u lastintrs %u spurious %u\n",
3166 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
3167
3168#ifdef DHD_WAKE_STATUS
3169 bcm_bprintf(strbuf, "wake %u rxwake %u readctrlwake %u\n",
3170 bcmsdh_get_total_wake(bus->sdh), bus->wake_counts.rxwake,
3171 bus->wake_counts.rcwake);
3172#ifdef DHD_WAKE_RX_STATUS
3173 bcm_bprintf(strbuf, " unicast %u multicast %u broadcast %u arp %u\n",
3174 bus->wake_counts.rx_ucast, bus->wake_counts.rx_mcast,
3175 bus->wake_counts.rx_bcast, bus->wake_counts.rx_arp);
3176 bcm_bprintf(strbuf, " multi4 %u multi6 %u icmp6 %u multiother %u\n",
3177 bus->wake_counts.rx_multi_ipv4, bus->wake_counts.rx_multi_ipv6,
3178 bus->wake_counts.rx_icmpv6, bus->wake_counts.rx_multi_other);
3179 bcm_bprintf(strbuf, " icmp6_ra %u, icmp6_na %u, icmp6_ns %u\n",
3180 bus->wake_counts.rx_icmpv6_ra, bus->wake_counts.rx_icmpv6_na,
3181 bus->wake_counts.rx_icmpv6_ns);
3182#endif /* DHD_WAKE_RX_STATUS */
3183#ifdef DHD_WAKE_EVENT_STATUS
3184 for (i = 0; i < WLC_E_LAST; i++)
3185 if (bus->wake_counts.rc_event[i] != 0)
3186 bcm_bprintf(strbuf, " %s = %u\n", bcmevent_get_name(i),
3187 bus->wake_counts.rc_event[i]);
3188 bcm_bprintf(strbuf, "\n");
3189#endif /* DHD_WAKE_EVENT_STATUS */
3190#endif /* DHD_WAKE_STATUS */
3191
3192 bcm_bprintf(strbuf, "pollrate %u pollcnt %u regfails %u\n",
3193 bus->pollrate, bus->pollcnt, bus->regfails);
3194
3195 bcm_bprintf(strbuf, "\nAdditional counters:\n");
3196#ifdef DHDENABLE_TAILPAD
3197 bcm_bprintf(strbuf, "tx_tailpad_chain %u tx_tailpad_pktget %u\n",
3198 bus->tx_tailpad_chain, bus->tx_tailpad_pktget);
3199#endif /* DHDENABLE_TAILPAD */
3200 bcm_bprintf(strbuf, "tx_sderrs %u fcqueued %u rxrtx %u rx_toolong %u rxc_errors %u\n",
3201 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
3202 bus->rxc_errors);
3203 bcm_bprintf(strbuf, "rx_hdrfail %u badhdr %u badseq %u\n",
3204 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
3205 bcm_bprintf(strbuf, "fc_rcvd %u, fc_xoff %u, fc_xon %u\n",
3206 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
3207 bcm_bprintf(strbuf, "rxglomfail %u, rxglomframes %u, rxglompkts %u\n",
3208 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
3209 bcm_bprintf(strbuf, "f2rx (hdrs/data) %u (%u/%u), f2tx %u f1regs %u\n",
3210 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs, bus->f2rxdata,
3211 bus->f2txdata, bus->f1regdata);
3212 {
3213 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
3214 (bus->f2rxhdrs + bus->f2rxdata));
3215 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets, bus->f1regdata);
3216 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
3217 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
3218 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets, bus->intrcount);
3219 bcm_bprintf(strbuf, "\n");
3220
3221 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
3222 bus->dhd->rx_packets);
3223 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts, bus->rxglomframes);
3224 bcm_bprintf(strbuf, "\n");
3225
3226 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets, bus->f2txdata);
3227 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets, bus->f1regdata);
3228 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
3229 (bus->f2txdata + bus->f1regdata));
3230 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets, bus->intrcount);
3231 bcm_bprintf(strbuf, "\n");
3232
3233 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
3234 (bus->dhd->tx_packets + bus->dhd->rx_packets),
3235 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
3236 dhd_dump_pct(strbuf, ", pkts/f1sd",
3237 (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->f1regdata);
3238 dhd_dump_pct(strbuf, ", pkts/sd",
3239 (bus->dhd->tx_packets + bus->dhd->rx_packets),
3240 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
3241 dhd_dump_pct(strbuf, ", pkts/int",
3242 (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->intrcount);
3243 bcm_bprintf(strbuf, "\n\n");
3244 }
3245
3246#ifdef SDTEST
3247 if (bus->pktgen_count) {
3248 bcm_bprintf(strbuf, "pktgen config and count:\n");
3249 bcm_bprintf(strbuf, "freq %u count %u print %u total %u min %u len %u\n",
3250 bus->pktgen_freq, bus->pktgen_count, bus->pktgen_print,
3251 bus->pktgen_total, bus->pktgen_minlen, bus->pktgen_maxlen);
3252 bcm_bprintf(strbuf, "send attempts %u rcvd %u fail %u\n",
3253 bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
3254 }
3255#endif /* SDTEST */
3256#ifdef DHD_DEBUG
3257 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
3258 bus->dpc_sched, (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
3259 bcm_bprintf(strbuf, "blocksize %u roundup %u\n", bus->blocksize, bus->roundup);
3260#endif /* DHD_DEBUG */
3261 bcm_bprintf(strbuf, "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
3262 bus->clkstate, bus->activity, bus->idletime, bus->idlecount, bus->sleeping);
3263 dhd_dump_pct(strbuf, "Tx: glom pct", (100 * bus->txglompkts), bus->dhd->tx_packets);
3264 dhd_dump_pct(strbuf, ", pkts/glom", bus->txglompkts, bus->txglomframes);
3265 bcm_bprintf(strbuf, "\n");
3266 bcm_bprintf(strbuf, "txglomframes %u, txglompkts %u\n", bus->txglomframes, bus->txglompkts);
3267 bcm_bprintf(strbuf, "\n");
3268}
3269
3270void
3271dhd_bus_clearcounts(dhd_pub_t *dhdp)
3272{
3273 dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
3274
3275 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
3276 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
3277 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
3278#ifdef DHDENABLE_TAILPAD
3279 bus->tx_tailpad_chain = bus->tx_tailpad_pktget = 0;
3280#endif /* DHDENABLE_TAILPAD */
3281 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
3282 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
3283 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
3284 bus->txglomframes = bus->txglompkts = 0;
3285}
3286
3287#ifdef SDTEST
3288static int
3289dhdsdio_pktgen_get(dhd_bus_t *bus, uint8 *arg)
3290{
3291 dhd_pktgen_t pktgen;
3292
3293 pktgen.version = DHD_PKTGEN_VERSION;
3294 pktgen.freq = bus->pktgen_freq;
3295 pktgen.count = bus->pktgen_count;
3296 pktgen.print = bus->pktgen_print;
3297 pktgen.total = bus->pktgen_total;
3298 pktgen.minlen = bus->pktgen_minlen;
3299 pktgen.maxlen = bus->pktgen_maxlen;
3300 pktgen.numsent = bus->pktgen_sent;
3301 pktgen.numrcvd = bus->pktgen_rcvd;
3302 pktgen.numfail = bus->pktgen_fail;
3303 pktgen.mode = bus->pktgen_mode;
3304 pktgen.stop = bus->pktgen_stop;
3305
3306 bcopy(&pktgen, arg, sizeof(pktgen));
3307
3308 return 0;
3309}
3310
3311static int
3312dhdsdio_pktgen_set(dhd_bus_t *bus, uint8 *arg)
3313{
3314 dhd_pktgen_t pktgen;
3315 uint oldcnt, oldmode;
3316
3317 bcopy(arg, &pktgen, sizeof(pktgen));
3318 if (pktgen.version != DHD_PKTGEN_VERSION)
3319 return BCME_BADARG;
3320
3321 oldcnt = bus->pktgen_count;
3322 oldmode = bus->pktgen_mode;
3323
3324 bus->pktgen_freq = pktgen.freq;
3325 bus->pktgen_count = pktgen.count;
3326 bus->pktgen_print = pktgen.print;
3327 bus->pktgen_total = pktgen.total;
3328 bus->pktgen_minlen = pktgen.minlen;
3329 bus->pktgen_maxlen = pktgen.maxlen;
3330 bus->pktgen_mode = pktgen.mode;
3331 bus->pktgen_stop = pktgen.stop;
3332
3333 bus->pktgen_tick = bus->pktgen_ptick = 0;
3334 bus->pktgen_prev_time = jiffies;
3335 bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen);
3336 bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen);
3337
3338 /* Clear counts for a new pktgen (mode change, or was stopped) */
3339 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode)) {
3340 bus->pktgen_sent = bus->pktgen_prev_sent = bus->pktgen_rcvd = 0;
3341 bus->pktgen_prev_rcvd = bus->pktgen_fail = 0;
3342 }
3343
3344 return 0;
3345}
3346#endif /* SDTEST */
3347
3348static void
3349dhdsdio_devram_remap(dhd_bus_t *bus, bool val)
3350{
3351 uint8 enable, protect, remap;
3352
3353 si_socdevram(bus->sih, FALSE, &enable, &protect, &remap);
3354 remap = val ? TRUE : FALSE;
3355 si_socdevram(bus->sih, TRUE, &enable, &protect, &remap);
3356}
3357
3358static int
3359dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, uint8 *data, uint size)
3360{
3361 int bcmerror = 0;
3362 uint32 sdaddr;
3363 uint dsize;
3364
3365 /* In remap mode, adjust address beyond socram and redirect
3366 * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize
3367 * is not backplane accessible
3368 */
3369 if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address)) {
3370 address -= bus->orig_ramsize;
3371 address += SOCDEVRAM_BP_ADDR;
3372 }
3373
3374 /* Determine initial transfer parameters */
3375 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
3376 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
3377 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
3378 else
3379 dsize = size;
07d6b24a
RC		 3380 if (dsize > MAX_MEM_BUF) {
3381 DHD_ERROR(("%s: dsize %d > %d\n", __FUNCTION__, dsize, MAX_MEM_BUF));
3382 goto xfer_done;
3383 }
010c3a89
RC		 3384
3385 /* Set the backplane window to include the start address */
3386 if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
3387 DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
3388 goto xfer_done;
3389 }
3390
3391 /* Do the transfer(s) */
3392 while (size) {
3393 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
3394 __FUNCTION__, (write ? "write" : "read"), dsize, sdaddr,
3395 (address & SBSDIO_SBWINDOW_MASK)));
07d6b24a
RC		 3396 if (write)
3397 memcpy(bus->membuf, data, dsize);
3398 if ((bcmerror = bcmsdh_rwdata(bus->sdh, write, sdaddr, bus->membuf, dsize))) {
010c3a89
RC		 3399 DHD_ERROR(("%s: membytes transfer failed\n", __FUNCTION__));
3400 break;
3401 }
07d6b24a
RC		 3402 if (!write)
3403 memcpy(data, bus->membuf, dsize);
010c3a89
RC		 3404
3405 /* Adjust for next transfer (if any) */
3406 if ((size -= dsize)) {
3407 data += dsize;
3408 address += dsize;
3409 if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
3410 DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
3411 break;
3412 }
3413 sdaddr = 0;
3414 dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size);
3415 }
3416
3417 }
3418
3419xfer_done:
3420 /* Return the window to backplane enumeration space for core access */
3421 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
3422 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n", __FUNCTION__,
3423 bcmsdh_cur_sbwad(bus->sdh)));
3424 }
3425
3426 return bcmerror;
3427}
3428
3429static int
3430dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
3431{
3432 uint32 addr;
3433 int rv, i;
3434 uint32 shaddr = 0;
3435
3436 if (bus->sih == NULL) {
3437 if (bus->dhd && bus->dhd->dongle_reset) {
3438 DHD_ERROR(("%s: Dongle is in reset state\n", __FUNCTION__));
3439 return BCME_NOTREADY;
3440 } else {
3441 ASSERT(bus->dhd);
3442 ASSERT(bus->sih);
3443 DHD_ERROR(("%s: The address of sih is invalid\n", __FUNCTION__));
3444 return BCME_ERROR;
3445 }
3446 }
3447 if ((CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
3448 CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) && !dhdsdio_sr_cap(bus))
3449 bus->srmemsize = 0;
3450
3451 shaddr = bus->dongle_ram_base + bus->ramsize - 4;
3452 i = 0;
3453 do {
3454 /* Read last word in memory to determine address of sdpcm_shared structure */
3455 if ((rv = dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&addr, 4)) < 0)
3456 return rv;
3457
3458 addr = ltoh32(addr);
3459
3460 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
3461
3462 /*
3463 * Check if addr is valid.
3464 * NVRAM length at the end of memory should have been overwritten.
3465 */
3466 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
3467 if ((bus->srmemsize > 0) && (i++ == 0)) {
3468 shaddr -= bus->srmemsize;
3469 } else {
3470 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
3471 __FUNCTION__, addr));
3472 return BCME_ERROR;
3473 }
3474 } else
3475 break;
3476 } while (i < 2);
3477
3478 /* Read hndrte_shared structure */
3479 if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)sh, sizeof(sdpcm_shared_t))) < 0)
3480 return rv;
3481
3482 /* Endianness */
3483 sh->flags = ltoh32(sh->flags);
3484 sh->trap_addr = ltoh32(sh->trap_addr);
3485 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
3486 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
3487 sh->assert_line = ltoh32(sh->assert_line);
3488 sh->console_addr = ltoh32(sh->console_addr);
3489 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
3490
3491 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) == 3 && SDPCM_SHARED_VERSION == 1)
3492 return BCME_OK;
3493
3494 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
3495 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
3496 "is different than sdpcm_shared version %d in dongle\n",
3497 __FUNCTION__, SDPCM_SHARED_VERSION,
3498 sh->flags & SDPCM_SHARED_VERSION_MASK));
3499 return BCME_ERROR;
3500 }
3501
3502 return BCME_OK;
3503}
3504
3505#define CONSOLE_LINE_MAX 192
3506
3507#ifdef DHD_DEBUG
3508static int
3509dhdsdio_readconsole(dhd_bus_t *bus)
3510{
3511 dhd_console_t *c = &bus->console;
3512 uint8 line[CONSOLE_LINE_MAX], ch;
3513 uint32 n, idx, addr;
3514 int rv;
3515
3516 /* Don't do anything until FWREADY updates console address */
3517 if (bus->console_addr == 0)
3518 return 0;
3519
3520 if (!KSO_ENAB(bus))
3521 return 0;
3522
3523 /* Read console log struct */
3524 addr = bus->console_addr + OFFSETOF(hnd_cons_t, log);
3525 if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
3526 return rv;
3527
3528 /* Allocate console buffer (one time only) */
3529 if (c->buf == NULL) {
3530 c->bufsize = ltoh32(c->log.buf_size);
3531 if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
3532 return BCME_NOMEM;
3533 }
3534
3535 idx = ltoh32(c->log.idx);
3536
3537 /* Protect against corrupt value */
3538 if (idx > c->bufsize)
3539 return BCME_ERROR;
3540
3541 /* Skip reading the console buffer if the index pointer has not moved */
3542 if (idx == c->last)
3543 return BCME_OK;
3544
3545 /* Read the console buffer */
3546 addr = ltoh32(c->log.buf);
3547 if ((rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
3548 return rv;
3549
3550 while (c->last != idx) {
3551 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
3552 if (c->last == idx) {
3553 /* This would output a partial line. Instead, back up
3554 * the buffer pointer and output this line next time around.
3555 */
3556 if (c->last >= n)
3557 c->last -= n;
3558 else
3559 c->last = c->bufsize - n;
3560 goto break2;
3561 }
3562 ch = c->buf[c->last];
3563 c->last = (c->last + 1) % c->bufsize;
3564 if (ch == '\n')
3565 break;
3566 line[n] = ch;
3567 }
3568
3569 if (n > 0) {
3570 if (line[n - 1] == '\r')
3571 n--;
3572 line[n] = 0;
3573 printf("CONSOLE: %s\n", line);
3574#ifdef LOG_INTO_TCPDUMP
3575 dhd_sendup_log(bus->dhd, line, n);
3576#endif /* LOG_INTO_TCPDUMP */
3577 }
3578 }
3579break2:
3580
3581 return BCME_OK;
3582}
3583#endif /* DHD_DEBUG */
3584
3585static int
3586dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size)
3587{
3588 int bcmerror = 0;
3589 uint msize = 512;
3590 char *mbuffer = NULL;
3591 char *console_buffer = NULL;
3592 uint maxstrlen = 256;
3593 char *str = NULL;
3594 sdpcm_shared_t l_sdpcm_shared;
3595 struct bcmstrbuf strbuf;
3596 uint32 console_ptr, console_size, console_index;
3597 uint8 line[CONSOLE_LINE_MAX], ch;
3598 uint32 n, i, addr;
3599 int rv;
3600
3601 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
3602
3603 if (DHD_NOCHECKDIED_ON())
3604 return 0;
3605
3606 if (data == NULL) {
3607 /*
3608 * Called after a rx ctrl timeout. "data" is NULL.
3609 * allocate memory to trace the trap or assert.
3610 */
3611 size = msize;
3612 mbuffer = data = MALLOC(bus->dhd->osh, msize);
3613 if (mbuffer == NULL) {
3614 DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
3615 bcmerror = BCME_NOMEM;
3616 goto done;
3617 }
3618 }
3619
3620 if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
3621 DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
3622 bcmerror = BCME_NOMEM;
3623 goto done;
3624 }
3625
3626 if ((bcmerror = dhdsdio_readshared(bus, &l_sdpcm_shared)) < 0)
3627 goto done;
3628
3629 bcm_binit(&strbuf, data, size);
3630
3631 bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
3632 l_sdpcm_shared.msgtrace_addr, l_sdpcm_shared.console_addr);
3633
3634 if ((l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3635 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
3636 * (Avoids conflict with real asserts for programmatic parsing of output.)
3637 */
3638 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
3639 }
3640
3641 if ((l_sdpcm_shared.flags & (SDPCM_SHARED_ASSERT|SDPCM_SHARED_TRAP)) == 0) {
3642 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
3643 * (Avoids conflict with real asserts for programmatic parsing of output.)
3644 */
3645 bcm_bprintf(&strbuf, "No trap%s in dongle",
3646 (l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
3647 ?"/assrt" :"");
3648 } else {
3649 if (l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
3650 /* Download assert */
3651 bcm_bprintf(&strbuf, "Dongle assert");
3652 if (l_sdpcm_shared.assert_exp_addr != 0) {
3653 str[0] = '\0';
3654 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
3655 l_sdpcm_shared.assert_exp_addr,
3656 (uint8 *)str, maxstrlen)) < 0)
3657 goto done;
3658
3659 str[maxstrlen - 1] = '\0';
3660 bcm_bprintf(&strbuf, " expr \"%s\"", str);
3661 }
3662
3663 if (l_sdpcm_shared.assert_file_addr != 0) {
3664 str[0] = '\0';
3665 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
3666 l_sdpcm_shared.assert_file_addr,
3667 (uint8 *)str, maxstrlen)) < 0)
3668 goto done;
3669
3670 str[maxstrlen - 1] = '\0';
3671 bcm_bprintf(&strbuf, " file \"%s\"", str);
3672 }
3673
3674 bcm_bprintf(&strbuf, " line %d ", l_sdpcm_shared.assert_line);
3675 }
3676
3677 if (l_sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
3678 trap_t *tr = &bus->dhd->last_trap_info;
3679 bus->dhd->dongle_trap_occured = TRUE;
3680 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
3681 l_sdpcm_shared.trap_addr,
3682 (uint8*)tr, sizeof(trap_t))) < 0)
3683 goto done;
3684
3685 bus->dongle_trap_addr = ltoh32(l_sdpcm_shared.trap_addr);
3686
3687 dhd_bus_dump_trap_info(bus, &strbuf);
3688
3689 addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log);
3690 if ((rv = dhdsdio_membytes(bus, FALSE, addr,
3691 (uint8 *)&console_ptr, sizeof(console_ptr))) < 0)
3692 goto printbuf;
3693
3694 addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.buf_size);
3695 if ((rv = dhdsdio_membytes(bus, FALSE, addr,
3696 (uint8 *)&console_size, sizeof(console_size))) < 0)
3697 goto printbuf;
3698
3699 addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.idx);
3700 if ((rv = dhdsdio_membytes(bus, FALSE, addr,
3701 (uint8 *)&console_index, sizeof(console_index))) < 0)
3702 goto printbuf;
3703
3704 console_ptr = ltoh32(console_ptr);
3705 console_size = ltoh32(console_size);
3706 console_index = ltoh32(console_index);
3707
3708 if (console_size > CONSOLE_BUFFER_MAX ||
3709 !(console_buffer = MALLOC(bus->dhd->osh, console_size)))
3710 goto printbuf;
3711
3712 if ((rv = dhdsdio_membytes(bus, FALSE, console_ptr,
3713 (uint8 *)console_buffer, console_size)) < 0)
3714 goto printbuf;
3715
3716 for (i = 0, n = 0; i < console_size; i += n + 1) {
3717 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
3718 ch = console_buffer[(console_index + i + n) % console_size];
3719 if (ch == '\n')
3720 break;
3721 line[n] = ch;
3722 }
3723
3724
3725 if (n > 0) {
3726 if (line[n - 1] == '\r')
3727 n--;
3728 line[n] = 0;
3729 /* Don't use DHD_ERROR macro since we print
3730 * a lot of information quickly. The macro
3731 * will truncate a lot of the printfs
3732 */
3733
3734 if (dhd_msg_level & DHD_ERROR_VAL)
3735 printf("CONSOLE: %s\n", line);
3736 }
3737 }
3738 }
3739 }
3740
3741printbuf:
3742 if (l_sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) {
3743 DHD_ERROR(("%s: %s\n", __FUNCTION__, strbuf.origbuf));
3744 }
3745
3746#if defined(DHD_FW_COREDUMP)
3747 if (bus->dhd->memdump_enabled && (l_sdpcm_shared.flags & SDPCM_SHARED_TRAP)) {
3748 /* Mem dump to a file on device */
3749 bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP;
3750 dhd_os_sdunlock(bus->dhd);
3751 dhdsdio_mem_dump(bus);
3752 dhd_os_sdlock(bus->dhd);
3753 }
3754#endif /* #if defined(DHD_FW_COREDUMP) */
3755
3756done:
3757 if (mbuffer)
3758 MFREE(bus->dhd->osh, mbuffer, msize);
3759 if (str)
3760 MFREE(bus->dhd->osh, str, maxstrlen);
3761 if (console_buffer)
3762 MFREE(bus->dhd->osh, console_buffer, console_size);
3763
3764 return bcmerror;
3765}
3766
3767#if defined(DHD_FW_COREDUMP)
3768int
3769dhd_bus_mem_dump(dhd_pub_t *dhdp)
3770{
3771 dhd_bus_t *bus = dhdp->bus;
3772 if (dhdp->busstate == DHD_BUS_SUSPEND) {
3773 DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__));
3774 return 0;
3775 }
3776 return dhdsdio_mem_dump(bus);
3777}
3778
3779static int
3780dhdsdio_mem_dump(dhd_bus_t *bus)
3781{
3782 int ret = 0;
3783 int size; /* Full mem size */
3784 uint32 start = bus->dongle_ram_base; /* Start address */
3785 uint read_size = 0; /* Read size of each iteration */
3786 uint8 *buf = NULL, *databuf = NULL;
3787
3788 /* Get full mem size */
3789 size = bus->ramsize;
3790 buf = dhd_get_fwdump_buf(bus->dhd, size);
3791 if (!buf) {
3792 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size));
3793 return -1;
3794 }
3795
3796 dhd_os_sdlock(bus->dhd);
3797 BUS_WAKE(bus);
3798 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
3799
3800 /* Read mem content */
3801 DHD_ERROR(("Dump dongle memory\n"));
3802 databuf = buf;
3803 while (size)
3804 {
3805 read_size = MIN(MEMBLOCK, size);
3806 if ((ret = dhdsdio_membytes(bus, FALSE, start, databuf, read_size)))
3807 {
3808 DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret));
3809 ret = BCME_ERROR;
3810 break;
3811 }
3812 /* Decrement size and increment start address */
3813 size -= read_size;
3814 start += read_size;
3815 databuf += read_size;
3816 }
3817
3818 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
3819 NO_OTHER_ACTIVE_BUS_USER(bus)) {
3820 bus->activity = FALSE;
3821 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
3822 }
3823
3824 dhd_os_sdunlock(bus->dhd);
3825
3826 /* schedule a work queue to perform actual memdump. dhd_mem_dump() performs the job */
3827 if (!ret) {
3828 /* buf, actually soc_ram free handled in dhd_{free,clear} */
3829 dhd_schedule_memdump(bus->dhd, buf, bus->ramsize);
3830 }
3831
3832 return ret;
3833}
3834#endif /* DHD_FW_COREDUMP */
3835
3836int
3837dhd_socram_dump(dhd_bus_t * bus)
3838{
3839#if defined(DHD_FW_COREDUMP)
3840 return (dhdsdio_mem_dump(bus));
3841#else
3842 return -1;
3843#endif
3844}
3845
3846int
3847dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
3848{
3849 int bcmerror = BCME_OK;
3850
3851 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
3852
3853 if (bus->dhd->up &&
3854#ifdef DHD_ULP
3855 (DHD_ULP_DISABLED == dhd_ulp_get_ulp_state(bus->dhd)) &&
3856#endif /* DHD_ULP */
3857 1) {
3858 bcmerror = BCME_NOTDOWN;
3859 goto err;
3860 }
3861 if (!len) {
3862 bcmerror = BCME_BUFTOOSHORT;
3863 goto err;
3864 }
3865
3866 /* Free the old ones and replace with passed variables */
3867 if (bus->vars)
3868 MFREE(bus->dhd->osh, bus->vars, bus->varsz);
3869
3870 bus->vars = MALLOC(bus->dhd->osh, len);
3871 bus->varsz = bus->vars ? len : 0;
3872 if (bus->vars == NULL) {
3873 bcmerror = BCME_NOMEM;
3874 goto err;
3875 }
3876
3877 /* Copy the passed variables, which should include the terminating double-null */
3878 bcopy(arg, bus->vars, bus->varsz);
3879err:
3880 return bcmerror;
3881}
3882
3883#ifdef DHD_DEBUG
3884
3885#define CC_PLL_CHIPCTRL_SERIAL_ENAB (1 << 24)
3886#define CC_CHIPCTRL_JTAG_SEL (1 << 3)
3887#define CC_CHIPCTRL_GPIO_SEL (0x3)
3888#define CC_PLL_CHIPCTRL_SERIAL_ENAB_4334 (1 << 28)
3889
3890static int
3891dhd_serialconsole(dhd_bus_t *bus, bool set, bool enable, int *bcmerror)
3892{
3893 int int_val;
3894 uint32 addr, data, uart_enab = 0;
3895 uint32 jtag_sel = CC_CHIPCTRL_JTAG_SEL;
3896 uint32 gpio_sel = CC_CHIPCTRL_GPIO_SEL;
3897
3898 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
3899 data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
3900 *bcmerror = 0;
3901
3902 bcmsdh_reg_write(bus->sdh, addr, 4, 1);
3903 if (bcmsdh_regfail(bus->sdh)) {
3904 *bcmerror = BCME_SDIO_ERROR;
3905 return -1;
3906 }
3907 int_val = bcmsdh_reg_read(bus->sdh, data, 4);
3908 if (bcmsdh_regfail(bus->sdh)) {
3909 *bcmerror = BCME_SDIO_ERROR;
3910 return -1;
3911 }
3912
3913 if (bus->sih->chip == BCM4330_CHIP_ID) {
3914 uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB;
3915 } else if (bus->sih->chip == BCM4334_CHIP_ID ||
3916 bus->sih->chip == BCM43340_CHIP_ID ||
3917 bus->sih->chip == BCM43341_CHIP_ID ||
3918 bus->sih->chip == BCM43342_CHIP_ID ||
3919 0) {
3920 if (enable) {
3921 /* Moved to PMU chipcontrol 1 from 4330 */
3922 int_val &= ~gpio_sel;
3923 int_val |= jtag_sel;
3924 } else {
3925 int_val |= gpio_sel;
3926 int_val &= ~jtag_sel;
3927 }
3928 uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB_4334;
3929 }
3930
3931 if (!set)
3932 return (int_val & uart_enab);
3933 if (enable)
3934 int_val |= uart_enab;
3935 else
3936 int_val &= ~uart_enab;
3937 bcmsdh_reg_write(bus->sdh, data, 4, int_val);
3938 if (bcmsdh_regfail(bus->sdh)) {
3939 *bcmerror = BCME_SDIO_ERROR;
3940 return -1;
3941 }
3942 if (bus->sih->chip == BCM4330_CHIP_ID) {
3943 uint32 chipcontrol;
3944 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol);
3945 chipcontrol = bcmsdh_reg_read(bus->sdh, addr, 4);
3946 chipcontrol &= ~jtag_sel;
3947 if (enable) {
3948 chipcontrol |= jtag_sel;
3949 chipcontrol &= ~gpio_sel;
3950 }
3951 bcmsdh_reg_write(bus->sdh, addr, 4, chipcontrol);
3952 }
3953
3954 return (int_val & uart_enab);
3955}
3956#endif
3957
3958static int
3959dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
3960 void *params, int plen, void *arg, int len, int val_size)
3961{
3962 int bcmerror = 0;
3963 int32 int_val = 0;
3964 bool bool_val = 0;
3965
3966 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
3967 __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
3968
3969 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
3970 goto exit;
3971
3972 if (plen >= (int)sizeof(int_val))
3973 bcopy(params, &int_val, sizeof(int_val));
3974
3975 bool_val = (int_val != 0) ? TRUE : FALSE;
3976
3977
3978 /* Some ioctls use the bus */
3979 dhd_os_sdlock(bus->dhd);
3980
3981 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
3982 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
3983 actionid == IOV_GVAL(IOV_DEVRESET))) {
3984 bcmerror = BCME_NOTREADY;
3985 goto exit;
3986 }
3987
3988 /*
3989 * Special handling for keepSdioOn: New SDIO Wake-up Mechanism
3990 */
3991 if ((vi->varid == IOV_KSO) && (IOV_ISSET(actionid))) {
3992 dhdsdio_clk_kso_iovar(bus, bool_val);
3993 goto exit;
3994 } else if ((vi->varid == IOV_DEVSLEEP) && (IOV_ISSET(actionid))) {
3995 {
3996 dhdsdio_clk_devsleep_iovar(bus, bool_val);
3997 if (!SLPAUTO_ENAB(bus) && (bool_val == FALSE) && (bus->ipend)) {
3998 DHD_ERROR(("INT pending in devsleep 1, dpc_sched: %d\n",
3999 bus->dpc_sched));
4000 if (!bus->dpc_sched) {
4001 bus->dpc_sched = TRUE;
4002 dhd_sched_dpc(bus->dhd);
4003 }
4004 }
4005 }
4006 goto exit;
4007 }
4008
4009 /* Handle sleep stuff before any clock mucking */
4010 if (vi->varid == IOV_SLEEP) {
4011 if (IOV_ISSET(actionid)) {
4012 bcmerror = dhdsdio_bussleep(bus, bool_val);
4013 } else {
4014 int_val = (int32)bus->sleeping;
4015 bcopy(&int_val, arg, val_size);
4016 }
4017 goto exit;
4018 }
4019
4020 /* Request clock to allow SDIO accesses */
4021 if (!bus->dhd->dongle_reset) {
4022 BUS_WAKE(bus);
4023 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4024 }
4025
4026 switch (actionid) {
4027 case IOV_GVAL(IOV_INTR):
4028 int_val = (int32)bus->intr;
4029 bcopy(&int_val, arg, val_size);
4030 break;
4031
4032 case IOV_SVAL(IOV_INTR):
4033 bus->intr = bool_val;
4034 bus->intdis = FALSE;
4035 if (bus->dhd->up) {
4036 if (bus->intr) {
4037 DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
4038 // terence 20141207: enbale intdis
4039 bus->intdis = TRUE;
4040 bcmsdh_intr_enable(bus->sdh);
4041 } else {
4042 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
4043 bcmsdh_intr_disable(bus->sdh);
4044 }
4045 }
4046 break;
4047
4048 case IOV_GVAL(IOV_POLLRATE):
4049 int_val = (int32)bus->pollrate;
4050 bcopy(&int_val, arg, val_size);
4051 break;
4052
4053 case IOV_SVAL(IOV_POLLRATE):
4054 bus->pollrate = (uint)int_val;
4055 bus->poll = (bus->pollrate != 0);
4056 break;
4057
4058 case IOV_GVAL(IOV_IDLETIME):
4059 int_val = bus->idletime;
4060 bcopy(&int_val, arg, val_size);
4061 break;
4062
4063 case IOV_SVAL(IOV_IDLETIME):
4064 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE)) {
4065 bcmerror = BCME_BADARG;
4066 } else {
4067 bus->idletime = int_val;
4068 }
4069 break;
4070
4071 case IOV_GVAL(IOV_IDLECLOCK):
4072 int_val = (int32)bus->idleclock;
4073 bcopy(&int_val, arg, val_size);
4074 break;
4075
4076 case IOV_SVAL(IOV_IDLECLOCK):
4077 bus->idleclock = int_val;
4078 break;
4079
4080 case IOV_GVAL(IOV_SD1IDLE):
4081 int_val = (int32)sd1idle;
4082 bcopy(&int_val, arg, val_size);
4083 break;
4084
4085 case IOV_SVAL(IOV_SD1IDLE):
4086 sd1idle = bool_val;
4087 break;
4088
4089
4090
4091 case IOV_GVAL(IOV_RAMSIZE):
4092 int_val = (int32)bus->ramsize;
4093 bcopy(&int_val, arg, val_size);
4094 break;
4095
4096 case IOV_GVAL(IOV_RAMSTART):
4097 int_val = (int32)bus->dongle_ram_base;
4098 bcopy(&int_val, arg, val_size);
4099 break;
4100
4101 case IOV_GVAL(IOV_SDIOD_DRIVE):
4102 int_val = (int32)dhd_sdiod_drive_strength;
4103 bcopy(&int_val, arg, val_size);
4104 break;
4105
4106 case IOV_SVAL(IOV_SDIOD_DRIVE):
4107 dhd_sdiod_drive_strength = int_val;
4108 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh, dhd_sdiod_drive_strength);
4109 break;
4110
4111 case IOV_SVAL(IOV_SET_DOWNLOAD_STATE):
4112 bcmerror = dhdsdio_download_state(bus, bool_val);
4113 break;
4114
4115 case IOV_SVAL(IOV_SOCRAM_STATE):
4116 bcmerror = dhdsdio_download_state(bus, bool_val);
4117 break;
4118
4119 case IOV_SVAL(IOV_VARS):
4120 bcmerror = dhdsdio_downloadvars(bus, arg, len);
4121 break;
4122
4123 case IOV_GVAL(IOV_READAHEAD):
4124 int_val = (int32)dhd_readahead;
4125 bcopy(&int_val, arg, val_size);
4126 break;
4127
4128 case IOV_SVAL(IOV_READAHEAD):
4129 if (bool_val && !dhd_readahead)
4130 bus->nextlen = 0;
4131 dhd_readahead = bool_val;
4132 break;
4133
4134 case IOV_GVAL(IOV_SDRXCHAIN):
4135 int_val = (int32)bus->use_rxchain;
4136 bcopy(&int_val, arg, val_size);
4137 break;
4138
4139 case IOV_SVAL(IOV_SDRXCHAIN):
4140 if (bool_val && !bus->sd_rxchain)
4141 bcmerror = BCME_UNSUPPORTED;
4142 else
4143 bus->use_rxchain = bool_val;
4144 break;
4145 case IOV_GVAL(IOV_ALIGNCTL):
4146 int_val = (int32)dhd_alignctl;
4147 bcopy(&int_val, arg, val_size);
4148 break;
4149
4150 case IOV_SVAL(IOV_ALIGNCTL):
4151 dhd_alignctl = bool_val;
4152 break;
4153
4154 case IOV_GVAL(IOV_SDALIGN):
4155 int_val = DHD_SDALIGN;
4156 bcopy(&int_val, arg, val_size);
4157 break;
4158
4159#ifdef DHD_DEBUG
4160 case IOV_GVAL(IOV_VARS):
4161 if (bus->varsz < (uint)len)
4162 bcopy(bus->vars, arg, bus->varsz);
4163 else
4164 bcmerror = BCME_BUFTOOSHORT;
4165 break;
4166#endif /* DHD_DEBUG */
4167
4168#ifdef DHD_DEBUG
4169 case IOV_GVAL(IOV_SDREG):
4170 {
4171 sdreg_t *sd_ptr;
4172 uintptr addr;
4173 uint size;
4174
4175 sd_ptr = (sdreg_t *)params;
4176
4177 addr = ((uintptr)bus->regs + sd_ptr->offset);
4178 size = sd_ptr->func;
4179 int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
4180 if (bcmsdh_regfail(bus->sdh))
4181 bcmerror = BCME_SDIO_ERROR;
4182 bcopy(&int_val, arg, sizeof(int32));
4183 break;
4184 }
4185
4186 case IOV_SVAL(IOV_SDREG):
4187 {
4188 sdreg_t *sd_ptr;
4189 uintptr addr;
4190 uint size;
4191
4192 sd_ptr = (sdreg_t *)params;
4193
4194 addr = ((uintptr)bus->regs + sd_ptr->offset);
4195 size = sd_ptr->func;
4196 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
4197 if (bcmsdh_regfail(bus->sdh))
4198 bcmerror = BCME_SDIO_ERROR;
4199 break;
4200 }
4201
4202 /* Same as above, but offset is not backplane (not SDIO core) */
4203 case IOV_GVAL(IOV_SBREG):
4204 {
4205 sdreg_t sdreg;
4206 uint32 addr, size;
4207
4208 bcopy(params, &sdreg, sizeof(sdreg));
4209
4210 addr = SI_ENUM_BASE + sdreg.offset;
4211 size = sdreg.func;
4212 int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
4213 if (bcmsdh_regfail(bus->sdh))
4214 bcmerror = BCME_SDIO_ERROR;
4215 bcopy(&int_val, arg, sizeof(int32));
4216 break;
4217 }
4218
4219 case IOV_SVAL(IOV_SBREG):
4220 {
4221 sdreg_t sdreg;
4222 uint32 addr, size;
4223
4224 bcopy(params, &sdreg, sizeof(sdreg));
4225
4226 addr = SI_ENUM_BASE + sdreg.offset;
4227 size = sdreg.func;
4228 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
4229 if (bcmsdh_regfail(bus->sdh))
4230 bcmerror = BCME_SDIO_ERROR;
4231 break;
4232 }
4233
4234 case IOV_GVAL(IOV_SDCIS):
4235 {
4236 *(char *)arg = 0;
4237
4238 bcmstrcat(arg, "\nFunc 0\n");
4239 bcmsdh_cis_read(bus->sdh, 0x10, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
4240 bcmstrcat(arg, "\nFunc 1\n");
4241 bcmsdh_cis_read(bus->sdh, 0x11, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
4242 bcmstrcat(arg, "\nFunc 2\n");
4243 bcmsdh_cis_read(bus->sdh, 0x12, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
4244 break;
4245 }
4246
4247 case IOV_GVAL(IOV_FORCEEVEN):
4248 int_val = (int32)forcealign;
4249 bcopy(&int_val, arg, val_size);
4250 break;
4251
4252 case IOV_SVAL(IOV_FORCEEVEN):
4253 forcealign = bool_val;
4254 break;
4255
4256 case IOV_GVAL(IOV_TXBOUND):
4257 int_val = (int32)dhd_txbound;
4258 bcopy(&int_val, arg, val_size);
4259 break;
4260
4261 case IOV_SVAL(IOV_TXBOUND):
4262 dhd_txbound = (uint)int_val;
4263 break;
4264
4265 case IOV_GVAL(IOV_RXBOUND):
4266 int_val = (int32)dhd_rxbound;
4267 bcopy(&int_val, arg, val_size);
4268 break;
4269
4270 case IOV_SVAL(IOV_RXBOUND):
4271 dhd_rxbound = (uint)int_val;
4272 break;
4273
4274 case IOV_GVAL(IOV_TXMINMAX):
4275 int_val = (int32)dhd_txminmax;
4276 bcopy(&int_val, arg, val_size);
4277 break;
4278
4279 case IOV_SVAL(IOV_TXMINMAX):
4280 dhd_txminmax = (uint)int_val;
4281 break;
4282
4283 case IOV_GVAL(IOV_SERIALCONS):
4284 int_val = dhd_serialconsole(bus, FALSE, 0, &bcmerror);
4285 if (bcmerror != 0)
4286 break;
4287
4288 bcopy(&int_val, arg, val_size);
4289 break;
4290
4291 case IOV_SVAL(IOV_SERIALCONS):
4292 dhd_serialconsole(bus, TRUE, bool_val, &bcmerror);
4293 break;
4294
4295
4296#endif /* DHD_DEBUG */
4297
4298
4299#ifdef SDTEST
4300 case IOV_GVAL(IOV_EXTLOOP):
4301 int_val = (int32)bus->ext_loop;
4302 bcopy(&int_val, arg, val_size);
4303 break;
4304
4305 case IOV_SVAL(IOV_EXTLOOP):
4306 bus->ext_loop = bool_val;
4307 break;
4308
4309 case IOV_GVAL(IOV_PKTGEN):
4310 bcmerror = dhdsdio_pktgen_get(bus, arg);
4311 break;
4312
4313 case IOV_SVAL(IOV_PKTGEN):
4314 bcmerror = dhdsdio_pktgen_set(bus, arg);
4315 break;
4316#endif /* SDTEST */
4317
4318#if defined(USE_SDIOFIFO_IOVAR)
4319 case IOV_GVAL(IOV_WATERMARK):
4320 int_val = (int32)watermark;
4321 bcopy(&int_val, arg, val_size);
4322 break;
4323
4324 case IOV_SVAL(IOV_WATERMARK):
4325 watermark = (uint)int_val;
4326 watermark = (watermark > SBSDIO_WATERMARK_MASK) ? SBSDIO_WATERMARK_MASK : watermark;
4327 DHD_ERROR(("Setting watermark as 0x%x.\n", watermark));
4328 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, (uint8)watermark, NULL);
4329 break;
4330
4331 case IOV_GVAL(IOV_MESBUSYCTRL):
4332 int_val = (int32)mesbusyctrl;
4333 bcopy(&int_val, arg, val_size);
4334 break;
4335
4336 case IOV_SVAL(IOV_MESBUSYCTRL):
4337 mesbusyctrl = (uint)int_val;
4338 mesbusyctrl = (mesbusyctrl > SBSDIO_MESBUSYCTRL_MASK)
4339 ? SBSDIO_MESBUSYCTRL_MASK : mesbusyctrl;
4340 DHD_ERROR(("Setting mesbusyctrl as 0x%x.\n", mesbusyctrl));
4341 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL,
4342 ((uint8)mesbusyctrl | 0x80), NULL);
4343 break;
4344#endif
4345
4346
4347 case IOV_GVAL(IOV_DONGLEISOLATION):
4348 int_val = bus->dhd->dongle_isolation;
4349 bcopy(&int_val, arg, val_size);
4350 break;
4351
4352 case IOV_SVAL(IOV_DONGLEISOLATION):
4353 bus->dhd->dongle_isolation = bool_val;
4354 break;
4355
4356 case IOV_SVAL(IOV_DEVRESET):
4357 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d busstate=%d\n",
4358 __FUNCTION__, bool_val, bus->dhd->dongle_reset,
4359 bus->dhd->busstate));
4360
4361 ASSERT(bus->dhd->osh);
4362 /* ASSERT(bus->cl_devid); */
4363
4364 dhd_bus_devreset(bus->dhd, (uint8)bool_val);
4365
4366 break;
4367 /*
4368 * softap firmware is updated through module parameter or android private command
4369 */
4370
4371 case IOV_GVAL(IOV_DEVRESET):
4372 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __FUNCTION__));
4373
4374 /* Get its status */
4375 int_val = (bool) bus->dhd->dongle_reset;
4376 bcopy(&int_val, arg, val_size);
4377
4378 break;
4379
4380 case IOV_GVAL(IOV_KSO):
4381 int_val = dhdsdio_sleepcsr_get(bus);
4382 bcopy(&int_val, arg, val_size);
4383 break;
4384
4385 case IOV_GVAL(IOV_DEVCAP):
4386 int_val = dhdsdio_devcap_get(bus);
4387 bcopy(&int_val, arg, val_size);
4388 break;
4389
4390 case IOV_SVAL(IOV_DEVCAP):
4391 dhdsdio_devcap_set(bus, (uint8) int_val);
4392 break;
4393 case IOV_GVAL(IOV_TXGLOMSIZE):
4394 int_val = (int32)bus->txglomsize;
4395 bcopy(&int_val, arg, val_size);
4396 break;
4397
4398 case IOV_SVAL(IOV_TXGLOMSIZE):
4399 if (int_val > SDPCM_MAXGLOM_SIZE) {
4400 bcmerror = BCME_ERROR;
4401 } else {
4402 bus->txglomsize = (uint)int_val;
4403 }
4404 break;
4405 case IOV_SVAL(IOV_HANGREPORT):
4406 bus->dhd->hang_report = bool_val;
4407 DHD_ERROR(("%s: Set hang_report as %d\n", __FUNCTION__, bus->dhd->hang_report));
4408 break;
4409
4410 case IOV_GVAL(IOV_HANGREPORT):
4411 int_val = (int32)bus->dhd->hang_report;
4412 bcopy(&int_val, arg, val_size);
4413 break;
4414
4415 case IOV_GVAL(IOV_TXINRX_THRES):
4416 int_val = bus->txinrx_thres;
4417 bcopy(&int_val, arg, val_size);
4418 break;
4419 case IOV_SVAL(IOV_TXINRX_THRES):
4420 if (int_val < 0) {
4421 bcmerror = BCME_BADARG;
4422 } else {
4423 bus->txinrx_thres = int_val;
4424 }
4425 break;
4426
4427 case IOV_GVAL(IOV_SDIO_SUSPEND):
4428 int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0;
4429 bcopy(&int_val, arg, val_size);
4430 break;
4431
4432 case IOV_SVAL(IOV_SDIO_SUSPEND):
4433 if (bool_val) { /* Suspend */
4434 dhdsdio_suspend(bus);
4435 }
4436 else { /* Resume */
4437 dhdsdio_resume(bus);
4438 }
4439 break;
4440
4441 default:
4442 bcmerror = BCME_UNSUPPORTED;
4443 break;
4444 }
4445
4446exit:
4447 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
4448 NO_OTHER_ACTIVE_BUS_USER(bus)) {
4449 bus->activity = FALSE;
4450 dhdsdio_bussleep(bus, TRUE);
4451 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4452 }
4453
4454 dhd_os_sdunlock(bus->dhd);
4455
4456 return bcmerror;
4457}
4458
4459static int
4460dhdsdio_write_vars(dhd_bus_t *bus)
4461{
4462 int bcmerror = 0;
4463 uint32 varsize, phys_size;
4464 uint32 varaddr;
4465 uint8 *vbuffer;
4466 uint32 varsizew;
4467#ifdef DHD_DEBUG
4468 uint8 *nvram_ularray;
4469#endif /* DHD_DEBUG */
4470
4471 /* Even if there are no vars are to be written, we still need to set the ramsize. */
4472 varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
4473 varaddr = (bus->ramsize - 4) - varsize;
4474
4475 // terence 20150412: fix for nvram failed to download
4476 if (bus->dhd->conf->chip == BCM43340_CHIP_ID ||
4477 bus->dhd->conf->chip == BCM43341_CHIP_ID) {
4478 varsize = varsize ? ROUNDUP(varsize, 64) : 0;
4479 varaddr = (bus->ramsize - 64) - varsize;
4480 }
4481
4482 varaddr += bus->dongle_ram_base;
4483
4484 if (bus->vars) {
4485 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 7)) {
4486 if (((varaddr & 0x3C) == 0x3C) && (varsize > 4)) {
4487 DHD_ERROR(("PR85623WAR in place\n"));
4488 varsize += 4;
4489 varaddr -= 4;
4490 }
4491 }
4492
4493 vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize);
4494 if (!vbuffer)
4495 return BCME_NOMEM;
4496
4497 bzero(vbuffer, varsize);
4498 bcopy(bus->vars, vbuffer, bus->varsz);
4499
4500 /* Write the vars list */
4501 bcmerror = dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize);
4502 if (bcmerror) {
4503 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
4504 __FUNCTION__, bcmerror, varsize, varaddr));
4505 return bcmerror;
4506 }
4507
4508#ifdef DHD_DEBUG
4509 /* Verify NVRAM bytes */
4510 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
4511 nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize);
4512 if (!nvram_ularray) {
4513 MFREE(bus->dhd->osh, vbuffer, varsize);
4514 return BCME_NOMEM;
4515 }
4516
4517 /* Upload image to verify downloaded contents. */
4518 memset(nvram_ularray, 0xaa, varsize);
4519
4520 /* Read the vars list to temp buffer for comparison */
4521 bcmerror = dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray, varsize);
4522 if (bcmerror) {
4523 DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n",
4524 __FUNCTION__, bcmerror, varsize, varaddr));
4525 }
4526 /* Compare the org NVRAM with the one read from RAM */
4527 if (memcmp(vbuffer, nvram_ularray, varsize)) {
4528 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__));
4529 } else
4530 DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n",
4531 __FUNCTION__));
4532
4533 MFREE(bus->dhd->osh, nvram_ularray, varsize);
4534#endif /* DHD_DEBUG */
4535
4536 MFREE(bus->dhd->osh, vbuffer, varsize);
4537 }
4538
4539 phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize;
4540
4541 phys_size += bus->dongle_ram_base;
4542
4543 /* adjust to the user specified RAM */
4544 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
4545 phys_size, bus->ramsize));
4546 DHD_INFO(("Vars are at %d, orig varsize is %d\n",
4547 varaddr, varsize));
4548 varsize = ((phys_size - 4) - varaddr);
4549
4550 /*
4551 * Determine the length token:
4552 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
4553 */
4554 if (bcmerror) {
4555 varsizew = 0;
4556 } else {
4557 varsizew = varsize / 4;
4558 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
4559 varsizew = htol32(varsizew);
4560 }
4561
4562 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
4563
4564 /* Write the length token to the last word */
4565 bcmerror = dhdsdio_membytes(bus, TRUE, (phys_size - 4),
4566 (uint8*)&varsizew, 4);
4567
4568 return bcmerror;
4569}
4570
4571static int
4572dhdsdio_download_state(dhd_bus_t *bus, bool enter)
4573{
4574 uint retries;
4575 int bcmerror = 0;
4576 int foundcr4 = 0;
4577
4578 if (!bus->sih)
4579 return BCME_ERROR;
4580 /* To enter download state, disable ARM and reset SOCRAM.
4581 * To exit download state, simply reset ARM (default is RAM boot).
4582 */
4583 if (enter) {
4584 bus->alp_only = TRUE;
4585
4586 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
4587 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
4588 if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
4589 foundcr4 = 1;
4590 } else {
4591 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
4592 bcmerror = BCME_ERROR;
4593 goto fail;
4594 }
4595 }
4596
4597 if (!foundcr4) {
4598 si_core_disable(bus->sih, 0);
4599 if (bcmsdh_regfail(bus->sdh)) {
4600 bcmerror = BCME_SDIO_ERROR;
4601 goto fail;
4602 }
4603
4604 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
4605 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
4606 bcmerror = BCME_ERROR;
4607 goto fail;
4608 }
4609
4610 si_core_reset(bus->sih, 0, 0);
4611 if (bcmsdh_regfail(bus->sdh)) {
4612 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
4613 __FUNCTION__));
4614 bcmerror = BCME_SDIO_ERROR;
4615 goto fail;
4616 }
4617
4618 /* Disable remap for download */
4619 if (REMAP_ENAB(bus) && si_socdevram_remap_isenb(bus->sih))
4620 dhdsdio_devram_remap(bus, FALSE);
4621
4622 if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID ||
4623 CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) {
4624 /* Disabling Remap for SRAM_3 */
4625 si_socram_set_bankpda(bus->sih, 0x3, 0x0);
4626 }
4627
4628 /* Clear the top bit of memory */
4629 if (bus->ramsize) {
4630 uint32 zeros = 0;
4631 if (dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
4632 (uint8*)&zeros, 4) < 0) {
4633 bcmerror = BCME_SDIO_ERROR;
4634 goto fail;
4635 }
4636 }
4637 } else {
4638 /* For CR4,
4639 * Halt ARM
4640 * Remove ARM reset
4641 * Read RAM base address [0x18_0000]
4642 * [next] Download firmware
4643 * [done at else] Populate the reset vector
4644 * [done at else] Remove ARM halt
4645 */
4646 /* Halt ARM & remove reset */
4647 si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT);
4648 }
4649 } else {
4650 if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
4651 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
4652 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
4653 bcmerror = BCME_ERROR;
4654 goto fail;
4655 }
4656
4657 if (!si_iscoreup(bus->sih)) {
4658 DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__));
4659 bcmerror = BCME_ERROR;
4660 goto fail;
4661 }
4662
4663 if ((bcmerror = dhdsdio_write_vars(bus))) {
4664 DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
4665 goto fail;
4666 }
4667
4668 /* Enable remap before ARM reset but after vars.
4669 * No backplane access in remap mode
4670 */
4671 if (REMAP_ENAB(bus) && !si_socdevram_remap_isenb(bus->sih))
4672 dhdsdio_devram_remap(bus, TRUE);
4673
4674 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
4675 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
4676 DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
4677 bcmerror = BCME_ERROR;
4678 goto fail;
4679 }
4680 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
4681
4682
4683 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
4684 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
4685 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
4686 bcmerror = BCME_ERROR;
4687 goto fail;
4688 }
4689 } else {
4690 /* cr4 has no socram, but tcm's */
4691 /* write vars */
4692 if ((bcmerror = dhdsdio_write_vars(bus))) {
4693 DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
4694 goto fail;
4695 }
4696
4697 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
4698 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
4699 DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
4700 bcmerror = BCME_ERROR;
4701 goto fail;
4702 }
4703 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
4704
4705 /* switch back to arm core again */
4706 if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
4707 DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__));
4708 bcmerror = BCME_ERROR;
4709 goto fail;
4710 }
4711 /* write address 0 with reset instruction */
4712 bcmerror = dhdsdio_membytes(bus, TRUE, 0,
4713 (uint8 *)&bus->resetinstr, sizeof(bus->resetinstr));
4714
4715 if (bcmerror == BCME_OK) {
4716 uint32 tmp;
07d6b24a 4717
010c3a89 4718 /* verify write */
565fad4d 4719 bcmerror = dhdsdio_membytes(bus, FALSE, 0,
07d6b24a
RC		 4720 (uint8 *)&tmp, sizeof(tmp));
4721
4722 if (bcmerror == BCME_OK && tmp != bus->resetinstr) {
4723 DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n",
010c3a89
RC		 4724 __FUNCTION__, bus->resetinstr));
4725 DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n",
07d6b24a 4726 __FUNCTION__, tmp));
010c3a89
RC		 4727 bcmerror = BCME_SDIO_ERROR;
4728 goto fail;
4729 }
4730 }
4731
4732 /* now remove reset and halt and continue to run CR4 */
4733 }
4734
4735 si_core_reset(bus->sih, 0, 0);
4736 if (bcmsdh_regfail(bus->sdh)) {
4737 DHD_ERROR(("%s: Failure trying to reset ARM core?\n", __FUNCTION__));
4738 bcmerror = BCME_SDIO_ERROR;
4739 goto fail;
4740 }
4741
4742 /* Allow HT Clock now that the ARM is running. */
4743 bus->alp_only = FALSE;
4744
4745 bus->dhd->busstate = DHD_BUS_LOAD;
4746 }
4747
4748fail:
4749 /* Always return to SDIOD core */
4750 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
4751 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
4752
4753 return bcmerror;
4754}
4755
4756int
4757dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
4758 void *params, int plen, void *arg, int len, bool set)
4759{
4760 dhd_bus_t *bus = dhdp->bus;
4761 const bcm_iovar_t *vi = NULL;
4762 int bcmerror = 0;
4763 int val_size;
4764 uint32 actionid;
4765
4766 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4767
4768 ASSERT(name);
4769 ASSERT(len >= 0);
4770
4771 /* Get MUST have return space */
4772 ASSERT(set || (arg && len));
4773
4774 /* Set does NOT take qualifiers */
4775 ASSERT(!set || (!params && !plen));
4776
4777 /* Look up var locally; if not found pass to host driver */
4778 if ((vi = bcm_iovar_lookup(dhdsdio_iovars, name)) == NULL) {
4779 dhd_os_sdlock(bus->dhd);
4780
4781 BUS_WAKE(bus);
4782
4783 /* Turn on clock in case SD command needs backplane */
4784 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4785
4786 bcmerror = bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len, set);
4787
4788 /* Check for bus configuration changes of interest */
4789
4790 /* If it was divisor change, read the new one */
4791 if (set && strcmp(name, "sd_divisor") == 0) {
4792 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
4793 &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
4794 bus->sd_divisor = -1;
4795 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
4796 } else {
4797 DHD_INFO(("%s: noted %s update, value now %d\n",
4798 __FUNCTION__, name, bus->sd_divisor));
4799 }
4800 }
4801 /* If it was a mode change, read the new one */
4802 if (set && strcmp(name, "sd_mode") == 0) {
4803 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
4804 &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
4805 bus->sd_mode = -1;
4806 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
4807 } else {
4808 DHD_INFO(("%s: noted %s update, value now %d\n",
4809 __FUNCTION__, name, bus->sd_mode));
4810 }
4811 }
4812 /* Similar check for blocksize change */
4813 if (set && strcmp(name, "sd_blocksize") == 0) {
4814 int32 fnum = 2;
4815 if (bcmsdh_iovar_op(bus->sdh, "sd_blocksize", &fnum, sizeof(int32),
4816 &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
4817 bus->blocksize = 0;
4818 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
4819 } else {
4820 DHD_INFO(("%s: noted %s update, value now %d\n",
4821 __FUNCTION__, "sd_blocksize", bus->blocksize));
4822
4823 dhdsdio_tune_fifoparam(bus);
4824 }
4825 }
4826 bus->roundup = MIN(max_roundup, bus->blocksize);
4827
4828 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
4829 NO_OTHER_ACTIVE_BUS_USER(bus)) {
4830 bus->activity = FALSE;
4831 dhdsdio_bussleep(bus, TRUE);
4832 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4833 }
4834
4835 dhd_os_sdunlock(bus->dhd);
4836 goto exit;
4837 }
4838
4839 DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
4840 name, (set ? "set" : "get"), len, plen));
4841
4842 /* set up 'params' pointer in case this is a set command so that
4843 * the convenience int and bool code can be common to set and get
4844 */
4845 if (params == NULL) {
4846 params = arg;
4847 plen = len;
4848 }
4849
4850 if (vi->type == IOVT_VOID)
4851 val_size = 0;
4852 else if (vi->type == IOVT_BUFFER)
4853 val_size = len;
4854 else
4855 /* all other types are integer sized */
4856 val_size = sizeof(int);
4857
4858 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
4859 bcmerror = dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size);
4860
4861exit:
4862 return bcmerror;
4863}
4864
4865void
4866dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
4867{
4868 osl_t *osh;
4869 uint32 local_hostintmask;
4870 uint8 saveclk;
4871 uint retries;
4872 int err;
4873 bool wlfc_enabled = FALSE;
4874 unsigned long flags;
4875
4876 if (!bus->dhd)
4877 return;
4878
4879 osh = bus->dhd->osh;
4880 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4881
4882 bcmsdh_waitlockfree(bus->sdh);
4883
4884 if (enforce_mutex)
4885 dhd_os_sdlock(bus->dhd);
4886
4887 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bus->dhd->hang_was_sent) {
4888 /* if Firmware already hangs disbale any interrupt */
4889 bus->dhd->busstate = DHD_BUS_DOWN;
4890 bus->hostintmask = 0;
4891 bcmsdh_intr_disable(bus->sdh);
4892 } else {
4893
4894 BUS_WAKE(bus);
4895
4896 if (KSO_ENAB(bus)) {
4897
4898 /* Enable clock for device interrupts */
4899 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4900
4901 /* Disable and clear interrupts at the chip level also */
4902 W_SDREG(0, &bus->regs->hostintmask, retries);
4903 local_hostintmask = bus->hostintmask;
4904 bus->hostintmask = 0;
4905
4906 /* Force clocks on backplane to be sure F2 interrupt propagates */
4907 saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4908 if (!err) {
4909 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4910 (saveclk | SBSDIO_FORCE_HT), &err);
4911 }
4912 if (err) {
4913 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
4914 __FUNCTION__, err));
4915 }
4916
4917 /* Turn off the bus (F2), free any pending packets */
4918 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
4919 bcmsdh_intr_disable(bus->sdh);
4920 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
4921
4922 /* Clear any pending interrupts now that F2 is disabled */
4923 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
4924 }
4925
4926 /* Turn off the backplane clock (only) */
4927 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
4928
4929 /* Change our idea of bus state */
4930 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
4931 bus->dhd->busstate = DHD_BUS_DOWN;
4932 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
4933 }
4934
4935#ifdef PROP_TXSTATUS
4936 wlfc_enabled = (dhd_wlfc_cleanup_txq(bus->dhd, NULL, 0) != WLFC_UNSUPPORTED);
4937#endif
4938 if (!wlfc_enabled) {
4939#ifdef DHDTCPACK_SUPPRESS
4940 /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
4941 * when there is a newly coming packet from network stack.
4942 */
4943 dhd_tcpack_info_tbl_clean(bus->dhd);
4944#endif /* DHDTCPACK_SUPPRESS */
4945 dhd_os_sdlock_txq(bus->dhd);
4946 /* Clear the data packet queues */
4947 pktq_flush(osh, &bus->txq, TRUE);
4948 dhd_os_sdunlock_txq(bus->dhd);
4949 }
4950
4951 /* Clear any held glomming stuff */
4952 if (bus->glomd)
4953 PKTFREE(osh, bus->glomd, FALSE);
4954
4955 if (bus->glom)
4956 PKTFREE(osh, bus->glom, FALSE);
4957
4958 bus->glom = bus->glomd = NULL;
4959
4960 /* Clear rx control and wake any waiters */
4961 bus->rxlen = 0;
4962 dhd_os_ioctl_resp_wake(bus->dhd);
4963
4964 /* Reset some F2 state stuff */
4965 bus->rxskip = FALSE;
4966 bus->tx_seq = bus->rx_seq = 0;
4967
4968 bus->tx_max = 4;
4969
4970 if (enforce_mutex)
4971 dhd_os_sdunlock(bus->dhd);
4972}
4973
4974#if defined(BCMSDIOH_TXGLOM) && defined(BCMSDIOH_STD)
4975extern uint sd_txglom;
4976#endif
4977void
4978dhd_txglom_enable(dhd_pub_t *dhdp, bool enable)
4979{
4980 /* can't enable host txglom by default, some platforms have no
4981 * (or crappy) ADMA support and txglom will cause kernel assertions (e.g.
4982 * panda board)
4983 */
4984 dhd_bus_t *bus = dhdp->bus;
4985#ifdef BCMSDIOH_TXGLOM
4986 uint32 rxglom;
4987 int32 ret;
4988
4989 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4990
4991#ifdef BCMSDIOH_STD
4992 if (enable)
4993 enable = sd_txglom;
4994#endif /* BCMSDIOH_STD */
4995
4996 if (enable) {
4997 rxglom = 1;
4998 ret = dhd_iovar(dhdp, 0, "bus:rxglom", (char *)&rxglom, sizeof(rxglom), NULL, 0,
4999 TRUE);
5000 if (ret >= 0)
5001 bus->txglom_enable = TRUE;
5002 else {
5003#ifdef BCMSDIOH_STD
5004 sd_txglom = 0;
5005#endif /* BCMSDIOH_STD */
5006 bus->txglom_enable = FALSE;
5007 }
5008 } else
5009#endif /* BCMSDIOH_TXGLOM */
5010 bus->txglom_enable = FALSE;
5011 printf("%s: enable %d\n", __FUNCTION__, bus->txglom_enable);
5012 dhd_conf_set_txglom_params(bus->dhd, bus->txglom_enable);
5013 bcmsdh_set_mode(bus->sdh, bus->dhd->conf->txglom_mode);
5014}
5015
5016int
5017dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
5018{
5019 dhd_bus_t *bus = dhdp->bus;
5020 dhd_timeout_t tmo;
5021 uint retries = 0;
5022 uint8 ready, enable;
5023 int err, ret = 0;
5024 uint8 saveclk;
5025
5026 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5027
5028 ASSERT(bus->dhd);
5029 if (!bus->dhd)
5030 return 0;
5031
5032 if (enforce_mutex)
5033 dhd_os_sdlock(bus->dhd);
5034
5035 if (bus->sih->chip == BCM43362_CHIP_ID) {
5036 printf("%s: delay 100ms for BCM43362\n", __FUNCTION__);
5037 OSL_DELAY(100000); // terence 20131209: delay for 43362
5038 }
5039
5040 /* Make sure backplane clock is on, needed to generate F2 interrupt */
5041 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5042 if (bus->clkstate != CLK_AVAIL) {
5043 DHD_ERROR(("%s: clock state is wrong. state = %d\n", __FUNCTION__, bus->clkstate));
5044 ret = -1;
5045 goto exit;
5046 }
5047
5048 /* Force clocks on backplane to be sure F2 interrupt propagates */
5049 saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
5050
5051 if (!err) {
5052 if (bus->sih->chip == BCM43012_CHIP_ID) {
5053 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5054 (saveclk | SBSDIO_HT_AVAIL_REQ), &err);
5055 } else {
5056 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5057 (saveclk | SBSDIO_FORCE_HT), &err);
5058 }
5059 }
5060
5061 if (err) {
5062 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", __FUNCTION__, err));
5063 ret = -1;
5064 goto exit;
5065 }
5066
5067 /* Enable function 2 (frame transfers) */
5068 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
5069 &bus->regs->tosbmailboxdata, retries);
5070 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
5071
5072 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
5073
5074 /* Give the dongle some time to do its thing and set IOR2 */
5075 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
5076
5077 ready = 0;
5078 while (ready != enable && !dhd_timeout_expired(&tmo))
5079 ready = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL);
5080
5081 DHD_ERROR(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
5082 __FUNCTION__, enable, ready, tmo.elapsed));
5083
5084
5085 /* If F2 successfully enabled, set core and enable interrupts */
5086 if (ready == enable) {
5087 /* Make sure we're talking to the core. */
5088 if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)))
5089 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5090 ASSERT(bus->regs != NULL);
5091
5092 /* Set up the interrupt mask and enable interrupts */
5093 bus->hostintmask = HOSTINTMASK;
5094 /* corerev 4 could use the newer interrupt logic to detect the frames */
5095 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 4) &&
5096 (bus->rxint_mode != SDIO_DEVICE_HMB_RXINT)) {
5097 bus->hostintmask &= ~I_HMB_FRAME_IND;
5098 bus->hostintmask |= I_XMTDATA_AVAIL;
5099 }
5100 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
5101
5102 if (bus->sih->buscorerev < 15) {
5103 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
5104 (uint8)watermark, &err);
5105 }
5106
5107 /* Set bus state according to enable result */
5108 dhdp->busstate = DHD_BUS_DATA;
5109
5110 /* Need to set fn2 block size to match fn1 block size.
5111 * Requests to fn2 go thru fn1. *
5112 * faltwig has this code contitioned with #if !BCMSPI_ANDROID.
5113 * It would be cleaner to use the ->sdh->block_sz[fno] instead of
5114 * 64, but this layer has no access to sdh types.
5115 */
5116
5117 /* bcmsdh_intr_unmask(bus->sdh); */
5118
5119 bus->intdis = FALSE;
5120 if (bus->intr) {
5121 DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
5122 bcmsdh_intr_enable(bus->sdh);
5123 } else {
5124 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
5125 bcmsdh_intr_disable(bus->sdh);
5126 }
5127
5128 }
5129
5130
5131 else {
5132 /* Disable F2 again */
5133 enable = SDIO_FUNC_ENABLE_1;
5134 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
5135 }
5136
5137 if (dhdsdio_sr_cap(bus)) {
5138 dhdsdio_sr_init(bus);
5139 /* Masking the chip active interrupt permanantly */
5140 bus->hostintmask &= ~I_CHIPACTIVE;
5141 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
5142 DHD_INFO(("%s: disable I_CHIPACTIVE in hostintmask[0x%08x]\n",
5143 __FUNCTION__, bus->hostintmask));
5144 } else {
5145 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
5146 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
5147 }
5148
5149 /* If we didn't come up, turn off backplane clock */
5150 if (dhdp->busstate != DHD_BUS_DATA)
5151 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
5152
5153exit:
5154 if (enforce_mutex)
5155 dhd_os_sdunlock(bus->dhd);
5156
5157 return ret;
5158}
5159
5160static void
5161dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
5162{
5163 bcmsdh_info_t *sdh = bus->sdh;
5164 sdpcmd_regs_t *regs = bus->regs;
5165 uint retries = 0;
5166 uint16 lastrbc;
5167 uint8 hi, lo;
5168 int err;
5169
5170 DHD_ERROR(("%s: %sterminate frame%s\n", __FUNCTION__,
5171 (abort ? "abort command, " : ""), (rtx ? ", send NAK" : "")));
5172
5173 if (!KSO_ENAB(bus)) {
5174 DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
5175 return;
5176 }
5177
5178 if (abort) {
5179 bcmsdh_abort(sdh, SDIO_FUNC_2);
5180 }
5181
5182 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, &err);
5183 if (err) {
5184 DHD_ERROR(("%s: SBSDIO_FUNC1_FRAMECTRL cmd err\n", __FUNCTION__));
5185 goto fail;
5186 }
5187 bus->f1regdata++;
5188
5189 /* Wait until the packet has been flushed (device/FIFO stable) */
5190 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
5191 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI, NULL);
5192 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO, &err);
5193 if (err) {
5194 DHD_ERROR(("%s: SBSDIO_FUNC1_RFAMEBCLO cmd err\n", __FUNCTION__));
5195 goto fail;
5196 }
5197
5198 bus->f1regdata += 2;
5199
5200 if ((hi == 0) && (lo == 0))
5201 break;
5202
5203 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
5204 DHD_ERROR(("%s: count growing: last 0x%04x now 0x%04x\n",
5205 __FUNCTION__, lastrbc, ((hi << 8) + lo)));
5206 }
5207 lastrbc = (hi << 8) + lo;
5208 }
5209
5210 if (!retries) {
5211 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n", __FUNCTION__, lastrbc));
5212 } else {
5213 DHD_INFO(("%s: flush took %d iterations\n", __FUNCTION__, (0xffff - retries)));
5214 }
5215
5216 if (rtx) {
5217 bus->rxrtx++;
5218 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
5219 bus->f1regdata++;
5220 if (retries <= retry_limit) {
5221 bus->rxskip = TRUE;
5222 }
5223 }
5224
5225 /* Clear partial in any case */
5226 bus->nextlen = 0;
5227
5228fail:
5229 /* If we can't reach the device, signal failure */
5230 if (err || bcmsdh_regfail(sdh))
5231 bus->dhd->busstate = DHD_BUS_DOWN;
5232}
5233
5234static void
5235dhdsdio_read_control(dhd_bus_t *bus, uint8 *hdr, uint len, uint doff)
5236{
5237 bcmsdh_info_t *sdh = bus->sdh;
5238 uint rdlen, pad;
5239
5240 int sdret;
5241
5242 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5243
5244 /* Control data already received in aligned rxctl */
5245 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
5246 goto gotpkt;
5247
5248 ASSERT(bus->rxbuf);
5249 /* Set rxctl for frame (w/optional alignment) */
5250 bus->rxctl = bus->rxbuf;
5251 if (dhd_alignctl) {
5252 bus->rxctl += firstread;
5253 if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
5254 bus->rxctl += (DHD_SDALIGN - pad);
5255 bus->rxctl -= firstread;
5256 }
5257 ASSERT(bus->rxctl >= bus->rxbuf);
5258
5259 /* Copy the already-read portion over */
5260 bcopy(hdr, bus->rxctl, firstread);
5261 if (len <= firstread)
5262 goto gotpkt;
5263
5264 /* Copy the full data pkt in gSPI case and process ioctl. */
5265 if (bus->bus == SPI_BUS) {
5266 bcopy(hdr, bus->rxctl, len);
5267 goto gotpkt;
5268 }
5269
5270 /* Raise rdlen to next SDIO block to avoid tail command */
5271 rdlen = len - firstread;
5272 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
5273 pad = bus->blocksize - (rdlen % bus->blocksize);
5274 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
5275 ((len + pad) < bus->dhd->maxctl))
5276 rdlen += pad;
5277 } else if (rdlen % DHD_SDALIGN) {
5278 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
5279 }
5280
5281 /* Satisfy length-alignment requirements */
5282 if (forcealign && (rdlen & (ALIGNMENT - 1)))
5283 rdlen = ROUNDUP(rdlen, ALIGNMENT);
5284
5285 /* Drop if the read is too big or it exceeds our maximum */
5286 if ((rdlen + firstread) > bus->dhd->maxctl) {
5287 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
5288 __FUNCTION__, rdlen, bus->dhd->maxctl));
5289 bus->dhd->rx_errors++;
5290 dhdsdio_rxfail(bus, FALSE, FALSE);
5291 goto done;
5292 }
5293
5294 if ((len - doff) > bus->dhd->maxctl) {
5295 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
5296 __FUNCTION__, len, (len - doff), bus->dhd->maxctl));
5297 bus->dhd->rx_errors++; bus->rx_toolong++;
5298 dhdsdio_rxfail(bus, FALSE, FALSE);
5299 goto done;
5300 }
5301
5302
5303 /* Read remainder of frame body into the rxctl buffer */
5304 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
5305 (bus->rxctl + firstread), rdlen, NULL, NULL, NULL);
5306 bus->f2rxdata++;
5307 ASSERT(sdret != BCME_PENDING);
5308
5309 /* Control frame failures need retransmission */
5310 if (sdret < 0) {
5311 DHD_ERROR(("%s: read %d control bytes failed: %d\n", __FUNCTION__, rdlen, sdret));
5312 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
5313 dhdsdio_rxfail(bus, TRUE, TRUE);
5314 goto done;
5315 }
5316
5317gotpkt:
5318
5319#ifdef DHD_DEBUG
5320 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
5321 prhex("RxCtrl", bus->rxctl, len);
5322 }
5323#endif
5324
5325 /* Point to valid data and indicate its length */
5326 bus->rxctl += doff;
5327 bus->rxlen = len - doff;
5328
5329done:
5330 /* Awake any waiters */
5331 dhd_os_ioctl_resp_wake(bus->dhd);
5332}
5333int
5334dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf, uint reorder_info_len,
5335 void **pkt, uint32 *pkt_count);
5336
5337static uint8
5338dhdsdio_rxglom(dhd_bus_t *bus, uint8 rxseq)
5339{
5340 uint16 dlen, totlen;
5341 uint8 *dptr, num = 0;
5342
5343 uint16 sublen, check;
5344 void *pfirst, *plast, *pnext;
5345 void * list_tail[DHD_MAX_IFS] = { NULL };
5346 void * list_head[DHD_MAX_IFS] = { NULL };
5347 uint8 idx;
5348 osl_t *osh = bus->dhd->osh;
5349
5350 int errcode;
5351 uint8 chan, seq, doff, sfdoff;
5352 uint8 txmax;
5353 uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
5354 uint reorder_info_len;
5355
5356 int ifidx = 0;
5357 bool usechain = bus->use_rxchain;
5358
5359 /* If packets, issue read(s) and send up packet chain */
5360 /* Return sequence numbers consumed? */
5361
5362 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd, bus->glom));
5363
5364 /* If there's a descriptor, generate the packet chain */
5365 if (bus->glomd) {
5366 dhd_os_sdlock_rxq(bus->dhd);
5367
5368 pfirst = plast = pnext = NULL;
5369 dlen = (uint16)PKTLEN(osh, bus->glomd);
5370 dptr = PKTDATA(osh, bus->glomd);
5371 if (!dlen || (dlen & 1)) {
5372 DHD_ERROR(("%s: bad glomd len (%d), ignore descriptor\n",
5373 __FUNCTION__, dlen));
5374 dlen = 0;
5375 }
5376
5377 for (totlen = num = 0; dlen; num++) {
5378 /* Get (and move past) next length */
5379 sublen = ltoh16_ua(dptr);
5380 dlen -= sizeof(uint16);
5381 dptr += sizeof(uint16);
5382 if ((sublen < SDPCM_HDRLEN) ||
5383 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
5384 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
5385 __FUNCTION__, num, sublen));
5386 pnext = NULL;
5387 break;
5388 }
5389 if (sublen % DHD_SDALIGN) {
5390 DHD_ERROR(("%s: sublen %d not a multiple of %d\n",
5391 __FUNCTION__, sublen, DHD_SDALIGN));
5392 usechain = FALSE;
5393 }
5394 totlen += sublen;
5395
5396 /* For last frame, adjust read len so total is a block multiple */
5397 if (!dlen) {
5398 sublen += (ROUNDUP(totlen, bus->blocksize) - totlen);
5399 totlen = ROUNDUP(totlen, bus->blocksize);
5400 }
5401
5402 /* Allocate/chain packet for next subframe */
5403 if ((pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE)) == NULL) {
5404 DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
5405 __FUNCTION__, num, sublen));
5406 break;
5407 }
5408 ASSERT(!PKTLINK(pnext));
5409 if (!pfirst) {
5410 ASSERT(!plast);
5411 pfirst = plast = pnext;
5412 } else {
5413 ASSERT(plast);
5414 PKTSETNEXT(osh, plast, pnext);
5415 plast = pnext;
5416 }
5417
5418 /* Adhere to start alignment requirements */
5419 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
5420 }
5421
5422 /* If all allocations succeeded, save packet chain in bus structure */
5423 if (pnext) {
5424 DHD_GLOM(("%s: allocated %d-byte packet chain for %d subframes\n",
5425 __FUNCTION__, totlen, num));
5426 if (DHD_GLOM_ON() && bus->nextlen) {
5427 if (totlen != bus->nextlen) {
5428 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d "
5429 "rxseq %d\n", __FUNCTION__, bus->nextlen,
5430 totlen, rxseq));
5431 }
5432 }
5433 bus->glom = pfirst;
5434 pfirst = pnext = NULL;
5435 } else {
5436 if (pfirst)
5437 PKTFREE(osh, pfirst, FALSE);
5438 bus->glom = NULL;
5439 num = 0;
5440 }
5441
5442 /* Done with descriptor packet */
5443 PKTFREE(osh, bus->glomd, FALSE);
5444 bus->glomd = NULL;
5445 bus->nextlen = 0;
5446
5447 dhd_os_sdunlock_rxq(bus->dhd);
5448 }
5449
5450 /* Ok -- either we just generated a packet chain, or had one from before */
5451 if (bus->glom) {
5452 if (DHD_GLOM_ON()) {
5453 DHD_GLOM(("%s: attempt superframe read, packet chain:\n", __FUNCTION__));
5454 for (pnext = bus->glom; pnext; pnext = PKTNEXT(osh, pnext)) {
5455 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
5456 pnext, (uint8*)PKTDATA(osh, pnext),
5457 PKTLEN(osh, pnext), PKTLEN(osh, pnext)));
5458 }
5459 }
5460
5461 pfirst = bus->glom;
5462 dlen = (uint16)pkttotlen(osh, pfirst);
5463
5464 /* Do an SDIO read for the superframe. Configurable iovar to
5465 * read directly into the chained packet, or allocate a large
5466 * packet and and copy into the chain.
5467 */
5468 if (usechain) {
5469 errcode = dhd_bcmsdh_recv_buf(bus,
5470 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
5471 F2SYNC, (uint8*)PKTDATA(osh, pfirst),
5472 dlen, pfirst, NULL, NULL);
5473 } else if (bus->dataptr) {
5474 errcode = dhd_bcmsdh_recv_buf(bus,
5475 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
5476 F2SYNC, bus->dataptr,
5477 dlen, NULL, NULL, NULL);
5478 sublen = (uint16)pktfrombuf(osh, pfirst, 0, dlen, bus->dataptr);
5479 if (sublen != dlen) {
5480 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
5481 __FUNCTION__, dlen, sublen));
5482 errcode = -1;
5483 }
5484 pnext = NULL;
5485 BCM_REFERENCE(pnext);
5486 } else {
5487 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", dlen));
5488 errcode = -1;
5489 }
5490 bus->f2rxdata++;
5491 ASSERT(errcode != BCME_PENDING);
5492
5493 /* On failure, kill the superframe, allow a couple retries */
5494 if (errcode < 0) {
5495 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
5496 __FUNCTION__, dlen, errcode));
5497 bus->dhd->rx_errors++;
5498
5499 if (bus->glomerr++ < 3) {
5500 dhdsdio_rxfail(bus, TRUE, TRUE);
5501 } else {
5502 bus->glomerr = 0;
5503 dhdsdio_rxfail(bus, TRUE, FALSE);
5504 dhd_os_sdlock_rxq(bus->dhd);
5505 PKTFREE(osh, bus->glom, FALSE);
5506 dhd_os_sdunlock_rxq(bus->dhd);
5507 bus->rxglomfail++;
5508 bus->glom = NULL;
5509 }
5510 return 0;
5511 }
5512
5513#ifdef DHD_DEBUG
5514 if (DHD_GLOM_ON()) {
5515 prhex("SUPERFRAME", PKTDATA(osh, pfirst),
5516 MIN(PKTLEN(osh, pfirst), 48));
5517 }
5518#endif
5519
5520
5521 /* Validate the superframe header */
5522 dptr = (uint8 *)PKTDATA(osh, pfirst);
5523 sublen = ltoh16_ua(dptr);
5524 check = ltoh16_ua(dptr + sizeof(uint16));
5525
5526 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
5527 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
5528 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
5529 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
5530 DHD_INFO(("%s: got frame w/nextlen too large (%d) seq %d\n",
5531 __FUNCTION__, bus->nextlen, seq));
5532 bus->nextlen = 0;
5533 }
5534 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
5535 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
5536
5537 errcode = 0;
5538 if ((uint16)~(sublen^check)) {
5539 DHD_ERROR(("%s (superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
5540 __FUNCTION__, sublen, check));
5541 errcode = -1;
5542 } else if (ROUNDUP(sublen, bus->blocksize) != dlen) {
5543 DHD_ERROR(("%s (superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
5544 __FUNCTION__, sublen, ROUNDUP(sublen, bus->blocksize), dlen));
5545 errcode = -1;
5546 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != SDPCM_GLOM_CHANNEL) {
5547 DHD_ERROR(("%s (superframe): bad channel %d\n", __FUNCTION__,
5548 SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN])));
5549 errcode = -1;
5550 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
5551 DHD_ERROR(("%s (superframe): got second descriptor?\n", __FUNCTION__));
5552 errcode = -1;
5553 } else if ((doff < SDPCM_HDRLEN) ||
5554 (doff > (PKTLEN(osh, pfirst) - SDPCM_HDRLEN))) {
5555 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d pkt %d min %d\n",
5556 __FUNCTION__, doff, sublen, PKTLEN(osh, pfirst),
5557 SDPCM_HDRLEN));
5558 errcode = -1;
5559 }
5560
5561 /* Check sequence number of superframe SW header */
5562 if (rxseq != seq) {
5563 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
5564 __FUNCTION__, seq, rxseq));
5565 bus->rx_badseq++;
5566 rxseq = seq;
5567 }
5568
5569 /* Check window for sanity */
5570 if ((uint8)(txmax - bus->tx_seq) > 0x70) {
5571 DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
5572 __FUNCTION__, txmax, bus->tx_seq));
5573 txmax = bus->tx_max;
5574 }
5575 bus->tx_max = txmax;
5576
5577 /* Remove superframe header, remember offset */
5578 PKTPULL(osh, pfirst, doff);
5579 sfdoff = doff;
5580
5581 /* Validate all the subframe headers */
5582 for (num = 0, pnext = pfirst; pnext && !errcode;
5583 num++, pnext = PKTNEXT(osh, pnext)) {
5584 dptr = (uint8 *)PKTDATA(osh, pnext);
5585 dlen = (uint16)PKTLEN(osh, pnext);
5586 sublen = ltoh16_ua(dptr);
5587 check = ltoh16_ua(dptr + sizeof(uint16));
5588 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
5589 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
5590#ifdef DHD_DEBUG
5591 if (DHD_GLOM_ON()) {
5592 prhex("subframe", dptr, 32);
5593 }
5594#endif
5595
5596 if ((uint16)~(sublen^check)) {
5597 DHD_ERROR(("%s (subframe %d): HW hdr error: "
5598 "len/check 0x%04x/0x%04x\n",
5599 __FUNCTION__, num, sublen, check));
5600 errcode = -1;
5601 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
5602 DHD_ERROR(("%s (subframe %d): length mismatch: "
5603 "len 0x%04x, expect 0x%04x\n",
5604 __FUNCTION__, num, sublen, dlen));
5605 errcode = -1;
5606 } else if ((chan != SDPCM_DATA_CHANNEL) &&
5607 (chan != SDPCM_EVENT_CHANNEL)) {
5608 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
5609 __FUNCTION__, num, chan));
5610 errcode = -1;
5611 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
5612 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
5613 __FUNCTION__, num, doff, sublen, SDPCM_HDRLEN));
5614 errcode = -1;
5615 }
5616 }
5617
5618 if (errcode) {
5619 /* Terminate frame on error, request a couple retries */
5620 if (bus->glomerr++ < 3) {
5621 /* Restore superframe header space */
5622 PKTPUSH(osh, pfirst, sfdoff);
5623 dhdsdio_rxfail(bus, TRUE, TRUE);
5624 } else {
5625 bus->glomerr = 0;
5626 dhdsdio_rxfail(bus, TRUE, FALSE);
5627 dhd_os_sdlock_rxq(bus->dhd);
5628 PKTFREE(osh, bus->glom, FALSE);
5629 dhd_os_sdunlock_rxq(bus->dhd);
5630 bus->rxglomfail++;
5631 bus->glom = NULL;
5632 }
5633 bus->nextlen = 0;
5634 return 0;
5635 }
5636
5637 /* Basic SD framing looks ok - process each packet (header) */
5638 bus->glom = NULL;
5639 plast = NULL;
5640
5641 dhd_os_sdlock_rxq(bus->dhd);
5642 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
5643 pnext = PKTNEXT(osh, pfirst);
5644 PKTSETNEXT(osh, pfirst, NULL);
5645
5646 dptr = (uint8 *)PKTDATA(osh, pfirst);
5647 sublen = ltoh16_ua(dptr);
5648 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
5649 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
5650 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
5651
5652 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
5653 __FUNCTION__, num, pfirst, PKTDATA(osh, pfirst),
5654 PKTLEN(osh, pfirst), sublen, chan, seq));
5655
5656 ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL));
5657
5658 if (rxseq != seq) {
5659 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
5660 __FUNCTION__, seq, rxseq));
5661 bus->rx_badseq++;
5662 rxseq = seq;
5663 }
5664
5665#ifdef DHD_DEBUG
5666 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
5667 prhex("Rx Subframe Data", dptr, dlen);
5668 }
5669#endif
5670
5671 PKTSETLEN(osh, pfirst, sublen);
5672 PKTPULL(osh, pfirst, doff);
5673
5674 reorder_info_len = sizeof(reorder_info_buf);
5675
5676 if (PKTLEN(osh, pfirst) == 0) {
5677 PKTFREE(bus->dhd->osh, pfirst, FALSE);
5678 continue;
5679 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst, reorder_info_buf,
5680 &reorder_info_len) != 0) {
5681 DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
5682 bus->dhd->rx_errors++;
5683 PKTFREE(osh, pfirst, FALSE);
5684 continue;
5685 }
5686 if (reorder_info_len) {
5687 uint32 free_buf_count;
5688 void *ppfirst;
5689
5690 ppfirst = pfirst;
5691 /* Reordering info from the firmware */
5692 dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf,
5693 reorder_info_len, &ppfirst, &free_buf_count);
5694
5695 if (free_buf_count == 0) {
5696 continue;
5697 } else {
5698 void *temp;
5699
5700 /* go to the end of the chain and attach the pnext there */
5701 temp = ppfirst;
5702 while (PKTNEXT(osh, temp) != NULL) {
5703 temp = PKTNEXT(osh, temp);
5704 }
5705 pfirst = temp;
5706 if (list_tail[ifidx] == NULL)
5707 list_head[ifidx] = ppfirst;
5708 else
5709 PKTSETNEXT(osh, list_tail[ifidx], ppfirst);
5710 list_tail[ifidx] = pfirst;
5711 }
5712
5713 num += (uint8)free_buf_count;
5714 } else {
5715 /* this packet will go up, link back into chain and count it */
5716
5717 if (list_tail[ifidx] == NULL) {
5718 list_head[ifidx] = list_tail[ifidx] = pfirst;
5719 } else {
5720 PKTSETNEXT(osh, list_tail[ifidx], pfirst);
5721 list_tail[ifidx] = pfirst;
5722 }
5723 num++;
5724 }
5725#ifdef DHD_DEBUG
5726 if (DHD_GLOM_ON()) {
5727 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) nxt/lnk %p/%p\n",
5728 __FUNCTION__, num, pfirst,
5729 PKTDATA(osh, pfirst), PKTLEN(osh, pfirst),
5730 PKTNEXT(osh, pfirst), PKTLINK(pfirst)));
5731 prhex("", (uint8 *)PKTDATA(osh, pfirst),
5732 MIN(PKTLEN(osh, pfirst), 32));
5733 }
5734#endif /* DHD_DEBUG */
5735 }
5736 dhd_os_sdunlock_rxq(bus->dhd);
5737
5738 for (idx = 0; idx < DHD_MAX_IFS; idx++) {
5739 if (list_head[idx]) {
5740 void *temp;
5741 uint8 cnt = 0;
5742 temp = list_head[idx];
5743 do {
5744 temp = PKTNEXT(osh, temp);
5745 cnt++;
5746 } while (temp);
5747 if (cnt) {
5748 dhd_os_sdunlock(bus->dhd);
5749 dhd_rx_frame(bus->dhd, idx, list_head[idx], cnt, 0);
5750 dhd_os_sdlock(bus->dhd);
5751#if defined(SDIO_ISR_THREAD)
5752 /* terence 20150615: fix for below error due to bussleep in watchdog after dhd_os_sdunlock here,
5753 * so call BUS_WAKE to wake up bus again
5754 * dhd_bcmsdh_recv_buf: Device asleep
5755 * dhdsdio_readframes: RXHEADER FAILED: -40
5756 * dhdsdio_rxfail: abort command, terminate frame, send NAK
5757 */
5758 BUS_WAKE(bus);
5759#endif
5760 }
5761 }
5762 }
5763 bus->rxglomframes++;
5764 bus->rxglompkts += num;
5765 }
5766 return num;
5767}
5768
5769
5770/* Return TRUE if there may be more frames to read */
5771static uint
5772dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
5773{
5774 osl_t *osh = bus->dhd->osh;
5775 bcmsdh_info_t *sdh = bus->sdh;
5776
5777 uint16 len, check; /* Extracted hardware header fields */
5778 uint8 chan, seq, doff; /* Extracted software header fields */
5779 uint8 fcbits; /* Extracted fcbits from software header */
5780 uint8 delta;
5781
5782 void *pkt; /* Packet for event or data frames */
5783 uint16 pad; /* Number of pad bytes to read */
5784 uint16 rdlen; /* Total number of bytes to read */
5785 uint8 rxseq; /* Next sequence number to expect */
5786 uint rxleft = 0; /* Remaining number of frames allowed */
5787 int sdret; /* Return code from bcmsdh calls */
5788 uint8 txmax; /* Maximum tx sequence offered */
5789 bool len_consistent; /* Result of comparing readahead len and len from hw-hdr */
5790 uint8 *rxbuf;
5791 int ifidx = 0;
5792 uint rxcount = 0; /* Total frames read */
5793 uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN];
5794 uint reorder_info_len;
5795 uint pkt_count;
5796
5797#if defined(DHD_DEBUG) || defined(SDTEST)
5798 bool sdtest = FALSE; /* To limit message spew from test mode */
5799#endif
5800
5801 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5802 bus->readframes = TRUE;
5803
5804 if (!KSO_ENAB(bus)) {
5805 DHD_ERROR(("%s: KSO off\n", __FUNCTION__));
5806 bus->readframes = FALSE;
5807 return 0;
5808 }
5809
5810 ASSERT(maxframes);
5811
5812#ifdef SDTEST
5813 /* Allow pktgen to override maxframes */
5814 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
5815 maxframes = bus->pktgen_count;
5816 sdtest = TRUE;
5817 }
5818#endif
5819
5820 /* Not finished unless we encounter no more frames indication */
5821 *finished = FALSE;
5822
5823
5824 for (rxseq = bus->rx_seq, rxleft = maxframes;
5825 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
5826 rxseq++, rxleft--) {
5827#ifdef DHDTCPACK_SUP_DBG
5828 if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_DELAYTX) {
5829 if (bus->dotxinrx == FALSE)
5830 DHD_ERROR(("%s %d: dotxinrx FALSE with tcpack_sub_mode %d\n",
5831 __FUNCTION__, __LINE__, bus->dhd->tcpack_sup_mode));
5832 }
5833#ifdef DEBUG_COUNTER
5834 else if (pktq_mlen(&bus->txq, ~bus->flowcontrol) > 0) {
5835 tack_tbl.cnt[bus->dotxinrx ? 6 : 7]++;
5836 }
5837#endif /* DEBUG_COUNTER */
5838#endif /* DHDTCPACK_SUP_DBG */
5839 /* tx more to improve rx performance */
5840 if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) {
5841 dhdsdio_sendpendctl(bus);
5842 } else if (bus->dotxinrx && (bus->clkstate == CLK_AVAIL) &&
5843 !bus->fcstate && DATAOK(bus) &&
d964ce36 5844 (pktq_mlen(&bus->txq, ~bus->flowcontrol) > bus->txinrx_thres)) {
010c3a89
RC		 5845 dhdsdio_sendfromq(bus, dhd_txbound);
5846#ifdef DHDTCPACK_SUPPRESS
5847 /* In TCPACK_SUP_DELAYTX mode, do txinrx only if
5848 * 1. Any DATA packet to TX
5849 * 2. TCPACK to TCPDATA PSH packets.
5850 * in bus txq.
5851 */
5852 bus->dotxinrx = (bus->dhd->tcpack_sup_mode == TCPACK_SUP_DELAYTX) ?
5853 FALSE : TRUE;
5854#endif
5855 }
5856
5857 /* Handle glomming separately */
5858 if (bus->glom || bus->glomd) {
5859 uint8 cnt;
5860 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
5861 __FUNCTION__, bus->glomd, bus->glom));
5862 cnt = dhdsdio_rxglom(bus, rxseq);
5863 DHD_GLOM(("%s: rxglom returned %d\n", __FUNCTION__, cnt));
5864 rxseq += cnt - 1;
5865 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
5866 continue;
5867 }
5868
5869 /* Try doing single read if we can */
5870 if (dhd_readahead && bus->nextlen) {
5871 uint16 nextlen = bus->nextlen;
5872 bus->nextlen = 0;
5873
5874 if (bus->bus == SPI_BUS) {
5875 rdlen = len = nextlen;
5876 } else {
5877 rdlen = len = nextlen << 4;
5878
5879 /* Pad read to blocksize for efficiency */
5880 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
5881 pad = bus->blocksize - (rdlen % bus->blocksize);
5882 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
5883 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
5884 rdlen += pad;
5885 } else if (rdlen % DHD_SDALIGN) {
5886 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
5887 }
5888 }
5889
5890 /* We use bus->rxctl buffer in WinXP for initial control pkt receives.
5891 * Later we use buffer-poll for data as well as control packets.
5892 * This is required because dhd receives full frame in gSPI unlike SDIO.
5893 * After the frame is received we have to distinguish whether it is data
5894 * or non-data frame.
5895 */
5896 /* Allocate a packet buffer */
5897 dhd_os_sdlock_rxq(bus->dhd);
5898 if (!(pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE))) {
5899 if (bus->bus == SPI_BUS) {
5900 bus->usebufpool = FALSE;
5901 bus->rxctl = bus->rxbuf;
5902 if (dhd_alignctl) {
5903 bus->rxctl += firstread;
5904 if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
5905 bus->rxctl += (DHD_SDALIGN - pad);
5906 bus->rxctl -= firstread;
5907 }
5908 ASSERT(bus->rxctl >= bus->rxbuf);
5909 rxbuf = bus->rxctl;
5910 /* Read the entire frame */
5911 sdret = dhd_bcmsdh_recv_buf(bus,
5912 bcmsdh_cur_sbwad(sdh),
5913 SDIO_FUNC_2,
5914 F2SYNC, rxbuf, rdlen,
5915 NULL, NULL, NULL);
5916 bus->f2rxdata++;
5917 ASSERT(sdret != BCME_PENDING);
5918
5919
5920 /* Control frame failures need retransmission */
5921 if (sdret < 0) {
5922 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
5923 __FUNCTION__, rdlen, sdret));
5924 /* dhd.rx_ctlerrs is higher level */
5925 bus->rxc_errors++;
5926 dhd_os_sdunlock_rxq(bus->dhd);
5927 dhdsdio_rxfail(bus, TRUE,
5928 (bus->bus == SPI_BUS) ? FALSE : TRUE);
5929 continue;
5930 }
5931 } else {
5932 /* Give up on data, request rtx of events */
5933 DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d "
5934 "expected rxseq %d\n",
5935 __FUNCTION__, len, rdlen, rxseq));
5936 /* Just go try again w/normal header read */
5937 dhd_os_sdunlock_rxq(bus->dhd);
5938 continue;
5939 }
5940 } else {
5941 if (bus->bus == SPI_BUS)
5942 bus->usebufpool = TRUE;
5943
5944 ASSERT(!PKTLINK(pkt));
5945 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
5946 rxbuf = (uint8 *)PKTDATA(osh, pkt);
5947 /* Read the entire frame */
5948 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
5949 SDIO_FUNC_2,
5950 F2SYNC, rxbuf, rdlen,
5951 pkt, NULL, NULL);
5952 bus->f2rxdata++;
5953 ASSERT(sdret != BCME_PENDING);
5954
5955 if (sdret < 0) {
5956 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
5957 __FUNCTION__, rdlen, sdret));
5958 PKTFREE(bus->dhd->osh, pkt, FALSE);
5959 bus->dhd->rx_errors++;
5960 dhd_os_sdunlock_rxq(bus->dhd);
5961 /* Force retry w/normal header read. Don't attempt NAK for
5962 * gSPI
5963 */
5964 dhdsdio_rxfail(bus, TRUE,
5965 (bus->bus == SPI_BUS) ? FALSE : TRUE);
5966 continue;
5967 }
5968 }
5969 dhd_os_sdunlock_rxq(bus->dhd);
5970
5971 /* Now check the header */
5972 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
5973
5974 /* Extract hardware header fields */
5975 len = ltoh16_ua(bus->rxhdr);
5976 check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
5977
5978 /* All zeros means readahead info was bad */
5979 if (!(len|check)) {
5980 DHD_INFO(("%s (nextlen): read zeros in HW header???\n",
5981 __FUNCTION__));
5982 dhd_os_sdlock_rxq(bus->dhd);
5983 PKTFREE2();
5984 dhd_os_sdunlock_rxq(bus->dhd);
5985 GSPI_PR55150_BAILOUT;
5986 continue;
5987 }
5988
5989 /* Validate check bytes */
5990 if ((uint16)~(len^check)) {
5991 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check"
5992 " 0x%04x/0x%04x/0x%04x\n", __FUNCTION__, nextlen,
5993 len, check));
5994 dhd_os_sdlock_rxq(bus->dhd);
5995 PKTFREE2();
5996 dhd_os_sdunlock_rxq(bus->dhd);
5997 bus->rx_badhdr++;
5998 dhdsdio_rxfail(bus, FALSE, FALSE);
5999 GSPI_PR55150_BAILOUT;
6000 continue;
6001 }
6002
6003 /* Validate frame length */
6004 if (len < SDPCM_HDRLEN) {
6005 DHD_ERROR(("%s (nextlen): HW hdr length invalid: %d\n",
6006 __FUNCTION__, len));
6007 dhd_os_sdlock_rxq(bus->dhd);
6008 PKTFREE2();
6009 dhd_os_sdunlock_rxq(bus->dhd);
6010 GSPI_PR55150_BAILOUT;
6011 continue;
6012 }
6013
6014 /* Check for consistency with readahead info */
6015 len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4));
6016 if (len_consistent) {
6017 /* Mismatch, force retry w/normal header (may be >4K) */
6018 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; "
6019 "expected rxseq %d\n",
6020 __FUNCTION__, nextlen, len, ROUNDUP(len, 16), rxseq));
6021 dhd_os_sdlock_rxq(bus->dhd);
6022 PKTFREE2();
6023 dhd_os_sdunlock_rxq(bus->dhd);
6024 dhdsdio_rxfail(bus, TRUE, (bus->bus == SPI_BUS) ? FALSE : TRUE);
6025 GSPI_PR55150_BAILOUT;
6026 continue;
6027 }
6028
6029
6030 /* Extract software header fields */
6031 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6032 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6033 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6034 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6035
6036 bus->nextlen =
6037 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
6038 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
6039 DHD_INFO(("%s (nextlen): got frame w/nextlen too large"
6040 " (%d), seq %d\n", __FUNCTION__, bus->nextlen,
6041 seq));
6042 bus->nextlen = 0;
6043 }
6044
6045 bus->dhd->rx_readahead_cnt ++;
6046 /* Handle Flow Control */
6047 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6048
6049 delta = 0;
6050 if (~bus->flowcontrol & fcbits) {
6051 bus->fc_xoff++;
6052 delta = 1;
6053 }
6054 if (bus->flowcontrol & ~fcbits) {
6055 bus->fc_xon++;
6056 delta = 1;
6057 }
6058
6059 if (delta) {
6060 bus->fc_rcvd++;
6061 bus->flowcontrol = fcbits;
6062 }
6063
6064 /* Check and update sequence number */
6065 if (rxseq != seq) {
6066 DHD_INFO(("%s (nextlen): rx_seq %d, expected %d\n",
6067 __FUNCTION__, seq, rxseq));
6068 bus->rx_badseq++;
6069 rxseq = seq;
6070 }
6071
6072 /* Check window for sanity */
6073 if ((uint8)(txmax - bus->tx_seq) > 0x70) {
6074 DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
6075 __FUNCTION__, txmax, bus->tx_seq));
6076 txmax = bus->tx_max;
6077 }
6078 bus->tx_max = txmax;
6079
6080#ifdef DHD_DEBUG
6081 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
6082 prhex("Rx Data", rxbuf, len);
6083 } else if (DHD_HDRS_ON()) {
6084 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
6085 }
6086#endif
6087
6088 if (chan == SDPCM_CONTROL_CHANNEL) {
6089 if (bus->bus == SPI_BUS) {
6090 dhdsdio_read_control(bus, rxbuf, len, doff);
6091 if (bus->usebufpool) {
6092 dhd_os_sdlock_rxq(bus->dhd);
6093 PKTFREE(bus->dhd->osh, pkt, FALSE);
6094 dhd_os_sdunlock_rxq(bus->dhd);
6095 }
6096 continue;
6097 } else {
6098 DHD_ERROR(("%s (nextlen): readahead on control"
6099 " packet %d?\n", __FUNCTION__, seq));
6100 /* Force retry w/normal header read */
6101 bus->nextlen = 0;
6102 dhdsdio_rxfail(bus, FALSE, TRUE);
6103 dhd_os_sdlock_rxq(bus->dhd);
6104 PKTFREE2();
6105 dhd_os_sdunlock_rxq(bus->dhd);
6106 continue;
6107 }
6108 }
6109
6110 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
6111 DHD_ERROR(("Received %d bytes on %d channel. Running out of "
6112 "rx pktbuf's or not yet malloced.\n", len, chan));
6113 continue;
6114 }
6115
6116 /* Validate data offset */
6117 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
6118 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
6119 __FUNCTION__, doff, len, SDPCM_HDRLEN));
6120 dhd_os_sdlock_rxq(bus->dhd);
6121 PKTFREE2();
6122 dhd_os_sdunlock_rxq(bus->dhd);
6123 ASSERT(0);
6124 dhdsdio_rxfail(bus, FALSE, FALSE);
6125 continue;
6126 }
6127
6128 /* All done with this one -- now deliver the packet */
6129 goto deliver;
6130 }
6131 /* gSPI frames should not be handled in fractions */
6132 if (bus->bus == SPI_BUS) {
6133 break;
6134 }
6135
6136 /* Read frame header (hardware and software) */
6137 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
6138 bus->rxhdr, firstread, NULL, NULL, NULL);
6139 bus->f2rxhdrs++;
6140 ASSERT(sdret != BCME_PENDING);
6141
6142 if (sdret < 0) {
6143 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __FUNCTION__, sdret));
6144 bus->rx_hdrfail++;
6145 dhdsdio_rxfail(bus, TRUE, TRUE);
6146 continue;
6147 }
6148
6149#ifdef DHD_DEBUG
6150 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
6151 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
6152 }
6153#endif
6154
6155 /* Extract hardware header fields */
6156 len = ltoh16_ua(bus->rxhdr);
6157 check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
6158
6159 /* All zeros means no more frames */
6160 if (!(len|check)) {
6161 *finished = TRUE;
6162 break;
6163 }
6164
6165 /* Validate check bytes */
6166 if ((uint16)~(len^check)) {
6167 DHD_ERROR(("%s: HW hdr error: len/check 0x%04x/0x%04x\n",
6168 __FUNCTION__, len, check));
6169 bus->rx_badhdr++;
6170 dhdsdio_rxfail(bus, FALSE, FALSE);
6171 continue;
6172 }
6173
6174 /* Validate frame length */
6175 if (len < SDPCM_HDRLEN) {
6176 DHD_ERROR(("%s: HW hdr length invalid: %d\n", __FUNCTION__, len));
6177 continue;
6178 }
6179
6180 /* Extract software header fields */
6181 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6182 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6183 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6184 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6185
6186 /* Validate data offset */
6187 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
6188 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d seq %d\n",
6189 __FUNCTION__, doff, len, SDPCM_HDRLEN, seq));
6190 bus->rx_badhdr++;
6191 ASSERT(0);
6192 dhdsdio_rxfail(bus, FALSE, FALSE);
6193 continue;
6194 }
6195
6196 /* Save the readahead length if there is one */
6197 bus->nextlen = bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
6198 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
6199 DHD_INFO(("%s (nextlen): got frame w/nextlen too large (%d), seq %d\n",
6200 __FUNCTION__, bus->nextlen, seq));
6201 bus->nextlen = 0;
6202 }
6203
6204 /* Handle Flow Control */
6205 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
6206
6207 delta = 0;
6208 if (~bus->flowcontrol & fcbits) {
6209 bus->fc_xoff++;
6210 delta = 1;
6211 }
6212 if (bus->flowcontrol & ~fcbits) {
6213 bus->fc_xon++;
6214 delta = 1;
6215 }
6216
6217 if (delta) {
6218 bus->fc_rcvd++;
6219 bus->flowcontrol = fcbits;
6220 }
6221
6222 /* Check and update sequence number */
6223 if (rxseq != seq) {
6224 DHD_INFO(("%s: rx_seq %d, expected %d\n", __FUNCTION__, seq, rxseq));
6225 bus->rx_badseq++;
6226 rxseq = seq;
6227 }
6228
6229 /* Check window for sanity */
6230 if ((uint8)(txmax - bus->tx_seq) > 0x70) {
6231 DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
6232 __FUNCTION__, txmax, bus->tx_seq));
6233 txmax = bus->tx_max;
6234 }
6235 bus->tx_max = txmax;
6236
6237 /* Call a separate function for control frames */
6238 if (chan == SDPCM_CONTROL_CHANNEL) {
6239 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
6240 continue;
6241 }
6242
6243 ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL) ||
6244 (chan == SDPCM_TEST_CHANNEL) || (chan == SDPCM_GLOM_CHANNEL));
6245
6246 /* Length to read */
6247 rdlen = (len > firstread) ? (len - firstread) : 0;
6248
6249 /* May pad read to blocksize for efficiency */
6250 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
6251 pad = bus->blocksize - (rdlen % bus->blocksize);
6252 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
6253 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
6254 rdlen += pad;
6255 } else if (rdlen % DHD_SDALIGN) {
6256 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
6257 }
6258
6259 /* Satisfy length-alignment requirements */
6260 if (forcealign && (rdlen & (ALIGNMENT - 1)))
6261 rdlen = ROUNDUP(rdlen, ALIGNMENT);
6262
6263 if ((rdlen + firstread) > MAX_RX_DATASZ) {
6264 /* Too long -- skip this frame */
6265 DHD_ERROR(("%s: too long: len %d rdlen %d\n", __FUNCTION__, len, rdlen));
6266 bus->dhd->rx_errors++; bus->rx_toolong++;
6267 dhdsdio_rxfail(bus, FALSE, FALSE);
6268 continue;
6269 }
6270
6271 dhd_os_sdlock_rxq(bus->dhd);
6272 if (!(pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE))) {
6273 /* Give up on data, request rtx of events */
6274 DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
6275 __FUNCTION__, rdlen, chan));
6276 bus->dhd->rx_dropped++;
6277 dhd_os_sdunlock_rxq(bus->dhd);
6278 dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan));
6279 continue;
6280 }
6281 dhd_os_sdunlock_rxq(bus->dhd);
6282
6283 ASSERT(!PKTLINK(pkt));
6284
6285 /* Leave room for what we already read, and align remainder */
6286 ASSERT(firstread < (PKTLEN(osh, pkt)));
6287 PKTPULL(osh, pkt, firstread);
6288 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
6289
6290 /* Read the remaining frame data */
6291 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
6292 ((uint8 *)PKTDATA(osh, pkt)), rdlen, pkt, NULL, NULL);
6293 bus->f2rxdata++;
6294 ASSERT(sdret != BCME_PENDING);
6295
6296 if (sdret < 0) {
6297 DHD_ERROR(("%s: read %d %s bytes failed: %d\n", __FUNCTION__, rdlen,
6298 ((chan == SDPCM_EVENT_CHANNEL) ? "event" :
6299 ((chan == SDPCM_DATA_CHANNEL) ? "data" : "test")), sdret));
6300 dhd_os_sdlock_rxq(bus->dhd);
6301 PKTFREE(bus->dhd->osh, pkt, FALSE);
6302 dhd_os_sdunlock_rxq(bus->dhd);
6303 bus->dhd->rx_errors++;
6304 dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan));
6305 continue;
6306 }
6307
6308 /* Copy the already-read portion */
6309 PKTPUSH(osh, pkt, firstread);
6310 bcopy(bus->rxhdr, PKTDATA(osh, pkt), firstread);
6311
6312#ifdef DHD_DEBUG
6313 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
6314 prhex("Rx Data", PKTDATA(osh, pkt), len);
6315 }
6316#endif
6317
6318deliver:
6319 /* Save superframe descriptor and allocate packet frame */
6320 if (chan == SDPCM_GLOM_CHANNEL) {
6321 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
6322 DHD_GLOM(("%s: got glom descriptor, %d bytes:\n",
6323 __FUNCTION__, len));
6324#ifdef DHD_DEBUG
6325 if (DHD_GLOM_ON()) {
6326 prhex("Glom Data", PKTDATA(osh, pkt), len);
6327 }
6328#endif
6329 PKTSETLEN(osh, pkt, len);
6330 ASSERT(doff == SDPCM_HDRLEN);
6331 PKTPULL(osh, pkt, SDPCM_HDRLEN);
6332 bus->glomd = pkt;
6333 } else {
6334 DHD_ERROR(("%s: glom superframe w/o descriptor!\n", __FUNCTION__));
6335 dhdsdio_rxfail(bus, FALSE, FALSE);
6336 }
6337 continue;
6338 }
6339
6340 /* Fill in packet len and prio, deliver upward */
6341 PKTSETLEN(osh, pkt, len);
6342 PKTPULL(osh, pkt, doff);
6343
6344#ifdef SDTEST
6345 /* Test channel packets are processed separately */
6346 if (chan == SDPCM_TEST_CHANNEL) {
6347 dhdsdio_testrcv(bus, pkt, seq);
6348 continue;
6349 }
6350#endif /* SDTEST */
6351
6352 if (PKTLEN(osh, pkt) == 0) {
6353 dhd_os_sdlock_rxq(bus->dhd);
6354 PKTFREE(bus->dhd->osh, pkt, FALSE);
6355 dhd_os_sdunlock_rxq(bus->dhd);
6356 continue;
6357 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt, reorder_info_buf,
6358 &reorder_info_len) != 0) {
6359 DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
6360 dhd_os_sdlock_rxq(bus->dhd);
6361 PKTFREE(bus->dhd->osh, pkt, FALSE);
6362 dhd_os_sdunlock_rxq(bus->dhd);
6363 bus->dhd->rx_errors++;
6364 continue;
6365 }
6366
6367 if (reorder_info_len) {
6368 /* Reordering info from the firmware */
6369 dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf, reorder_info_len,
6370 &pkt, &pkt_count);
6371 if (pkt_count == 0)
6372 continue;
6373 } else {
6374 pkt_count = 1;
6375 }
6376
6377 /* Unlock during rx call */
6378 dhd_os_sdunlock(bus->dhd);
6379 dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, chan);
6380 dhd_os_sdlock(bus->dhd);
6381#if defined(SDIO_ISR_THREAD)
6382 /* terence 20150615: fix for below error due to bussleep in watchdog after dhd_os_sdunlock here,
6383 * so call BUS_WAKE to wake up bus again
6384 * dhd_bcmsdh_recv_buf: Device asleep
6385 * dhdsdio_readframes: RXHEADER FAILED: -40
6386 * dhdsdio_rxfail: abort command, terminate frame, send NAK
6387 */
6388 BUS_WAKE(bus);
6389#endif
6390 }
6391 rxcount = maxframes - rxleft;
6392#ifdef DHD_DEBUG
6393 /* Message if we hit the limit */
6394 if (!rxleft && !sdtest)
6395 DHD_DATA(("%s: hit rx limit of %d frames\n", __FUNCTION__, maxframes));
6396 else
6397#endif /* DHD_DEBUG */
6398 DHD_DATA(("%s: processed %d frames\n", __FUNCTION__, rxcount));
6399 /* Back off rxseq if awaiting rtx, update rx_seq */
6400 if (bus->rxskip)
6401 rxseq--;
6402 bus->rx_seq = rxseq;
6403
6404 if (bus->reqbussleep)
6405 {
6406 dhdsdio_bussleep(bus, TRUE);
6407 bus->reqbussleep = FALSE;
6408 }
6409 bus->readframes = FALSE;
6410
6411 return rxcount;
6412}
6413
6414static uint32
6415dhdsdio_hostmail(dhd_bus_t *bus, uint32 *hmbd)
6416{
6417 sdpcmd_regs_t *regs = bus->regs;
6418 uint32 intstatus = 0;
6419 uint32 hmb_data;
6420 uint8 fcbits;
6421 uint retries = 0;
6422
6423 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
6424
6425 /* Read mailbox data and ack that we did so */
6426 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
6427 if (retries <= retry_limit)
6428 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
6429 bus->f1regdata += 2;
6430
6431 /* Dongle recomposed rx frames, accept them again */
6432 if (hmb_data & HMB_DATA_NAKHANDLED) {
6433 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n", bus->rx_seq));
6434 if (!bus->rxskip) {
6435 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __FUNCTION__));
6436 }
6437 bus->rxskip = FALSE;
6438 intstatus |= FRAME_AVAIL_MASK(bus);
6439 }
6440
6441 /*
6442 * DEVREADY does not occur with gSPI.
6443 */
6444 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
6445 bus->sdpcm_ver = (hmb_data & HMB_DATA_VERSION_MASK) >> HMB_DATA_VERSION_SHIFT;
6446 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
6447 DHD_ERROR(("Version mismatch, dongle reports %d, expecting %d\n",
6448 bus->sdpcm_ver, SDPCM_PROT_VERSION));
6449 else
6450 DHD_INFO(("Dongle ready, protocol version %d\n", bus->sdpcm_ver));
6451 /* make sure for the SDIO_DEVICE_RXDATAINT_MODE_1 corecontrol is proper */
6452 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
6453 (bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_1)) {
6454 uint32 val;
6455
6456 val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
6457 val &= ~CC_XMTDATAAVAIL_MODE;
6458 val |= CC_XMTDATAAVAIL_CTRL;
6459 W_REG(bus->dhd->osh, &bus->regs->corecontrol, val);
6460
6461 val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
6462 }
6463
6464#ifdef DHD_DEBUG
6465 /* Retrieve console state address now that firmware should have updated it */
6466 {
6467 sdpcm_shared_t shared;
6468 if (dhdsdio_readshared(bus, &shared) == 0)
6469 bus->console_addr = shared.console_addr;
6470 }
6471#endif /* DHD_DEBUG */
6472 }
6473
6474 /*
6475 * Flow Control has been moved into the RX headers and this out of band
6476 * method isn't used any more. Leave this here for possibly remaining backward
6477 * compatible with older dongles
6478 */
6479 if (hmb_data & HMB_DATA_FC) {
6480 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
6481
6482 if (fcbits & ~bus->flowcontrol)
6483 bus->fc_xoff++;
6484 if (bus->flowcontrol & ~fcbits)
6485 bus->fc_xon++;
6486
6487 bus->fc_rcvd++;
6488 bus->flowcontrol = fcbits;
6489 }
6490
6491 /* At least print a message if FW halted */
6492 if (hmb_data & HMB_DATA_FWHALT) {
6493 DHD_ERROR(("INTERNAL ERROR: FIRMWARE HALTED : set BUS DOWN\n"));
6494 dhdsdio_checkdied(bus, NULL, 0);
6495 bus->dhd->busstate = DHD_BUS_DOWN;
6496 }
6497
6498 /* Shouldn't be any others */
6499 if (hmb_data & ~(HMB_DATA_DEVREADY |
6500 HMB_DATA_FWHALT |
6501 HMB_DATA_NAKHANDLED |
6502 HMB_DATA_FC |
6503 HMB_DATA_FWREADY |
6504 HMB_DATA_FCDATA_MASK |
6505 HMB_DATA_VERSION_MASK)) {
6506 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
6507 }
6508
6509 if (hmbd) {
6510 *hmbd = hmb_data;
6511 }
6512
6513 return intstatus;
6514}
6515
6516static bool
6517dhdsdio_dpc(dhd_bus_t *bus)
6518{
6519 bcmsdh_info_t *sdh = bus->sdh;
6520 sdpcmd_regs_t *regs = bus->regs;
6521 uint32 intstatus, newstatus = 0;
6522 uint retries = 0;
6523 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
6524 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
6525 uint framecnt = 0; /* Temporary counter of tx/rx frames */
6526 bool rxdone = TRUE; /* Flag for no more read data */
6527 bool resched = FALSE; /* Flag indicating resched wanted */
6528 unsigned long flags;
6529#ifdef DEBUG_DPC_THREAD_WATCHDOG
6530 bool is_resched_by_readframe = FALSE;
6531#endif /* DEBUG_DPC_THREAD_WATCHDOG */
6532 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
6533
6534 dhd_os_sdlock(bus->dhd);
6535 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
6536 if (bus->dhd->busstate == DHD_BUS_DOWN) {
6537 DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__));
6538 bus->intstatus = 0;
6539 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
6540 dhd_os_sdunlock(bus->dhd);
6541 return 0;
6542 }
6543
6544 DHD_BUS_BUSY_SET_IN_DPC(bus->dhd);
6545 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
6546
6547 /* Start with leftover status bits */
6548 intstatus = bus->intstatus;
6549
6550 if (!SLPAUTO_ENAB(bus) && !KSO_ENAB(bus)) {
6551 DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
6552 goto exit;
6553 }
6554
6555 /* If waiting for HTAVAIL, check status */
6556 if (!SLPAUTO_ENAB(bus) && (bus->clkstate == CLK_PENDING)) {
6557 int err;
6558 uint8 clkctl, devctl = 0;
6559
6560#ifdef DHD_DEBUG
6561 /* Check for inconsistent device control */
6562 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
6563 if (err) {
6564 DHD_ERROR(("%s: error reading DEVCTL: %d\n", __FUNCTION__, err));
6565 bus->dhd->busstate = DHD_BUS_DOWN;
6566 } else {
6567 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
6568 }
6569#endif /* DHD_DEBUG */
6570
6571 /* Read CSR, if clock on switch to AVAIL, else ignore */
6572 clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
6573 if (err) {
6574 DHD_ERROR(("%s: error reading CSR: %d\n", __FUNCTION__, err));
6575 bus->dhd->busstate = DHD_BUS_DOWN;
6576 }
6577
6578 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl, clkctl));
6579
6580 if (SBSDIO_HTAV(clkctl)) {
6581 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
6582 if (err) {
6583 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
6584 __FUNCTION__, err));
6585 bus->dhd->busstate = DHD_BUS_DOWN;
6586 }
6587 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
6588 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
6589 if (err) {
6590 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
6591 __FUNCTION__, err));
6592 bus->dhd->busstate = DHD_BUS_DOWN;
6593 }
6594 bus->clkstate = CLK_AVAIL;
6595 } else {
6596 goto clkwait;
6597 }
6598 }
6599
6600 BUS_WAKE(bus);
6601
6602 /* Make sure backplane clock is on */
6603 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
6604 if (bus->clkstate != CLK_AVAIL)
6605 goto clkwait;
6606
6607 /* Pending interrupt indicates new device status */
6608 if (bus->ipend) {
6609 bus->ipend = FALSE;
6610#if defined(BT_OVER_SDIO)
6611 bcmsdh_btsdio_process_f3_intr();
6612#endif /* defined (BT_OVER_SDIO) */
6613
6614 R_SDREG(newstatus, &regs->intstatus, retries);
6615 bus->f1regdata++;
6616 if (bcmsdh_regfail(bus->sdh))
6617 newstatus = 0;
6618 newstatus &= bus->hostintmask;
6619 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
6620 if (newstatus) {
6621 bus->f1regdata++;
6622 if ((bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_0) &&
6623 (newstatus == I_XMTDATA_AVAIL)) {
6624 } else
6625 W_SDREG(newstatus, &regs->intstatus, retries);
6626 }
6627 }
6628
6629 /* Merge new bits with previous */
6630 intstatus |= newstatus;
6631 bus->intstatus = 0;
6632
6633 /* Handle flow-control change: read new state in case our ack
6634 * crossed another change interrupt. If change still set, assume
6635 * FC ON for safety, let next loop through do the debounce.
6636 */
6637 if (intstatus & I_HMB_FC_CHANGE) {
6638 intstatus &= ~I_HMB_FC_CHANGE;
6639 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
6640 R_SDREG(newstatus, &regs->intstatus, retries);
6641 bus->f1regdata += 2;
6642 bus->fcstate = !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
6643 intstatus |= (newstatus & bus->hostintmask);
6644 }
6645
6646 /* Handle host mailbox indication */
6647 if (intstatus & I_HMB_HOST_INT) {
6648 uint32 hmbdata = 0;
6649
6650 intstatus &= ~I_HMB_HOST_INT;
6651 intstatus |= dhdsdio_hostmail(bus, &hmbdata);
6652
6653#ifdef DHD_ULP
6654 /* ULP prototyping. Redowload fw on oob interupt */
6655
6656 /* all the writes after this point CAN use cached sbwad value */
6657 bcmsdh_force_sbwad_calc(bus->sdh, FALSE);
6658
6659 if (dhd_ulp_pre_redownload_check(bus->dhd, bus->sdh, hmbdata)) {
6660 if (dhd_bus_ulp_reinit_fw(bus) < 0) {
6661 DHD_ERROR(("%s:%d FW redownload failed\n",
6662 __FUNCTION__, __LINE__));
6663 goto exit;
6664 }
6665 }
6666#endif
6667
6668 }
6669
6670 /* Just being here means nothing more to do for chipactive */
6671 if (intstatus & I_CHIPACTIVE) {
6672 /* ASSERT(bus->clkstate == CLK_AVAIL); */
6673 intstatus &= ~I_CHIPACTIVE;
6674 }
6675
6676 /* Handle host mailbox indication */
6677 if (intstatus & I_HMB_HOST_INT) {
6678 intstatus &= ~I_HMB_HOST_INT;
6679 intstatus |= dhdsdio_hostmail(bus, NULL);
6680 }
6681
6682 /* Generally don't ask for these, can get CRC errors... */
6683 if (intstatus & I_WR_OOSYNC) {
6684 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
6685 intstatus &= ~I_WR_OOSYNC;
6686 }
6687
6688 if (intstatus & I_RD_OOSYNC) {
6689 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
6690 intstatus &= ~I_RD_OOSYNC;
6691 }
6692
6693 if (intstatus & I_SBINT) {
6694 DHD_ERROR(("Dongle reports SBINT\n"));
6695 intstatus &= ~I_SBINT;
6696 }
6697
6698 /* Would be active due to wake-wlan in gSPI */
6699 if (intstatus & I_CHIPACTIVE) {
6700 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
6701 intstatus &= ~I_CHIPACTIVE;
6702 }
6703
6704 if (intstatus & I_HMB_FC_STATE) {
6705 DHD_INFO(("Dongle reports HMB_FC_STATE\n"));
6706 intstatus &= ~I_HMB_FC_STATE;
6707 }
6708
6709 /* Ignore frame indications if rxskip is set */
6710 if (bus->rxskip) {
6711 intstatus &= ~FRAME_AVAIL_MASK(bus);
6712 }
6713
6714 /* On frame indication, read available frames */
6715 if (PKT_AVAILABLE(bus, intstatus)) {
6716
6717 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
6718 if (rxdone || bus->rxskip)
6719 intstatus &= ~FRAME_AVAIL_MASK(bus);
6720 rxlimit -= MIN(framecnt, rxlimit);
6721 }
6722
6723 /* Keep still-pending events for next scheduling */
6724 bus->intstatus = intstatus;
6725
6726clkwait:
6727 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
6728 * or clock availability. (Allows tx loop to check ipend if desired.)
6729 * (Unless register access seems hosed, as we may not be able to ACK...)
6730 */
6731 if (!bus->dhd->conf->oob_enabled_later && bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
6732 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
6733 __FUNCTION__, rxdone, framecnt));
6734 bus->intdis = FALSE;
6735#if defined(OOB_INTR_ONLY)
6736 bcmsdh_oob_intr_set(bus->sdh, TRUE);
6737#endif /* defined(OOB_INTR_ONLY) */
6738 bcmsdh_intr_enable(sdh);
6739 }
6740
6741#if defined(OOB_INTR_ONLY) && !defined(HW_OOB)
6742 /* In case of SW-OOB(using edge trigger),
6743 * Check interrupt status in the dongle again after enable irq on the host.
6744 * and rechedule dpc if interrupt is pended in the dongle.
6745 * There is a chance to miss OOB interrupt while irq is disabled on the host.
6746 * No need to do this with HW-OOB(level trigger)
6747 */
6748 R_SDREG(newstatus, &regs->intstatus, retries);
6749 if (bcmsdh_regfail(bus->sdh))
6750 newstatus = 0;
6751 if (newstatus & bus->hostintmask) {
6752 bus->ipend = TRUE;
6753 resched = TRUE;
6754 }
6755#endif /* defined(OOB_INTR_ONLY) && !defined(HW_OOB) */
6756
6757#ifdef PROP_TXSTATUS
6758 dhd_wlfc_commit_packets(bus->dhd, (f_commitpkt_t)dhd_bus_txdata, (void *)bus, NULL, FALSE);
6759#endif
6760
6761 if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL))
6762 dhdsdio_sendpendctl(bus);
6763
6764 /* Send queued frames (limit 1 if rx may still be pending) */
6765 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
6766 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && DATAOK(bus)) {
6767
6768#ifdef DHD_ULP
6769 if (dhd_ulp_f2_ready(bus->dhd, bus->sdh)) {
6770#endif /* DHD_ULP */
6771 if (bus->dhd->conf->dhd_txminmax < 0)
6772 framecnt = rxdone ? txlimit : MIN(txlimit, DATABUFCNT(bus));
6773 else
6774 framecnt = rxdone ? txlimit : MIN(txlimit, bus->dhd->conf->dhd_txminmax);
6775 framecnt = dhdsdio_sendfromq(bus, framecnt);
6776 txlimit -= framecnt;
6777#ifdef DHD_ULP
6778 } else {
6779 /* In other transient states like DHD_ULP_, after the states are
6780 * DHD_ULP_F2ENAB_CLEARING and DHD_ULP_F2ENAB_SETTING,
6781 * dpc is scheduled after steady-state and dhdsdio_sendfromq() will
6782 * execute again
6783 */
6784 }
6785#endif /* DHD_ULP */
6786 }
6787 /* Resched the DPC if ctrl cmd is pending on bus credit */
6788 if (bus->ctrl_frame_stat) {
ccd15baf 6789 if (bus->dhd->conf->txctl_tmo_fix > 0) {
010c3a89
RC		 6790 set_current_state(TASK_INTERRUPTIBLE);
6791 if (!kthread_should_stop())
6792 schedule_timeout(1);
6793 set_current_state(TASK_RUNNING);
6794 }
6795 resched = TRUE;
6796 }
6797
6798 /* Resched if events or tx frames are pending, else await next interrupt */
6799 /* On failed register access, all bets are off: no resched or interrupts */
6800 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
6801 if ((bus->sih && bus->sih->buscorerev >= 12) && !(dhdsdio_sleepcsr_get(bus) &
6802 SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
6803 /* Bus failed because of KSO */
6804 DHD_ERROR(("%s: Bus failed due to KSO\n", __FUNCTION__));
6805 bus->kso = FALSE;
6806 } else {
6807 DHD_ERROR(("%s: failed backplane access over SDIO, halting operation\n",
6808 __FUNCTION__));
6809 bus->dhd->busstate = DHD_BUS_DOWN;
6810 bus->intstatus = 0;
6811 }
6812 } else if (bus->clkstate == CLK_PENDING) {
6813 /* Awaiting I_CHIPACTIVE; don't resched */
6814 } else if (bus->intstatus || bus->ipend ||
6815 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) && DATAOK(bus)) ||
6816 PKT_AVAILABLE(bus, bus->intstatus)) { /* Read multiple frames */
6817 resched = TRUE;
6818 }
6819
6820 bus->dpc_sched = resched;
6821
6822 /* If we're done for now, turn off clock request. */
6823 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && (bus->clkstate != CLK_PENDING) &&
6824 NO_OTHER_ACTIVE_BUS_USER(bus)) {
6825 bus->activity = FALSE;
6826 dhdsdio_bussleep(bus, TRUE);
6827 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
6828 }
6829
6830exit:
6831
6832 if (!resched) {
6833 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
6834 * or clock availability. (Allows tx loop to check ipend if desired.)
6835 * (Unless register access seems hosed, as we may not be able to ACK...)
6836 */
6837 if (bus->dhd->conf->oob_enabled_later && bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
6838 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
6839 __FUNCTION__, rxdone, framecnt));
6840 bus->intdis = FALSE;
6841#if defined(OOB_INTR_ONLY)
6842 bcmsdh_oob_intr_set(bus->sdh, TRUE);
6843#endif /* defined(OOB_INTR_ONLY) */
6844 bcmsdh_intr_enable(sdh);
6845 }
6846 if (dhd_dpcpoll) {
6847 if (dhdsdio_readframes(bus, dhd_rxbound, &rxdone) != 0) {
6848 resched = TRUE;
6849#ifdef DEBUG_DPC_THREAD_WATCHDOG
6850 is_resched_by_readframe = TRUE;
6851#endif /* DEBUG_DPC_THREAD_WATCHDOG */
6852 }
6853 }
6854 }
6855
dfb0f3ae
RC		 6856 if (bus->ctrl_wait && TXCTLOK(bus))
6857 wake_up_interruptible(&bus->ctrl_tx_wait);
010c3a89
RC		 6858 dhd_os_sdunlock(bus->dhd);
6859#ifdef DEBUG_DPC_THREAD_WATCHDOG
6860 if (bus->dhd->dhd_bug_on) {
6861 DHD_INFO(("%s: resched = %d ctrl_frame_stat = %d intstatus 0x%08x"
6862 " ipend = %d pktq_mlen = %d is_resched_by_readframe = %d \n",
6863 __FUNCTION__, resched, bus->ctrl_frame_stat,
6864 bus->intstatus, bus->ipend,
6865 pktq_mlen(&bus->txq, ~bus->flowcontrol), is_resched_by_readframe));
6866
6867 bus->dhd->dhd_bug_on = FALSE;
6868 }
6869#endif /* DEBUG_DPC_THREAD_WATCHDOG */
6870
6871 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
6872 DHD_BUS_BUSY_CLEAR_IN_DPC(bus->dhd);
6873 dhd_os_busbusy_wake(bus->dhd);
6874 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
6875
6876 return resched;
6877}
6878
6879bool
6880dhd_bus_dpc(struct dhd_bus *bus)
6881{
6882 bool resched;
6883
6884 /* Call the DPC directly. */
6885 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
6886 resched = dhdsdio_dpc(bus);
6887
6888 return resched;
6889}
6890
6891void
6892dhdsdio_isr(void *arg)
6893{
6894 dhd_bus_t *bus = (dhd_bus_t*)arg;
6895 bcmsdh_info_t *sdh;
6896
6897 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
6898
6899 if (!bus) {
6900 DHD_ERROR(("%s : bus is null pointer , exit \n", __FUNCTION__));
6901 return;
6902 }
6903 sdh = bus->sdh;
6904
6905 if (bus->dhd->busstate == DHD_BUS_DOWN) {
6906 DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
6907 return;
6908 }
6909
6910 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
6911
6912 /* Count the interrupt call */
6913 bus->intrcount++;
6914 bus->ipend = TRUE;
6915
6916 /* Shouldn't get this interrupt if we're sleeping? */
6917 if (!SLPAUTO_ENAB(bus)) {
6918 if (bus->sleeping) {
6919 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
6920 return;
6921 } else if (!KSO_ENAB(bus)) {
6922 DHD_ERROR(("ISR in devsleep 1\n"));
6923 }
6924 }
6925
6926 /* Disable additional interrupts (is this needed now)? */
6927 if (bus->intr) {
6928 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
6929 } else {
6930 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
6931 }
6932
6933 bcmsdh_intr_disable(sdh);
6934 bus->intdis = TRUE;
6935
6936#if defined(SDIO_ISR_THREAD)
6937 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
6938 DHD_OS_WAKE_LOCK(bus->dhd);
6939 /* terence 20150209: dpc should be scheded again if dpc_sched is TRUE or dhd_bus_txdata can
6940 not schedule anymore because dpc_sched is TRUE now.
6941 */
6942 if (dhdsdio_dpc(bus)) {
6943 bus->dpc_sched = TRUE;
6944 dhd_sched_dpc(bus->dhd);
6945 }
6946 DHD_OS_WAKE_UNLOCK(bus->dhd);
6947#else
6948 bus->dpc_sched = TRUE;
6949 dhd_sched_dpc(bus->dhd);
6950#endif /* defined(SDIO_ISR_THREAD) */
6951
6952}
6953
6954#ifdef PKT_STATICS
6955void dhdsdio_txpktstatics(void)
6956{
6957 uint i, total = 0;
6958
6959 printf("%s: TYPE EVENT: %d pkts (size=%d) transfered\n",
6960 __FUNCTION__, tx_statics.event_count, tx_statics.event_size);
6961 printf("%s: TYPE CTRL: %d pkts (size=%d) transfered\n",
6962 __FUNCTION__, tx_statics.ctrl_count, tx_statics.ctrl_size);
6963 printf("%s: TYPE DATA: %d pkts (size=%d) transfered\n",
6964 __FUNCTION__, tx_statics.data_count, tx_statics.data_size);
6965 printf("%s: Glom size distribution:\n", __FUNCTION__);
6966 for (i=0;i<tx_statics.glom_max;i++) {
6967 total += tx_statics.glom_cnt[i];
6968 }
6969 for (i=0;i<tx_statics.glom_max;i++) {
6970 printf("%02d: %d", i+1, tx_statics.glom_cnt[i]);
6971 if ((i+1)%8)
6972 printf(", ");
6973 else
6974 printf("\n");
6975 }
6976 printf("\n");
6977 for (i=0;i<tx_statics.glom_max;i++) {
6978 printf("%02d:%3d%%", i+1, (tx_statics.glom_cnt[i]*100)/total);
6979 if ((i+1)%8)
6980 printf(", ");
6981 else
6982 printf("\n");
6983 }
6984 printf("\n");
6985 printf("%s: data/glom=%d, glom_max=%d\n",
6986 __FUNCTION__, tx_statics.data_count/total, tx_statics.glom_max);
6987 printf("%s: TYPE RX GLOM: %d pkts (size=%d) transfered\n",
6988 __FUNCTION__, tx_statics.glom_count, tx_statics.glom_size);
6989 printf("%s: TYPE TEST: %d pkts (size=%d) transfered\n\n\n",
6990 __FUNCTION__, tx_statics.test_count, tx_statics.test_size);
6991}
6992#endif
6993
6994#ifdef SDTEST
6995static void
6996dhdsdio_pktgen_init(dhd_bus_t *bus)
6997{
6998 /* Default to specified length, or full range */
6999 if (dhd_pktgen_len) {
7000 bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN);
7001 bus->pktgen_minlen = bus->pktgen_maxlen;
7002 } else {
7003 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
7004 bus->pktgen_minlen = 0;
7005 }
7006 bus->pktgen_len = (uint16)bus->pktgen_minlen;
7007
7008 /* Default to per-watchdog burst with 10s print time */
7009 bus->pktgen_freq = 1;
7010 bus->pktgen_print = dhd_watchdog_ms ? (10000 / dhd_watchdog_ms) : 0;
7011 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
7012
7013 /* Default to echo mode */
7014 bus->pktgen_mode = DHD_PKTGEN_ECHO;
7015 bus->pktgen_stop = 1;
7016}
7017
7018static void
7019dhdsdio_pktgen(dhd_bus_t *bus)
7020{
7021 void *pkt;
7022 uint8 *data;
7023 uint pktcount;
7024 uint fillbyte;
7025 osl_t *osh = bus->dhd->osh;
7026 uint16 len;
7027 ulong time_lapse;
7028 uint sent_pkts;
7029 uint rcvd_pkts;
7030
7031 /* Display current count if appropriate */
7032 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
7033 bus->pktgen_ptick = 0;
7034 printf("%s: send attempts %d, rcvd %d, errors %d\n",
7035 __FUNCTION__, bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
7036
7037 /* Print throughput stats only for constant length packet runs */
7038 if (bus->pktgen_minlen == bus->pktgen_maxlen) {
7039 time_lapse = jiffies - bus->pktgen_prev_time;
7040 bus->pktgen_prev_time = jiffies;
7041 sent_pkts = bus->pktgen_sent - bus->pktgen_prev_sent;
7042 bus->pktgen_prev_sent = bus->pktgen_sent;
7043 rcvd_pkts = bus->pktgen_rcvd - bus->pktgen_prev_rcvd;
7044 bus->pktgen_prev_rcvd = bus->pktgen_rcvd;
7045
7046 printf("%s: Tx Throughput %d kbps, Rx Throughput %d kbps\n",
7047 __FUNCTION__,
7048 (sent_pkts * bus->pktgen_len / jiffies_to_msecs(time_lapse)) * 8,
7049 (rcvd_pkts * bus->pktgen_len / jiffies_to_msecs(time_lapse)) * 8);
7050 }
7051 }
7052
7053 /* For recv mode, just make sure dongle has started sending */
7054 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
7055 if (bus->pktgen_rcv_state == PKTGEN_RCV_IDLE) {
7056 bus->pktgen_rcv_state = PKTGEN_RCV_ONGOING;
7057 dhdsdio_sdtest_set(bus, bus->pktgen_total);
7058 }
7059 return;
7060 }
7061
7062 /* Otherwise, generate or request the specified number of packets */
7063 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
7064 /* Stop if total has been reached */
7065 if (bus->pktgen_total && (bus->pktgen_sent >= bus->pktgen_total)) {
7066 bus->pktgen_count = 0;
7067 break;
7068 }
7069
7070 /* Allocate an appropriate-sized packet */
7071 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) {
7072 len = SDPCM_TEST_PKT_CNT_FLD_LEN;
7073 } else {
7074 len = bus->pktgen_len;
7075 }
7076 if (!(pkt = PKTGET(osh, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
7077 TRUE))) {;
7078 DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
7079 break;
7080 }
7081 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
7082 data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
7083
7084 /* Write test header cmd and extra based on mode */
7085 switch (bus->pktgen_mode) {
7086 case DHD_PKTGEN_ECHO:
7087 *data++ = SDPCM_TEST_ECHOREQ;
7088 *data++ = (uint8)bus->pktgen_sent;
7089 break;
7090
7091 case DHD_PKTGEN_SEND:
7092 *data++ = SDPCM_TEST_DISCARD;
7093 *data++ = (uint8)bus->pktgen_sent;
7094 break;
7095
7096 case DHD_PKTGEN_RXBURST:
7097 *data++ = SDPCM_TEST_BURST;
7098 *data++ = (uint8)bus->pktgen_count; /* Just for backward compatability */
7099 break;
7100
7101 default:
7102 DHD_ERROR(("Unrecognized pktgen mode %d\n", bus->pktgen_mode));
7103 PKTFREE(osh, pkt, TRUE);
7104 bus->pktgen_count = 0;
7105 return;
7106 }
7107
7108 /* Write test header length field */
7109 *data++ = (bus->pktgen_len >> 0);
7110 *data++ = (bus->pktgen_len >> 8);
7111
7112 /* Write frame count in a 4 byte field adjucent to SDPCM test header for
7113 * burst mode
7114 */
7115 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) {
7116 *data++ = (uint8)(bus->pktgen_count >> 0);
7117 *data++ = (uint8)(bus->pktgen_count >> 8);
7118 *data++ = (uint8)(bus->pktgen_count >> 16);
7119 *data++ = (uint8)(bus->pktgen_count >> 24);
7120 } else {
7121
7122 /* Then fill in the remainder -- N/A for burst */
7123 for (fillbyte = 0; fillbyte < len; fillbyte++)
7124 *data++ = SDPCM_TEST_FILL(fillbyte, (uint8)bus->pktgen_sent);
7125 }
7126
7127#ifdef DHD_DEBUG
7128 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
7129 data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
7130 prhex("dhdsdio_pktgen: Tx Data", data, PKTLEN(osh, pkt) - SDPCM_HDRLEN);
7131 }
7132#endif
7133
7134 /* Send it */
7135 if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK) {
7136 bus->pktgen_fail++;
7137 if (bus->pktgen_stop && bus->pktgen_stop == bus->pktgen_fail)
7138 bus->pktgen_count = 0;
7139 }
7140 bus->pktgen_sent++;
7141
7142 /* Bump length if not fixed, wrap at max */
7143 if (++bus->pktgen_len > bus->pktgen_maxlen)
7144 bus->pktgen_len = (uint16)bus->pktgen_minlen;
7145
7146 /* Special case for burst mode: just send one request! */
7147 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
7148 break;
7149 }
7150}
7151
7152static void
7153dhdsdio_sdtest_set(dhd_bus_t *bus, uint count)
7154{
7155 void *pkt;
7156 uint8 *data;
7157 osl_t *osh = bus->dhd->osh;
7158
7159 /* Allocate the packet */
7160 if (!(pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
7161 SDPCM_TEST_PKT_CNT_FLD_LEN + DHD_SDALIGN, TRUE))) {
7162 DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
7163 return;
7164 }
7165 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
7166 SDPCM_TEST_PKT_CNT_FLD_LEN), DHD_SDALIGN);
7167 data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
7168
7169 /* Fill in the test header */
7170 *data++ = SDPCM_TEST_SEND;
7171 *data++ = (count > 0)?TRUE:FALSE;
7172 *data++ = (bus->pktgen_maxlen >> 0);
7173 *data++ = (bus->pktgen_maxlen >> 8);
7174 *data++ = (uint8)(count >> 0);
7175 *data++ = (uint8)(count >> 8);
7176 *data++ = (uint8)(count >> 16);
7177 *data++ = (uint8)(count >> 24);
7178
7179 /* Send it */
7180 if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK)
7181 bus->pktgen_fail++;
7182}
7183
7184
7185static void
7186dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
7187{
7188 osl_t *osh = bus->dhd->osh;
7189 uint8 *data;
7190 uint pktlen;
7191
7192 uint8 cmd;
7193 uint8 extra;
7194 uint16 len;
7195 uint16 offset;
7196
7197 /* Check for min length */
7198 if ((pktlen = PKTLEN(osh, pkt)) < SDPCM_TEST_HDRLEN) {
7199 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n", pktlen));
7200 PKTFREE(osh, pkt, FALSE);
7201 return;
7202 }
7203
7204 /* Extract header fields */
7205 data = PKTDATA(osh, pkt);
7206 cmd = *data++;
7207 extra = *data++;
7208 len = *data++; len += *data++ << 8;
7209 DHD_TRACE(("%s:cmd:%d, xtra:%d,len:%d\n", __FUNCTION__, cmd, extra, len));
7210 /* Check length for relevant commands */
7211 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ || cmd == SDPCM_TEST_ECHORSP) {
7212 if (pktlen != len + SDPCM_TEST_HDRLEN) {
7213 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, pktlen %d seq %d"
7214 " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
7215 PKTFREE(osh, pkt, FALSE);
7216 return;
7217 }
7218 }
7219
7220 /* Process as per command */
7221 switch (cmd) {
7222 case SDPCM_TEST_ECHOREQ:
7223 /* Rx->Tx turnaround ok (even on NDIS w/current implementation) */
7224 *(uint8 *)(PKTDATA(osh, pkt)) = SDPCM_TEST_ECHORSP;
7225 if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) == BCME_OK) {
7226 bus->pktgen_sent++;
7227 } else {
7228 bus->pktgen_fail++;
7229 PKTFREE(osh, pkt, FALSE);
7230 }
7231 bus->pktgen_rcvd++;
7232 break;
7233
7234 case SDPCM_TEST_ECHORSP:
7235 if (bus->ext_loop) {
7236 PKTFREE(osh, pkt, FALSE);
7237 bus->pktgen_rcvd++;
7238 break;
7239 }
7240
7241 for (offset = 0; offset < len; offset++, data++) {
7242 if (*data != SDPCM_TEST_FILL(offset, extra)) {
7243 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: "
7244 "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
7245 offset, len, SDPCM_TEST_FILL(offset, extra), *data));
7246 break;
7247 }
7248 }
7249 PKTFREE(osh, pkt, FALSE);
7250 bus->pktgen_rcvd++;
7251 break;
7252
7253 case SDPCM_TEST_DISCARD:
7254 {
7255 int i = 0;
7256 uint8 *prn = data;
7257 uint8 testval = extra;
7258 for (i = 0; i < len; i++) {
7259 if (*prn != testval) {
7260 DHD_ERROR(("DIErr@Pkt#:%d,Ix:%d, expected:0x%x, got:0x%x\n",
7261 i, bus->pktgen_rcvd_rcvsession, testval, *prn));
7262 prn++; testval++;
7263 }
7264 }
7265 }
7266 PKTFREE(osh, pkt, FALSE);
7267 bus->pktgen_rcvd++;
7268 break;
7269
7270 case SDPCM_TEST_BURST:
7271 case SDPCM_TEST_SEND:
7272 default:
7273 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, pktlen %d seq %d"
7274 " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
7275 PKTFREE(osh, pkt, FALSE);
7276 break;
7277 }
7278
7279 /* For recv mode, stop at limit (and tell dongle to stop sending) */
7280 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
7281 if (bus->pktgen_rcv_state != PKTGEN_RCV_IDLE) {
7282 bus->pktgen_rcvd_rcvsession++;
7283
7284 if (bus->pktgen_total &&
7285 (bus->pktgen_rcvd_rcvsession >= bus->pktgen_total)) {
7286 bus->pktgen_count = 0;
7287 DHD_ERROR(("Pktgen:rcv test complete!\n"));
7288 bus->pktgen_rcv_state = PKTGEN_RCV_IDLE;
7289 dhdsdio_sdtest_set(bus, FALSE);
7290 bus->pktgen_rcvd_rcvsession = 0;
7291 }
7292 }
7293 }
7294}
7295#endif /* SDTEST */
7296
7297int dhd_bus_oob_intr_register(dhd_pub_t *dhdp)
7298{
7299 int err = 0;
7300
7301#if defined(OOB_INTR_ONLY)
7302 err = bcmsdh_oob_intr_register(dhdp->bus->sdh, dhdsdio_isr, dhdp->bus);
7303#endif
7304 return err;
7305}
7306
7307void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp)
7308{
7309#if defined(OOB_INTR_ONLY)
7310 bcmsdh_oob_intr_unregister(dhdp->bus->sdh);
7311#endif
7312}
7313
7314void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable)
7315{
7316#if defined(OOB_INTR_ONLY)
7317 bcmsdh_oob_intr_set(dhdp->bus->sdh, enable);
7318#endif
7319}
7320
7321void dhd_bus_dev_pm_stay_awake(dhd_pub_t *dhdpub)
7322{
7323 bcmsdh_dev_pm_stay_awake(dhdpub->bus->sdh);
7324}
7325
7326void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub)
7327{
7328 bcmsdh_dev_relax(dhdpub->bus->sdh);
7329}
7330
7331bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub)
7332{
7333 bool enabled = FALSE;
7334
7335 enabled = bcmsdh_dev_pm_enabled(dhdpub->bus->sdh);
7336 return enabled;
7337}
7338
7339extern bool
7340dhd_bus_watchdog(dhd_pub_t *dhdp)
7341{
7342 dhd_bus_t *bus;
7343 unsigned long flags;
7344
7345 DHD_TIMER(("%s: Enter\n", __FUNCTION__));
7346
7347 bus = dhdp->bus;
7348
7349 if (bus->dhd->dongle_reset)
7350 return FALSE;
7351
7352 if (bus->dhd->hang_was_sent) {
7353 dhd_os_wd_timer(bus->dhd, 0);
7354 return FALSE;
7355 }
7356
7357 /* Ignore the timer if simulating bus down */
7358 if (!SLPAUTO_ENAB(bus) && bus->sleeping)
7359 return FALSE;
7360
7361 DHD_LINUX_GENERAL_LOCK(dhdp, flags);
7362 if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhdp) ||
7363 DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp)) {
7364 DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
7365 return FALSE;
7366 }
7367 DHD_BUS_BUSY_SET_IN_WD(dhdp);
7368 DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
7369
7370 dhd_os_sdlock(bus->dhd);
7371
7372 /* Poll period: check device if appropriate. */
7373 // terence 20160615: remove !SLPAUTO_ENAB(bus) to fix not able to polling if sr supported
7374 if (1 && (bus->poll && (++bus->polltick >= bus->pollrate))) {
7375 uint32 intstatus = 0;
7376
7377 /* Reset poll tick */
7378 bus->polltick = 0;
7379
7380 /* Check device if no interrupts */
7381 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
7382
7383 if (!bus->dpc_sched) {
7384 uint8 devpend;
7385 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
7386 SDIOD_CCCR_INTPEND, NULL);
7387 intstatus = devpend & (INTR_STATUS_FUNC1 | INTR_STATUS_FUNC2);
7388 }
7389
7390 /* If there is something, make like the ISR and schedule the DPC */
7391 if (intstatus) {
7392 bus->pollcnt++;
7393 bus->ipend = TRUE;
7394 if (bus->intr) {
7395 bcmsdh_intr_disable(bus->sdh);
7396 }
7397 bus->dpc_sched = TRUE;
7398 dhd_sched_dpc(bus->dhd);
7399 }
7400 }
7401
7402 /* Update interrupt tracking */
7403 bus->lastintrs = bus->intrcount;
7404 }
7405
7406 if ((!bus->dpc_sched) && pktq_len(&bus->txq)) {
7407 bus->dpc_sched = TRUE;
7408 dhd_sched_dpc(bus->dhd);
7409 }
7410
7411#ifdef DHD_DEBUG
7412 /* Poll for console output periodically */
7413 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
7414 bus->console.count += dhd_watchdog_ms;
7415 if (bus->console.count >= dhd_console_ms) {
7416 bus->console.count -= dhd_console_ms;
7417 /* Make sure backplane clock is on */
7418 if (SLPAUTO_ENAB(bus))
7419 dhdsdio_bussleep(bus, FALSE);
7420 else
7421 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
7422 if (dhdsdio_readconsole(bus) < 0)
7423 dhd_console_ms = 0; /* On error, stop trying */
7424 }
7425 }
7426#endif /* DHD_DEBUG */
7427
7428#ifdef SDTEST
7429 /* Generate packets if configured */
7430 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
7431 /* Make sure backplane clock is on */
7432 if (SLPAUTO_ENAB(bus))
7433 dhdsdio_bussleep(bus, FALSE);
7434 else
7435 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
7436 bus->pktgen_tick = 0;
7437 dhdsdio_pktgen(bus);
7438 }
7439#endif
7440
7441 /* On idle timeout clear activity flag and/or turn off clock */
7442#ifdef DHD_USE_IDLECOUNT
7443 if (bus->activity)
7444 bus->activity = FALSE;
7445 else {
7446 bus->idlecount++;
7447
7448 /*
7449 * If the condition to switch off the clock is reached And if
7450 * BT is inactive (in case of BT_OVER_SDIO build) turn off clk.
7451 *
7452 * Consider the following case, DHD is configured with
7453 * 1) idletime == DHD_IDLE_IMMEDIATE
7454 * 2) BT is the last user of the clock
7455 * We cannot disable the clock from __dhdsdio_clk_disable
7456 * since WLAN might be using it. If WLAN is active then
7457 * from the respective function/context after doing the job
7458 * the clk is turned off.
7459 * But if WLAN is actually inactive then the watchdog should
7460 * disable the clock. So the condition check below should be
7461 * bus->idletime != 0 instead of idletime == 0
7462 */
7463 if ((bus->idletime != 0) && (bus->idlecount >= bus->idletime) &&
7464 NO_OTHER_ACTIVE_BUS_USER(bus)) {
7465 DHD_TIMER(("%s: DHD Idle state!!\n", __FUNCTION__));
7466 if (!bus->poll && SLPAUTO_ENAB(bus)) {
7467 if (dhdsdio_bussleep(bus, TRUE) != BCME_BUSY)
7468 dhd_os_wd_timer(bus->dhd, 0);
7469 } else
7470 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
7471
7472 bus->idlecount = 0;
7473 }
7474 }
7475#else
7476 if ((bus->idletime != 0) && (bus->clkstate == CLK_AVAIL) &&
7477 NO_OTHER_ACTIVE_BUS_USER(bus)) {
7478 if (++bus->idlecount >= bus->idletime) {
7479 bus->idlecount = 0;
7480 if (bus->activity) {
7481 bus->activity = FALSE;
7482 if (!bus->poll && SLPAUTO_ENAB(bus)) {
7483 if (!bus->readframes)
7484 dhdsdio_bussleep(bus, TRUE);
7485 else
7486 bus->reqbussleep = TRUE;
7487 } else {
7488 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
7489 }
7490 }
7491 }
7492 }
7493#endif /* DHD_USE_IDLECOUNT */
7494
7495 dhd_os_sdunlock(bus->dhd);
7496
7497 DHD_LINUX_GENERAL_LOCK(dhdp, flags);
7498 DHD_BUS_BUSY_CLEAR_IN_WD(dhdp);
7499 dhd_os_busbusy_wake(dhdp);
7500 DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
7501
7502 return bus->ipend;
7503}
7504
7505extern int
7506dhd_bus_console_in(dhd_pub_t *dhdp, uchar *msg, uint msglen)
7507{
7508 dhd_bus_t *bus = dhdp->bus;
7509 uint32 addr, val;
7510 int rv;
7511 void *pkt;
7512
7513 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
7514 if (bus->console_addr == 0)
7515 return BCME_UNSUPPORTED;
7516
7517 /* Exclusive bus access */
7518 dhd_os_sdlock(bus->dhd);
7519
7520 /* Don't allow input if dongle is in reset */
7521 if (bus->dhd->dongle_reset) {
7522 dhd_os_sdunlock(bus->dhd);
7523 return BCME_NOTREADY;
7524 }
7525
7526 /* Request clock to allow SDIO accesses */
7527 BUS_WAKE(bus);
7528 /* No pend allowed since txpkt is called later, ht clk has to be on */
7529 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
7530
7531 /* Zero cbuf_index */
7532 addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx);
7533 val = htol32(0);
7534 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
7535 goto done;
7536
7537 /* Write message into cbuf */
7538 addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf);
7539 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
7540 goto done;
7541
7542 /* Write length into vcons_in */
7543 addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in);
7544 val = htol32(msglen);
7545 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
7546 goto done;
7547
7548 /* Bump dongle by sending an empty packet on the event channel.
7549 * sdpcm_sendup (RX) checks for virtual console input.
7550 */
7551 if ((pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE)) != NULL)
7552 rv = dhdsdio_txpkt(bus, SDPCM_EVENT_CHANNEL, &pkt, 1, TRUE);
7553
7554done:
7555 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched &&
7556 NO_OTHER_ACTIVE_BUS_USER(bus)) {
7557 bus->activity = FALSE;
7558 dhdsdio_bussleep(bus, TRUE);
7559 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
7560 }
7561
7562 dhd_os_sdunlock(bus->dhd);
7563
7564 return rv;
7565}
7566
7567#ifdef DHD_DEBUG
7568static void
7569dhd_dump_cis(uint fn, uint8 *cis)
7570{
7571 uint byte, tag, tdata;
7572 DHD_INFO(("Function %d CIS:\n", fn));
7573
7574 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
7575 if ((byte % 16) == 0)
7576 DHD_INFO((" "));
7577 DHD_INFO(("%02x ", cis[byte]));
7578 if ((byte % 16) == 15)
7579 DHD_INFO(("\n"));
7580 if (!tdata--) {
7581 tag = cis[byte];
7582 if (tag == 0xff)
7583 break;
7584 else if (!tag)
7585 tdata = 0;
7586 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
7587 tdata = cis[byte + 1] + 1;
7588 else
7589 DHD_INFO(("]"));
7590 }
7591 }
7592 if ((byte % 16) != 15)
7593 DHD_INFO(("\n"));
7594}
7595#endif /* DHD_DEBUG */
7596
7597static bool
7598dhdsdio_chipmatch(uint16 chipid)
7599{
7600 if (chipid == BCM4336_CHIP_ID)
7601 return TRUE;
7602 if (chipid == BCM4330_CHIP_ID)
7603 return TRUE;
7604 if (chipid == BCM43237_CHIP_ID)
7605 return TRUE;
7606 if (chipid == BCM43362_CHIP_ID)
7607 return TRUE;
7608 if (chipid == BCM4314_CHIP_ID)
7609 return TRUE;
7610 if (chipid == BCM43242_CHIP_ID)
7611 return TRUE;
7612 if (chipid == BCM43340_CHIP_ID)
7613 return TRUE;
7614 if (chipid == BCM43341_CHIP_ID)
7615 return TRUE;
7616 if (chipid == BCM43143_CHIP_ID)
7617 return TRUE;
7618 if (chipid == BCM43342_CHIP_ID)
7619 return TRUE;
7620 if (chipid == BCM4334_CHIP_ID)
7621 return TRUE;
7622 if (chipid == BCM43239_CHIP_ID)
7623 return TRUE;
7624 if (chipid == BCM4324_CHIP_ID)
7625 return TRUE;
7626 if (chipid == BCM4335_CHIP_ID)
7627 return TRUE;
7628 if (chipid == BCM4339_CHIP_ID)
7629 return TRUE;
7630 if (chipid == BCM43349_CHIP_ID)
7631 return TRUE;
7632 if (BCM4345_CHIP(chipid))
7633 return TRUE;
7634 if (chipid == BCM4350_CHIP_ID)
7635 return TRUE;
7636 if (chipid == BCM4354_CHIP_ID)
7637 return TRUE;
7638 if (chipid == BCM4358_CHIP_ID)
7639 return TRUE;
7640 if (chipid == BCM43569_CHIP_ID)
7641 return TRUE;
7642 if (chipid == BCM4371_CHIP_ID)
7643 return TRUE;
7644 if (chipid == BCM43430_CHIP_ID)
7645 return TRUE;
7646 if (chipid == BCM43018_CHIP_ID)
7647 return TRUE;
7648 if (BCM4349_CHIP(chipid))
7649 return TRUE;
7650 if (BCM4347_CHIP(chipid))
7651 return TRUE;
7652 if (chipid == BCM4364_CHIP_ID)
7653 return TRUE;
7654
7655 if (chipid == BCM43012_CHIP_ID)
7656 return TRUE;
dfb0f3ae 7657 if (chipid == BCM4362_CHIP_ID)
210a9a5c
W		 7658 return TRUE;
7659
010c3a89
RC		 7660 return FALSE;
7661}
7662
010c3a89
RC		 7663static void *
7664dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, uint16 slot,
7665 uint16 func, uint bustype, void *regsva, osl_t * osh, void *sdh)
7666{
7667 int ret;
7668 dhd_bus_t *bus;
7669#ifdef GET_OTP_MAC_ENABLE
7670 struct ether_addr ea_addr;
7671#endif
7672
d964ce36 7673 DHD_MUTEX_LOCK();
010c3a89
RC		 7674
7675 /* Init global variables at run-time, not as part of the declaration.
7676 * This is required to support init/de-init of the driver. Initialization
7677 * of globals as part of the declaration results in non-deterministic
7678 * behavior since the value of the globals may be different on the
7679 * first time that the driver is initialized vs subsequent initializations.
7680 */
7681 dhd_txbound = DHD_TXBOUND;
7682 dhd_rxbound = DHD_RXBOUND;
7683 dhd_alignctl = TRUE;
7684 sd1idle = TRUE;
7685 dhd_readahead = TRUE;
7686 retrydata = FALSE;
7687
7688#ifdef DISABLE_FLOW_CONTROL
7689 dhd_doflow = FALSE;
7690#endif /* DISABLE_FLOW_CONTROL */
7691 dhd_dongle_ramsize = 0;
7692 dhd_txminmax = DHD_TXMINMAX;
7693
7694 forcealign = TRUE;
7695
7696 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
7697 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __FUNCTION__, venid, devid));
7698
7699 /* We make assumptions about address window mappings */
7700 ASSERT((uintptr)regsva == SI_ENUM_BASE);
7701
7702 /* BCMSDH passes venid and devid based on CIS parsing -- but low-power start
7703 * means early parse could fail, so here we should get either an ID
7704 * we recognize OR (-1) indicating we must request power first.
7705 */
7706 /* Check the Vendor ID */
7707 switch (venid) {
7708 case 0x0000:
7709 case VENDOR_BROADCOM:
7710 break;
7711 default:
7712 DHD_ERROR(("%s: unknown vendor: 0x%04x\n",
7713 __FUNCTION__, venid));
7714 goto forcereturn;
7715 }
7716
7717 /* Check the Device ID and make sure it's one that we support */
7718 switch (devid) {
7719 case 0:
7720 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
7721 __FUNCTION__));
7722 break;
7723
7724 default:
7725 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
7726 __FUNCTION__, venid, devid));
7727 goto forcereturn;
7728 }
7729
7730 if (osh == NULL) {
7731 DHD_ERROR(("%s: osh is NULL!\n", __FUNCTION__));
7732 goto forcereturn;
7733 }
7734
7735 /* Allocate private bus interface state */
7736 if (!(bus = MALLOC(osh, sizeof(dhd_bus_t)))) {
7737 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
7738 goto fail;
7739 }
7740 bzero(bus, sizeof(dhd_bus_t));
7741 bus->sdh = sdh;
7742 bus->cl_devid = (uint16)devid;
7743 bus->bus = DHD_BUS;
7744 bus->bus_num = bus_no;
7745 bus->slot_num = slot;
7746 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
7747 bus->usebufpool = FALSE; /* Use bufpool if allocated, else use locally malloced rxbuf */
7748#ifdef BT_OVER_SDIO
7749 bus->bt_use_count = 0;
7750#endif
7751
7752#if defined(SUPPORT_P2P_GO_PS)
7753 init_waitqueue_head(&bus->bus_sleep);
7754#endif /* LINUX && SUPPORT_P2P_GO_PS */
dfb0f3ae 7755 init_waitqueue_head(&bus->ctrl_tx_wait);
010c3a89
RC		 7756
7757 /* attempt to attach to the dongle */
7758 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
7759 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __FUNCTION__));
7760 goto fail;
7761 }
7762
7763 /* Attach to the dhd/OS/network interface */
7764 if (!(bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE))) {
7765 DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
7766 goto fail;
7767 }
7768#if defined(BT_OVER_SDIO)
7769 g_dhd_pub = bus->dhd;
7770 DHD_ERROR(("%s: g_dhd_pub %p\n", __FUNCTION__, g_dhd_pub));
7771#endif /* defined (BT_OVER_SDIO) */
7772
7773 /* Allocate buffers */
7774 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
7775 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __FUNCTION__));
7776 goto fail;
7777 }
7778
7779 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
7780 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __FUNCTION__));
7781 goto fail;
7782 }
7783
7784 if (bus->intr) {
7785 /* Register interrupt callback, but mask it (not operational yet). */
7786 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n", __FUNCTION__));
7787 bcmsdh_intr_disable(sdh);
7788 if ((ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus)) != 0) {
7789 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
7790 __FUNCTION__, ret));
7791 goto fail;
7792 }
7793 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __FUNCTION__));
7794 } else {
7795 DHD_INFO(("%s: SDIO interrupt function is NOT registered due to polling mode\n",
7796 __FUNCTION__));
7797 }
7798
7799 DHD_INFO(("%s: completed!!\n", __FUNCTION__));
7800
7801 /* if firmware path present try to download and bring up bus */
7802 bus->dhd->hang_report = TRUE;
7803#if 0 // terence 20150325: fix for WPA/WPA2 4-way handshake fail in hostapd
7804 if (dhd_download_fw_on_driverload) {
7805 if ((ret = dhd_bus_start(bus->dhd)) != 0) {
7806 DHD_ERROR(("%s: dhd_bus_start failed\n", __FUNCTION__));
7807 goto fail;
7808 }
7809 }
7810 else {
7811 /* Set random MAC address during boot time */
7812 get_random_bytes(&bus->dhd->mac.octet[3], 3);
7813 /* Adding BRCM OUI */
7814 bus->dhd->mac.octet[0] = 0;
7815 bus->dhd->mac.octet[1] = 0x90;
7816 bus->dhd->mac.octet[2] = 0x4C;
7817 }
7818#endif
7819#if defined(BT_OVER_SDIO)
7820 /* At this point Regulators are turned on and iconditionaly sdio bus is started
7821 * based upon dhd_download_fw_on_driverload check, so
7822 * increase the bus user count, this count will only be disabled inside
7823 * dhd_register_if() function if flag dhd_download_fw_on_driverload is set to false,
7824 * i.e FW download during insmod is not needed, otherwise it will not be decremented
7825 * so that WALN will always hold the bus untill rmmod is done.
7826 */
7827 dhdsdio_bus_usr_cnt_inc(bus->dhd);
7828#endif /* BT_OVER_SDIO */
7829
7830#ifdef GET_OTP_MAC_ENABLE
7831 if (dhd_conf_get_mac(bus->dhd, sdh, ea_addr.octet)) {
7832 DHD_TRACE(("%s: Can not read MAC address\n", __FUNCTION__));
7833 } else
7834 memcpy(bus->dhd->mac.octet, (void *)&ea_addr, ETHER_ADDR_LEN);
7835#endif /* GET_CUSTOM_MAC_ENABLE */
7836
7837 /* Ok, have the per-port tell the stack we're open for business */
7838 if (dhd_register_if(bus->dhd, 0, TRUE) != 0) {
7839 DHD_ERROR(("%s: Net attach failed!!\n", __FUNCTION__));
7840 goto fail;
7841 }
7842
7843#ifdef BCMHOST_XTAL_PU_TIME_MOD
7844 bcmsdh_reg_write(bus->sdh, 0x18000620, 2, 11);
7845#ifdef BCM4330_CHIP
7846 bcmsdh_reg_write(bus->sdh, 0x18000628, 4, 0x0000F801);
7847#else
7848 bcmsdh_reg_write(bus->sdh, 0x18000628, 4, 0x00F80001);
7849#endif /* BCM4330_CHIP */
7850#endif /* BCMHOST_XTAL_PU_TIME_MOD */
7851
7852#if defined(MULTIPLE_SUPPLICANT)
7853 wl_android_post_init(); // terence 20120530: fix critical section in dhd_open and dhdsdio_probe
d964ce36 7854#endif /* MULTIPLE_SUPPLICANT */
7855 DHD_MUTEX_UNLOCK();
010c3a89
RC		 7856
7857 return bus;
7858
7859fail:
7860 dhdsdio_release(bus, osh);
7861
7862forcereturn:
d964ce36 7863 DHD_MUTEX_UNLOCK();
010c3a89
RC		 7864
7865 return NULL;
7866}
7867
7868static bool
7869dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
7870 uint16 devid)
7871{
7872 uint8 clkctl = 0;
7873 uint fn, numfn;
7874 uint8 *cis[SDIOD_MAX_IOFUNCS];
7875 int err = 0;
7876
7877
7878 bus->alp_only = TRUE;
7879 bus->sih = NULL;
7880
7881 /* Return the window to backplane enumeration space for core access */
7882 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE)) {
7883 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __FUNCTION__));
7884 }
7885
7886#if defined(DHD_DEBUG) && !defined(CUSTOMER_HW4_DEBUG)
7887 DHD_ERROR(("F1 signature read @0x18000000=0x%4x\n",
7888 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4)));
7889#endif /* DHD_DEBUG && !CUSTOMER_HW4_DEBUG */
7890
7891
7892 /* Force PLL off until si_attach() programs PLL control regs */
7893
7894
7895
7896 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, DHD_INIT_CLKCTL1, &err);
7897 if (!err)
7898 clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
7899
7900 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
7901 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
7902 err, DHD_INIT_CLKCTL1, clkctl));
7903 goto fail;
7904 }
7905 numfn = bcmsdh_query_iofnum(sdh);
7906 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
7907
7908 /* Make sure ALP is available before trying to read CIS */
7909 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
7910 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
7911 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
7912
7913 /* Now request ALP be put on the bus */
7914 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
7915 DHD_INIT_CLKCTL2, &err);
7916 OSL_DELAY(200);
dfb0f3ae 7917
010c3a89
RC		 7918 if (DHD_INFO_ON()) {
7919 for (fn = 0; fn <= numfn; fn++) {
7920 if (!(cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT))) {
7921 DHD_INFO(("dhdsdio_probe: fn %d cis malloc failed\n", fn));
7922 break;
7923 }
7924 bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
7925
7926 if ((err = bcmsdh_cis_read(sdh, fn, cis[fn],
7927 SBSDIO_CIS_SIZE_LIMIT))) {
7928 DHD_INFO(("dhdsdio_probe: fn %d cis read err %d\n", fn, err));
7929 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
7930 break;
7931 }
7932#if 0
7933 /* Reading the F1, F2 and F3 max blocksize values from CIS
7934 * and writing into the F1, F2 and F3 block size registers.
7935 * There is no max block size register value available for F0 in CIS register.
7936 * So, setting default value for F0 block size as 32 (which was set earlier
7937 * in iovar). IOVAR takes only one arguement.
7938 * So, we are passing the function number alongwith the value (fn<<16)
7939 */
7940 if (!fn)
7941 value = F0_BLOCK_SIZE;
7942 else
7943 value = (cis[fn][25]<<8) | cis[fn][24] | (fn<<16);
7944 printf("%s: fn=%d, value=%d\n", __FUNCTION__, fn, value);
7945 if (bcmsdh_iovar_op(sdh, "sd_blocksize", NULL, 0, &value,
7946 sizeof(value), TRUE) != BCME_OK) {
7947 bus->blocksize = 0;
7948 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__,
7949 "sd_blocksize"));
7950 }
7951#endif
7952#ifdef DHD_DEBUG
7953 if (DHD_INFO_ON()) {
7954 dhd_dump_cis(fn, cis[fn]);
7955 }
7956#endif /* DHD_DEBUG */
7957 }
7958 while (fn-- > 0) {
7959 ASSERT(cis[fn]);
7960 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
7961 }
7962 }
7963#if 0
7964 if (dhd_conf_set_blksize(sdh)) {
7965 bus->blocksize = 0;
7966 }
7967#endif
7968 if (err) {
7969 DHD_ERROR(("dhdsdio_probe: failure reading or parsing CIS\n"));
7970 goto fail;
7971 }
7972 /* si_attach() will provide an SI handle and scan the backplane */
7973 if (!(bus->sih = si_attach((uint)devid, osh, regsva, DHD_BUS, sdh,
7974 &bus->vars, &bus->varsz))) {
7975 DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
7976 goto fail;
7977 }
7978
7979#ifdef DHD_DEBUG
7980 DHD_ERROR(("F1 signature OK, socitype:0x%x chip:0x%4x rev:0x%x pkg:0x%x\n",
7981 bus->sih->socitype, bus->sih->chip, bus->sih->chiprev, bus->sih->chippkg));
7982#endif /* DHD_DEBUG */
7983
7984
7985 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
7986
7987 if (!dhdsdio_chipmatch((uint16)bus->sih->chip)) {
7988 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
7989 __FUNCTION__, bus->sih->chip));
7990 goto fail;
7991 }
7992
7993 if (bus->sih->buscorerev >= 12)
7994 dhdsdio_clk_kso_init(bus);
7995 else
7996 bus->kso = TRUE;
7997
7998 if (CST4330_CHIPMODE_SDIOD(bus->sih->chipst)) {
7999 }
8000
8001 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
8002
8003
8004 /* Get info on the ARM and SOCRAM cores... */
8005 if (!DHD_NOPMU(bus)) {
8006 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
8007 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) ||
8008 (si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) {
8009 bus->armrev = si_corerev(bus->sih);
8010 } else {
8011 DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
8012 goto fail;
8013 }
8014
8015 if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
8016 if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
8017 DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
8018 goto fail;
8019 }
8020 } else {
8021 /* cr4 has a different way to find the RAM size from TCM's */
8022 if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) {
8023 DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__));
8024 goto fail;
8025 }
8026 /* also populate base address */
8027 switch ((uint16)bus->sih->chip) {
8028 case BCM4335_CHIP_ID:
8029 case BCM4339_CHIP_ID:
8030 case BCM43349_CHIP_ID:
8031 bus->dongle_ram_base = CR4_4335_RAM_BASE;
8032 break;
8033 case BCM4350_CHIP_ID:
8034 case BCM4354_CHIP_ID:
8035 case BCM4358_CHIP_ID:
8036 case BCM43569_CHIP_ID:
8037 case BCM4371_CHIP_ID:
8038 bus->dongle_ram_base = CR4_4350_RAM_BASE;
8039 break;
8040 case BCM4360_CHIP_ID:
8041 bus->dongle_ram_base = CR4_4360_RAM_BASE;
8042 break;
8043 CASE_BCM4345_CHIP:
8044 bus->dongle_ram_base = (bus->sih->chiprev < 6) /* from 4345C0 */
8045 ? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE;
8046 break;
8047 case BCM4349_CHIP_GRPID:
8048 /* RAM based changed from 4349c0(revid=9) onwards */
8049 bus->dongle_ram_base = ((bus->sih->chiprev < 9) ?
8050 CR4_4349_RAM_BASE: CR4_4349_RAM_BASE_FROM_REV_9);
8051 break;
8052 case BCM4364_CHIP_ID:
8053 bus->dongle_ram_base = CR4_4364_RAM_BASE;
8054 break;
8055 case BCM4347_CHIP_GRPID:
8056 bus->dongle_ram_base = CR4_4347_RAM_BASE;
8057 break;
dfb0f3ae
RC		 8058 case BCM4362_CHIP_ID:
8059 bus->dongle_ram_base = CR4_4362_RAM_BASE;
210a9a5c 8060 break;
010c3a89
RC		 8061 default:
8062 bus->dongle_ram_base = 0;
8063 DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
8064 __FUNCTION__, bus->dongle_ram_base));
8065 }
8066 }
8067 bus->ramsize = bus->orig_ramsize;
8068 if (dhd_dongle_ramsize)
8069 dhd_dongle_setramsize(bus, dhd_dongle_ramsize);
8070
8071 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n",
8072 bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base));
8073
8074 bus->srmemsize = si_socram_srmem_size(bus->sih);
8075 }
8076
8077 /* ...but normally deal with the SDPCMDEV core */
8078 if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) &&
8079 !(bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0))) {
8080 DHD_ERROR(("%s: failed to find SDIODEV core!\n", __FUNCTION__));
8081 goto fail;
8082 }
8083 bus->sdpcmrev = si_corerev(bus->sih);
8084
8085 /* Set core control so an SDIO reset does a backplane reset */
8086 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
8087 bus->rxint_mode = SDIO_DEVICE_HMB_RXINT;
8088
8089 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
8090 (bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_1))
8091 {
8092 uint32 val;
8093
8094 val = R_REG(osh, &bus->regs->corecontrol);
8095 val &= ~CC_XMTDATAAVAIL_MODE;
8096 val |= CC_XMTDATAAVAIL_CTRL;
8097 W_REG(osh, &bus->regs->corecontrol, val);
8098 }
8099
8100
8101 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
8102
8103 /* Locate an appropriately-aligned portion of hdrbuf */
8104 bus->rxhdr = (uint8 *)ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN);
8105
8106 /* Set the poll and/or interrupt flags */
8107 bus->intr = (bool)dhd_intr;
8108 if ((bus->poll = (bool)dhd_poll))
8109 bus->pollrate = 1;
8110
8111 /* Setting default Glom size */
8112 bus->txglomsize = SDPCM_DEFGLOM_SIZE;
8113
8114 return TRUE;
8115
8116fail:
8117 if (bus->sih != NULL) {
8118 si_detach(bus->sih);
8119 bus->sih = NULL;
8120 }
8121 return FALSE;
8122}
8123
8124static bool
8125dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
8126{
8127 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8128
8129 if (bus->dhd->maxctl) {
8130 bus->rxblen = ROUNDUP((bus->dhd->maxctl+SDPCM_HDRLEN), ALIGNMENT) + DHD_SDALIGN;
8131 if (!(bus->rxbuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_RXBUF, bus->rxblen))) {
8132 DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
8133 __FUNCTION__, bus->rxblen));
8134 goto fail;
8135 }
8136 }
8137 /* Allocate buffer to receive glomed packet */
8138 if (!(bus->databuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_DATABUF, MAX_DATA_BUF))) {
8139 DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
8140 __FUNCTION__, MAX_DATA_BUF));
8141 /* release rxbuf which was already located as above */
8142 if (!bus->rxblen)
8143 DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen);
8144 goto fail;
8145 }
07d6b24a
RC		 8146 /* Allocate buffer to membuf */
8147 bus->membuf = MALLOC(osh, MAX_MEM_BUF);
8148 if (bus->membuf == NULL) {
8149 DHD_ERROR(("%s: MALLOC of %d-byte membuf failed\n",
8150 __FUNCTION__, MAX_MEM_BUF));
8151 if (bus->databuf) {
8152#ifndef CONFIG_DHD_USE_STATIC_BUF
8153 MFREE(osh, bus->databuf, MAX_DATA_BUF);
8154#endif
8155 bus->databuf = NULL;
8156 }
8157 /* release rxbuf which was already located as above */
8158 if (!bus->rxblen)
8159 DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen);
8160 goto fail;
8161 }
8162 memset(bus->membuf, 0, MAX_MEM_BUF);
010c3a89
RC		 8163
8164 /* Align the buffer */
8165 if ((uintptr)bus->databuf % DHD_SDALIGN)
8166 bus->dataptr = bus->databuf + (DHD_SDALIGN - ((uintptr)bus->databuf % DHD_SDALIGN));
8167 else
8168 bus->dataptr = bus->databuf;
8169
8170 return TRUE;
8171
8172fail:
8173 return FALSE;
8174}
8175
8176static bool
8177dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
8178{
8179 int32 fnum;
8180
8181 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8182
8183 bus->_srenab = FALSE;
8184
8185#ifdef SDTEST
8186 dhdsdio_pktgen_init(bus);
8187#endif /* SDTEST */
8188
8189 /* set PMU minimum resource mask to default */
8190 dhd_bus_set_default_min_res_mask(bus);
8191 /* Disable F2 to clear any intermediate frame state on the dongle */
8192 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
8193
8194 bus->dhd->busstate = DHD_BUS_DOWN;
8195 bus->sleeping = FALSE;
8196 bus->rxflow = FALSE;
8197 bus->prev_rxlim_hit = 0;
8198
8199 /* Done with backplane-dependent accesses, can drop clock... */
8200 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
8201
8202 /* ...and initialize clock/power states */
8203 bus->clkstate = CLK_SDONLY;
8204 bus->idletime = (int32)dhd_idletime;
8205 bus->idleclock = DHD_IDLE_ACTIVE;
8206
8207 /* Query the SD clock speed */
8208 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
8209 &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
8210 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_divisor"));
8211 bus->sd_divisor = -1;
8212 } else {
8213 DHD_INFO(("%s: Initial value for %s is %d\n",
8214 __FUNCTION__, "sd_divisor", bus->sd_divisor));
8215 }
8216
8217 /* Query the SD bus mode */
8218 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
8219 &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
8220 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_mode"));
8221 bus->sd_mode = -1;
8222 } else {
8223 DHD_INFO(("%s: Initial value for %s is %d\n",
8224 __FUNCTION__, "sd_mode", bus->sd_mode));
8225 }
8226
8227 /* Query the F2 block size, set roundup accordingly */
8228 fnum = 2;
8229 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(int32),
8230 &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
8231 bus->blocksize = 0;
8232 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
8233 } else {
8234 DHD_INFO(("%s: Initial value for %s is %d\n",
8235 __FUNCTION__, "sd_blocksize", bus->blocksize));
8236
8237 dhdsdio_tune_fifoparam(bus);
8238 }
8239 bus->roundup = MIN(max_roundup, bus->blocksize);
8240
8241#ifdef DHDENABLE_TAILPAD
8242 if (bus->pad_pkt)
8243 PKTFREE(osh, bus->pad_pkt, FALSE);
8244 bus->pad_pkt = PKTGET(osh, SDIO_MAX_BLOCK_SIZE, FALSE);
8245 if (bus->pad_pkt == NULL)
8246 DHD_ERROR(("failed to allocate padding packet\n"));
8247 else {
8248 int alignment_offset = 0;
8249 uintptr pktprt = (uintptr)PKTDATA(osh, bus->pad_pkt);
8250 if (!(pktprt&1) && (pktprt = (pktprt % DHD_SDALIGN)))
8251 PKTPUSH(osh, bus->pad_pkt, alignment_offset);
8252 PKTSETNEXT(osh, bus->pad_pkt, NULL);
8253 }
8254#endif /* DHDENABLE_TAILPAD */
8255
8256 /* Query if bus module supports packet chaining, default to use if supported */
8257 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
8258 &bus->sd_rxchain, sizeof(int32), FALSE) != BCME_OK) {
8259 bus->sd_rxchain = FALSE;
8260 } else {
8261 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
8262 __FUNCTION__, (bus->sd_rxchain ? "supports" : "does not support")));
8263 }
8264 bus->use_rxchain = (bool)bus->sd_rxchain;
8265 bus->txinrx_thres = CUSTOM_TXINRX_THRES;
8266 /* TX first in dhdsdio_readframes() */
8267 bus->dotxinrx = TRUE;
8268
8269#ifdef PKT_STATICS
8270 memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t));
8271#endif
8272
8273 return TRUE;
8274}
8275
8276int
8277dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
8278 char *pfw_path, char *pnv_path,
8279 char *pclm_path, char *pconf_path)
8280{
8281 int ret;
8282
8283 bus->fw_path = pfw_path;
8284 bus->nv_path = pnv_path;
8285 bus->dhd->clm_path = pclm_path;
8286 bus->dhd->conf_path = pconf_path;
8287
8288 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
8289
8290 return ret;
8291}
8292
8293void
8294dhd_set_path_params(struct dhd_bus *bus)
8295{
8296 /* External conf takes precedence if specified */
8297 dhd_conf_preinit(bus->dhd);
8298
8299 if (bus->dhd->conf_path[0] == '\0') {
8300 dhd_conf_set_path(bus->dhd, "config.txt", bus->dhd->conf_path, bus->nv_path);
8301 }
8302 if (bus->dhd->clm_path[0] == '\0') {
8303 dhd_conf_set_path(bus->dhd, "clm.blob", bus->dhd->clm_path, bus->fw_path);
8304 }
8305#ifdef CONFIG_PATH_AUTO_SELECT
8306 dhd_conf_set_conf_name_by_chip(bus->dhd, bus->dhd->conf_path);
8307#endif
8308
8309 dhd_conf_read_config(bus->dhd, bus->dhd->conf_path);
8310
8311 dhd_conf_set_fw_name_by_chip(bus->dhd, bus->fw_path);
8312 dhd_conf_set_nv_name_by_chip(bus->dhd, bus->nv_path);
8313 dhd_conf_set_clm_name_by_chip(bus->dhd, bus->dhd->clm_path);
8314
8315 dhd_conf_set_fw_name_by_mac(bus->dhd, bus->sdh, bus->fw_path);
8316 dhd_conf_set_nv_name_by_mac(bus->dhd, bus->sdh, bus->nv_path);
8317
8318 printf("Final fw_path=%s\n", bus->fw_path);
8319 printf("Final nv_path=%s\n", bus->nv_path);
8320 printf("Final clm_path=%s\n", bus->dhd->clm_path);
8321 printf("Final conf_path=%s\n", bus->dhd->conf_path);
8322
8323}
8324
8325void
8326dhd_set_bus_params(struct dhd_bus *bus)
8327{
8328 if (bus->dhd->conf->dhd_poll >= 0) {
8329 bus->poll = bus->dhd->conf->dhd_poll;
8330 if (!bus->pollrate)
8331 bus->pollrate = 1;
8332 printf("%s: set polling mode %d\n", __FUNCTION__, bus->dhd->conf->dhd_poll);
8333 }
8334 if (bus->dhd->conf->use_rxchain >= 0) {
8335 bus->use_rxchain = (bool)bus->dhd->conf->use_rxchain;
010c3a89
RC		 8336 }
8337 if (bus->dhd->conf->txinrx_thres >= 0) {
8338 bus->txinrx_thres = bus->dhd->conf->txinrx_thres;
010c3a89
RC		 8339 }
8340 if (bus->dhd->conf->txglomsize >= 0) {
8341 bus->txglomsize = bus->dhd->conf->txglomsize;
010c3a89
RC		 8342 }
8343}
8344
8345static int
8346dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
8347{
8348 int ret;
8349
8350
8351#if defined(DHD_BLOB_EXISTENCE_CHECK)
8352 dhd_set_blob_support(bus->dhd, bus->fw_path);
8353#endif /* DHD_BLOB_EXISTENCE_CHECK */
8354
8355 DHD_TRACE_HW4(("%s: firmware path=%s, nvram path=%s\n",
8356 __FUNCTION__, bus->fw_path, bus->nv_path));
8357 DHD_OS_WAKE_LOCK(bus->dhd);
8358
8359 /* Download the firmware */
8360 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
8361
8362 dhd_set_path_params(bus);
8363 dhd_set_bus_params(bus);
8364
8365 ret = _dhdsdio_download_firmware(bus);
8366
8367 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
8368
8369 DHD_OS_WAKE_UNLOCK(bus->dhd);
8370 return ret;
8371}
8372
8373/* Detach and free everything */
8374static void
8375dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
8376{
8377 bool dongle_isolation = FALSE;
8378 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8379
8380 if (bus) {
8381 ASSERT(osh);
8382
8383 if (bus->dhd) {
8384 dongle_isolation = bus->dhd->dongle_isolation;
8385 dhd_detach(bus->dhd);
8386 }
8387
8388 /* De-register interrupt handler */
8389 bcmsdh_intr_disable(bus->sdh);
8390 bcmsdh_intr_dereg(bus->sdh);
8391
8392 if (bus->dhd) {
8393 dhdsdio_release_dongle(bus, osh, dongle_isolation, TRUE);
8394 dhd_free(bus->dhd);
8395 bus->dhd = NULL;
8396 }
8397
8398 dhdsdio_release_malloc(bus, osh);
8399
8400#ifdef DHD_DEBUG
8401 if (bus->console.buf != NULL)
8402 MFREE(osh, bus->console.buf, bus->console.bufsize);
8403#endif
8404
8405#ifdef DHDENABLE_TAILPAD
8406 if (bus->pad_pkt)
8407 PKTFREE(osh, bus->pad_pkt, FALSE);
8408#endif /* DHDENABLE_TAILPAD */
8409
8410 MFREE(osh, bus, sizeof(dhd_bus_t));
8411 }
8412
8413 DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
8414}
8415
8416static void
8417dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
8418{
8419 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8420
8421 if (bus->dhd && bus->dhd->dongle_reset)
8422 return;
8423
8424 if (bus->rxbuf) {
8425#ifndef CONFIG_DHD_USE_STATIC_BUF
8426 MFREE(osh, bus->rxbuf, bus->rxblen);
8427#endif
8428 bus->rxctl = bus->rxbuf = NULL;
8429 bus->rxlen = 0;
8430 }
8431
8432 if (bus->databuf) {
8433#ifndef CONFIG_DHD_USE_STATIC_BUF
8434 MFREE(osh, bus->databuf, MAX_DATA_BUF);
8435#endif
8436 bus->databuf = NULL;
8437 }
8438
07d6b24a
RC		 8439 if (bus->membuf) {
8440 MFREE(osh, bus->membuf, MAX_DATA_BUF);
8441 bus->membuf = NULL;
8442 }
8443
010c3a89
RC		 8444 if (bus->vars && bus->varsz) {
8445 MFREE(osh, bus->vars, bus->varsz);
8446 bus->vars = NULL;
8447 }
8448
8449}
8450
8451
8452static void
8453dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
8454{
8455 DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
8456 bus->dhd, bus->dhd->dongle_reset));
8457
8458 if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag)
8459 return;
8460
8461 if (bus->sih) {
8462 /* In Win10, system will be BSOD if using "sysprep" to do OS image */
8463 /* Skip this will not cause the BSOD. */
8464#if !defined(BCMLXSDMMC)
8465 if (bus->dhd) {
8466 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
8467 }
8468 if (KSO_ENAB(bus) && (dongle_isolation == FALSE))
8469 si_watchdog(bus->sih, 4);
8470#endif /* !defined(BCMLXSDMMC) */
8471 if (bus->dhd) {
8472 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
8473 }
8474 si_detach(bus->sih);
8475 bus->sih = NULL;
8476 if (bus->vars && bus->varsz)
8477 MFREE(osh, bus->vars, bus->varsz);
8478 bus->vars = NULL;
8479 }
8480
8481 DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
8482}
8483
8484static void
8485dhdsdio_disconnect(void *ptr)
8486{
8487 dhd_bus_t *bus = (dhd_bus_t *)ptr;
8488
8489 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8490
d964ce36 8491 DHD_MUTEX_LOCK();
010c3a89
RC		 8492 if (bus) {
8493 ASSERT(bus->dhd);
ccd15baf
RC		 8494 /* Advertise bus remove during rmmod */
8495 dhdsdio_advertise_bus_remove(bus->dhd);
010c3a89
RC		 8496 dhdsdio_release(bus, bus->dhd->osh);
8497 }
d964ce36 8498 DHD_MUTEX_UNLOCK();
010c3a89
RC		 8499
8500 DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
8501}
8502
8503static int
8504dhdsdio_suspend(void *context)
8505{
8506 int ret = 0;
8507#ifdef SUPPORT_P2P_GO_PS
8508 int wait_time = 0;
8509#endif /* SUPPORT_P2P_GO_PS */
8510
8511 dhd_bus_t *bus = (dhd_bus_t*)context;
8512 unsigned long flags;
8513
8514 DHD_ERROR(("%s Enter\n", __FUNCTION__));
8515 if (bus->dhd == NULL) {
8516 DHD_ERROR(("bus not inited\n"));
8517 return BCME_ERROR;
8518 }
8519 if (bus->dhd->prot == NULL) {
8520 DHD_ERROR(("prot is not inited\n"));
8521 return BCME_ERROR;
8522 }
8523
8524 if (bus->dhd->up == FALSE) {
8525 return BCME_OK;
8526 }
8527
8528 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
8529 if (bus->dhd->busstate != DHD_BUS_DATA && bus->dhd->busstate != DHD_BUS_SUSPEND) {
8530 DHD_ERROR(("not in a readystate to LPBK is not inited\n"));
8531 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8532 return BCME_ERROR;
8533 }
8534 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8535 if (bus->dhd->dongle_reset) {
8536 DHD_ERROR(("Dongle is in reset state.\n"));
8537 return -EIO;
8538 }
8539
8540 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
8541 bus->dhd->busstate = DHD_BUS_SUSPEND;
8542 if (DHD_BUS_BUSY_CHECK_IN_TX(bus->dhd)) {
8543 DHD_ERROR(("Tx Request is not ended\n"));
8544 bus->dhd->busstate = DHD_BUS_DATA;
8545 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8546 return -EBUSY;
8547 }
8548 DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
8549 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8550
8551#ifdef SUPPORT_P2P_GO_PS
8552 if (bus->idletime > 0) {
8553 wait_time = msecs_to_jiffies(bus->idletime * dhd_watchdog_ms);
8554 }
8555#endif /* SUPPORT_P2P_GO_PS */
8556 ret = dhd_os_check_wakelock(bus->dhd);
8557#ifdef SUPPORT_P2P_GO_PS
8558 // terence 20141124: fix for suspend issue
8559 if (SLPAUTO_ENAB(bus) && (!ret) && (bus->dhd->up) && (bus->dhd->op_mode != DHD_FLAG_HOSTAP_MODE)) {
8560 if (wait_event_timeout(bus->bus_sleep, bus->sleeping, wait_time) == 0) {
8561 if (!bus->sleeping) {
8562 ret = 1;
8563 }
8564 }
8565 }
8566#endif /* SUPPORT_P2P_GO_PS */
8567
8568 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
8569 if (ret) {
8570 bus->dhd->busstate = DHD_BUS_DATA;
8571 }
8572 DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
8573 dhd_os_busbusy_wake(bus->dhd);
8574 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8575 return ret;
8576}
8577
8578static int
8579dhdsdio_resume(void *context)
8580{
8581 dhd_bus_t *bus = (dhd_bus_t*)context;
8582 ulong flags;
8583
8584 DHD_ERROR(("%s Enter\n", __FUNCTION__));
8585
8586 if (bus->dhd->up == FALSE) {
8587 return BCME_OK;
8588 }
8589
8590 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
8591 DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
8592 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8593
8594#if defined(OOB_INTR_ONLY)
8595 if (dhd_os_check_if_up(bus->dhd))
8596 bcmsdh_oob_intr_set(bus->sdh, TRUE);
8597#endif
8598
8599 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
8600 DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
8601 bus->dhd->busstate = DHD_BUS_DATA;
8602 dhd_os_busbusy_wake(bus->dhd);
8603 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
8604
8605 return 0;
8606}
8607
8608
8609/* Register/Unregister functions are called by the main DHD entry
8610 * point (e.g. module insertion) to link with the bus driver, in
8611 * order to look for or await the device.
8612 */
8613
8614static bcmsdh_driver_t dhd_sdio = {
8615 dhdsdio_probe,
8616 dhdsdio_disconnect,
8617 dhdsdio_suspend,
8618 dhdsdio_resume
8619};
8620
8621int
8622dhd_bus_register(void)
8623{
8624 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8625
8626 return bcmsdh_register(&dhd_sdio);
8627}
8628
8629void
8630dhd_bus_unregister(void)
8631{
8632 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
8633
8634 bcmsdh_unregister();
8635}
8636
8637#if defined(BCMLXSDMMC)
8638/* Register a dummy SDIO client driver in order to be notified of new SDIO device */
8639int dhd_bus_reg_sdio_notify(void* semaphore)
8640{
8641 return bcmsdh_reg_sdio_notify(semaphore);
8642}
8643
8644void dhd_bus_unreg_sdio_notify(void)
8645{
8646 bcmsdh_unreg_sdio_notify();
8647}
8648#endif /* defined(BCMLXSDMMC) */
8649
8650#ifdef BCMEMBEDIMAGE
8651static int
8652dhdsdio_download_code_array(struct dhd_bus *bus)
8653{
8654 int bcmerror = -1;
8655 int offset = 0;
8656 unsigned char *ularray = NULL;
8657
8658 DHD_INFO(("%s: download embedded firmware...\n", __FUNCTION__));
8659
8660 /* Download image */
8661 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
8662 /* check if CR4 */
8663 if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
8664 /* if address is 0, store the reset instruction to be written in 0 */
8665
8666 if (offset == 0) {
8667 bus->resetinstr = *(((uint32*)dlarray));
8668 /* Add start of RAM address to the address given by user */
8669 offset += bus->dongle_ram_base;
8670 }
8671 }
8672
8673 bcmerror = dhdsdio_membytes(bus, TRUE, offset,
8674 (uint8 *) (dlarray + offset), MEMBLOCK);
8675 if (bcmerror) {
8676 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
8677 __FUNCTION__, bcmerror, MEMBLOCK, offset));
8678 goto err;
8679 }
8680
8681 offset += MEMBLOCK;
8682 }
8683
8684 if (offset < sizeof(dlarray)) {
8685 bcmerror = dhdsdio_membytes(bus, TRUE, offset,
8686 (uint8 *) (dlarray + offset), sizeof(dlarray) - offset);
8687 if (bcmerror) {
8688 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
8689 __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
8690 goto err;
8691 }
8692 }
8693
8694#ifdef DHD_DEBUG
8695 /* Upload and compare the downloaded code */
8696 {
8697 ularray = MALLOC(bus->dhd->osh, bus->ramsize);
8698 /* Upload image to verify downloaded contents. */
8699 offset = 0;
8700 memset(ularray, 0xaa, bus->ramsize);
8701 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
8702 bcmerror = dhdsdio_membytes(bus, FALSE, offset, ularray + offset, MEMBLOCK);
8703 if (bcmerror) {
8704 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
8705 __FUNCTION__, bcmerror, MEMBLOCK, offset));
8706 goto err;
8707 }
8708
8709 offset += MEMBLOCK;
8710 }
8711
8712 if (offset < sizeof(dlarray)) {
8713 bcmerror = dhdsdio_membytes(bus, FALSE, offset,
8714 ularray + offset, sizeof(dlarray) - offset);
8715 if (bcmerror) {
8716 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
8717 __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
8718 goto err;
8719 }
8720 }
8721
8722 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
8723 DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
8724 __FUNCTION__, dlimagename, dlimagever, dlimagedate));
8725 goto err;
8726 } else
8727 DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
8728 __FUNCTION__, dlimagename, dlimagever, dlimagedate));
8729
8730 }
8731#endif /* DHD_DEBUG */
8732
8733err:
8734 if (ularray)
8735 MFREE(bus->dhd->osh, ularray, bus->ramsize);
8736 return bcmerror;
8737}
8738#endif /* BCMEMBEDIMAGE */
8739
8740static int
8741dhdsdio_download_code_file(struct dhd_bus *bus, char *pfw_path)
8742{
8743 int bcmerror = -1;
8744 int offset = 0;
8745 int len;
8746 void *image = NULL;
8747 uint8 *memblock = NULL, *memptr;
8748 uint8 *memptr_tmp = NULL; // terence: check downloaded firmware is correct
8749 uint memblock_size = MEMBLOCK;
8750#ifdef DHD_DEBUG_DOWNLOADTIME
8751 unsigned long initial_jiffies = 0;
8752 uint firmware_sz = 0;
8753#endif
8754
8755 DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
8756
8757 image = dhd_os_open_image(pfw_path);
8758 if (image == NULL) {
8759 printf("%s: Open firmware file failed %s\n", __FUNCTION__, pfw_path);
8760 goto err;
8761 }
8762
8763 /* Update the dongle image download block size depending on the F1 block size */
8764 if (sd_f1_blocksize == 512)
8765 memblock_size = MAX_MEMBLOCK;
8766
8767 memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN);
8768 if (memblock == NULL) {
8769 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
8770 memblock_size));
8771 goto err;
8772 }
8773 if (dhd_msg_level & DHD_TRACE_VAL) {
8774 memptr_tmp = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
8775 if (memptr_tmp == NULL) {
8776 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
8777 goto err;
8778 }
8779 }
8780 if ((uint32)(uintptr)memblock % DHD_SDALIGN)
8781 memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
8782
8783#ifdef DHD_DEBUG_DOWNLOADTIME
8784 initial_jiffies = jiffies;
8785#endif
8786
8787 /* Download image */
8788 while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) {
8789 // terence 20150412: fix for firmware failed to download
8790 if (bus->dhd->conf->chip == BCM43340_CHIP_ID ||
8791 bus->dhd->conf->chip == BCM43341_CHIP_ID) {
8792 if (len % 64 != 0) {
8793 memset(memptr+len, 0, len%64);
8794 len += (64 - len%64);
8795 }
8796 }
8797 if (len < 0) {
8798 DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
8799 bcmerror = BCME_ERROR;
8800 goto err;
8801 }
8802 /* check if CR4 */
8803 if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
8804 /* if address is 0, store the reset instruction to be written in 0 */
8805
8806 if (offset == 0) {
8807 bus->resetinstr = *(((uint32*)memptr));
8808 /* Add start of RAM address to the address given by user */
8809 offset += bus->dongle_ram_base;
8810 }
8811 }
8812
8813 bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len);
8814 if (bcmerror) {
8815 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
8816 __FUNCTION__, bcmerror, memblock_size, offset));
8817 goto err;
8818 }
8819
8820 if (dhd_msg_level & DHD_TRACE_VAL) {
8821 bcmerror = dhdsdio_membytes(bus, FALSE, offset, memptr_tmp, len);
8822 if (bcmerror) {
8823 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
8824 __FUNCTION__, bcmerror, MEMBLOCK, offset));
8825 goto err;
8826 }
8827 if (memcmp(memptr_tmp, memptr, len)) {
8828 DHD_ERROR(("%s: Downloaded image is corrupted.\n", __FUNCTION__));
8829 goto err;
8830 } else
8831 DHD_INFO(("%s: Download, Upload and compare succeeded.\n", __FUNCTION__));
8832 }
8833
8834 offset += memblock_size;
8835#ifdef DHD_DEBUG_DOWNLOADTIME
8836 firmware_sz += len;
8837#endif
8838 }
8839
8840#ifdef DHD_DEBUG_DOWNLOADTIME
8841 DHD_ERROR(("Firmware download time for %u bytes: %u ms\n",
8842 firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies)));
8843#endif
8844
8845err:
8846 if (memblock)
8847 MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN);
8848 if (dhd_msg_level & DHD_TRACE_VAL) {
8849 if (memptr_tmp)
8850 MFREE(bus->dhd->osh, memptr_tmp, MEMBLOCK + DHD_SDALIGN);
8851 }
8852
8853 if (image)
8854 dhd_os_close_image(image);
8855
8856 return bcmerror;
8857}
8858
8859#ifdef DHD_UCODE_DOWNLOAD
8860/* Currently supported only for the chips in which ucode RAM is AXI addressable */
8861static uint32
8862dhdsdio_ucode_base(struct dhd_bus *bus)
8863{
8864 uint32 ucode_base = 0;
8865
8866 switch ((uint16)bus->sih->chip) {
8867 case BCM43012_CHIP_ID:
8868 ucode_base = 0xE8020000;
8869 break;
8870 default:
8871 DHD_ERROR(("%s: Unsupported!\n", __func__));
8872 break;
8873 }
8874
8875 return ucode_base;
8876}
8877
8878static int
8879dhdsdio_download_ucode_file(struct dhd_bus *bus, char *ucode_path)
8880{
8881 int bcmerror = -1;
8882 int offset = 0;
8883 int len;
8884 uint32 ucode_base;
8885 void *image = NULL;
8886 uint8 *memblock = NULL, *memptr;
8887 uint memblock_size = MEMBLOCK;
8888#ifdef DHD_DEBUG_DOWNLOADTIME
8889 unsigned long initial_jiffies = 0;
8890 uint firmware_sz = 0;
8891#endif
8892
8893 DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, ucode_path));
8894
8895 ucode_base = dhdsdio_ucode_base(bus);
8896
8897 image = dhd_os_open_image(ucode_path);
8898 if (image == NULL)
8899 goto err;
8900
8901 /* Update the dongle image download block size depending on the F1 block size */
8902 if (sd_f1_blocksize == 512)
8903 memblock_size = MAX_MEMBLOCK;
8904
8905 memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN);
8906 if (memblock == NULL) {
8907 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
8908 memblock_size));
8909 goto err;
8910 }
8911 if ((uint32)(uintptr)memblock % DHD_SDALIGN)
8912 memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
8913
8914#ifdef DHD_DEBUG_DOWNLOADTIME
8915 initial_jiffies = jiffies;
8916#endif
8917
8918 /* Download image */
8919 while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) {
8920 if (len < 0) {
8921 DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
8922 bcmerror = BCME_ERROR;
8923 goto err;
8924 }
8925
8926 bcmerror = dhdsdio_membytes(bus, TRUE, (ucode_base + offset), memptr, len);
8927 if (bcmerror) {
8928 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
8929 __FUNCTION__, bcmerror, memblock_size, offset));
8930 goto err;
8931 }
8932
8933 offset += memblock_size;
8934#ifdef DHD_DEBUG_DOWNLOADTIME
8935 firmware_sz += len;
8936#endif
8937 }
8938
8939#ifdef DHD_DEBUG_DOWNLOADTIME
8940 DHD_ERROR(("ucode download time for %u bytes: %u ms\n",
8941 firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies)));
8942#endif
8943
8944err:
8945 if (memblock)
8946 MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN);
8947
8948 if (image)
8949 dhd_os_close_image(image);
8950
8951 return bcmerror;
8952}
8953
8954void
8955dhd_bus_ucode_download(struct dhd_bus *bus)
8956{
8957 uint32 shaddr = 0, shdata = 0;
8958
8959 shaddr = bus->dongle_ram_base + bus->ramsize - 4;
8960 dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&shdata, 4);
8961
8962 DHD_TRACE(("%s: shdata:[0x%08x :0x%08x]\n", __func__, shaddr, shdata));
8963
8964 if (shdata == UCODE_DOWNLOAD_REQUEST)
8965 {
8966 DHD_ERROR(("%s: Received ucode download request!\n", __func__));
8967
8968 /* Download the ucode */
8969 if (!dhd_get_ucode_path(bus->dhd)) {
8970 DHD_ERROR(("%s: bus->uc_path not set!\n", __func__));
8971 return;
8972 }
8973 dhdsdio_download_ucode_file(bus, dhd_get_ucode_path(bus->dhd));
8974
8975 DHD_ERROR(("%s: Ucode downloaded successfully!\n", __func__));
8976
8977 shdata = UCODE_DOWNLOAD_COMPLETE;
8978 dhdsdio_membytes(bus, TRUE, shaddr, (uint8 *)&shdata, 4);
8979 }
8980}
8981
8982#endif /* DHD_UCODE_DOWNLOAD */
8983
8984static int
8985dhdsdio_download_nvram(struct dhd_bus *bus)
8986{
8987 int bcmerror = -1;
8988 uint len;
8989 void * image = NULL;
8990 char * memblock = NULL;
8991 char *bufp;
8992 char *pnv_path;
8993 bool nvram_file_exists;
8994
8995 pnv_path = bus->nv_path;
8996
8997 nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
8998
8999 /* For Get nvram from UEFI */
9000 if (nvram_file_exists) {
9001 image = dhd_os_open_image(pnv_path);
9002 if (image == NULL) {
9003 printf("%s: Open nvram file failed %s\n", __FUNCTION__, pnv_path);
9004 goto err;
9005 }
9006 }
9007
9008 memblock = MALLOC(bus->dhd->osh, MAX_NVRAMBUF_SIZE);
9009 if (memblock == NULL) {
9010 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
9011 __FUNCTION__, MAX_NVRAMBUF_SIZE));
9012 goto err;
9013 }
9014
9015 /* For Get nvram from image or UEFI (when image == NULL ) */
9016 len = dhd_os_get_image_block(memblock, MAX_NVRAMBUF_SIZE, image);
9017
9018 if (len > 0 && len < MAX_NVRAMBUF_SIZE) {
9019 bufp = (char *)memblock;
9020 bufp[len] = 0;
9021 len = process_nvram_vars(bufp, len);
9022 if (len % 4) {
9023 len += 4 - (len % 4);
9024 }
9025 bufp += len;
9026 *bufp++ = 0;
9027 if (len)
9028 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
9029 if (bcmerror) {
9030 DHD_ERROR(("%s: error downloading vars: %d\n",
9031 __FUNCTION__, bcmerror));
9032 }
9033 } else {
9034 DHD_ERROR(("%s: error reading nvram file: %d\n",
9035 __FUNCTION__, len));
9036 bcmerror = BCME_SDIO_ERROR;
9037 }
9038
9039err:
9040 if (memblock)
9041 MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
9042
9043 if (image)
9044 dhd_os_close_image(image);
9045
9046 return bcmerror;
9047}
9048
9049static int
9050_dhdsdio_download_firmware(struct dhd_bus *bus)
9051{
9052 int bcmerror = -1;
9053
9054 bool embed = FALSE; /* download embedded firmware */
9055 bool dlok = FALSE; /* download firmware succeeded */
9056
9057 /* Out immediately if no image to download */
9058 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
9059#ifdef BCMEMBEDIMAGE
9060 embed = TRUE;
9061#else
9062 return 0;
9063#endif
9064 }
9065
9066 /* Keep arm in reset */
9067 if (dhdsdio_download_state(bus, TRUE)) {
9068 DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
9069 goto err;
9070 }
9071
9072 /* External image takes precedence if specified */
9073 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
9074 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
9075 DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
9076#ifdef BCMEMBEDIMAGE
9077 embed = TRUE;
9078#else
9079 goto err;
9080#endif
9081 } else {
9082 embed = FALSE;
9083 dlok = TRUE;
9084 }
9085 }
9086
9087#ifdef BCMEMBEDIMAGE
9088 if (embed) {
9089 if (dhdsdio_download_code_array(bus)) {
9090 DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
9091 goto err;
9092 } else {
9093 dlok = TRUE;
9094 }
9095 }
9096#else
9097 BCM_REFERENCE(embed);
9098#endif
9099 if (!dlok) {
9100 DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
9101 goto err;
9102 }
9103
9104 /* External nvram takes precedence if specified */
9105 if (dhdsdio_download_nvram(bus)) {
9106 DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
9107 goto err;
9108 }
9109
9110 /* Take arm out of reset */
9111 if (dhdsdio_download_state(bus, FALSE)) {
9112 DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
9113 goto err;
9114 }
9115
9116 bcmerror = 0;
9117
9118err:
9119 return bcmerror;
9120}
9121
9122static int
9123dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
9124 void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle)
9125{
9126 int status;
9127
9128 if (!KSO_ENAB(bus)) {
9129 DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
9130 return BCME_NODEVICE;
9131 }
9132
9133 status = bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete_fn, handle);
9134
9135 return status;
9136}
9137
9138static int
9139dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
9140 void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle, int max_retry)
9141{
9142 int ret;
9143 int i = 0;
9144 int retries = 0;
9145 bcmsdh_info_t *sdh;
9146
9147 if (!KSO_ENAB(bus)) {
9148 DHD_ERROR(("%s: Device asleep\n", __FUNCTION__));
9149 return BCME_NODEVICE;
9150 }
9151
9152 sdh = bus->sdh;
9153 do {
9154 ret = bcmsdh_send_buf(bus->sdh, addr, fn, flags, buf, nbytes,
9155 pkt, complete_fn, handle);
9156
9157 bus->f2txdata++;
9158 ASSERT(ret != BCME_PENDING);
9159
9160 if (ret == BCME_NODEVICE) {
9161 DHD_ERROR(("%s: Device asleep already\n", __FUNCTION__));
9162 } else if (ret < 0) {
9163 /* On failure, abort the command and terminate the frame */
9164 DHD_ERROR(("%s: sdio error %d, abort command and terminate frame.\n",
9165 __FUNCTION__, ret));
9166 bus->tx_sderrs++;
9167 bus->f1regdata++;
9168 bus->dhd->tx_errors++;
9169 bcmsdh_abort(sdh, SDIO_FUNC_2);
9170 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
9171 SFC_WF_TERM, NULL);
9172 for (i = 0; i < READ_FRM_CNT_RETRIES; i++) {
9173 uint8 hi, lo;
9174 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCHI,
9175 NULL);
9176 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCLO,
9177 NULL);
9178 bus->f1regdata += 2;
9179 if ((hi == 0) && (lo == 0))
9180 break;
9181 }
9182 }
9183 } while ((ret < 0) && retrydata && ++retries < max_retry);
9184
9185 return ret;
9186}
9187
9188uint8
9189dhd_bus_is_ioready(struct dhd_bus *bus)
9190{
9191 uint8 enable;
9192 bcmsdh_info_t *sdh;
9193 ASSERT(bus);
9194 ASSERT(bus->sih != NULL);
9195 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
9196 sdh = bus->sdh;
9197 return (enable == bcmsdh_cfg_read(sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL));
9198}
9199
9200uint
9201dhd_bus_chip(struct dhd_bus *bus)
9202{
9203 ASSERT(bus->sih != NULL);
9204 return bus->sih->chip;
9205}
9206
9207uint
9208dhd_bus_chiprev(struct dhd_bus *bus)
9209{
9210 ASSERT(bus);
9211 ASSERT(bus->sih != NULL);
9212 return bus->sih->chiprev;
9213}
9214
9215void *
9216dhd_bus_pub(struct dhd_bus *bus)
9217{
9218 return bus->dhd;
9219}
9220
9221const void *
9222dhd_bus_sih(struct dhd_bus *bus)
9223{
9224 return (const void *)bus->sih;
9225}
9226
9227void *
9228dhd_bus_txq(struct dhd_bus *bus)
9229{
9230 return &bus->txq;
9231}
9232
9233uint
9234dhd_bus_hdrlen(struct dhd_bus *bus)
9235{
9236 return (bus->txglom_enable) ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN;
9237}
9238
9239void
9240dhd_bus_set_dotxinrx(struct dhd_bus *bus, bool val)
9241{
9242 bus->dotxinrx = val;
9243}
9244
9245/*
9246 * dhdsdio_advertise_bus_cleanup advertises that clean up is under progress
9247 * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
9248 * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
9249 * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so
9250 * they will exit from there itself without marking dhd_bus_busy_state as BUSY.
9251 */
9252static void
9253dhdsdio_advertise_bus_cleanup(dhd_pub_t *dhdp)
9254{
9255 unsigned long flags;
9256 int timeleft;
9257
9258 DHD_LINUX_GENERAL_LOCK(dhdp, flags);
9259 dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
9260 DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
9261
9262 timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
9263 if ((timeleft == 0) || (timeleft == 1)) {
9264 DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
9265 __FUNCTION__, dhdp->dhd_bus_busy_state));
9266 ASSERT(0);
9267 }
9268
9269 return;
9270}
9271
ccd15baf
RC		 9272static void
9273dhdsdio_advertise_bus_remove(dhd_pub_t *dhdp)
9274{
9275 unsigned long flags;
9276 int timeleft;
9277
9278 DHD_LINUX_GENERAL_LOCK(dhdp, flags);
9279 dhdp->busstate = DHD_BUS_REMOVE;
9280 DHD_LINUX_GENERAL_UNLOCK(dhdp, flags);
9281
9282 timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
9283 if ((timeleft == 0) || (timeleft == 1)) {
9284 DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
9285 __FUNCTION__, dhdp->dhd_bus_busy_state));
9286 ASSERT(0);
9287 }
9288
9289 return;
9290}
9291
9292
010c3a89
RC		 9293int
9294dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
9295{
9296 int bcmerror = 0;
9297 dhd_bus_t *bus;
9298 unsigned long flags;
9299
9300 bus = dhdp->bus;
9301
9302 if (flag == TRUE) {
9303 if (!bus->dhd->dongle_reset) {
9304 DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__));
9305 dhdsdio_advertise_bus_cleanup(bus->dhd);
9306 dhd_os_sdlock(dhdp);
9307 dhd_os_wd_timer(dhdp, 0);
9308#if !defined(IGNORE_ETH0_DOWN)
9309 /* Force flow control as protection when stop come before ifconfig_down */
9310 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
9311#endif /* !defined(IGNORE_ETH0_DOWN) */
9312 /* Expect app to have torn down any connection before calling */
9313 /* Stop the bus, disable F2 */
9314 dhd_bus_stop(bus, FALSE);
9315
9316#if defined(OOB_INTR_ONLY)
9317 /* Clean up any pending IRQ */
9318 dhd_enable_oob_intr(bus, FALSE);
9319 bcmsdh_oob_intr_set(bus->sdh, FALSE);
9320 bcmsdh_oob_intr_unregister(bus->sdh);
9321#endif
9322
9323 /* Clean tx/rx buffer pointers, detach from the dongle */
9324 dhdsdio_release_dongle(bus, bus->dhd->osh, TRUE, TRUE);
9325
9326 bus->dhd->dongle_reset = TRUE;
9327 bus->dhd->up = FALSE;
9328 dhd_txglom_enable(dhdp, FALSE);
9329 dhd_os_sdunlock(dhdp);
9330
9331 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
9332 bus->dhd->busstate = DHD_BUS_DOWN;
9333 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
9334
9335 printf("%s: WLAN OFF DONE\n", __FUNCTION__);
9336 /* App can now remove power from device */
9337 } else
9338 bcmerror = BCME_SDIO_ERROR;
9339 } else {
9340 /* App must have restored power to device before calling */
9341
9342 printf("\n\n%s: == WLAN ON ==\n", __FUNCTION__);
9343
9344 if (bus->dhd->dongle_reset) {
9345 /* Turn on WLAN */
9346 dhd_os_sdlock(dhdp);
9347 /* Reset SD client */
9348 bcmsdh_reset(bus->sdh);
9349
9350 /* Attempt to re-attach & download */
9351 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
9352 (uint32 *)SI_ENUM_BASE,
9353 bus->cl_devid)) {
9354
9355 DHD_LINUX_GENERAL_LOCK(bus->dhd, flags);
9356 bus->dhd->busstate = DHD_BUS_DOWN;
9357 DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags);
9358 /* Attempt to download binary to the dongle */
9359 if (dhdsdio_probe_init(bus, bus->dhd->osh, bus->sdh) &&
9360 dhdsdio_download_firmware(bus, bus->dhd->osh, bus->sdh) >= 0) {
9361
9362 /* Re-init bus, enable F2 transfer */
9363 bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
9364 if (bcmerror == BCME_OK) {
9365#if defined(OOB_INTR_ONLY)
9366 dhd_enable_oob_intr(bus, TRUE);
9367 bcmsdh_oob_intr_register(bus->sdh,
9368 dhdsdio_isr, bus);
9369 bcmsdh_oob_intr_set(bus->sdh, TRUE);
9370#elif defined(FORCE_WOWLAN)
9371 dhd_enable_oob_intr(bus, TRUE);
9372#endif
9373
9374 bus->dhd->dongle_reset = FALSE;
9375 bus->dhd->up = TRUE;
9376
9377#if !defined(IGNORE_ETH0_DOWN)
9378 /* Restore flow control */
9379 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
9380#endif
9381 dhd_os_wd_timer(dhdp, dhd_watchdog_ms);
9382
9383 DHD_TRACE(("%s: WLAN ON DONE\n", __FUNCTION__));
9384 } else {
9385 dhd_bus_stop(bus, FALSE);
9386 dhdsdio_release_dongle(bus, bus->dhd->osh,
9387 TRUE, FALSE);
9388 }
9389 } else {
9390 DHD_ERROR(("%s Failed to download binary to the dongle\n",
9391 __FUNCTION__));
9392 if (bus->sih != NULL) {
9393 si_detach(bus->sih);
9394 bus->sih = NULL;
9395 }
9396 bcmerror = BCME_SDIO_ERROR;
9397 }
9398 } else
9399 bcmerror = BCME_SDIO_ERROR;
9400
9401 dhd_os_sdunlock(dhdp);
9402 } else {
9403 printf("%s called when dongle is not in reset\n",
9404 __FUNCTION__);
9405 printf("Will call dhd_bus_start instead\n");
9406 dhd_bus_resume(dhdp, 1);
9407#if defined(HW_OOB) || defined(FORCE_WOWLAN)
9408 dhd_conf_set_hw_oob_intr(bus->sdh, bus->sih->chip); // terence 20120615: fix for OOB initial issue
9409#endif
9410 if ((bcmerror = dhd_bus_start(dhdp)) != 0)
9411 DHD_ERROR(("%s: dhd_bus_start fail with %d\n",
9412 __FUNCTION__, bcmerror));
9413 }
9414 }
9415
9416#ifdef PKT_STATICS
9417 memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t));
9418#endif
9419 return bcmerror;
9420}
9421
9422int dhd_bus_suspend(dhd_pub_t *dhdpub)
9423{
9424 return bcmsdh_stop(dhdpub->bus->sdh);
9425}
9426
9427int dhd_bus_resume(dhd_pub_t *dhdpub, int stage)
9428{
9429 return bcmsdh_start(dhdpub->bus->sdh, stage);
9430}
9431
9432/* Get Chip ID version */
9433uint dhd_bus_chip_id(dhd_pub_t *dhdp)
9434{
9435 dhd_bus_t *bus = dhdp->bus;
9436
9437 if (bus && bus->sih)
9438 return bus->sih->chip;
9439 else
9440 return 0;
9441}
9442
9443/* Get Chip Rev ID version */
9444uint dhd_bus_chiprev_id(dhd_pub_t *dhdp)
9445{
9446 dhd_bus_t *bus = dhdp->bus;
9447
9448 if (bus && bus->sih)
9449 return bus->sih->chiprev;
9450 else
9451 return 0;
9452}
9453
9454/* Get Chip Pkg ID version */
9455uint dhd_bus_chippkg_id(dhd_pub_t *dhdp)
9456{
9457 dhd_bus_t *bus = dhdp->bus;
9458
9459 return bus->sih->chippkg;
9460}
9461
9462int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num, uint32 *slot_num)
9463{
9464 *bus_type = bus->bus;
9465 *bus_num = bus->bus_num;
9466 *slot_num = bus->slot_num;
9467 return 0;
9468}
9469
9470int
9471dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size)
9472{
9473 dhd_bus_t *bus;
9474
9475 bus = dhdp->bus;
9476 return dhdsdio_membytes(bus, set, address, data, size);
9477}
9478
9479
9480void
9481dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path,
9482 char *pclm_path, char *pconf_path)
9483{
9484 bus->fw_path = pfw_path;
9485 bus->nv_path = pnv_path;
9486 bus->dhd->clm_path = pclm_path;
9487 bus->dhd->conf_path = pconf_path;
9488}
9489
9490int
9491dhd_enableOOB(dhd_pub_t *dhd, bool sleep)
9492{
9493 dhd_bus_t *bus = dhd->bus;
9494 sdpcmd_regs_t *regs = bus->regs;
9495 uint retries = 0;
9496
9497 if (sleep) {
9498 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
9499 /* Tell device to start using OOB wakeup */
9500 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
9501 if (retries > retry_limit) {
9502 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
9503 return BCME_BUSY;
9504 }
9505 /* Turn off our contribution to the HT clock request */
9506 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
9507 } else {
9508 /* Make sure the controller has the bus up */
9509 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
9510
9511 /* Send misc interrupt to indicate OOB not needed */
9512 W_SDREG(0, &regs->tosbmailboxdata, retries);
9513 if (retries <= retry_limit)
9514 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
9515
9516 if (retries > retry_limit)
9517 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
9518
9519 /* Make sure we have SD bus access */
9520 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
9521 }
9522 return BCME_OK;
9523}
9524
9525void
9526dhd_bus_pktq_flush(dhd_pub_t *dhdp)
9527{
9528 dhd_bus_t *bus = dhdp->bus;
9529 bool wlfc_enabled = FALSE;
9530
9531#ifdef PROP_TXSTATUS
9532 wlfc_enabled = (dhd_wlfc_cleanup_txq(dhdp, NULL, 0) != WLFC_UNSUPPORTED);
9533#endif
9534 if (!wlfc_enabled) {
9535#ifdef DHDTCPACK_SUPPRESS
9536 /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt,
9537 * when there is a newly coming packet from network stack.
9538 */
9539 dhd_tcpack_info_tbl_clean(bus->dhd);
9540#endif /* DHDTCPACK_SUPPRESS */
9541 /* Clear the data packet queues */
9542 pktq_flush(dhdp->osh, &bus->txq, TRUE);
9543 }
9544}
9545
9546#ifdef BCMSDIO
9547int
9548dhd_sr_config(dhd_pub_t *dhd, bool on)
9549{
9550 dhd_bus_t *bus = dhd->bus;
9551
9552 if (!bus->_srenab)
9553 return -1;
9554
9555 return dhdsdio_clk_devsleep_iovar(bus, on);
9556}
9557
9558uint16
9559dhd_get_chipid(dhd_pub_t *dhd)
9560{
9561 dhd_bus_t *bus = dhd->bus;
9562
9563 if (bus && bus->sih)
9564 return (uint16)bus->sih->chip;
9565 else
9566 return 0;
9567}
9568#endif /* BCMSDIO */
9569
9570#ifdef DEBUGGER
9571uint32 dhd_sdio_reg_read(void *h, uint32 addr)
9572{
9573 uint32 rval;
9574 struct dhd_bus *bus = (struct dhd_bus *) h;
9575
9576 dhd_os_sdlock(bus->dhd);
9577
9578 BUS_WAKE(bus);
9579
9580 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
9581
9582 rval = bcmsdh_reg_read(bus->sdh, addr, 4);
9583
9584 dhd_os_sdunlock(bus->dhd);
9585
9586 return rval;
9587}
9588
9589void dhd_sdio_reg_write(void *h, uint32 addr, uint32 val)
9590{
9591 struct dhd_bus *bus = (struct dhd_bus *) h;
9592
9593 dhd_os_sdlock(bus->dhd);
9594
9595 BUS_WAKE(bus);
9596
9597 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
9598
9599 bcmsdh_reg_write(bus->sdh, addr, 4, val);
9600
9601 dhd_os_sdunlock(bus->dhd);
9602}
9603
9604#endif /* DEBUGGER */
9605
9606
9607#if defined(BT_OVER_SDIO)
9608uint8 dhd_bus_cfg_read(void *h, uint fun_num, uint32 addr, int *err)
9609{
9610 uint8 intrd;
9611 dhd_pub_t *dhdp = (dhd_pub_t *)h;
9612 dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
9613
9614 dhd_os_sdlock(bus->dhd);
9615
9616 intrd = bcmsdh_cfg_read(bus->sdh, fun_num, addr, err);
9617
9618 dhd_os_sdunlock(bus->dhd);
9619
9620 return intrd;
9621} EXPORT_SYMBOL(dhd_bus_cfg_read);
9622
9623void dhd_bus_cfg_write(void *h, uint fun_num, uint32 addr, uint8 val, int *err)
9624{
9625 dhd_pub_t *dhdp = (dhd_pub_t *)h;
9626 dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
9627
9628 dhd_os_sdlock(bus->dhd);
9629
9630 bcmsdh_cfg_write(bus->sdh, fun_num, addr, val, err);
9631
9632 dhd_os_sdunlock(bus->dhd);
9633
9634} EXPORT_SYMBOL(dhd_bus_cfg_write);
9635
9636static int
9637extract_hex_field(char * line, uint16 start_pos, uint16 num_chars, uint16 * value)
9638{
9639 char field [8];
9640
9641 strncpy(field, line + start_pos, num_chars);
9642 field [num_chars] = '\0';
9643
9644 return (sscanf (field, "%hX", value) == 1);
9645}
9646
9647static int
9648read_more_btbytes(struct dhd_bus *bus, void * file, char *line, int * addr_mode, uint16 * hi_addr,
9649 uint32 * dest_addr, uint8 *data_bytes, uint32 * num_bytes)
9650{
9651 int str_len;
9652 uint16 num_data_bytes, addr, data_pos, type, w, i;
9653 uint32 abs_base_addr32 = 0;
9654 *num_bytes = 0;
9655
9656 while (!*num_bytes)
9657 {
9658 str_len = dhd_os_gets_image(bus->dhd, line, BTFW_MAX_STR_LEN, file);
9659
9660 DHD_TRACE(("%s: Len :0x%x %s\n", __FUNCTION__, str_len, line));
9661
9662 if (str_len == 0) {
9663 break;
9664 } else if (str_len > 9) {
9665 extract_hex_field(line, 1, 2, &num_data_bytes);
9666 extract_hex_field(line, 3, 4, &addr);
9667 extract_hex_field(line, 7, 2, &type);
9668
9669 data_pos = 9;
9670 for (i = 0; i < num_data_bytes; i++) {
9671 extract_hex_field(line, data_pos, 2, &w);
9672 data_bytes [i] = (uint8)(w & 0x00FF);
9673 data_pos += 2;
9674 }
9675
9676 if (type == BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS) {
9677 *hi_addr = (data_bytes [0] << 8) | data_bytes [1];
9678 *addr_mode = BTFW_ADDR_MODE_EXTENDED;
9679 } else if (type == BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS) {
9680 *hi_addr = (data_bytes [0] << 8) | data_bytes [1];
9681 *addr_mode = BTFW_ADDR_MODE_SEGMENT;
9682 } else if (type == BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS) {
9683 abs_base_addr32 = (data_bytes [0] << 24) | (data_bytes [1] << 16) |
9684 (data_bytes [2] << 8) | data_bytes [3];
9685 *addr_mode = BTFW_ADDR_MODE_LINEAR32;
9686 } else if (type == BTFW_HEX_LINE_TYPE_DATA) {
9687 *dest_addr = addr;
9688 if (*addr_mode == BTFW_ADDR_MODE_EXTENDED)
9689 *dest_addr += (*hi_addr << 16);
9690 else if (*addr_mode == BTFW_ADDR_MODE_SEGMENT)
9691 *dest_addr += (*hi_addr << 4);
9692 else if (*addr_mode == BTFW_ADDR_MODE_LINEAR32)
9693 *dest_addr += abs_base_addr32;
9694 *num_bytes = num_data_bytes;
9695 }
9696 }
9697 }
9698 return (*num_bytes > 0);
9699}
9700
9701static int
9702_dhdsdio_download_btfw(struct dhd_bus *bus)
9703{
9704 int bcm_error = -1;
9705 void *image = NULL;
9706 uint8 *mem_blk = NULL, *mem_ptr = NULL, *data_ptr = NULL;
9707
9708
9709 uint32 offset_addr = 0, offset_len = 0, bytes_to_write = 0;
9710
9711 char *line = NULL;
9712 uint32 dest_addr = 0, num_bytes;
9713 uint16 hiAddress = 0;
9714 uint32 start_addr, start_data, end_addr, end_data, i, index, pad;
9715 uint32 bt2wlan_pwrup_adr;
9716
9717 int addr_mode = BTFW_ADDR_MODE_EXTENDED;
9718
9719 /* Out immediately if no image to download */
9720 if ((bus->btfw_path == NULL) || (bus->btfw_path[0] == '\0')) {
9721 return 0;
9722 }
9723
9724 image = dhd_os_open_image(bus->btfw_path);
9725 if (image == NULL)
9726 goto err;
9727
9728 mem_ptr = mem_blk = MALLOC(bus->dhd->osh, BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN);
9729 if (mem_blk == NULL) {
9730 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
9731 BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN));
9732 goto err;
9733 }
9734 if ((uint32)(uintptr)mem_blk % DHD_SDALIGN)
9735 mem_ptr += (DHD_SDALIGN - ((uint32)(uintptr)mem_blk % DHD_SDALIGN));
9736
9737 data_ptr = MALLOC(bus->dhd->osh, BTFW_DOWNLOAD_BLK_SIZE - 8);
9738 if (data_ptr == NULL) {
9739 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__,
9740 BTFW_DOWNLOAD_BLK_SIZE - 8));
9741 goto err;
9742 }
9743 /* Write to BT register to hold WLAN wake high during BT FW download */
9744 bt2wlan_pwrup_adr = BTMEM_OFFSET + BT2WLAN_PWRUP_ADDR;
9745 bcmsdh_reg_write(bus->sdh, bt2wlan_pwrup_adr, 4, BT2WLAN_PWRUP_WAKE);
9746 /*
9747 * Wait for at least 2msec for the clock to be ready/Available.
9748 */
9749 OSL_DELAY(2000);
9750
9751 line = MALLOC(bus->dhd->osh, BTFW_MAX_STR_LEN);
9752 if (line == NULL) {
9753 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
9754 __FUNCTION__, BTFW_MAX_STR_LEN));
9755 goto err;
9756 }
9757 memset(line, 0, BTFW_MAX_STR_LEN);
9758
9759 while (read_more_btbytes (bus, image, line, &addr_mode, &hiAddress, &dest_addr,
9760 data_ptr, &num_bytes)) {
9761
9762 DHD_TRACE(("read %d bytes at address %08X\n", num_bytes, dest_addr));
9763
9764 start_addr = BTMEM_OFFSET + dest_addr;
9765 index = 0;
9766
9767 /* Make sure the start address is 4 byte aligned to avoid alignment issues
9768 * with SD host controllers
9769 */
9770 if (!ISALIGNED(start_addr, 4)) {
9771 pad = start_addr % 4;
9772 start_addr = ROUNDDN(start_addr, 4);
9773 start_data = bcmsdh_reg_read(bus->sdh, start_addr, 4);
9774 for (i = 0; i < pad; i++, index++) {
9775 mem_ptr[index] = (uint8)((uint8 *)&start_data)[i];
9776 }
9777 }
9778 bcopy(data_ptr, &(mem_ptr[index]), num_bytes);
9779 index += num_bytes;
9780
9781 /* Make sure the length is multiple of 4bytes to avoid alignment issues
9782 * with SD host controllers
9783 */
9784 end_addr = start_addr + index;
9785 if (!ISALIGNED(end_addr, 4)) {
9786 end_addr = ROUNDDN(end_addr, 4);
9787 end_data = bcmsdh_reg_read(bus->sdh, end_addr, 4);
9788 for (i = (index % 4); i < 4; i++, index++) {
9789 mem_ptr[index] = (uint8)((uint8 *)&end_data)[i];
9790 }
9791 }
9792
9793 offset_addr = start_addr & 0xFFF;
9794 offset_len = offset_addr + index;
9795 if (offset_len <= 0x1000) {
9796 bcm_error = dhdsdio_membytes(bus, TRUE, start_addr, mem_ptr, index);
9797 if (bcm_error) {
9798 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
9799 __FUNCTION__, bcm_error, num_bytes, start_addr));
9800 goto err;
9801 }
9802 }
9803 else {
9804 bytes_to_write = 0x1000 - offset_addr;
9805 bcm_error = dhdsdio_membytes(bus, TRUE, start_addr, mem_ptr,
9806 bytes_to_write);
9807 if (bcm_error) {
9808 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
9809 __FUNCTION__, bcm_error, num_bytes, start_addr));
9810 goto err;
9811 }
9812
9813 OSL_DELAY(10000);
9814
9815 bcm_error = dhdsdio_membytes(bus, TRUE, (start_addr + bytes_to_write),
9816 (mem_ptr + bytes_to_write), (index - bytes_to_write));
9817 if (bcm_error) {
9818 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
9819 __FUNCTION__, bcm_error, num_bytes, start_addr));
9820 goto err;
9821 }
9822 }
9823 memset(line, 0, BTFW_MAX_STR_LEN);
9824 }
9825
9826 bcm_error = 0;
9827err:
9828 if (mem_blk)
9829 MFREE(bus->dhd->osh, mem_blk, BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN);
9830
9831 if (data_ptr)
9832 MFREE(bus->dhd->osh, data_ptr, BTFW_DOWNLOAD_BLK_SIZE - 8);
9833
9834 if (line)
9835 MFREE(bus->dhd->osh, line, BTFW_MAX_STR_LEN);
9836
9837 if (image)
9838 dhd_os_close_image(image);
9839
9840 return bcm_error;
9841}
9842
9843static int
9844dhdsdio_download_btfw(struct dhd_bus *bus, osl_t *osh, void *sdh)
9845{
9846 int ret;
9847
9848 DHD_TRACE(("%s: btfw path=%s\n",
9849 __FUNCTION__, bus->btfw_path));
9850 DHD_OS_WAKE_LOCK(bus->dhd);
9851 dhd_os_sdlock(bus->dhd);
9852
9853 /* Download the firmware */
9854 ret = _dhdsdio_download_btfw(bus);
9855
9856 dhd_os_sdunlock(bus->dhd);
9857 DHD_OS_WAKE_UNLOCK(bus->dhd);
9858
9859 return ret;
9860}
9861
9862int
9863dhd_bus_download_btfw(struct dhd_bus *bus, osl_t *osh,
9864 char *pbtfw_path)
9865{
9866 int ret;
9867
9868 bus->btfw_path = pbtfw_path;
9869
9870 ret = dhdsdio_download_btfw(bus, osh, bus->sdh);
9871
9872 return ret;
9873}
9874#endif /* defined (BT_OVER_SDIO) */
9875
9876void
9877dhd_bus_dump_trap_info(dhd_bus_t *bus, struct bcmstrbuf *strbuf)
9878{
9879 trap_t *tr = &bus->dhd->last_trap_info;
9880
9881 bcm_bprintf(strbuf,
9882 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
9883 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
9884 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
9885 "r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
9886 ltoh32(tr->type), ltoh32(tr->epc), ltoh32(tr->cpsr), ltoh32(tr->spsr),
9887 ltoh32(tr->r13), ltoh32(tr->r14), ltoh32(tr->pc),
9888 ltoh32(bus->dongle_trap_addr),
9889 ltoh32(tr->r0), ltoh32(tr->r1), ltoh32(tr->r2), ltoh32(tr->r3),
9890 ltoh32(tr->r4), ltoh32(tr->r5), ltoh32(tr->r6), ltoh32(tr->r7));
9891
9892}
9893
9894static int
9895dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len)
9896{
9897 int ret = -1;
9898
9899 ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(((dhd_bus_t*)bus)->sdh),
9900 SDIO_FUNC_2, F2SYNC, frame, len, NULL, NULL, NULL, TXRETRIES);
9901
9902 if (ret == BCME_OK)
9903 ((dhd_bus_t*)bus)->tx_seq = (((dhd_bus_t*)bus)->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
9904
9905 return ret;
9906}
9907
9908/* Function to set the min res mask depending on the chip ID used */
9909bool
9910dhd_bus_set_default_min_res_mask(struct dhd_bus *bus)
9911{
9912 if ((bus == NULL) || (bus->sih == NULL)) {
9913 DHD_ERROR(("%s(): Invalid Arguments \r\n", __FUNCTION__));
9914 return FALSE;
9915 }
9916
9917 switch (bus->sih->chip) {
9918 case BCM4339_CHIP_ID:
9919 bcmsdh_reg_write(bus->sdh, SI_ENUM_BASE + 0x618, 4, 0x3fcaf377);
9920 if (bcmsdh_regfail(bus->sdh)) {
9921 DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
9922 return FALSE;
9923 }
9924 break;
9925
9926 case BCM43012_CHIP_ID:
9927 bcmsdh_reg_write(bus->sdh,
9928 si_get_pmu_reg_addr(bus->sih, OFFSETOF(pmuregs_t, min_res_mask)),
9929 4, DEFAULT_43012_MIN_RES_MASK);
9930 if (bcmsdh_regfail(bus->sdh)) {
9931 DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
9932 return FALSE;
9933 }
9934 break;
9935
9936 default:
9937 DHD_ERROR(("%s: Unhandled chip id\n", __FUNCTION__));
9938 return FALSE;
9939 }
9940
9941 return TRUE;
9942}
9943
9944/* Function to reset PMU registers */
9945void
9946dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp)
9947{
9948 struct dhd_bus *bus = dhdp->bus;
9949 bcmsdh_reg_write(bus->sdh, si_get_pmu_reg_addr(bus->sih,
9950 OFFSETOF(pmuregs_t, swscratch)), 4, 0x0);
9951 if (bcmsdh_regfail(bus->sdh)) {
9952 DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__));
9953 }
9954}
9955
9956
9957#ifdef DHD_ULP
9958/* Function to disable console messages on entering ULP mode */
9959void
9960dhd_bus_ulp_disable_console(dhd_pub_t *dhdp)
9961{
9962#ifdef DHD_DEBUG
9963 DHD_ERROR(("Flushing and disabling console messages\n"));
9964
9965 /* Save the console print interval */
9966 dhd_ulp_save_console_interval(dhdp);
9967
9968 /* Flush the console buffer before disabling */
9969 dhdsdio_readconsole(dhdp->bus);
9970 dhd_console_ms = 0;
9971#endif /* DHD_DEBUG */
9972}
9973
9974/* Function for redownloading firmaware */
9975static int
9976dhd_bus_ulp_reinit_fw(dhd_bus_t *bus)
9977{
9978 int bcmerror = 0;
9979
9980 /* After firmware redownload tx/rx seq are reset accordingly these values are
9981 reset on DHD side tx_max is initially set to 4, which later is updated by FW
9982 */
9983 bus->tx_seq = bus->rx_seq = 0;
9984 bus->tx_max = 4;
9985
9986 if (dhd_bus_download_firmware(bus, bus->dhd->osh,
9987 bus->fw_path, bus->nv_path) >= 0) {
9988
9989 /* Re-init bus, enable F2 transfer */
9990 bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
9991 if (bcmerror == BCME_OK) {
9992 bus->dhd->up = TRUE;
9993 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
9994
9995 dhd_ulp_set_ulp_state(bus->dhd, DHD_ULP_READY);
9996#if defined(OOB_INTR_ONLY)
9997 dhd_enable_oob_intr(bus, TRUE);
9998 bcmsdh_oob_intr_set(bus->sdh, TRUE);
9999#endif
10000#ifdef DHD_DEBUG
10001 /* Re-enable the console messages on FW redownload to default value */
10002 dhd_ulp_restore_console_interval(bus->dhd);
10003#endif /* DHD_DEBUG */
10004 } else {
10005 DHD_ERROR(("bus init failed\n"));
10006 dhd_bus_stop(bus, FALSE);
10007 dhdsdio_release_dongle(bus, bus->dhd->osh,
10008 TRUE, FALSE);
10009 }
10010 } else
10011 bcmerror = BCME_SDIO_ERROR;
10012
10013 return bcmerror;
10014}
10015#endif /* DHD_ULP */
10016
10017int
10018dhd_bus_readwrite_bp_addr(dhd_pub_t *dhdp, uint addr, uint size, uint* data, bool read)
10019{
10020 int bcmerror = 0;
10021 struct dhd_bus *bus = dhdp->bus;
10022
10023 if (read) {
10024 *data = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
10025 } else {
10026 bcmsdh_reg_write(bus->sdh, addr, size, *data);
10027 }
10028
10029 if (bcmsdh_regfail(bus->sdh))
10030 bcmerror = BCME_SDIO_ERROR;
10031
10032 return bcmerror;
10033}
10034
10035int dhd_get_idletime(dhd_pub_t *dhd)
10036{
10037 return dhd->bus->idletime;
10038}
10039
10040#ifdef DHD_WAKE_STATUS
10041wake_counts_t*
10042dhd_bus_get_wakecount(dhd_pub_t *dhd)
10043{
10044 if (!dhd->bus) {
10045 return NULL;
10046 }
10047 return &dhd->bus->wake_counts;
10048}
10049int
10050dhd_bus_get_bus_wake(dhd_pub_t *dhd)
10051{
10052 return bcmsdh_set_get_wake(dhd->bus->sdh, 0);
10053}
10054#endif /* DHD_WAKE_STATUS */