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010c3a89 RC |
1 | /* |
2 | * DHD Bus Module for SDIO | |
3 | * | |
4 | * Copyright (C) 1999-2017, Broadcom Corporation | |
5 | * | |
6 | * Unless you and Broadcom execute a separate written software license | |
7 | * agreement governing use of this software, this software is licensed to you | |
8 | * under the terms of the GNU General Public License version 2 (the "GPL"), | |
9 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the | |
10 | * following added to such license: | |
11 | * | |
12 | * As a special exception, the copyright holders of this software give you | |
13 | * permission to link this software with independent modules, and to copy and | |
14 | * distribute the resulting executable under terms of your choice, provided that | |
15 | * you also meet, for each linked independent module, the terms and conditions of | |
16 | * the license of that module. An independent module is a module which is not | |
17 | * derived from this software. The special exception does not apply to any | |
18 | * modifications of the software. | |
19 | * | |
20 | * Notwithstanding the above, under no circumstances may you combine this | |
21 | * software in any way with any other Broadcom software provided under a license | |
22 | * other than the GPL, without Broadcom's express prior written consent. | |
23 | * | |
24 | * | |
25 | * <<Broadcom-WL-IPTag/Open:>> | |
26 | * | |
27 | * $Id: dhd_sdio.c 705650 2017-06-19 03:00:50Z $ | |
28 | */ | |
29 | ||
30 | #include <typedefs.h> | |
31 | #include <osl.h> | |
32 | #include <bcmsdh.h> | |
33 | ||
34 | #ifdef BCMEMBEDIMAGE | |
35 | #include BCMEMBEDIMAGE | |
36 | #endif /* BCMEMBEDIMAGE */ | |
37 | ||
38 | #include <bcmdefs.h> | |
39 | #include <bcmutils.h> | |
40 | #include <bcmendian.h> | |
41 | #include <bcmdevs.h> | |
42 | ||
43 | #include <siutils.h> | |
44 | #include <hndpmu.h> | |
45 | #include <hndsoc.h> | |
46 | #include <bcmsdpcm.h> | |
47 | #include <hnd_armtrap.h> | |
48 | #include <hnd_cons.h> | |
49 | #include <sbchipc.h> | |
50 | #include <sbhnddma.h> | |
51 | ||
52 | #include <sdio.h> | |
53 | #include <sbsdio.h> | |
54 | #include <sbsdpcmdev.h> | |
55 | #include <bcmsdpcm.h> | |
56 | #include <bcmsdbus.h> | |
57 | ||
58 | #include <ethernet.h> | |
59 | #include <802.1d.h> | |
60 | #include <802.11.h> | |
61 | ||
62 | #include <dngl_stats.h> | |
63 | #include <dhd.h> | |
64 | #include <dhd_bus.h> | |
65 | #include <dhd_proto.h> | |
66 | #include <dhd_dbg.h> | |
67 | #include <dhdioctl.h> | |
68 | #include <sdiovar.h> | |
69 | #include <dhd_config.h> | |
70 | ||
71 | #ifdef PROP_TXSTATUS | |
72 | #include <dhd_wlfc.h> | |
73 | #endif | |
74 | #ifdef DHDTCPACK_SUPPRESS | |
75 | #include <dhd_ip.h> | |
76 | #endif /* DHDTCPACK_SUPPRESS */ | |
77 | ||
78 | #ifdef BT_OVER_SDIO | |
79 | #include <dhd_bt_interface.h> | |
80 | #endif /* BT_OVER_SDIO */ | |
81 | ||
82 | bool dhd_mp_halting(dhd_pub_t *dhdp); | |
83 | extern void bcmsdh_waitfor_iodrain(void *sdh); | |
84 | extern void bcmsdh_reject_ioreqs(void *sdh, bool reject); | |
85 | extern bool bcmsdh_fatal_error(void *sdh); | |
86 | static int dhdsdio_suspend(void *context); | |
87 | static int dhdsdio_resume(void *context); | |
88 | ||
89 | ||
90 | #ifndef DHDSDIO_MEM_DUMP_FNAME | |
91 | #define DHDSDIO_MEM_DUMP_FNAME "mem_dump" | |
92 | #endif | |
93 | ||
94 | #define QLEN (1024) /* bulk rx and tx queue lengths */ | |
95 | #define FCHI (QLEN - 10) | |
96 | #define FCLOW (FCHI / 2) | |
97 | #define PRIOMASK 7 | |
98 | ||
99 | #define F0_BLOCK_SIZE 32 | |
100 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
101 | #define READ_FRM_CNT_RETRIES 3 | |
102 | #ifndef DHD_RXBOUND | |
103 | #define DHD_RXBOUND 50 /* Default for max rx frames in one scheduling */ | |
104 | #endif | |
105 | ||
106 | #ifndef DHD_TXBOUND | |
107 | #define DHD_TXBOUND 20 /* Default for max tx frames in one scheduling */ | |
108 | #endif | |
109 | ||
110 | #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
111 | ||
112 | #define MEMBLOCK 2048 /* Block size used for downloading of dongle image */ | |
113 | #define MAX_MEMBLOCK (32 * 1024) /* Block size used for downloading of dongle image */ | |
114 | ||
115 | #define MAX_DATA_BUF (64 * 1024) /* Must be large enough to hold biggest possible glom */ | |
07d6b24a | 116 | #define MAX_MEM_BUF 4096 |
010c3a89 RC |
117 | |
118 | #ifndef DHD_FIRSTREAD | |
119 | #define DHD_FIRSTREAD 32 | |
120 | #endif | |
121 | #if !ISPOWEROF2(DHD_FIRSTREAD) | |
122 | #error DHD_FIRSTREAD is not a power of 2! | |
123 | #endif | |
124 | ||
125 | /* Total length of frame header for dongle protocol */ | |
126 | #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN) | |
127 | #define SDPCM_HDRLEN_TXGLOM (SDPCM_HDRLEN + SDPCM_HWEXT_LEN) | |
128 | #define MAX_TX_PKTCHAIN_CNT SDPCM_MAXGLOM_SIZE | |
129 | ||
130 | #ifdef SDTEST | |
131 | #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN) | |
132 | #else | |
133 | #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN) | |
134 | #endif | |
135 | ||
136 | /* Space for header read, limit for data packets */ | |
137 | #ifndef MAX_HDR_READ | |
138 | #define MAX_HDR_READ 32 | |
139 | #endif | |
140 | #if !ISPOWEROF2(MAX_HDR_READ) | |
141 | #error MAX_HDR_READ is not a power of 2! | |
142 | #endif | |
143 | ||
144 | #define MAX_RX_DATASZ 2048 | |
145 | ||
146 | /* Maximum milliseconds to wait for F2 to come up */ | |
147 | #define DHD_WAIT_F2RDY 3000 | |
148 | ||
149 | /* Maximum usec to wait for HTAVAIL to come up */ | |
150 | #define DHD_WAIT_HTAVAIL 10000 | |
151 | ||
152 | /* Bump up limit on waiting for HT to account for first startup; | |
153 | * if the image is doing a CRC calculation before programming the PMU | |
154 | * for HT availability, it could take a couple hundred ms more, so | |
155 | * max out at a 1 second (1000000us). | |
156 | */ | |
157 | #if (PMU_MAX_TRANSITION_DLY <= 1000000) | |
158 | #undef PMU_MAX_TRANSITION_DLY | |
159 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
160 | #endif | |
161 | ||
162 | /* hooks for limiting threshold custom tx num in rx processing */ | |
163 | #define DEFAULT_TXINRX_THRES 0 | |
164 | #ifndef CUSTOM_TXINRX_THRES | |
165 | #define CUSTOM_TXINRX_THRES DEFAULT_TXINRX_THRES | |
166 | #endif | |
167 | ||
168 | /* Value for ChipClockCSR during initial setup */ | |
169 | #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ) | |
170 | #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP) | |
171 | ||
172 | /* Flags for SDH calls */ | |
173 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
174 | ||
175 | /* Packet free applicable unconditionally for sdio and sdspi. Conditional if | |
176 | * bufpool was present for gspi bus. | |
177 | */ | |
178 | #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \ | |
179 | PKTFREE(bus->dhd->osh, pkt, FALSE); | |
180 | DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep); | |
181 | ||
182 | #ifdef PKT_STATICS | |
183 | pkt_statics_t tx_statics = {0}; | |
184 | #endif | |
185 | ||
010c3a89 RC |
186 | #ifdef SUPPORT_MULTIPLE_BOARD_REV_FROM_HW |
187 | extern unsigned int system_hw_rev; | |
188 | #endif /* SUPPORT_MULTIPLE_BOARD_REV_FROM_HW */ | |
189 | ||
190 | /* Device console log buffer state */ | |
191 | #define CONSOLE_LINE_MAX 192 | |
192 | #define CONSOLE_BUFFER_MAX 2024 | |
193 | typedef struct dhd_console { | |
194 | uint count; /* Poll interval msec counter */ | |
195 | uint log_addr; /* Log struct address (fixed) */ | |
196 | hnd_log_t log; /* Log struct (host copy) */ | |
197 | uint bufsize; /* Size of log buffer */ | |
198 | uint8 *buf; /* Log buffer (host copy) */ | |
199 | uint last; /* Last buffer read index */ | |
200 | } dhd_console_t; | |
201 | ||
202 | #define REMAP_ENAB(bus) ((bus)->remap) | |
203 | #define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize))) | |
204 | #define KSO_ENAB(bus) ((bus)->kso) | |
205 | #define SR_ENAB(bus) ((bus)->_srenab) | |
206 | #define SLPAUTO_ENAB(bus) ((SR_ENAB(bus)) && ((bus)->_slpauto)) | |
207 | ||
208 | #define MIN_RSRC_SR 0x3 | |
209 | #define CORE_CAPEXT_ADDR_OFFSET (0x64c) | |
210 | #define CORE_CAPEXT_SR_SUPPORTED_MASK (1 << 1) | |
211 | #define RCTL_MACPHY_DISABLE_MASK (1 << 26) | |
212 | #define RCTL_LOGIC_DISABLE_MASK (1 << 27) | |
213 | ||
214 | #define OOB_WAKEUP_ENAB(bus) ((bus)->_oobwakeup) | |
215 | #define GPIO_DEV_SRSTATE 16 /* Host gpio17 mapped to device gpio0 SR state */ | |
216 | #define GPIO_DEV_SRSTATE_TIMEOUT 320000 /* 320ms */ | |
217 | #define GPIO_DEV_WAKEUP 17 /* Host gpio17 mapped to device gpio1 wakeup */ | |
218 | #define CC_CHIPCTRL2_GPIO1_WAKEUP (1 << 0) | |
219 | #define CC_CHIPCTRL3_SR_ENG_ENABLE (1 << 2) | |
220 | #define OVERFLOW_BLKSZ512_WM 96 | |
221 | #define OVERFLOW_BLKSZ512_MES 80 | |
222 | ||
223 | #define CC_PMUCC3 (0x3) | |
224 | ||
225 | #ifdef DHD_UCODE_DOWNLOAD | |
226 | /* Ucode host download related macros */ | |
227 | #define UCODE_DOWNLOAD_REQUEST 0xCAFECAFE | |
228 | #define UCODE_DOWNLOAD_COMPLETE 0xABCDABCD | |
229 | #endif /* DHD_UCODE_DOWNLOAD */ | |
230 | ||
231 | #if defined(BT_OVER_SDIO) | |
232 | #define BTMEM_OFFSET 0x19000000 | |
233 | /* BIT0 => WLAN Power UP and BIT1=> WLAN Wake */ | |
234 | #define BT2WLAN_PWRUP_WAKE 0x03 | |
235 | #define BT2WLAN_PWRUP_ADDR 0x640894 /* This address is specific to 43012B0 */ | |
236 | ||
237 | #define BTFW_MAX_STR_LEN 600 | |
238 | #define BTFW_DOWNLOAD_BLK_SIZE (BTFW_MAX_STR_LEN/2 + 8) | |
239 | ||
240 | #define BTFW_ADDR_MODE_UNKNOWN 0 | |
241 | #define BTFW_ADDR_MODE_EXTENDED 1 | |
242 | #define BTFW_ADDR_MODE_SEGMENT 2 | |
243 | #define BTFW_ADDR_MODE_LINEAR32 3 | |
244 | ||
245 | #define BTFW_HEX_LINE_TYPE_DATA 0 | |
246 | #define BTFW_HEX_LINE_TYPE_END_OF_DATA 1 | |
247 | #define BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS 2 | |
248 | #define BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS 4 | |
249 | #define BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS 5 | |
250 | ||
251 | #endif /* defined (BT_OVER_SDIO) */ | |
252 | ||
253 | /* Private data for SDIO bus interaction */ | |
254 | typedef struct dhd_bus { | |
255 | dhd_pub_t *dhd; | |
256 | ||
257 | bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */ | |
258 | si_t *sih; /* Handle for SI calls */ | |
259 | char *vars; /* Variables (from CIS and/or other) */ | |
260 | uint varsz; /* Size of variables buffer */ | |
261 | uint32 sbaddr; /* Current SB window pointer (-1, invalid) */ | |
262 | ||
263 | sdpcmd_regs_t *regs; /* Registers for SDIO core */ | |
264 | uint sdpcmrev; /* SDIO core revision */ | |
265 | uint armrev; /* CPU core revision */ | |
266 | uint ramrev; /* SOCRAM core revision */ | |
267 | uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
268 | uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
269 | uint32 srmemsize; /* Size of SRMEM */ | |
270 | ||
271 | uint32 bus; /* gSPI or SDIO bus */ | |
272 | uint32 bus_num; /* bus number */ | |
273 | uint32 slot_num; /* slot ID */ | |
274 | uint32 hostintmask; /* Copy of Host Interrupt Mask */ | |
275 | uint32 intstatus; /* Intstatus bits (events) pending */ | |
276 | bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ | |
277 | bool fcstate; /* State of dongle flow-control */ | |
278 | ||
279 | uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */ | |
280 | char *fw_path; /* module_param: path to firmware image */ | |
281 | char *nv_path; /* module_param: path to nvram vars file */ | |
282 | ||
283 | uint blocksize; /* Block size of SDIO transfers */ | |
284 | uint roundup; /* Max roundup limit */ | |
285 | ||
286 | struct pktq txq; /* Queue length used for flow-control */ | |
287 | uint8 flowcontrol; /* per prio flow control bitmask */ | |
288 | uint8 tx_seq; /* Transmit sequence number (next) */ | |
289 | uint8 tx_max; /* Maximum transmit sequence allowed */ | |
290 | ||
291 | uint8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN]; | |
292 | uint8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ | |
293 | uint16 nextlen; /* Next Read Len from last header */ | |
294 | uint8 rx_seq; /* Receive sequence number (expected) */ | |
295 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ | |
296 | ||
297 | void *glomd; /* Packet containing glomming descriptor */ | |
298 | void *glom; /* Packet chain for glommed superframe */ | |
299 | uint glomerr; /* Glom packet read errors */ | |
300 | ||
301 | uint8 *rxbuf; /* Buffer for receiving control packets */ | |
302 | uint rxblen; /* Allocated length of rxbuf */ | |
303 | uint8 *rxctl; /* Aligned pointer into rxbuf */ | |
304 | uint8 *databuf; /* Buffer for receiving big glom packet */ | |
305 | uint8 *dataptr; /* Aligned pointer into databuf */ | |
306 | uint rxlen; /* Length of valid data in buffer */ | |
307 | ||
308 | uint8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
309 | ||
310 | bool intr; /* Use interrupts */ | |
311 | bool poll; /* Use polling */ | |
312 | bool ipend; /* Device interrupt is pending */ | |
313 | bool intdis; /* Interrupts disabled by isr */ | |
314 | uint intrcount; /* Count of device interrupt callbacks */ | |
315 | uint lastintrs; /* Count as of last watchdog timer */ | |
316 | uint spurious; /* Count of spurious interrupts */ | |
317 | uint pollrate; /* Ticks between device polls */ | |
318 | uint polltick; /* Tick counter */ | |
319 | uint pollcnt; /* Count of active polls */ | |
320 | ||
321 | dhd_console_t console; /* Console output polling support */ | |
322 | uint console_addr; /* Console address from shared struct */ | |
323 | ||
324 | uint regfails; /* Count of R_REG/W_REG failures */ | |
325 | ||
326 | uint clkstate; /* State of sd and backplane clock(s) */ | |
327 | bool activity; /* Activity flag for clock down */ | |
328 | int32 idletime; /* Control for activity timeout */ | |
329 | int32 idlecount; /* Activity timeout counter */ | |
330 | int32 idleclock; /* How to set bus driver when idle */ | |
331 | int32 sd_divisor; /* Speed control to bus driver */ | |
332 | int32 sd_mode; /* Mode control to bus driver */ | |
333 | int32 sd_rxchain; /* If bcmsdh api accepts PKT chains */ | |
334 | bool use_rxchain; /* If dhd should use PKT chains */ | |
335 | bool sleeping; /* Is SDIO bus sleeping? */ | |
336 | #if defined(SUPPORT_P2P_GO_PS) | |
337 | wait_queue_head_t bus_sleep; | |
338 | #endif /* LINUX && SUPPORT_P2P_GO_PS */ | |
dfb0f3ae RC |
339 | bool ctrl_wait; |
340 | wait_queue_head_t ctrl_tx_wait; | |
010c3a89 RC |
341 | uint rxflow_mode; /* Rx flow control mode */ |
342 | bool rxflow; /* Is rx flow control on */ | |
343 | uint prev_rxlim_hit; /* Is prev rx limit exceeded (per dpc schedule) */ | |
344 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
345 | /* Field to decide if rx of control frames happen in rxbuf or lb-pool */ | |
346 | bool usebufpool; | |
347 | int32 txinrx_thres; /* num of in-queued pkts */ | |
348 | int32 dotxinrx; /* tx first in dhdsdio_readframes */ | |
349 | #ifdef SDTEST | |
350 | /* external loopback */ | |
351 | bool ext_loop; | |
352 | uint8 loopid; | |
353 | ||
354 | /* pktgen configuration */ | |
355 | uint pktgen_freq; /* Ticks between bursts */ | |
356 | uint pktgen_count; /* Packets to send each burst */ | |
357 | uint pktgen_print; /* Bursts between count displays */ | |
358 | uint pktgen_total; /* Stop after this many */ | |
359 | uint pktgen_minlen; /* Minimum packet data len */ | |
360 | uint pktgen_maxlen; /* Maximum packet data len */ | |
361 | uint pktgen_mode; /* Configured mode: tx, rx, or echo */ | |
362 | uint pktgen_stop; /* Number of tx failures causing stop */ | |
363 | ||
364 | /* active pktgen fields */ | |
365 | uint pktgen_tick; /* Tick counter for bursts */ | |
366 | uint pktgen_ptick; /* Burst counter for printing */ | |
367 | uint pktgen_sent; /* Number of test packets generated */ | |
368 | uint pktgen_rcvd; /* Number of test packets received */ | |
369 | uint pktgen_prev_time; /* Time at which previous stats where printed */ | |
370 | uint pktgen_prev_sent; /* Number of test packets generated when | |
371 | * previous stats were printed | |
372 | */ | |
373 | uint pktgen_prev_rcvd; /* Number of test packets received when | |
374 | * previous stats were printed | |
375 | */ | |
376 | uint pktgen_fail; /* Number of failed send attempts */ | |
377 | uint16 pktgen_len; /* Length of next packet to send */ | |
378 | #define PKTGEN_RCV_IDLE (0) | |
379 | #define PKTGEN_RCV_ONGOING (1) | |
380 | uint16 pktgen_rcv_state; /* receive state */ | |
381 | uint pktgen_rcvd_rcvsession; /* test pkts rcvd per rcv session. */ | |
382 | #endif /* SDTEST */ | |
383 | ||
384 | /* Some additional counters */ | |
385 | uint tx_sderrs; /* Count of tx attempts with sd errors */ | |
386 | uint fcqueued; /* Tx packets that got queued */ | |
387 | uint rxrtx; /* Count of rtx requests (NAK to dongle) */ | |
388 | uint rx_toolong; /* Receive frames too long to receive */ | |
389 | uint rxc_errors; /* SDIO errors when reading control frames */ | |
390 | uint rx_hdrfail; /* SDIO errors on header reads */ | |
391 | uint rx_badhdr; /* Bad received headers (roosync?) */ | |
392 | uint rx_badseq; /* Mismatched rx sequence number */ | |
393 | uint fc_rcvd; /* Number of flow-control events received */ | |
394 | uint fc_xoff; /* Number which turned on flow-control */ | |
395 | uint fc_xon; /* Number which turned off flow-control */ | |
396 | uint rxglomfail; /* Failed deglom attempts */ | |
397 | uint rxglomframes; /* Number of glom frames (superframes) */ | |
398 | uint rxglompkts; /* Number of packets from glom frames */ | |
399 | uint f2rxhdrs; /* Number of header reads */ | |
400 | uint f2rxdata; /* Number of frame data reads */ | |
401 | uint f2txdata; /* Number of f2 frame writes */ | |
402 | uint f1regdata; /* Number of f1 register accesses */ | |
403 | wake_counts_t wake_counts; /* Wake up counter */ | |
404 | #ifdef DHDENABLE_TAILPAD | |
405 | uint tx_tailpad_chain; /* Number of tail padding by chaining pad_pkt */ | |
406 | uint tx_tailpad_pktget; /* Number of tail padding by new PKTGET */ | |
407 | #endif /* DHDENABLE_TAILPAD */ | |
408 | uint8 *ctrl_frame_buf; | |
409 | uint32 ctrl_frame_len; | |
410 | bool ctrl_frame_stat; | |
411 | uint32 rxint_mode; /* rx interrupt mode */ | |
412 | bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram | |
413 | * Available with socram rev 16 | |
414 | * Remap region not DMA-able | |
415 | */ | |
416 | bool kso; | |
417 | bool _slpauto; | |
418 | bool _oobwakeup; | |
419 | bool _srenab; | |
420 | bool readframes; | |
421 | bool reqbussleep; | |
422 | uint32 resetinstr; | |
423 | uint32 dongle_ram_base; | |
424 | ||
425 | void *glom_pkt_arr[SDPCM_MAXGLOM_SIZE]; /* Array of pkts for glomming */ | |
426 | uint32 txglom_cnt; /* Number of pkts in the glom array */ | |
427 | uint32 txglom_total_len; /* Total length of pkts in glom array */ | |
428 | bool txglom_enable; /* Flag to indicate whether tx glom is enabled/disabled */ | |
429 | uint32 txglomsize; /* Glom size limitation */ | |
430 | #ifdef DHDENABLE_TAILPAD | |
431 | void *pad_pkt; | |
432 | #endif /* DHDENABLE_TAILPAD */ | |
433 | uint32 dongle_trap_addr; /* device trap addr location in device memory */ | |
434 | #if defined(BT_OVER_SDIO) | |
435 | char *btfw_path; /* module_param: path to BT firmware image */ | |
436 | uint32 bt_use_count; /* Counter that tracks whether BT is using the bus */ | |
437 | #endif /* defined (BT_OVER_SDIO) */ | |
438 | uint txglomframes; /* Number of tx glom frames (superframes) */ | |
439 | uint txglompkts; /* Number of packets from tx glom frames */ | |
32c27b7a | 440 | uint8 *membuf; /* Buffer for dhdsdio_membytes */ |
010c3a89 RC |
441 | } dhd_bus_t; |
442 | ||
443 | ||
444 | /* | |
445 | * Whenever DHD_IDLE_IMMEDIATE condition is handled, we have to now check if | |
446 | * BT is active too. Instead of adding #ifdef code in all the places, we thought | |
447 | * of adding one macro check as part of the if condition that checks for DHD_IDLE_IMMEDIATE | |
448 | * In case of non BT over SDIO builds, this macro will always return TRUE. In case | |
449 | * of the builds where BT_OVER_SDIO is enabled, it will expand to a condition check | |
450 | * that checks if bt_use_count is zero. So this macro will return equate to 1 if | |
451 | * bt_use_count is 0, indicating that there are no active users and if bt_use_count | |
452 | * is non zero it would return 0 there by preventing the caller from executing the | |
453 | * sleep calls. | |
454 | */ | |
455 | #ifdef BT_OVER_SDIO | |
456 | #define NO_OTHER_ACTIVE_BUS_USER(bus) (bus->bt_use_count == 0) | |
457 | #else | |
458 | #define NO_OTHER_ACTIVE_BUS_USER(bus) (1) | |
459 | #endif /* BT_OVER_SDIO */ | |
460 | ||
461 | /* clkstate */ | |
462 | #define CLK_NONE 0 | |
463 | #define CLK_SDONLY 1 | |
464 | #define CLK_PENDING 2 /* Not used yet */ | |
465 | #define CLK_AVAIL 3 | |
466 | ||
467 | #define DHD_NOPMU(dhd) (FALSE) | |
468 | ||
469 | #if defined(BCMSDIOH_STD) | |
470 | #define BLK_64_MAXTXGLOM 20 | |
471 | #endif /* BCMSDIOH_STD */ | |
472 | ||
473 | #ifdef DHD_DEBUG | |
474 | static int qcount[NUMPRIO]; | |
475 | static int tx_packets[NUMPRIO]; | |
476 | #endif /* DHD_DEBUG */ | |
477 | ||
478 | /* Deferred transmit */ | |
479 | const uint dhd_deferred_tx = 1; | |
480 | ||
481 | extern uint dhd_watchdog_ms; | |
482 | extern uint sd_f1_blocksize; | |
483 | ||
484 | ||
485 | #if defined(BT_OVER_SDIO) | |
486 | extern dhd_pub_t *g_dhd_pub; | |
487 | #endif /* (BT_OVER_SDIO) */ | |
488 | extern void dhd_os_wd_timer(void *bus, uint wdtick); | |
489 | int dhd_enableOOB(dhd_pub_t *dhd, bool sleep); | |
490 | ||
491 | ||
492 | /* Tx/Rx bounds */ | |
493 | uint dhd_txbound; | |
494 | uint dhd_rxbound; | |
495 | uint dhd_txminmax = DHD_TXMINMAX; | |
496 | ||
497 | /* override the RAM size if possible */ | |
498 | #define DONGLE_MIN_RAMSIZE (128 *1024) | |
499 | int dhd_dongle_ramsize; | |
500 | ||
501 | uint dhd_doflow = TRUE; | |
502 | uint dhd_dpcpoll = FALSE; | |
503 | ||
504 | module_param(dhd_doflow, uint, 0644); | |
505 | module_param(dhd_dpcpoll, uint, 0644); | |
506 | ||
507 | static bool dhd_alignctl; | |
508 | ||
509 | static bool sd1idle; | |
510 | ||
511 | static bool retrydata; | |
512 | #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata) | |
513 | ||
514 | static uint watermark = 8; | |
515 | static uint mesbusyctrl = 0; | |
516 | static const uint firstread = DHD_FIRSTREAD; | |
517 | ||
518 | /* Retry count for register access failures */ | |
519 | static const uint retry_limit = 2; | |
520 | ||
521 | /* Force even SD lengths (some host controllers mess up on odd bytes) */ | |
522 | static bool forcealign; | |
523 | ||
524 | #define ALIGNMENT 4 | |
525 | ||
526 | #if (defined(OOB_INTR_ONLY) && defined(HW_OOB)) || defined(FORCE_WOWLAN) | |
527 | extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable); | |
528 | #endif | |
529 | ||
530 | #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) | |
531 | #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD | |
532 | #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */ | |
533 | #define PKTALIGN(osh, p, len, align) \ | |
534 | do { \ | |
535 | uintptr datalign; \ | |
536 | datalign = (uintptr)PKTDATA((osh), (p)); \ | |
537 | datalign = ROUNDUP(datalign, (align)) - datalign; \ | |
538 | ASSERT(datalign < (align)); \ | |
539 | ASSERT(PKTLEN((osh), (p)) >= ((len) + datalign)); \ | |
540 | if (datalign) \ | |
541 | PKTPULL((osh), (p), (uint)datalign); \ | |
542 | PKTSETLEN((osh), (p), (len)); \ | |
543 | } while (0) | |
544 | ||
545 | /* Limit on rounding up frames */ | |
546 | static const uint max_roundup = 512; | |
547 | ||
548 | /* Try doing readahead */ | |
549 | static bool dhd_readahead; | |
550 | ||
551 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
552 | bool | |
553 | dhdsdio_is_dataok(dhd_bus_t *bus) { | |
554 | return (((uint8)(bus->tx_max - bus->tx_seq) - bus->dhd->conf->tx_max_offset > 1) && \ | |
555 | (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0)); | |
556 | } | |
557 | ||
558 | uint8 | |
559 | dhdsdio_get_databufcnt(dhd_bus_t *bus) { | |
560 | return ((uint8)(bus->tx_max - bus->tx_seq) - 1 - bus->dhd->conf->tx_max_offset); | |
561 | } | |
562 | #endif | |
563 | ||
564 | /* To check if there's window offered */ | |
565 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
566 | #define DATAOK(bus) dhdsdio_is_dataok(bus) | |
567 | #else | |
568 | #define DATAOK(bus) \ | |
569 | (((uint8)(bus->tx_max - bus->tx_seq) > 1) && \ | |
570 | (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0)) | |
571 | #endif | |
572 | ||
573 | /* To check if there's window offered for ctrl frame */ | |
574 | #define TXCTLOK(bus) \ | |
575 | (((uint8)(bus->tx_max - bus->tx_seq) != 0) && \ | |
576 | (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0)) | |
577 | ||
578 | /* Number of pkts available in dongle for data RX */ | |
579 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
580 | #define DATABUFCNT(bus) dhdsdio_get_databufcnt(bus) | |
581 | #else | |
582 | #define DATABUFCNT(bus) \ | |
583 | ((uint8)(bus->tx_max - bus->tx_seq) - 1) | |
584 | #endif | |
585 | ||
586 | /* Macros to get register read/write status */ | |
587 | /* NOTE: these assume a local dhdsdio_bus_t *bus! */ | |
588 | #define R_SDREG(regvar, regaddr, retryvar) \ | |
589 | do { \ | |
590 | retryvar = 0; \ | |
591 | do { \ | |
592 | regvar = R_REG(bus->dhd->osh, regaddr); \ | |
593 | } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \ | |
594 | if (retryvar) { \ | |
595 | bus->regfails += (retryvar-1); \ | |
596 | if (retryvar > retry_limit) { \ | |
597 | DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \ | |
598 | __FUNCTION__, __LINE__)); \ | |
599 | regvar = 0; \ | |
600 | } \ | |
601 | } \ | |
602 | } while (0) | |
603 | ||
604 | #define W_SDREG(regval, regaddr, retryvar) \ | |
605 | do { \ | |
606 | retryvar = 0; \ | |
607 | do { \ | |
608 | W_REG(bus->dhd->osh, regaddr, regval); \ | |
609 | } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \ | |
610 | if (retryvar) { \ | |
611 | bus->regfails += (retryvar-1); \ | |
612 | if (retryvar > retry_limit) \ | |
613 | DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \ | |
614 | __FUNCTION__, __LINE__)); \ | |
615 | } \ | |
616 | } while (0) | |
617 | ||
618 | #define BUS_WAKE(bus) \ | |
619 | do { \ | |
620 | bus->idlecount = 0; \ | |
621 | if ((bus)->sleeping) \ | |
622 | dhdsdio_bussleep((bus), FALSE); \ | |
623 | } while (0); | |
624 | ||
625 | /* | |
626 | * pktavail interrupts from dongle to host can be managed in 3 different ways | |
627 | * whenever there is a packet available in dongle to transmit to host. | |
628 | * | |
629 | * Mode 0: Dongle writes the software host mailbox and host is interrupted. | |
630 | * Mode 1: (sdiod core rev >= 4) | |
631 | * Device sets a new bit in the intstatus whenever there is a packet | |
632 | * available in fifo. Host can't clear this specific status bit until all the | |
633 | * packets are read from the FIFO. No need to ack dongle intstatus. | |
634 | * Mode 2: (sdiod core rev >= 4) | |
635 | * Device sets a bit in the intstatus, and host acks this by writing | |
636 | * one to this bit. Dongle won't generate anymore packet interrupts | |
637 | * until host reads all the packets from the dongle and reads a zero to | |
638 | * figure that there are no more packets. No need to disable host ints. | |
639 | * Need to ack the intstatus. | |
640 | */ | |
641 | ||
642 | #define SDIO_DEVICE_HMB_RXINT 0 /* default old way */ | |
643 | #define SDIO_DEVICE_RXDATAINT_MODE_0 1 /* from sdiod rev 4 */ | |
644 | #define SDIO_DEVICE_RXDATAINT_MODE_1 2 /* from sdiod rev 4 */ | |
645 | ||
646 | ||
647 | #define FRAME_AVAIL_MASK(bus) \ | |
648 | ((bus->rxint_mode == SDIO_DEVICE_HMB_RXINT) ? I_HMB_FRAME_IND : I_XMTDATA_AVAIL) | |
649 | ||
650 | #define DHD_BUS SDIO_BUS | |
651 | ||
652 | #define PKT_AVAILABLE(bus, intstatus) ((intstatus) & (FRAME_AVAIL_MASK(bus))) | |
653 | ||
654 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) | |
655 | ||
656 | #define GSPI_PR55150_BAILOUT | |
657 | ||
658 | #ifdef SDTEST | |
659 | static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq); | |
660 | static void dhdsdio_sdtest_set(dhd_bus_t *bus, uint count); | |
661 | #endif | |
662 | ||
663 | static int dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size); | |
664 | #ifdef DHD_DEBUG | |
665 | static int dhd_serialconsole(dhd_bus_t *bus, bool get, bool enable, int *bcmerror); | |
666 | #endif /* DHD_DEBUG */ | |
667 | ||
668 | #if defined(DHD_FW_COREDUMP) | |
669 | static int dhdsdio_mem_dump(dhd_bus_t *bus); | |
670 | #endif /* DHD_FW_COREDUMP */ | |
671 | static int dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap); | |
672 | static int dhdsdio_download_state(dhd_bus_t *bus, bool enter); | |
673 | ||
674 | static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh); | |
675 | static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh); | |
676 | static void dhdsdio_disconnect(void *ptr); | |
677 | static bool dhdsdio_chipmatch(uint16 chipid); | |
678 | static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh, | |
679 | void * regsva, uint16 devid); | |
680 | static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh); | |
681 | static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh); | |
682 | static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, | |
683 | bool reset_flag); | |
684 | ||
685 | static void dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size); | |
686 | static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, | |
687 | uint8 *buf, uint nbytes, | |
688 | void *pkt, bcmsdh_cmplt_fn_t complete, void *handle); | |
689 | static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, | |
690 | uint8 *buf, uint nbytes, | |
691 | void *pkt, bcmsdh_cmplt_fn_t complete, void *handle, int max_retry); | |
692 | static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt); | |
693 | static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq, | |
694 | int prev_chain_total_len, bool last_chained_pkt, | |
695 | int *pad_pkt_len, void **new_pkt | |
696 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
91a2c117 | 697 | , int first_frame |
010c3a89 RC |
698 | #endif |
699 | ); | |
700 | static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt); | |
701 | ||
702 | static int dhdsdio_download_firmware(dhd_bus_t *bus, osl_t *osh, void *sdh); | |
703 | static int _dhdsdio_download_firmware(dhd_bus_t *bus); | |
704 | ||
705 | #ifdef DHD_UCODE_DOWNLOAD | |
706 | static int dhdsdio_download_ucode_file(struct dhd_bus *bus, char *ucode_path); | |
707 | #endif /* DHD_UCODE_DOWNLOAD */ | |
708 | static int dhdsdio_download_code_file(dhd_bus_t *bus, char *image_path); | |
709 | static int dhdsdio_download_nvram(dhd_bus_t *bus); | |
710 | #ifdef BCMEMBEDIMAGE | |
711 | static int dhdsdio_download_code_array(dhd_bus_t *bus); | |
712 | #endif | |
713 | static int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep); | |
714 | static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok); | |
715 | static uint8 dhdsdio_sleepcsr_get(dhd_bus_t *bus); | |
716 | static bool dhdsdio_dpc(dhd_bus_t *bus); | |
717 | static int dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len); | |
718 | static int dhdsdio_set_sdmode(dhd_bus_t *bus, int32 sd_mode); | |
719 | static int dhdsdio_sdclk(dhd_bus_t *bus, bool on); | |
720 | static void dhdsdio_advertise_bus_cleanup(dhd_pub_t *dhdp); | |
ccd15baf | 721 | static void dhdsdio_advertise_bus_remove(dhd_pub_t *dhdp); |
010c3a89 RC |
722 | #ifdef SUPPORT_MULTIPLE_BOARD_REV_FROM_DT |
723 | int dhd_get_system_rev(void); | |
724 | #endif /* SUPPORT_MULTIPLE_BOARD_REV_FROM_DT */ | |
725 | ||
726 | #ifdef WLMEDIA_HTSF | |
727 | #include <htsf.h> | |
728 | extern uint32 dhd_get_htsf(void *dhd, int ifidx); | |
729 | #endif /* WLMEDIA_HTSF */ | |
730 | ||
731 | #if defined(BT_OVER_SDIO) | |
732 | static int extract_hex_field(char * line, uint16 start_pos, uint16 num_chars, uint16 * value); | |
733 | static int read_more_btbytes(struct dhd_bus *bus, void * file, char *line, int * addr_mode, | |
734 | uint16 * hi_addr, uint32 * dest_addr, uint8 *data_bytes, uint32 * num_bytes); | |
735 | static int dhdsdio_download_btfw(struct dhd_bus *bus, osl_t *osh, void *sdh); | |
736 | static int _dhdsdio_download_btfw(struct dhd_bus *bus); | |
737 | #endif /* defined (BT_OVER_SDIO) */ | |
738 | ||
739 | #ifdef DHD_ULP | |
740 | #include <dhd_ulp.h> | |
741 | static int dhd_bus_ulp_reinit_fw(dhd_bus_t *bus); | |
742 | #endif /* DHD_ULP */ | |
743 | ||
744 | #ifdef DHD_WAKE_STATUS | |
745 | int bcmsdh_get_total_wake(bcmsdh_info_t *bcmsdh); | |
746 | int bcmsdh_set_get_wake(bcmsdh_info_t *bcmsdh, int flag); | |
747 | #endif /* DHD_WAKE_STATUS */ | |
748 | ||
749 | static void | |
750 | dhdsdio_tune_fifoparam(struct dhd_bus *bus) | |
751 | { | |
752 | int err; | |
753 | uint8 devctl, wm, mes; | |
754 | ||
755 | if (bus->sih->buscorerev >= 15) { | |
756 | /* See .ppt in PR for these recommended values */ | |
757 | if (bus->blocksize == 512) { | |
758 | wm = OVERFLOW_BLKSZ512_WM; | |
759 | mes = OVERFLOW_BLKSZ512_MES; | |
760 | } else { | |
761 | mes = bus->blocksize/4; | |
762 | wm = bus->blocksize/4; | |
763 | } | |
764 | ||
765 | watermark = wm; | |
766 | mesbusyctrl = mes; | |
767 | } else { | |
768 | DHD_INFO(("skip fifotune: SdioRev(%d) is lower than minimal requested ver\n", | |
769 | bus->sih->buscorerev)); | |
770 | return; | |
771 | } | |
772 | ||
773 | /* Update watermark */ | |
774 | if (wm > 0) { | |
775 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, wm, &err); | |
776 | ||
777 | devctl = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err); | |
778 | devctl |= SBSDIO_DEVCTL_F2WM_ENAB; | |
779 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err); | |
780 | } | |
781 | ||
782 | /* Update MES */ | |
783 | if (mes > 0) { | |
784 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL, | |
785 | (mes | SBSDIO_MESBUSYCTRL_ENAB), &err); | |
786 | } | |
787 | ||
788 | DHD_INFO(("Apply overflow WAR: 0x%02x 0x%02x 0x%02x\n", | |
789 | bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err), | |
790 | bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, &err), | |
791 | bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL, &err))); | |
792 | } | |
793 | ||
794 | static void | |
795 | dhd_dongle_setramsize(struct dhd_bus *bus, int mem_size) | |
796 | { | |
797 | int32 min_size = DONGLE_MIN_RAMSIZE; | |
798 | /* Restrict the ramsize to user specified limit */ | |
799 | DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n", | |
800 | dhd_dongle_ramsize, min_size)); | |
801 | if ((dhd_dongle_ramsize > min_size) && | |
802 | (dhd_dongle_ramsize < (int32)bus->orig_ramsize)) | |
803 | bus->ramsize = dhd_dongle_ramsize; | |
804 | } | |
805 | ||
806 | static int | |
807 | dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address) | |
808 | { | |
809 | int err = 0; | |
810 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, | |
811 | (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err); | |
812 | if (!err) | |
813 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, | |
814 | (address >> 16) & SBSDIO_SBADDRMID_MASK, &err); | |
815 | if (!err) | |
816 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, | |
817 | (address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err); | |
818 | return err; | |
819 | } | |
820 | ||
821 | ||
822 | #ifdef USE_OOB_GPIO1 | |
823 | static int | |
824 | dhdsdio_oobwakeup_init(dhd_bus_t *bus) | |
825 | { | |
826 | uint32 val, addr, data; | |
827 | ||
828 | bcmsdh_gpioouten(bus->sdh, GPIO_DEV_WAKEUP); | |
829 | ||
830 | addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr); | |
831 | data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data); | |
832 | ||
833 | /* Set device for gpio1 wakeup */ | |
834 | bcmsdh_reg_write(bus->sdh, addr, 4, 2); | |
835 | val = bcmsdh_reg_read(bus->sdh, data, 4); | |
836 | val |= CC_CHIPCTRL2_GPIO1_WAKEUP; | |
837 | bcmsdh_reg_write(bus->sdh, data, 4, val); | |
838 | ||
839 | bus->_oobwakeup = TRUE; | |
840 | ||
841 | return 0; | |
842 | } | |
843 | #endif /* USE_OOB_GPIO1 */ | |
844 | ||
845 | /* | |
846 | * Query if FW is in SR mode | |
847 | */ | |
848 | static bool | |
849 | dhdsdio_sr_cap(dhd_bus_t *bus) | |
850 | { | |
851 | bool cap = FALSE; | |
852 | uint32 core_capext, addr, data; | |
853 | ||
854 | if (bus->sih->chip == BCM43430_CHIP_ID || | |
855 | bus->sih->chip == BCM43018_CHIP_ID) { | |
856 | /* check if fw initialized sr engine */ | |
857 | addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, sr_control1); | |
858 | if (bcmsdh_reg_read(bus->sdh, addr, 4) != 0) | |
859 | cap = TRUE; | |
860 | ||
861 | return cap; | |
862 | } | |
863 | if (bus->sih->chip == BCM4324_CHIP_ID) { | |
864 | addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr); | |
865 | data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data); | |
866 | bcmsdh_reg_write(bus->sdh, addr, 4, 3); | |
867 | core_capext = bcmsdh_reg_read(bus->sdh, data, 4); | |
868 | } else if ((bus->sih->chip == BCM4330_CHIP_ID) || | |
869 | (bus->sih->chip == BCM43362_CHIP_ID) || | |
870 | (BCM4347_CHIP(bus->sih->chip))) { | |
871 | core_capext = FALSE; | |
872 | } else if ((bus->sih->chip == BCM4335_CHIP_ID) || | |
873 | (bus->sih->chip == BCM4339_CHIP_ID) || | |
874 | (bus->sih->chip == BCM43349_CHIP_ID) || | |
875 | BCM4345_CHIP(bus->sih->chip) || | |
876 | (bus->sih->chip == BCM4354_CHIP_ID) || | |
877 | (bus->sih->chip == BCM4358_CHIP_ID) || | |
878 | (bus->sih->chip == BCM43569_CHIP_ID) || | |
879 | (bus->sih->chip == BCM4371_CHIP_ID) || | |
880 | (BCM4349_CHIP(bus->sih->chip)) || | |
881 | (bus->sih->chip == BCM4350_CHIP_ID) || | |
dfb0f3ae RC |
882 | (bus->sih->chip == BCM43012_CHIP_ID) || |
883 | (bus->sih->chip == BCM4362_CHIP_ID)) { | |
010c3a89 RC |
884 | core_capext = TRUE; |
885 | } else { | |
886 | core_capext = bcmsdh_reg_read(bus->sdh, | |
887 | si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, core_cap_ext)), | |
888 | 4); | |
889 | core_capext = (core_capext & CORE_CAPEXT_SR_SUPPORTED_MASK); | |
890 | } | |
891 | if (!(core_capext)) | |
892 | return FALSE; | |
893 | ||
894 | if (bus->sih->chip == BCM4324_CHIP_ID) { | |
895 | /* FIX: Should change to query SR control register instead */ | |
896 | cap = TRUE; | |
897 | } else if ((bus->sih->chip == BCM4335_CHIP_ID) || | |
898 | (bus->sih->chip == BCM4339_CHIP_ID) || | |
899 | (bus->sih->chip == BCM43349_CHIP_ID) || | |
900 | BCM4345_CHIP(bus->sih->chip) || | |
901 | (bus->sih->chip == BCM4354_CHIP_ID) || | |
902 | (bus->sih->chip == BCM4358_CHIP_ID) || | |
903 | (bus->sih->chip == BCM43569_CHIP_ID) || | |
904 | (bus->sih->chip == BCM4371_CHIP_ID) || | |
905 | (bus->sih->chip == BCM4350_CHIP_ID)) { | |
906 | uint32 enabval = 0; | |
907 | addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr); | |
908 | data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data); | |
909 | bcmsdh_reg_write(bus->sdh, addr, 4, CC_PMUCC3); | |
910 | enabval = bcmsdh_reg_read(bus->sdh, data, 4); | |
911 | ||
912 | if ((bus->sih->chip == BCM4350_CHIP_ID) || | |
913 | BCM4345_CHIP(bus->sih->chip) || | |
914 | (bus->sih->chip == BCM4354_CHIP_ID) || | |
915 | (bus->sih->chip == BCM4358_CHIP_ID) || | |
916 | (bus->sih->chip == BCM43569_CHIP_ID) || | |
917 | (bus->sih->chip == BCM4371_CHIP_ID)) | |
918 | enabval &= CC_CHIPCTRL3_SR_ENG_ENABLE; | |
919 | ||
920 | if (enabval) | |
921 | cap = TRUE; | |
922 | } else { | |
923 | data = bcmsdh_reg_read(bus->sdh, | |
924 | si_get_pmu_reg_addr(bus->sih, OFFSETOF(chipcregs_t, retention_ctl)), | |
925 | 4); | |
926 | if ((data & (RCTL_MACPHY_DISABLE_MASK | RCTL_LOGIC_DISABLE_MASK)) == 0) | |
927 | cap = TRUE; | |
928 | } | |
929 | ||
930 | return cap; | |
931 | } | |
932 | ||
933 | static int | |
934 | dhdsdio_srwar_init(dhd_bus_t *bus) | |
935 | { | |
936 | bcmsdh_gpio_init(bus->sdh); | |
937 | ||
938 | #ifdef USE_OOB_GPIO1 | |
939 | dhdsdio_oobwakeup_init(bus); | |
940 | #endif | |
941 | ||
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | static int | |
947 | dhdsdio_sr_init(dhd_bus_t *bus) | |
948 | { | |
949 | uint8 val; | |
950 | int err = 0; | |
951 | ||
952 | if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2)) | |
953 | dhdsdio_srwar_init(bus); | |
954 | ||
955 | ||
956 | if (bus->sih->chip == BCM43012_CHIP_ID) { | |
957 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL); | |
958 | val |= 1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT; | |
959 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, | |
960 | 1 << SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT, &err); | |
961 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL); | |
962 | } else { | |
963 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL); | |
964 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
965 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, | |
966 | 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT, &err); | |
967 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WAKEUPCTRL, NULL); | |
968 | } | |
969 | ||
970 | #ifdef USE_CMD14 | |
971 | /* Add CMD14 Support */ | |
972 | dhdsdio_devcap_set(bus, | |
973 | (SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT)); | |
974 | #endif /* USE_CMD14 */ | |
975 | ||
976 | if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID || | |
977 | CHIPID(bus->sih->chip) == BCM43018_CHIP_ID || | |
978 | CHIPID(bus->sih->chip) == BCM4339_CHIP_ID || | |
dfb0f3ae RC |
979 | CHIPID(bus->sih->chip) == BCM43012_CHIP_ID || |
980 | CHIPID(bus->sih->chip) == BCM4362_CHIP_ID) | |
010c3a89 RC |
981 | dhdsdio_devcap_set(bus, SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC); |
982 | ||
983 | if (bus->sih->chip == BCM43012_CHIP_ID) { | |
984 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, | |
985 | SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_HT_AVAIL_REQ, &err); | |
986 | } else { | |
987 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, | |
988 | SBSDIO_FUNC1_CHIPCLKCSR, SBSDIO_FORCE_HT, &err); | |
989 | } | |
990 | bus->_slpauto = dhd_slpauto ? TRUE : FALSE; | |
991 | ||
992 | bus->_srenab = TRUE; | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
997 | /* | |
998 | * FIX: Be sure KSO bit is enabled | |
999 | * Currently, it's defaulting to 0 which should be 1. | |
1000 | */ | |
1001 | static int | |
1002 | dhdsdio_clk_kso_init(dhd_bus_t *bus) | |
1003 | { | |
1004 | uint8 val; | |
1005 | int err = 0; | |
1006 | ||
1007 | /* set flag */ | |
1008 | bus->kso = TRUE; | |
1009 | ||
1010 | /* | |
1011 | * Enable KeepSdioOn (KSO) bit for normal operation | |
1012 | * Default is 0 (4334A0) so set it. Fixed in B0. | |
1013 | */ | |
1014 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, NULL); | |
1015 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
1016 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
1017 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, val, &err); | |
1018 | if (err) | |
1019 | DHD_ERROR(("%s: SBSDIO_FUNC1_SLEEPCSR err: 0x%x\n", __FUNCTION__, err)); | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | #define KSO_DBG(x) | |
1026 | #define KSO_WAIT_US 50 | |
1027 | #define KSO_WAIT_MS 1 | |
1028 | #define KSO_SLEEP_RETRY_COUNT 20 | |
1029 | #define KSO_WAKE_RETRY_COUNT 100 | |
1030 | #define ERROR_BCME_NODEVICE_MAX 1 | |
1031 | ||
1032 | #define DEFAULT_MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
1033 | #ifndef CUSTOM_MAX_KSO_ATTEMPTS | |
1034 | #define CUSTOM_MAX_KSO_ATTEMPTS DEFAULT_MAX_KSO_ATTEMPTS | |
1035 | #endif | |
1036 | ||
1037 | static int | |
1038 | dhdsdio_clk_kso_enab(dhd_bus_t *bus, bool on) | |
1039 | { | |
1040 | uint8 wr_val = 0, rd_val, cmp_val, bmask; | |
1041 | int err = 0; | |
1042 | int try_cnt = 0; | |
91a2c117 | 1043 | |
010c3a89 RC |
1044 | KSO_DBG(("%s> op:%s\n", __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"))); |
1045 | ||
1046 | wr_val |= (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
1047 | ||
1048 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); | |
1049 | ||
1050 | ||
1051 | /* In case of 43012 chip, the chip could go down immediately after KSO bit is cleared. | |
1052 | * So the further reads of KSO register could fail. Thereby just bailing out immediately | |
1053 | * after clearing KSO bit, to avoid polling of KSO bit. | |
1054 | */ | |
1055 | if ((!on) && (bus->sih->chip == BCM43012_CHIP_ID)) { | |
1056 | return err; | |
1057 | } | |
1058 | ||
1059 | if (on) { | |
1060 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
1061 | bmask = cmp_val; | |
1062 | ||
1063 | OSL_SLEEP(3); | |
1064 | ||
1065 | } else { | |
1066 | /* Put device to sleep, turn off KSO */ | |
1067 | cmp_val = 0; | |
1068 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
1069 | } | |
1070 | ||
1071 | do { | |
1072 | rd_val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err); | |
1073 | if (((rd_val & bmask) == cmp_val) && !err) | |
1074 | break; | |
1075 | ||
1076 | KSO_DBG(("%s> KSO wr/rd retry:%d, ERR:%x \n", __FUNCTION__, try_cnt, err)); | |
1077 | ||
1078 | if (((try_cnt + 1) % KSO_SLEEP_RETRY_COUNT) == 0) { | |
1079 | OSL_SLEEP(KSO_WAIT_MS); | |
1080 | } else | |
1081 | OSL_DELAY(KSO_WAIT_US); | |
1082 | ||
1083 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); | |
1084 | } while (try_cnt++ < CUSTOM_MAX_KSO_ATTEMPTS); | |
1085 | ||
1086 | ||
1087 | if (try_cnt > 2) | |
1088 | KSO_DBG(("%s> op:%s, try_cnt:%d, rd_val:%x, ERR:%x \n", | |
1089 | __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err)); | |
1090 | ||
1091 | if (try_cnt > CUSTOM_MAX_KSO_ATTEMPTS) { | |
1092 | DHD_ERROR(("%s> op:%s, ERROR: try_cnt:%d, rd_val:%x, ERR:%x \n", | |
1093 | __FUNCTION__, (on ? "KSO_SET" : "KSO_CLR"), try_cnt, rd_val, err)); | |
1094 | } | |
1095 | ||
1096 | return err; | |
1097 | } | |
1098 | ||
1099 | static int | |
1100 | dhdsdio_clk_kso_iovar(dhd_bus_t *bus, bool on) | |
1101 | { | |
1102 | int err = 0; | |
1103 | ||
1104 | if (on == FALSE) { | |
1105 | ||
1106 | BUS_WAKE(bus); | |
1107 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
1108 | ||
1109 | DHD_ERROR(("%s: KSO disable clk: 0x%x\n", __FUNCTION__, | |
1110 | bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, | |
1111 | SBSDIO_FUNC1_CHIPCLKCSR, &err))); | |
1112 | dhdsdio_clk_kso_enab(bus, FALSE); | |
1113 | } else { | |
1114 | DHD_ERROR(("%s: KSO enable\n", __FUNCTION__)); | |
1115 | ||
1116 | /* Make sure we have SD bus access */ | |
1117 | if (bus->clkstate == CLK_NONE) { | |
1118 | DHD_ERROR(("%s: Request SD clk\n", __FUNCTION__)); | |
1119 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
1120 | } | |
1121 | ||
1122 | dhdsdio_clk_kso_enab(bus, TRUE); | |
1123 | ||
1124 | DHD_ERROR(("%s: sleepcsr: 0x%x\n", __FUNCTION__, | |
1125 | dhdsdio_sleepcsr_get(bus))); | |
1126 | } | |
1127 | ||
1128 | bus->kso = on; | |
1129 | BCM_REFERENCE(err); | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | static uint8 | |
1135 | dhdsdio_sleepcsr_get(dhd_bus_t *bus) | |
1136 | { | |
1137 | int err = 0; | |
1138 | uint8 val = 0; | |
1139 | ||
1140 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SLEEPCSR, &err); | |
1141 | if (err) | |
1142 | DHD_TRACE(("Failed to read SLEEPCSR: %d\n", err)); | |
1143 | ||
1144 | return val; | |
1145 | } | |
1146 | ||
1147 | uint8 | |
1148 | dhdsdio_devcap_get(dhd_bus_t *bus) | |
1149 | { | |
1150 | return bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, NULL); | |
1151 | } | |
1152 | ||
1153 | static int | |
1154 | dhdsdio_devcap_set(dhd_bus_t *bus, uint8 cap) | |
1155 | { | |
1156 | int err = 0; | |
1157 | ||
1158 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_BRCM_CARDCAP, cap, &err); | |
1159 | if (err) | |
1160 | DHD_ERROR(("%s: devcap set err: 0x%x\n", __FUNCTION__, err)); | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static int | |
1166 | dhdsdio_clk_devsleep_iovar(dhd_bus_t *bus, bool on) | |
1167 | { | |
1168 | int err = 0, retry; | |
1169 | uint8 val; | |
1170 | ||
1171 | retry = 0; | |
1172 | if (on == TRUE) { | |
1173 | /* Enter Sleep */ | |
1174 | ||
1175 | /* Be sure we request clk before going to sleep | |
1176 | * so we can wake-up with clk request already set | |
1177 | * else device can go back to sleep immediately | |
1178 | */ | |
1179 | if (!SLPAUTO_ENAB(bus)) | |
1180 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
1181 | else { | |
1182 | val = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
1183 | if ((val & SBSDIO_CSR_MASK) == 0) { | |
1184 | DHD_ERROR(("%s: No clock before enter sleep:0x%x\n", | |
1185 | __FUNCTION__, val)); | |
1186 | ||
1187 | /* Reset clock request */ | |
1188 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
1189 | SBSDIO_ALP_AVAIL_REQ, &err); | |
1190 | DHD_ERROR(("%s: clock before sleep:0x%x\n", __FUNCTION__, | |
1191 | bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, | |
1192 | SBSDIO_FUNC1_CHIPCLKCSR, &err))); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | DHD_TRACE(("%s: clk before sleep: 0x%x\n", __FUNCTION__, | |
1197 | bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, | |
1198 | SBSDIO_FUNC1_CHIPCLKCSR, &err))); | |
1199 | #ifdef USE_CMD14 | |
1200 | err = bcmsdh_sleep(bus->sdh, TRUE); | |
1201 | #else | |
1202 | if ((SLPAUTO_ENAB(bus)) && (bus->idleclock == DHD_IDLE_STOP)) { | |
1203 | if (sd1idle) { | |
1204 | /* Change to SD1 mode */ | |
1205 | dhdsdio_set_sdmode(bus, 1); | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | err = dhdsdio_clk_kso_enab(bus, FALSE); | |
1210 | if (OOB_WAKEUP_ENAB(bus)) | |
1211 | { | |
1212 | err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, FALSE); /* GPIO_1 is off */ | |
1213 | } | |
1214 | #endif /* USE_CMD14 */ | |
1215 | ||
1216 | if ((SLPAUTO_ENAB(bus)) && (bus->idleclock != DHD_IDLE_ACTIVE)) { | |
1217 | DHD_TRACE(("%s: Turnoff SD clk\n", __FUNCTION__)); | |
1218 | /* Now remove the SD clock */ | |
1219 | err = dhdsdio_sdclk(bus, FALSE); | |
1220 | } | |
1221 | } else { | |
1222 | /* Exit Sleep */ | |
1223 | /* Make sure we have SD bus access */ | |
1224 | if (bus->clkstate == CLK_NONE) { | |
1225 | DHD_TRACE(("%s: Request SD clk\n", __FUNCTION__)); | |
1226 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
1227 | } | |
1228 | ||
1229 | if ((bus->sih->chip == BCM4334_CHIP_ID) && (bus->sih->chiprev == 2)) { | |
1230 | SPINWAIT_SLEEP(sdioh_spinwait_sleep, | |
1231 | (bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) != TRUE), | |
1232 | GPIO_DEV_SRSTATE_TIMEOUT); | |
1233 | ||
1234 | if (bcmsdh_gpioin(bus->sdh, GPIO_DEV_SRSTATE) == FALSE) { | |
1235 | DHD_ERROR(("ERROR: GPIO_DEV_SRSTATE still low!\n")); | |
1236 | } | |
1237 | } | |
1238 | #ifdef USE_CMD14 | |
1239 | err = bcmsdh_sleep(bus->sdh, FALSE); | |
1240 | if (SLPAUTO_ENAB(bus) && (err != 0)) { | |
1241 | OSL_DELAY(10000); | |
1242 | DHD_TRACE(("%s: Resync device sleep\n", __FUNCTION__)); | |
1243 | ||
1244 | /* Toggle sleep to resync with host and device */ | |
1245 | err = bcmsdh_sleep(bus->sdh, TRUE); | |
1246 | OSL_DELAY(10000); | |
1247 | err = bcmsdh_sleep(bus->sdh, FALSE); | |
1248 | ||
1249 | if (err) { | |
1250 | OSL_DELAY(10000); | |
1251 | DHD_ERROR(("%s: CMD14 exit failed again!\n", __FUNCTION__)); | |
1252 | ||
1253 | /* Toggle sleep to resync with host and device */ | |
1254 | err = bcmsdh_sleep(bus->sdh, TRUE); | |
1255 | OSL_DELAY(10000); | |
1256 | err = bcmsdh_sleep(bus->sdh, FALSE); | |
1257 | if (err) { | |
1258 | DHD_ERROR(("%s: CMD14 exit failed twice!\n", __FUNCTION__)); | |
1259 | DHD_ERROR(("%s: FATAL: Device non-response!\n", | |
1260 | __FUNCTION__)); | |
1261 | err = 0; | |
1262 | } | |
1263 | } | |
1264 | } | |
1265 | #else | |
1266 | if (OOB_WAKEUP_ENAB(bus)) | |
1267 | { | |
1268 | err = bcmsdh_gpioout(bus->sdh, GPIO_DEV_WAKEUP, TRUE); /* GPIO_1 is on */ | |
1269 | } | |
1270 | do { | |
1271 | err = dhdsdio_clk_kso_enab(bus, TRUE); | |
1272 | if (err) | |
1273 | OSL_SLEEP(10); | |
1274 | } while ((err != 0) && (++retry < 3)); | |
1275 | ||
1276 | if (err != 0) { | |
1277 | DHD_ERROR(("ERROR: kso set failed retry: %d\n", retry)); | |
1278 | #ifndef BT_OVER_SDIO | |
1279 | err = 0; /* continue anyway */ | |
1280 | #endif /* BT_OVER_SDIO */ | |
1281 | } | |
1282 | ||
1283 | if ((SLPAUTO_ENAB(bus)) && (bus->idleclock == DHD_IDLE_STOP)) { | |
1284 | dhdsdio_set_sdmode(bus, bus->sd_mode); | |
1285 | } | |
1286 | #endif /* !USE_CMD14 */ | |
1287 | ||
1288 | if (err == 0) { | |
1289 | uint8 csr; | |
1290 | ||
1291 | /* Wait for device ready during transition to wake-up */ | |
1292 | SPINWAIT_SLEEP(sdioh_spinwait_sleep, | |
1293 | (((csr = dhdsdio_sleepcsr_get(bus)) & | |
1294 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK) != | |
1295 | (SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)), (20000)); | |
1296 | ||
1297 | DHD_TRACE(("%s: ExitSleep sleepcsr: 0x%x\n", __FUNCTION__, csr)); | |
1298 | ||
1299 | if (!(csr & SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)) { | |
1300 | DHD_ERROR(("%s:ERROR: ExitSleep device NOT Ready! 0x%x\n", | |
1301 | __FUNCTION__, csr)); | |
1302 | err = BCME_NODEVICE; | |
1303 | } | |
1304 | ||
1305 | SPINWAIT_SLEEP(sdioh_spinwait_sleep, | |
1306 | (((csr = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, | |
1307 | SBSDIO_FUNC1_CHIPCLKCSR, &err)) & SBSDIO_HT_AVAIL) != | |
1308 | (SBSDIO_HT_AVAIL)), (DHD_WAIT_HTAVAIL)); | |
1309 | ||
1310 | DHD_TRACE(("%s: SBSDIO_FUNC1_CHIPCLKCSR : 0x%x\n", __FUNCTION__, csr)); | |
1311 | if (!err && ((csr & SBSDIO_HT_AVAIL) != SBSDIO_HT_AVAIL)) { | |
1312 | DHD_ERROR(("%s:ERROR: device NOT Ready! 0x%x\n", | |
1313 | __FUNCTION__, csr)); | |
1314 | err = BCME_NODEVICE; | |
1315 | } | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | /* Update if successful */ | |
1320 | if (err == 0) | |
1321 | bus->kso = on ? FALSE : TRUE; | |
1322 | else { | |
1323 | DHD_ERROR(("%s: Sleep request failed: kso:%d on:%d err:%d\n", | |
1324 | __FUNCTION__, bus->kso, on, err)); | |
1325 | if (!on && retry > 2) | |
1326 | bus->kso = FALSE; | |
1327 | } | |
1328 | ||
1329 | return err; | |
1330 | } | |
1331 | ||
1332 | /* Turn backplane clock on or off */ | |
1333 | static int | |
1334 | dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok) | |
1335 | { | |
1336 | #define HT_AVAIL_ERROR_MAX 10 | |
1337 | static int ht_avail_error = 0; | |
1338 | int err; | |
1339 | uint8 clkctl, clkreq, devctl; | |
1340 | bcmsdh_info_t *sdh; | |
1341 | ||
1342 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
1343 | ||
1344 | clkctl = 0; | |
1345 | sdh = bus->sdh; | |
1346 | ||
1347 | ||
1348 | if (!KSO_ENAB(bus)) | |
1349 | return BCME_OK; | |
1350 | ||
1351 | if (SLPAUTO_ENAB(bus)) { | |
1352 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
1353 | return BCME_OK; | |
1354 | } | |
1355 | ||
1356 | if (on) { | |
1357 | /* Request HT Avail */ | |
1358 | clkreq = bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
1359 | ||
1360 | ||
1361 | ||
1362 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); | |
1363 | if (err) { | |
1364 | ht_avail_error++; | |
1365 | if (ht_avail_error < HT_AVAIL_ERROR_MAX) { | |
1366 | DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err)); | |
1367 | } | |
1368 | ||
1369 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) | |
1370 | else if (ht_avail_error == HT_AVAIL_ERROR_MAX) { | |
1371 | bus->dhd->hang_reason = HANG_REASON_HT_AVAIL_ERROR; | |
1372 | dhd_os_send_hang_message(bus->dhd); | |
1373 | } | |
1374 | #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) */ | |
1375 | return BCME_ERROR; | |
1376 | } else { | |
1377 | ht_avail_error = 0; | |
1378 | } | |
1379 | ||
1380 | ||
1381 | /* Check current status */ | |
1382 | clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
1383 | if (err) { | |
1384 | DHD_ERROR(("%s: HT Avail read error: %d\n", __FUNCTION__, err)); | |
1385 | return BCME_ERROR; | |
1386 | } | |
1387 | ||
1388 | #if !defined(OOB_INTR_ONLY) | |
1389 | /* Go to pending and await interrupt if appropriate */ | |
1390 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
1391 | /* Allow only clock-available interrupt */ | |
1392 | devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err); | |
1393 | if (err) { | |
1394 | DHD_ERROR(("%s: Devctl access error setting CA: %d\n", | |
1395 | __FUNCTION__, err)); | |
1396 | return BCME_ERROR; | |
1397 | } | |
1398 | ||
1399 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
1400 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err); | |
1401 | DHD_INFO(("CLKCTL: set PENDING\n")); | |
1402 | bus->clkstate = CLK_PENDING; | |
1403 | return BCME_OK; | |
1404 | } else | |
1405 | #endif /* !defined (OOB_INTR_ONLY) */ | |
1406 | { | |
1407 | if (bus->clkstate == CLK_PENDING) { | |
1408 | /* Cancel CA-only interrupt filter */ | |
1409 | devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err); | |
1410 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
1411 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err); | |
1412 | } | |
1413 | } | |
1414 | ||
1415 | /* Otherwise, wait here (polling) for HT Avail */ | |
1416 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
1417 | SPINWAIT_SLEEP(sdioh_spinwait_sleep, | |
1418 | ((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, | |
1419 | SBSDIO_FUNC1_CHIPCLKCSR, &err)), | |
1420 | !SBSDIO_CLKAV(clkctl, bus->alp_only)), PMU_MAX_TRANSITION_DLY); | |
1421 | } | |
1422 | if (err) { | |
1423 | DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err)); | |
1424 | return BCME_ERROR; | |
1425 | } | |
1426 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
1427 | DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n", | |
1428 | __FUNCTION__, PMU_MAX_TRANSITION_DLY, clkctl)); | |
1429 | return BCME_ERROR; | |
1430 | } | |
1431 | ||
1432 | /* Mark clock available */ | |
1433 | bus->clkstate = CLK_AVAIL; | |
1434 | DHD_INFO(("CLKCTL: turned ON\n")); | |
1435 | ||
1436 | #if defined(DHD_DEBUG) | |
1437 | if (bus->alp_only == TRUE) { | |
1438 | #if !defined(BCMLXSDMMC) | |
1439 | if (!SBSDIO_ALPONLY(clkctl)) { | |
1440 | DHD_ERROR(("%s: HT Clock, when ALP Only\n", __FUNCTION__)); | |
1441 | } | |
1442 | #endif /* !defined(BCMLXSDMMC) */ | |
1443 | } else { | |
1444 | if (SBSDIO_ALPONLY(clkctl)) { | |
1445 | DHD_ERROR(("%s: HT Clock should be on.\n", __FUNCTION__)); | |
1446 | } | |
1447 | } | |
1448 | #endif /* defined (DHD_DEBUG) */ | |
1449 | ||
1450 | bus->activity = TRUE; | |
1451 | #ifdef DHD_USE_IDLECOUNT | |
1452 | bus->idlecount = 0; | |
1453 | #endif /* DHD_USE_IDLECOUNT */ | |
1454 | } else { | |
1455 | clkreq = 0; | |
1456 | ||
1457 | if (bus->clkstate == CLK_PENDING) { | |
1458 | /* Cancel CA-only interrupt filter */ | |
1459 | devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err); | |
1460 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
1461 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err); | |
1462 | } | |
1463 | ||
1464 | bus->clkstate = CLK_SDONLY; | |
1465 | if (!SR_ENAB(bus)) { | |
1466 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); | |
1467 | DHD_INFO(("CLKCTL: turned OFF\n")); | |
1468 | if (err) { | |
1469 | DHD_ERROR(("%s: Failed access turning clock off: %d\n", | |
1470 | __FUNCTION__, err)); | |
1471 | return BCME_ERROR; | |
1472 | } | |
1473 | } | |
1474 | } | |
1475 | return BCME_OK; | |
1476 | } | |
1477 | ||
1478 | /* Change SD1/SD4 bus mode */ | |
1479 | static int | |
1480 | dhdsdio_set_sdmode(dhd_bus_t *bus, int32 sd_mode) | |
1481 | { | |
1482 | int err; | |
1483 | ||
1484 | err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0, | |
1485 | &sd_mode, sizeof(sd_mode), TRUE); | |
1486 | if (err) { | |
1487 | DHD_ERROR(("%s: error changing sd_mode: %d\n", | |
1488 | __FUNCTION__, err)); | |
1489 | return BCME_ERROR; | |
1490 | } | |
1491 | return BCME_OK; | |
1492 | } | |
1493 | ||
1494 | /* Change idle/active SD state */ | |
1495 | static int | |
1496 | dhdsdio_sdclk(dhd_bus_t *bus, bool on) | |
1497 | { | |
1498 | int err; | |
1499 | int32 iovalue; | |
1500 | ||
1501 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
1502 | ||
1503 | if (on) { | |
1504 | if (bus->idleclock == DHD_IDLE_STOP) { | |
1505 | /* Turn on clock and restore mode */ | |
1506 | iovalue = 1; | |
1507 | err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0, | |
1508 | &iovalue, sizeof(iovalue), TRUE); | |
1509 | if (err) { | |
1510 | DHD_ERROR(("%s: error enabling sd_clock: %d\n", | |
1511 | __FUNCTION__, err)); | |
1512 | return BCME_ERROR; | |
1513 | } | |
1514 | ||
1515 | } else if (bus->idleclock != DHD_IDLE_ACTIVE) { | |
1516 | /* Restore clock speed */ | |
1517 | iovalue = bus->sd_divisor; | |
1518 | err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0, | |
1519 | &iovalue, sizeof(iovalue), TRUE); | |
1520 | if (err) { | |
1521 | DHD_ERROR(("%s: error restoring sd_divisor: %d\n", | |
1522 | __FUNCTION__, err)); | |
1523 | return BCME_ERROR; | |
1524 | } | |
1525 | } | |
1526 | bus->clkstate = CLK_SDONLY; | |
1527 | } else { | |
1528 | /* Stop or slow the SD clock itself */ | |
1529 | if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) { | |
1530 | DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n", | |
1531 | __FUNCTION__, bus->sd_divisor, bus->sd_mode)); | |
1532 | return BCME_ERROR; | |
1533 | } | |
1534 | if (bus->idleclock == DHD_IDLE_STOP) { | |
1535 | iovalue = 0; | |
1536 | err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0, | |
1537 | &iovalue, sizeof(iovalue), TRUE); | |
1538 | if (err) { | |
1539 | DHD_ERROR(("%s: error disabling sd_clock: %d\n", | |
1540 | __FUNCTION__, err)); | |
1541 | return BCME_ERROR; | |
1542 | } | |
1543 | } else if (bus->idleclock != DHD_IDLE_ACTIVE) { | |
1544 | /* Set divisor to idle value */ | |
1545 | iovalue = bus->idleclock; | |
1546 | err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0, | |
1547 | &iovalue, sizeof(iovalue), TRUE); | |
1548 | if (err) { | |
1549 | DHD_ERROR(("%s: error changing sd_divisor: %d\n", | |
1550 | __FUNCTION__, err)); | |
1551 | return BCME_ERROR; | |
1552 | } | |
1553 | } | |
1554 | bus->clkstate = CLK_NONE; | |
1555 | } | |
1556 | ||
1557 | return BCME_OK; | |
1558 | } | |
1559 | ||
1560 | /* Transition SD and backplane clock readiness */ | |
1561 | static int | |
1562 | dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok) | |
1563 | { | |
1564 | int ret = BCME_OK; | |
1565 | #ifdef DHD_DEBUG | |
1566 | uint oldstate = bus->clkstate; | |
1567 | #endif /* DHD_DEBUG */ | |
1568 | ||
1569 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
1570 | ||
1571 | /* Early exit if we're already there */ | |
1572 | if (bus->clkstate == target) { | |
1573 | if (target == CLK_AVAIL) { | |
1574 | dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms); | |
1575 | bus->activity = TRUE; | |
1576 | #ifdef DHD_USE_IDLECOUNT | |
1577 | bus->idlecount = 0; | |
1578 | #endif /* DHD_USE_IDLECOUNT */ | |
1579 | } | |
1580 | return ret; | |
1581 | } | |
1582 | ||
1583 | switch (target) { | |
1584 | case CLK_AVAIL: | |
1585 | /* Make sure SD clock is available */ | |
1586 | if (bus->clkstate == CLK_NONE) | |
1587 | dhdsdio_sdclk(bus, TRUE); | |
1588 | /* Now request HT Avail on the backplane */ | |
1589 | ret = dhdsdio_htclk(bus, TRUE, pendok); | |
1590 | if (ret == BCME_OK) { | |
1591 | dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms); | |
1592 | bus->activity = TRUE; | |
1593 | #ifdef DHD_USE_IDLECOUNT | |
1594 | bus->idlecount = 0; | |
1595 | #endif /* DHD_USE_IDLECOUNT */ | |
1596 | } | |
1597 | break; | |
1598 | ||
1599 | case CLK_SDONLY: | |
1600 | ||
1601 | #ifdef BT_OVER_SDIO | |
1602 | /* | |
1603 | * If the request is to switch off Back plane clock, | |
1604 | * confirm that BT is inactive before doing so. | |
1605 | * If this call had come from Non Watchdog context any way | |
1606 | * the Watchdog would switch off the clock again when | |
1607 | * nothing is to be done & Bt has finished using the bus. | |
1608 | */ | |
1609 | if (bus->bt_use_count != 0) { | |
1610 | DHD_INFO(("%s(): Req CLK_SDONLY, BT is active %d not switching off \r\n", | |
1611 | __FUNCTION__, bus->bt_use_count)); | |
1612 | ret = BCME_OK; | |
1613 | dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms); | |
1614 | break; | |
1615 | } | |
1616 | ||
1617 | DHD_INFO(("%s(): Request CLK_NONE BT is NOT active switching off \r\n", | |
1618 | __FUNCTION__)); | |
1619 | #endif /* BT_OVER_SDIO */ | |
1620 | ||
1621 | /* Remove HT request, or bring up SD clock */ | |
1622 | if (bus->clkstate == CLK_NONE) | |
1623 | ret = dhdsdio_sdclk(bus, TRUE); | |
1624 | else if (bus->clkstate == CLK_AVAIL) | |
1625 | ret = dhdsdio_htclk(bus, FALSE, FALSE); | |
1626 | else | |
1627 | DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n", | |
1628 | bus->clkstate, target)); | |
1629 | if (ret == BCME_OK) { | |
1630 | dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms); | |
1631 | } | |
1632 | break; | |
1633 | ||
1634 | case CLK_NONE: | |
1635 | ||
1636 | #ifdef BT_OVER_SDIO | |
1637 | /* | |
1638 | * If the request is to switch off Back plane clock, | |
1639 | * confirm that BT is inactive before doing so. | |
1640 | * If this call had come from Non Watchdog context any way | |
1641 | * the Watchdog would switch off the clock again when | |
1642 | * nothing is to be done & Bt has finished using the bus. | |
1643 | */ | |
1644 | if (bus->bt_use_count != 0) { | |
1645 | DHD_INFO(("%s(): Request CLK_NONE BT is active %d not switching off \r\n", | |
1646 | __FUNCTION__, bus->bt_use_count)); | |
1647 | ret = BCME_OK; | |
1648 | break; | |
1649 | } | |
1650 | ||
1651 | DHD_INFO(("%s(): Request CLK_NONE BT is NOT active switching off \r\n", | |
1652 | __FUNCTION__)); | |
1653 | #endif /* BT_OVER_SDIO */ | |
1654 | ||
1655 | /* Make sure to remove HT request */ | |
1656 | if (bus->clkstate == CLK_AVAIL) | |
1657 | ret = dhdsdio_htclk(bus, FALSE, FALSE); | |
1658 | /* Now remove the SD clock */ | |
1659 | ret = dhdsdio_sdclk(bus, FALSE); | |
1660 | #ifdef DHD_DEBUG | |
1661 | if (dhd_console_ms == 0) | |
1662 | #endif /* DHD_DEBUG */ | |
1663 | if (bus->poll == 0) | |
1664 | dhd_os_wd_timer(bus->dhd, 0); | |
1665 | break; | |
1666 | } | |
1667 | #ifdef DHD_DEBUG | |
1668 | DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate)); | |
1669 | #endif /* DHD_DEBUG */ | |
1670 | ||
1671 | return ret; | |
1672 | } | |
1673 | ||
1674 | static int | |
1675 | dhdsdio_bussleep(dhd_bus_t *bus, bool sleep) | |
1676 | { | |
1677 | int err = 0; | |
1678 | bcmsdh_info_t *sdh = bus->sdh; | |
1679 | sdpcmd_regs_t *regs = bus->regs; | |
1680 | uint retries = 0; | |
1681 | ||
1682 | DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n", | |
1683 | (sleep ? "SLEEP" : "WAKE"), | |
1684 | (bus->sleeping ? "SLEEP" : "WAKE"))); | |
1685 | ||
1686 | if (bus->dhd->hang_was_sent) | |
1687 | return BCME_ERROR; | |
1688 | ||
1689 | /* Done if we're already in the requested state */ | |
1690 | if (sleep == bus->sleeping) | |
1691 | return BCME_OK; | |
1692 | ||
1693 | /* Going to sleep: set the alarm and turn off the lights... */ | |
1694 | if (sleep) { | |
1695 | /* Don't sleep if something is pending */ | |
1696 | #ifdef DHD_USE_IDLECOUNT | |
1697 | if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq) || bus->readframes || | |
1698 | bus->ctrl_frame_stat) | |
1699 | #else | |
1700 | if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq)) | |
1701 | #endif /* DHD_USE_IDLECOUNT */ | |
1702 | return BCME_BUSY; | |
1703 | ||
1704 | #ifdef BT_OVER_SDIO | |
1705 | /* | |
1706 | * The following is the assumption based on which the hook is placed. | |
1707 | * From WLAN driver, either from the active contexts OR from the Watchdog contexts | |
1708 | * we will be attempting to Go to Sleep. AT that moment if we see that BT is still | |
1709 | * actively using the bus, we will return BCME_BUSY from here, but the bus->sleeping | |
1710 | * state would not have changed. So the caller can then schedule the Watchdog again | |
1711 | * which will come and attempt to sleep at a later point. | |
1712 | * | |
1713 | * In case if BT is the only one and is the last user, we don't switch off the clock | |
1714 | * immediately, we allow the WLAN to decide when to sleep i.e from the watchdog. | |
1715 | * Now if the watchdog becomes active and attempts to switch off the clock and if | |
1716 | * another WLAN context is active they are any way serialized with sdlock. | |
1717 | */ | |
1718 | if (bus->bt_use_count != 0) { | |
1719 | DHD_INFO(("%s(): Cannot sleep BT is active \r\n", __FUNCTION__)); | |
1720 | return BCME_BUSY; | |
1721 | } | |
1722 | #endif /* !BT_OVER_SDIO */ | |
1723 | ||
1724 | ||
1725 | if (!SLPAUTO_ENAB(bus)) { | |
1726 | /* Disable SDIO interrupts (no longer interested) */ | |
1727 | bcmsdh_intr_disable(bus->sdh); | |
1728 | ||
1729 | /* Make sure the controller has the bus up */ | |
1730 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
1731 | ||
1732 | /* Tell device to start using OOB wakeup */ | |
1733 | W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries); | |
1734 | if (retries > retry_limit) | |
1735 | DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n")); | |
1736 | ||
1737 | /* Turn off our contribution to the HT clock request */ | |
1738 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
1739 | ||
1740 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
1741 | SBSDIO_FORCE_HW_CLKREQ_OFF, NULL); | |
1742 | ||
1743 | /* Isolate the bus */ | |
1744 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, | |
1745 | SBSDIO_DEVCTL_PADS_ISO, NULL); | |
1746 | } else { | |
1747 | /* Leave interrupts enabled since device can exit sleep and | |
1748 | * interrupt host | |
1749 | */ | |
1750 | err = dhdsdio_clk_devsleep_iovar(bus, TRUE /* sleep */); | |
1751 | } | |
1752 | ||
1753 | /* Change state */ | |
1754 | bus->sleeping = TRUE; | |
1755 | #if defined(SUPPORT_P2P_GO_PS) | |
1756 | wake_up(&bus->bus_sleep); | |
1757 | #endif /* LINUX && SUPPORT_P2P_GO_PS */ | |
1758 | } else { | |
1759 | /* Waking up: bus power up is ok, set local state */ | |
1760 | ||
1761 | if (!SLPAUTO_ENAB(bus)) { | |
1762 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, &err); | |
1763 | ||
1764 | /* Force pad isolation off if possible (in case power never toggled) */ | |
1765 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0, NULL); | |
1766 | ||
1767 | ||
1768 | /* Make sure the controller has the bus up */ | |
1769 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
1770 | ||
1771 | /* Send misc interrupt to indicate OOB not needed */ | |
1772 | W_SDREG(0, ®s->tosbmailboxdata, retries); | |
1773 | if (retries <= retry_limit) | |
1774 | W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries); | |
1775 | ||
1776 | if (retries > retry_limit) | |
1777 | DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n")); | |
1778 | ||
1779 | /* Make sure we have SD bus access */ | |
1780 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
1781 | ||
1782 | /* Enable interrupts again */ | |
1783 | if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) { | |
1784 | bus->intdis = FALSE; | |
1785 | bcmsdh_intr_enable(bus->sdh); | |
1786 | } | |
1787 | } else { | |
1788 | err = dhdsdio_clk_devsleep_iovar(bus, FALSE /* wake */); | |
1789 | #ifdef BT_OVER_SDIO | |
1790 | if (err < 0) { | |
1791 | struct net_device *net = NULL; | |
1792 | dhd_pub_t *dhd = bus->dhd; | |
1793 | net = dhd_idx2net(dhd, 0); | |
1794 | if (net != NULL) { | |
1795 | DHD_ERROR(("<<<<<< WIFI HANG by KSO Enabled failure\n")); | |
1796 | dhd_os_sdunlock(dhd); | |
1797 | net_os_send_hang_message(net); | |
1798 | dhd_os_sdlock(dhd); | |
1799 | } else { | |
1800 | DHD_ERROR(("<<<<< WIFI HANG Fail because net is NULL\n")); | |
1801 | } | |
1802 | } | |
1803 | #endif /* BT_OVER_SDIO */ | |
1804 | } | |
1805 | ||
1806 | if (err == 0) { | |
1807 | /* Change state */ | |
1808 | bus->sleeping = FALSE; | |
1809 | } | |
1810 | } | |
1811 | ||
1812 | return err; | |
1813 | } | |
1814 | ||
1815 | #ifdef BT_OVER_SDIO | |
1816 | /* | |
1817 | * Call this function to Get the Clock running. | |
1818 | * Assumes that the caller holds the sdlock. | |
1819 | * bus - Pointer to the dhd_bus handle | |
1820 | * can_wait - TRUE if the caller can wait until the clock becomes ready | |
1821 | * FALSE if the caller cannot wait | |
1822 | */ | |
1823 | int __dhdsdio_clk_enable(struct dhd_bus *bus, bus_owner_t owner, int can_wait) | |
1824 | { | |
1825 | int ret = BCME_ERROR; | |
1826 | ||
1827 | BCM_REFERENCE(owner); | |
1828 | ||
1829 | bus->bt_use_count++; | |
1830 | ||
1831 | /* | |
1832 | * We can call BUS_WAKE, clkctl multiple times, both of the items | |
1833 | * have states and if its already ON, no new configuration is done | |
1834 | */ | |
1835 | ||
1836 | /* Wake up the Dongle FW from SR */ | |
1837 | BUS_WAKE(bus); | |
1838 | ||
1839 | /* | |
1840 | * Make sure back plane ht clk is on | |
1841 | * CLK_AVAIL - Turn On both SD & HT clock | |
1842 | */ | |
1843 | ret = dhdsdio_clkctl(bus, CLK_AVAIL, can_wait); | |
1844 | ||
1845 | DHD_INFO(("%s():bt_use_count %d \r\n", __FUNCTION__, | |
1846 | bus->bt_use_count)); | |
1847 | return ret; | |
1848 | } | |
1849 | ||
1850 | /* | |
1851 | * Call this function to relinquish the Clock. | |
1852 | * Assumes that the caller holds the sdlock. | |
1853 | * bus - Pointer to the dhd_bus handle | |
1854 | * can_wait - TRUE if the caller can wait until the clock becomes ready | |
1855 | * FALSE if the caller cannot wait | |
1856 | */ | |
1857 | int __dhdsdio_clk_disable(struct dhd_bus *bus, bus_owner_t owner, int can_wait) | |
1858 | { | |
1859 | int ret = BCME_ERROR; | |
1860 | ||
1861 | BCM_REFERENCE(owner); | |
1862 | BCM_REFERENCE(can_wait); | |
1863 | ||
1864 | if (bus->bt_use_count == 0) { | |
1865 | DHD_ERROR(("%s(): Clocks are already turned off \r\n", | |
1866 | __FUNCTION__)); | |
1867 | return ret; | |
1868 | } | |
1869 | ||
1870 | bus->bt_use_count--; | |
1871 | ||
1872 | /* | |
1873 | * When the SDIO Bus is shared between BT & WLAN, we turn Off the clock | |
1874 | * once the last user has relinqushed the same. But there are two schemes | |
1875 | * in that too. We consider WLAN as the bus master (even if its not | |
1876 | * active). Even when the WLAN is OFF the DHD Watchdog is active. | |
1877 | * So this Bus Watchdog is the context whill put the Bus to sleep. | |
1878 | * Refer dhd_bus_watchdog function | |
1879 | */ | |
1880 | ||
1881 | ret = BCME_OK; | |
1882 | DHD_INFO(("%s():bt_use_count %d \r\n", __FUNCTION__, | |
1883 | bus->bt_use_count)); | |
1884 | return ret; | |
1885 | } | |
1886 | ||
1887 | void dhdsdio_reset_bt_use_count(struct dhd_bus *bus) | |
1888 | { | |
1889 | /* reset bt use count */ | |
1890 | bus->bt_use_count = 0; | |
1891 | } | |
1892 | #endif /* BT_OVER_SDIO */ | |
1893 | ||
1894 | int dhdsdio_func_blocksize(dhd_pub_t *dhd, int function_num, int block_size) | |
1895 | { | |
1896 | int func_blk_size = function_num; | |
1897 | int bcmerr = 0; | |
1898 | int result; | |
1899 | ||
1900 | bcmerr = dhd_bus_iovar_op(dhd, "sd_blocksize", &func_blk_size, | |
1901 | sizeof(int), &result, sizeof(int), IOV_GET); | |
1902 | ||
1903 | if (bcmerr != BCME_OK) { | |
1904 | DHD_ERROR(("%s: Get F%d Block size error\n", __FUNCTION__, function_num)); | |
1905 | return BCME_ERROR; | |
1906 | } | |
1907 | ||
1908 | if (result != block_size) { | |
1909 | DHD_ERROR(("%s: F%d Block size set from %d to %d\n", | |
1910 | __FUNCTION__, function_num, result, block_size)); | |
1911 | func_blk_size = function_num << 16 | block_size; | |
1912 | bcmerr = dhd_bus_iovar_op(dhd, "sd_blocksize", NULL, | |
1913 | 0, &func_blk_size, sizeof(int32), IOV_SET); | |
1914 | if (bcmerr != BCME_OK) { | |
1915 | DHD_ERROR(("%s: Set F2 Block size error\n", __FUNCTION__)); | |
1916 | return BCME_ERROR; | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | return BCME_OK; | |
1921 | } | |
1922 | ||
1923 | #if defined(OOB_INTR_ONLY) || defined(FORCE_WOWLAN) | |
1924 | void | |
1925 | dhd_enable_oob_intr(struct dhd_bus *bus, bool enable) | |
1926 | { | |
1927 | #if defined(HW_OOB) || defined(FORCE_WOWLAN) | |
1928 | bcmsdh_enable_hw_oob_intr(bus->sdh, enable); | |
1929 | #else | |
1930 | sdpcmd_regs_t *regs = bus->regs; | |
1931 | uint retries = 0; | |
1932 | ||
1933 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
1934 | if (enable == TRUE) { | |
1935 | ||
1936 | /* Tell device to start using OOB wakeup */ | |
1937 | W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries); | |
1938 | if (retries > retry_limit) | |
1939 | DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n")); | |
1940 | ||
1941 | } else { | |
1942 | /* Send misc interrupt to indicate OOB not needed */ | |
1943 | W_SDREG(0, ®s->tosbmailboxdata, retries); | |
1944 | if (retries <= retry_limit) | |
1945 | W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries); | |
1946 | } | |
1947 | ||
1948 | /* Turn off our contribution to the HT clock request */ | |
1949 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
1950 | #endif /* !defined(HW_OOB) */ | |
1951 | } | |
1952 | #endif | |
1953 | ||
1954 | int | |
1955 | dhd_bus_txdata(struct dhd_bus *bus, void *pkt) | |
1956 | { | |
1957 | int ret = BCME_ERROR; | |
1958 | osl_t *osh; | |
1959 | uint datalen, prec; | |
1960 | ||
1961 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
1962 | ||
1963 | osh = bus->dhd->osh; | |
1964 | datalen = PKTLEN(osh, pkt); | |
1965 | ||
1966 | #ifdef SDTEST | |
1967 | /* Push the test header if doing loopback */ | |
1968 | if (bus->ext_loop) { | |
1969 | uint8* data; | |
1970 | PKTPUSH(osh, pkt, SDPCM_TEST_HDRLEN); | |
1971 | data = PKTDATA(osh, pkt); | |
1972 | *data++ = SDPCM_TEST_ECHOREQ; | |
1973 | *data++ = (uint8)bus->loopid++; | |
1974 | *data++ = (datalen >> 0); | |
1975 | *data++ = (datalen >> 8); | |
1976 | datalen += SDPCM_TEST_HDRLEN; | |
1977 | } | |
1978 | #else /* SDTEST */ | |
1979 | BCM_REFERENCE(datalen); | |
1980 | #endif /* SDTEST */ | |
1981 | ||
1982 | prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK)); | |
1983 | ||
dfb0f3ae RC |
1984 | /* move from dhdsdio_sendfromq(), try to orphan skb early */ |
1985 | if (bus->dhd->conf->orphan_move) | |
1986 | PKTORPHAN(pkt, bus->dhd->conf->tsq); | |
1987 | ||
010c3a89 RC |
1988 | /* Check for existing queue, current flow-control, pending event, or pending clock */ |
1989 | if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq) || bus->dpc_sched || | |
1990 | (!DATAOK(bus)) || (bus->flowcontrol & NBITVAL(prec)) || | |
1991 | (bus->clkstate != CLK_AVAIL)) { | |
1992 | bool deq_ret; | |
dfb0f3ae | 1993 | int pkq_len = 0; |
010c3a89 RC |
1994 | |
1995 | DHD_TRACE(("%s: deferring pktq len %d\n", __FUNCTION__, pktq_len(&bus->txq))); | |
1996 | bus->fcqueued++; | |
1997 | ||
1998 | /* Priority based enq */ | |
1999 | dhd_os_sdlock_txq(bus->dhd); | |
2000 | deq_ret = dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec); | |
2001 | dhd_os_sdunlock_txq(bus->dhd); | |
2002 | ||
2003 | if (!deq_ret) { | |
2004 | #ifdef PROP_TXSTATUS | |
2005 | if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt)) == 0) | |
2006 | #endif /* PROP_TXSTATUS */ | |
2007 | { | |
2008 | #ifdef DHDTCPACK_SUPPRESS | |
2009 | if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) { | |
2010 | DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using\n", | |
2011 | __FUNCTION__, __LINE__)); | |
2012 | dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF); | |
2013 | } | |
2014 | #endif /* DHDTCPACK_SUPPRESS */ | |
2015 | dhd_txcomplete(bus->dhd, pkt, FALSE); | |
2016 | PKTFREE(osh, pkt, TRUE); | |
2017 | } | |
2018 | ret = BCME_NORESOURCE; | |
2019 | } else | |
2020 | ret = BCME_OK; | |
2021 | ||
dfb0f3ae RC |
2022 | if (dhd_doflow) { |
2023 | dhd_os_sdlock_txq(bus->dhd); | |
2024 | pkq_len = pktq_len(&bus->txq); | |
2025 | dhd_os_sdunlock_txq(bus->dhd); | |
2026 | } | |
2027 | if (dhd_doflow && pkq_len >= FCHI) { | |
010c3a89 RC |
2028 | bool wlfc_enabled = FALSE; |
2029 | #ifdef PROP_TXSTATUS | |
2030 | wlfc_enabled = (dhd_wlfc_flowcontrol(bus->dhd, ON, FALSE) != | |
2031 | WLFC_UNSUPPORTED); | |
2032 | #endif | |
2033 | if (!wlfc_enabled && dhd_doflow) { | |
2034 | dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON); | |
2035 | } | |
2036 | } | |
2037 | ||
2038 | #ifdef DHD_DEBUG | |
2039 | dhd_os_sdlock_txq(bus->dhd); | |
2040 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) | |
2041 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2042 | dhd_os_sdunlock_txq(bus->dhd); | |
2043 | #endif | |
2044 | ||
2045 | /* Schedule DPC if needed to send queued packet(s) */ | |
2046 | if (dhd_deferred_tx && !bus->dpc_sched) { | |
2047 | if (bus->dhd->conf->deferred_tx_len) { | |
2048 | if(dhd_os_wd_timer_enabled(bus->dhd) == FALSE) { | |
2049 | bus->dpc_sched = TRUE; | |
2050 | dhd_sched_dpc(bus->dhd); | |
2051 | } | |
2052 | if(pktq_len(&bus->txq) >= bus->dhd->conf->deferred_tx_len && | |
2053 | dhd_os_wd_timer_enabled(bus->dhd) == FALSE) { | |
2054 | bus->dpc_sched = TRUE; | |
2055 | dhd_sched_dpc(bus->dhd); | |
2056 | } | |
2057 | } else { | |
2058 | bus->dpc_sched = TRUE; | |
2059 | dhd_sched_dpc(bus->dhd); | |
2060 | } | |
2061 | } | |
2062 | } else { | |
2063 | int chan = SDPCM_DATA_CHANNEL; | |
2064 | ||
2065 | #ifdef SDTEST | |
2066 | chan = (bus->ext_loop ? SDPCM_TEST_CHANNEL : SDPCM_DATA_CHANNEL); | |
2067 | #endif | |
2068 | /* Lock: we're about to use shared data/code (and SDIO) */ | |
2069 | dhd_os_sdlock(bus->dhd); | |
2070 | ||
2071 | /* Otherwise, send it now */ | |
2072 | BUS_WAKE(bus); | |
2073 | /* Make sure back plane ht clk is on, no pending allowed */ | |
2074 | dhdsdio_clkctl(bus, CLK_AVAIL, TRUE); | |
2075 | ||
2076 | ret = dhdsdio_txpkt(bus, chan, &pkt, 1, TRUE); | |
2077 | ||
2078 | if (ret != BCME_OK) | |
2079 | bus->dhd->tx_errors++; | |
2080 | else | |
2081 | bus->dhd->dstats.tx_bytes += datalen; | |
2082 | ||
2083 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched && | |
2084 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
2085 | bus->activity = FALSE; | |
2086 | dhdsdio_bussleep(bus, TRUE); | |
2087 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
2088 | } | |
2089 | ||
2090 | dhd_os_sdunlock(bus->dhd); | |
2091 | } | |
2092 | ||
2093 | return ret; | |
2094 | } | |
2095 | ||
2096 | /* align packet data pointer and packet length to n-byte boundary, process packet headers, | |
2097 | * a new packet may be allocated if there is not enough head and/or tail from for padding. | |
2098 | * the caller is responsible for updating the glom size in the head packet (when glom is | |
2099 | * used) | |
2100 | * | |
2101 | * pad_pkt_len: returns the length of extra padding needed from the padding packet, this parameter | |
2102 | * is taken in tx glom mode only | |
2103 | * | |
2104 | * new_pkt: out, pointer of the new packet allocated due to insufficient head room for alignment | |
2105 | * padding, NULL if not needed, the caller is responsible for freeing the new packet | |
2106 | * | |
2107 | * return: positive value - length of the packet, including head and tail padding | |
2108 | * negative value - errors | |
2109 | */ | |
2110 | static int dhdsdio_txpkt_preprocess(dhd_bus_t *bus, void *pkt, int chan, int txseq, | |
2111 | int prev_chain_total_len, bool last_chained_pkt, | |
2112 | int *pad_pkt_len, void **new_pkt | |
2113 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
2114 | , int first_frame | |
2115 | #endif | |
2116 | ) | |
2117 | { | |
2118 | osl_t *osh; | |
2119 | uint8 *frame; | |
2120 | int pkt_len; | |
2121 | int modulo; | |
2122 | int head_padding; | |
2123 | int tail_padding = 0; | |
2124 | uint32 swheader; | |
2125 | uint32 swhdr_offset; | |
2126 | bool alloc_new_pkt = FALSE; | |
2127 | uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN; | |
2128 | #ifdef PKT_STATICS | |
2129 | uint16 len; | |
2130 | #endif | |
2131 | ||
2132 | *new_pkt = NULL; | |
2133 | osh = bus->dhd->osh; | |
2134 | ||
2135 | #ifdef DHDTCPACK_SUPPRESS | |
2136 | if (dhd_tcpack_check_xmit(bus->dhd, pkt) == BCME_ERROR) { | |
2137 | DHD_ERROR(("%s %d: tcpack_suppress ERROR!!! Stop using it\n", | |
2138 | __FUNCTION__, __LINE__)); | |
2139 | dhd_tcpack_suppress_set(bus->dhd, TCPACK_SUP_OFF); | |
2140 | } | |
2141 | #endif /* DHDTCPACK_SUPPRESS */ | |
2142 | ||
2143 | /* Add space for the SDPCM hardware/software headers */ | |
2144 | PKTPUSH(osh, pkt, sdpcm_hdrlen); | |
2145 | ASSERT(ISALIGNED((uintptr)PKTDATA(osh, pkt), 2)); | |
2146 | ||
2147 | frame = (uint8*)PKTDATA(osh, pkt); | |
2148 | pkt_len = (uint16)PKTLEN(osh, pkt); | |
2149 | ||
2150 | #ifdef WLMEDIA_HTSF | |
2151 | frame = (uint8*)PKTDATA(osh, pkt); | |
2152 | if (PKTLEN(osh, pkt) >= 100) { | |
2153 | htsf_ts = (htsfts_t*) (frame + HTSF_HOSTOFFSET + 12); | |
2154 | if (htsf_ts->magic == HTSFMAGIC) { | |
2155 | htsf_ts->c20 = get_cycles(); | |
2156 | htsf_ts->t20 = dhd_get_htsf(bus->dhd->info, 0); | |
2157 | } | |
2158 | } | |
2159 | #endif /* WLMEDIA_HTSF */ | |
2160 | #ifdef PKT_STATICS | |
2161 | len = (uint16)PKTLEN(osh, pkt); | |
2162 | switch(chan) { | |
2163 | case SDPCM_CONTROL_CHANNEL: | |
2164 | tx_statics.ctrl_count++; | |
2165 | tx_statics.ctrl_size += len; | |
2166 | break; | |
2167 | case SDPCM_DATA_CHANNEL: | |
2168 | tx_statics.data_count++; | |
2169 | tx_statics.data_size += len; | |
2170 | break; | |
2171 | case SDPCM_GLOM_CHANNEL: | |
2172 | tx_statics.glom_count++; | |
2173 | tx_statics.glom_size += len; | |
2174 | break; | |
2175 | case SDPCM_EVENT_CHANNEL: | |
2176 | tx_statics.event_count++; | |
2177 | tx_statics.event_size += len; | |
2178 | break; | |
2179 | case SDPCM_TEST_CHANNEL: | |
2180 | tx_statics.test_count++; | |
2181 | tx_statics.test_size += len; | |
2182 | break; | |
2183 | ||
2184 | default: | |
2185 | break; | |
2186 | } | |
2187 | #endif /* PKT_STATICS */ | |
2188 | #ifdef DHD_DEBUG | |
2189 | if (PKTPRIO(pkt) < ARRAYSIZE(tx_packets)) | |
2190 | tx_packets[PKTPRIO(pkt)]++; | |
2191 | #endif /* DHD_DEBUG */ | |
2192 | ||
2193 | /* align the data pointer, allocate a new packet if there is not enough space (new | |
2194 | * packet data pointer will be aligned thus no padding will be needed) | |
2195 | */ | |
2196 | head_padding = (uintptr)frame % DHD_SDALIGN; | |
2197 | if (PKTHEADROOM(osh, pkt) < head_padding) { | |
2198 | head_padding = 0; | |
2199 | alloc_new_pkt = TRUE; | |
2200 | } else { | |
2201 | uint cur_chain_total_len; | |
2202 | int chain_tail_padding = 0; | |
2203 | ||
2204 | /* All packets need to be aligned by DHD_SDALIGN */ | |
2205 | modulo = (pkt_len + head_padding) % DHD_SDALIGN; | |
2206 | tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0; | |
2207 | ||
2208 | /* Total pkt chain length needs to be aligned by block size, | |
2209 | * unless it is a single pkt chain with total length less than one block size, | |
2210 | * which we prefer sending by byte mode. | |
2211 | * | |
2212 | * Do the chain alignment here if | |
2213 | * 1. This is the last pkt of the chain of multiple pkts or a single pkt. | |
2214 | * 2-1. This chain is of multiple pkts, or | |
2215 | * 2-2. This is a single pkt whose size is longer than one block size. | |
2216 | */ | |
2217 | cur_chain_total_len = prev_chain_total_len + | |
2218 | (head_padding + pkt_len + tail_padding); | |
2219 | if (last_chained_pkt && bus->blocksize != 0 && | |
2220 | (cur_chain_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) { | |
2221 | modulo = cur_chain_total_len % bus->blocksize; | |
2222 | chain_tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0; | |
2223 | } | |
2224 | ||
2225 | #ifdef DHDENABLE_TAILPAD | |
2226 | if (PKTTAILROOM(osh, pkt) < tail_padding) { | |
2227 | /* We don't have tail room to align by DHD_SDALIGN */ | |
2228 | alloc_new_pkt = TRUE; | |
2229 | bus->tx_tailpad_pktget++; | |
2230 | } else if (PKTTAILROOM(osh, pkt) < tail_padding + chain_tail_padding) { | |
2231 | /* We have tail room for tail_padding of this pkt itself, but not for | |
2232 | * total pkt chain alignment by block size. | |
2233 | * Use the padding packet to avoid memory copy if applicable, | |
2234 | * otherwise, just allocate a new pkt. | |
2235 | */ | |
2236 | if (bus->pad_pkt) { | |
2237 | *pad_pkt_len = chain_tail_padding; | |
2238 | bus->tx_tailpad_chain++; | |
2239 | } else { | |
2240 | alloc_new_pkt = TRUE; | |
2241 | bus->tx_tailpad_pktget++; | |
2242 | } | |
2243 | } else | |
2244 | /* This last pkt's tailroom is sufficient to hold both tail_padding | |
2245 | * of the pkt itself and chain_tail_padding of total pkt chain | |
2246 | */ | |
2247 | #endif /* DHDENABLE_TAILPAD */ | |
2248 | tail_padding += chain_tail_padding; | |
2249 | } | |
2250 | ||
2251 | DHD_INFO(("%s sdhdr len + orig_pkt_len %d h_pad %d t_pad %d pad_pkt_len %d\n", | |
2252 | __FUNCTION__, pkt_len, head_padding, tail_padding, *pad_pkt_len)); | |
2253 | ||
2254 | if (alloc_new_pkt) { | |
2255 | void *tmp_pkt; | |
2256 | int newpkt_size; | |
2257 | int cur_total_len; | |
2258 | ||
2259 | ASSERT(*pad_pkt_len == 0); | |
2260 | ||
2261 | DHD_INFO(("%s allocating new packet for padding\n", __FUNCTION__)); | |
2262 | ||
2263 | /* head pointer is aligned now, no padding needed */ | |
2264 | head_padding = 0; | |
2265 | ||
2266 | /* update the tail padding as it depends on the head padding, since a new packet is | |
2267 | * allocated, the head padding is non longer needed and packet length is chagned | |
2268 | */ | |
2269 | ||
2270 | cur_total_len = prev_chain_total_len + pkt_len; | |
2271 | if (last_chained_pkt && bus->blocksize != 0 && | |
2272 | (cur_total_len > (int)bus->blocksize || prev_chain_total_len > 0)) { | |
2273 | modulo = cur_total_len % bus->blocksize; | |
2274 | tail_padding = modulo > 0 ? (bus->blocksize - modulo) : 0; | |
2275 | } else { | |
2276 | modulo = pkt_len % DHD_SDALIGN; | |
2277 | tail_padding = modulo > 0 ? (DHD_SDALIGN - modulo) : 0; | |
2278 | } | |
2279 | ||
2280 | newpkt_size = PKTLEN(osh, pkt) + bus->blocksize + DHD_SDALIGN; | |
2281 | bus->dhd->tx_realloc++; | |
2282 | tmp_pkt = PKTGET(osh, newpkt_size, TRUE); | |
2283 | if (tmp_pkt == NULL) { | |
2284 | DHD_ERROR(("failed to alloc new %d byte packet\n", newpkt_size)); | |
2285 | return BCME_NOMEM; | |
2286 | } | |
2287 | PKTALIGN(osh, tmp_pkt, PKTLEN(osh, pkt), DHD_SDALIGN); | |
2288 | bcopy(PKTDATA(osh, pkt), PKTDATA(osh, tmp_pkt), PKTLEN(osh, pkt)); | |
2289 | *new_pkt = tmp_pkt; | |
2290 | pkt = tmp_pkt; | |
2291 | } | |
2292 | ||
2293 | if (head_padding) | |
2294 | PKTPUSH(osh, pkt, head_padding); | |
2295 | ||
2296 | frame = (uint8*)PKTDATA(osh, pkt); | |
2297 | bzero(frame, head_padding + sdpcm_hdrlen); | |
2298 | pkt_len = (uint16)PKTLEN(osh, pkt); | |
2299 | ||
2300 | /* the header has the followming format | |
2301 | * 4-byte HW frame tag: length, ~length (for glom this is the total length) | |
2302 | * | |
2303 | * 8-byte HW extesion flags (glom mode only) as the following: | |
2304 | * 2-byte packet length, excluding HW tag and padding | |
2305 | * 2-byte frame channel and frame flags (e.g. next frame following) | |
2306 | * 2-byte header length | |
2307 | * 2-byte tail padding size | |
2308 | * | |
2309 | * 8-byte SW frame tags as the following | |
2310 | * 4-byte flags: host tx seq, channel, data offset | |
2311 | * 4-byte flags: TBD | |
2312 | */ | |
2313 | ||
2314 | swhdr_offset = SDPCM_FRAMETAG_LEN; | |
2315 | ||
2316 | /* hardware frame tag: | |
2317 | * | |
2318 | * in tx-glom mode, dongle only checks the hardware frame tag in the first | |
2319 | * packet and sees it as the total lenght of the glom (including tail padding), | |
2320 | * for each packet in the glom, the packet length needs to be updated, (see | |
2321 | * below PKTSETLEN) | |
2322 | * | |
2323 | * in non tx-glom mode, PKTLEN still need to include tail padding as to be | |
2324 | * referred to in sdioh_request_buffer(). The tail length will be excluded in | |
2325 | * dhdsdio_txpkt_postprocess(). | |
2326 | */ | |
2327 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
2328 | if (bus->dhd->conf->txglom_bucket_size) | |
2329 | tail_padding = 0; | |
2330 | #endif | |
2331 | *(uint16*)frame = (uint16)htol16(pkt_len); | |
2332 | *(((uint16*)frame) + 1) = (uint16)htol16(~pkt_len); | |
2333 | pkt_len += tail_padding; | |
2334 | ||
2335 | /* hardware extesion flags */ | |
2336 | if (bus->txglom_enable) { | |
2337 | uint32 hwheader1; | |
2338 | uint32 hwheader2; | |
2339 | #ifdef BCMSDIOH_TXGLOM_EXT | |
2340 | uint32 act_len = pkt_len - tail_padding; | |
2341 | uint32 real_pad = 0; | |
2342 | if(bus->dhd->conf->txglom_ext && !last_chained_pkt) { | |
2343 | tail_padding = 0; | |
2344 | if(first_frame == 0) { | |
2345 | // first pkt, add pad to bucket size - recv offset | |
2346 | pkt_len = bus->dhd->conf->txglom_bucket_size - TXGLOM_RECV_OFFSET; | |
2347 | } else { | |
2348 | // add pad to bucket size | |
2349 | pkt_len = bus->dhd->conf->txglom_bucket_size; | |
2350 | } | |
2351 | swhdr_offset += SDPCM_HWEXT_LEN; | |
2352 | hwheader1 = (act_len - SDPCM_FRAMETAG_LEN) | (last_chained_pkt << 24); | |
2353 | hwheader2 = (pkt_len - act_len) << 16; | |
2354 | htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN); | |
2355 | htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4); | |
2356 | real_pad = pkt_len - act_len; | |
2357 | ||
2358 | if (PKTTAILROOM(osh, pkt) < real_pad) { | |
2359 | DHD_INFO(("%s : insufficient tailroom %d for %d real_pad\n", | |
2360 | __func__, (int)PKTTAILROOM(osh, pkt), real_pad)); | |
2361 | if (PKTPADTAILROOM(osh, pkt, real_pad)) { | |
2362 | DHD_ERROR(("CHK1: padding error size %d\n", real_pad)); | |
2363 | } else | |
2364 | frame = (uint8 *)PKTDATA(osh, pkt); | |
2365 | } | |
2366 | } else | |
2367 | #endif | |
2368 | { | |
2369 | swhdr_offset += SDPCM_HWEXT_LEN; | |
2370 | hwheader1 = (pkt_len - SDPCM_FRAMETAG_LEN - tail_padding) | | |
2371 | (last_chained_pkt << 24); | |
2372 | hwheader2 = (tail_padding) << 16; | |
2373 | htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN); | |
2374 | htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4); | |
2375 | } | |
2376 | } | |
2377 | PKTSETLEN((osh), (pkt), (pkt_len)); | |
2378 | ||
2379 | /* software frame tags */ | |
2380 | swheader = ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | |
2381 | | (txseq % SDPCM_SEQUENCE_WRAP) | | |
2382 | (((head_padding + sdpcm_hdrlen) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK); | |
2383 | htol32_ua_store(swheader, frame + swhdr_offset); | |
2384 | htol32_ua_store(0, frame + swhdr_offset + sizeof(swheader)); | |
2385 | ||
2386 | return pkt_len; | |
2387 | } | |
2388 | ||
2389 | static int dhdsdio_txpkt_postprocess(dhd_bus_t *bus, void *pkt) | |
2390 | { | |
2391 | osl_t *osh; | |
2392 | uint8 *frame; | |
2393 | int data_offset; | |
2394 | int tail_padding; | |
2395 | int swhdr_offset = SDPCM_FRAMETAG_LEN + (bus->txglom_enable ? SDPCM_HWEXT_LEN : 0); | |
2396 | ||
2397 | (void)osh; | |
2398 | osh = bus->dhd->osh; | |
2399 | ||
2400 | /* restore pkt buffer pointer, but keeps the header pushed by dhd_prot_hdrpush */ | |
2401 | frame = (uint8*)PKTDATA(osh, pkt); | |
2402 | ||
2403 | DHD_INFO(("%s PKTLEN before postprocess %d", | |
2404 | __FUNCTION__, PKTLEN(osh, pkt))); | |
2405 | ||
2406 | /* PKTLEN still includes tail_padding, so exclude it. | |
2407 | * We shall have head_padding + original pkt_len for PKTLEN afterwards. | |
2408 | */ | |
2409 | if (bus->txglom_enable) { | |
2410 | /* txglom pkts have tail_padding length in HW ext header */ | |
2411 | tail_padding = ltoh32_ua(frame + SDPCM_FRAMETAG_LEN + 4) >> 16; | |
2412 | PKTSETLEN(osh, pkt, PKTLEN(osh, pkt) - tail_padding); | |
2413 | DHD_INFO((" txglom pkt: tail_padding %d PKTLEN %d\n", | |
2414 | tail_padding, PKTLEN(osh, pkt))); | |
2415 | } else { | |
2416 | /* non-txglom pkts have head_padding + original pkt length in HW frame tag. | |
2417 | * We cannot refer to this field for txglom pkts as the first pkt of the chain will | |
2418 | * have the field for the total length of the chain. | |
2419 | */ | |
2420 | PKTSETLEN(osh, pkt, *(uint16*)frame); | |
2421 | DHD_INFO((" non-txglom pkt: HW frame tag len %d after PKTLEN %d\n", | |
2422 | *(uint16*)frame, PKTLEN(osh, pkt))); | |
2423 | } | |
2424 | ||
2425 | data_offset = ltoh32_ua(frame + swhdr_offset); | |
2426 | data_offset = (data_offset & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT; | |
2427 | /* Get rid of sdpcm header + head_padding */ | |
2428 | PKTPULL(osh, pkt, data_offset); | |
2429 | ||
2430 | DHD_INFO(("%s data_offset %d, PKTLEN %d\n", | |
2431 | __FUNCTION__, data_offset, PKTLEN(osh, pkt))); | |
2432 | ||
2433 | return BCME_OK; | |
2434 | } | |
2435 | ||
2436 | static int dhdsdio_txpkt(dhd_bus_t *bus, uint chan, void** pkts, int num_pkt, bool free_pkt) | |
2437 | { | |
2438 | int i; | |
2439 | int ret = 0; | |
2440 | osl_t *osh; | |
2441 | bcmsdh_info_t *sdh; | |
2442 | void *pkt = NULL; | |
2443 | void *pkt_chain; | |
2444 | int total_len = 0; | |
2445 | void *head_pkt = NULL; | |
2446 | void *prev_pkt = NULL; | |
2447 | int pad_pkt_len = 0; | |
2448 | int new_pkt_num = 0; | |
2449 | void *new_pkts[MAX_TX_PKTCHAIN_CNT]; | |
2450 | bool wlfc_enabled = FALSE; | |
2451 | ||
2452 | if (bus->dhd->dongle_reset) | |
2453 | return BCME_NOTREADY; | |
2454 | ||
2455 | if (num_pkt <= 0) | |
2456 | return BCME_BADARG; | |
2457 | ||
2458 | sdh = bus->sdh; | |
2459 | osh = bus->dhd->osh; | |
2460 | /* init new_pkts[0] to make some compiler happy, not necessary as we check new_pkt_num */ | |
2461 | new_pkts[0] = NULL; | |
2462 | ||
2463 | for (i = 0; i < num_pkt; i++) { | |
2464 | int pkt_len; | |
2465 | bool last_pkt; | |
2466 | void *new_pkt = NULL; | |
2467 | ||
2468 | pkt = pkts[i]; | |
2469 | ASSERT(pkt); | |
2470 | last_pkt = (i == num_pkt - 1); | |
2471 | pkt_len = dhdsdio_txpkt_preprocess(bus, pkt, chan, bus->tx_seq + i, | |
2472 | total_len, last_pkt, &pad_pkt_len, &new_pkt | |
2473 | #if defined(BCMSDIOH_TXGLOM_EXT) | |
2474 | , i | |
2475 | #endif | |
2476 | ); | |
2477 | if (pkt_len <= 0) | |
2478 | goto done; | |
2479 | if (new_pkt) { | |
2480 | pkt = new_pkt; | |
2481 | new_pkts[new_pkt_num++] = new_pkt; | |
2482 | } | |
2483 | total_len += pkt_len; | |
2484 | ||
2485 | PKTSETNEXT(osh, pkt, NULL); | |
2486 | /* insert the packet into the list */ | |
2487 | head_pkt ? PKTSETNEXT(osh, prev_pkt, pkt) : (head_pkt = pkt); | |
2488 | prev_pkt = pkt; | |
2489 | ||
2490 | } | |
2491 | ||
2492 | /* Update the HW frame tag (total length) in the first pkt of the glom */ | |
2493 | if (bus->txglom_enable) { | |
2494 | uint8 *frame; | |
2495 | ||
2496 | total_len += pad_pkt_len; | |
2497 | frame = (uint8*)PKTDATA(osh, head_pkt); | |
2498 | *(uint16*)frame = (uint16)htol16(total_len); | |
2499 | *(((uint16*)frame) + 1) = (uint16)htol16(~total_len); | |
2500 | ||
2501 | } | |
2502 | ||
2503 | #ifdef DHDENABLE_TAILPAD | |
2504 | /* if a padding packet if needed, insert it to the end of the link list */ | |
2505 | if (pad_pkt_len) { | |
2506 | PKTSETLEN(osh, bus->pad_pkt, pad_pkt_len); | |
2507 | PKTSETNEXT(osh, pkt, bus->pad_pkt); | |
2508 | } | |
2509 | #endif /* DHDENABLE_TAILPAD */ | |
2510 | ||
2511 | /* dhd_bcmsdh_send_buf ignores the buffer pointer if he packet | |
2512 | * parameter is not NULL, for non packet chian we pass NULL pkt pointer | |
2513 | * so it will take the aligned length and buffer pointer. | |
2514 | */ | |
2515 | pkt_chain = PKTNEXT(osh, head_pkt) ? head_pkt : NULL; | |
2516 | ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC, | |
2517 | PKTDATA(osh, head_pkt), total_len, pkt_chain, NULL, NULL, TXRETRIES); | |
2518 | if (ret == BCME_OK) | |
2519 | bus->tx_seq = (bus->tx_seq + num_pkt) % SDPCM_SEQUENCE_WRAP; | |
2520 | ||
2521 | /* if a padding packet was needed, remove it from the link list as it not a data pkt */ | |
2522 | if (pad_pkt_len && pkt) | |
2523 | PKTSETNEXT(osh, pkt, NULL); | |
2524 | ||
2525 | done: | |
2526 | pkt = head_pkt; | |
2527 | while (pkt) { | |
2528 | void *pkt_next = PKTNEXT(osh, pkt); | |
2529 | PKTSETNEXT(osh, pkt, NULL); | |
2530 | dhdsdio_txpkt_postprocess(bus, pkt); | |
2531 | pkt = pkt_next; | |
2532 | } | |
2533 | ||
2534 | /* new packets might be allocated due to insufficient room for padding, but we | |
2535 | * still have to indicate the original packets to upper layer | |
2536 | */ | |
2537 | for (i = 0; i < num_pkt; i++) { | |
2538 | pkt = pkts[i]; | |
2539 | wlfc_enabled = FALSE; | |
2540 | #ifdef PROP_TXSTATUS | |
2541 | if (DHD_PKTTAG_WLFCPKT(PKTTAG(pkt))) { | |
2542 | wlfc_enabled = (dhd_wlfc_txcomplete(bus->dhd, pkt, ret == 0) != | |
2543 | WLFC_UNSUPPORTED); | |
2544 | } | |
2545 | #endif /* PROP_TXSTATUS */ | |
2546 | if (!wlfc_enabled) { | |
2547 | PKTSETNEXT(osh, pkt, NULL); | |
2548 | dhd_txcomplete(bus->dhd, pkt, ret != 0); | |
2549 | if (free_pkt) | |
2550 | PKTFREE(osh, pkt, TRUE); | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | for (i = 0; i < new_pkt_num; i++) | |
2555 | PKTFREE(osh, new_pkts[i], TRUE); | |
2556 | ||
2557 | return ret; | |
2558 | } | |
2559 | ||
2560 | static uint | |
2561 | dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes) | |
2562 | { | |
2563 | uint cnt = 0; | |
2564 | uint8 tx_prec_map; | |
2565 | uint16 txpktqlen = 0; | |
2566 | uint32 intstatus = 0; | |
2567 | uint retries = 0; | |
2568 | osl_t *osh; | |
2569 | uint datalen = 0; | |
2570 | dhd_pub_t *dhd = bus->dhd; | |
2571 | sdpcmd_regs_t *regs = bus->regs; | |
2572 | #ifdef DHD_LOSSLESS_ROAMING | |
2573 | uint8 *pktdata; | |
2574 | struct ether_header *eh; | |
2575 | #endif /* DHD_LOSSLESS_ROAMING */ | |
2576 | ||
2577 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
2578 | ||
2579 | if (!KSO_ENAB(bus)) { | |
2580 | DHD_ERROR(("%s: Device asleep\n", __FUNCTION__)); | |
2581 | return BCME_NODEVICE; | |
2582 | } | |
2583 | ||
2584 | osh = dhd->osh; | |
2585 | tx_prec_map = ~bus->flowcontrol; | |
2586 | #ifdef DHD_LOSSLESS_ROAMING | |
2587 | tx_prec_map &= dhd->dequeue_prec_map; | |
2588 | #endif /* DHD_LOSSLESS_ROAMING */ | |
2589 | for (cnt = 0; (cnt < maxframes) && DATAOK(bus);) { | |
2590 | int i; | |
2591 | int num_pkt = 1; | |
2592 | void *pkts[MAX_TX_PKTCHAIN_CNT]; | |
2593 | int prec_out; | |
2594 | ||
2595 | dhd_os_sdlock_txq(bus->dhd); | |
2596 | if (bus->txglom_enable) { | |
2597 | uint32 glomlimit = (uint32)bus->txglomsize; | |
2598 | #if defined(BCMSDIOH_STD) | |
2599 | if (bus->blocksize == 64) { | |
2600 | glomlimit = MIN((uint32)bus->txglomsize, BLK_64_MAXTXGLOM); | |
2601 | } | |
2602 | #endif /* BCMSDIOH_STD */ | |
2603 | num_pkt = MIN((uint32)DATABUFCNT(bus), glomlimit); | |
2604 | num_pkt = MIN(num_pkt, ARRAYSIZE(pkts)); | |
2605 | } | |
2606 | num_pkt = MIN(num_pkt, pktq_mlen(&bus->txq, tx_prec_map)); | |
2607 | for (i = 0; i < num_pkt; i++) { | |
2608 | pkts[i] = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out); | |
2609 | if (!pkts[i]) { | |
2610 | DHD_ERROR(("%s: pktq_mlen non-zero when no pkt\n", | |
2611 | __FUNCTION__)); | |
2612 | ASSERT(0); | |
2613 | break; | |
2614 | } | |
2615 | #ifdef DHD_LOSSLESS_ROAMING | |
2616 | pktdata = (uint8 *)PKTDATA(osh, pkts[i]); | |
2617 | #ifdef BDC | |
2618 | /* Skip BDC header */ | |
2619 | pktdata += BDC_HEADER_LEN + ((struct bdc_header *)pktdata)->dataOffset; | |
2620 | #endif | |
2621 | eh = (struct ether_header *)pktdata; | |
2622 | if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) { | |
2623 | uint8 prio = (uint8)PKTPRIO(pkts[i]); | |
2624 | ||
2625 | /* Restore to original priority for 802.1X packet */ | |
2626 | if (prio == PRIO_8021D_NC) { | |
2627 | PKTSETPRIO(pkts[i], dhd->prio_8021x); | |
2628 | } | |
2629 | } | |
2630 | #endif /* DHD_LOSSLESS_ROAMING */ | |
dfb0f3ae RC |
2631 | if (!bus->dhd->conf->orphan_move) |
2632 | PKTORPHAN(pkts[i], bus->dhd->conf->tsq); | |
010c3a89 RC |
2633 | datalen += PKTLEN(osh, pkts[i]); |
2634 | } | |
2635 | dhd_os_sdunlock_txq(bus->dhd); | |
2636 | ||
2637 | if (i == 0) | |
2638 | break; | |
2639 | if (dhdsdio_txpkt(bus, SDPCM_DATA_CHANNEL, pkts, i, TRUE) != BCME_OK) | |
2640 | dhd->tx_errors++; | |
2641 | else { | |
2642 | dhd->dstats.tx_bytes += datalen; | |
2643 | bus->txglomframes++; | |
2644 | bus->txglompkts += num_pkt; | |
2645 | } | |
2646 | cnt += i; | |
2647 | #ifdef PKT_STATICS | |
2648 | if (num_pkt) { | |
2649 | tx_statics.glom_cnt[num_pkt-1]++; | |
2650 | if (num_pkt > tx_statics.glom_max) | |
2651 | tx_statics.glom_max = num_pkt; | |
2652 | } | |
2653 | #endif | |
2654 | ||
2655 | /* In poll mode, need to check for other events */ | |
2656 | if (!bus->intr && cnt) | |
2657 | { | |
2658 | /* Check device status, signal pending interrupt */ | |
2659 | R_SDREG(intstatus, ®s->intstatus, retries); | |
2660 | bus->f2txdata++; | |
2661 | if (bcmsdh_regfail(bus->sdh)) | |
2662 | break; | |
2663 | if (intstatus & bus->hostintmask) | |
2664 | bus->ipend = TRUE; | |
2665 | } | |
2666 | ||
2667 | } | |
2668 | ||
dfb0f3ae RC |
2669 | if (dhd_doflow) { |
2670 | dhd_os_sdlock_txq(bus->dhd); | |
2671 | txpktqlen = pktq_len(&bus->txq); | |
2672 | dhd_os_sdunlock_txq(bus->dhd); | |
2673 | } | |
010c3a89 RC |
2674 | |
2675 | /* Do flow-control if needed */ | |
2676 | if (dhd->up && (dhd->busstate == DHD_BUS_DATA) && (txpktqlen < FCLOW)) { | |
2677 | bool wlfc_enabled = FALSE; | |
2678 | #ifdef PROP_TXSTATUS | |
2679 | wlfc_enabled = (dhd_wlfc_flowcontrol(dhd, OFF, TRUE) != WLFC_UNSUPPORTED); | |
2680 | #endif | |
2681 | if (!wlfc_enabled && dhd_doflow && dhd->txoff) { | |
2682 | dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF); | |
2683 | } | |
2684 | } | |
2685 | ||
2686 | return cnt; | |
2687 | } | |
2688 | ||
2689 | static void | |
2690 | dhdsdio_sendpendctl(dhd_bus_t *bus) | |
2691 | { | |
2692 | bcmsdh_info_t *sdh = bus->sdh; | |
2693 | int ret; | |
2694 | uint8* frame_seq = bus->ctrl_frame_buf + SDPCM_FRAMETAG_LEN; | |
2695 | ||
2696 | if (bus->txglom_enable) | |
2697 | frame_seq += SDPCM_HWEXT_LEN; | |
2698 | ||
2699 | if (*frame_seq != bus->tx_seq) { | |
2700 | DHD_INFO(("%s IOCTL frame seq lag detected!" | |
2701 | " frm_seq:%d != bus->tx_seq:%d, corrected\n", | |
2702 | __FUNCTION__, *frame_seq, bus->tx_seq)); | |
2703 | *frame_seq = bus->tx_seq; | |
2704 | } | |
2705 | ||
2706 | ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC, | |
2707 | (uint8 *)bus->ctrl_frame_buf, (uint32)bus->ctrl_frame_len, | |
2708 | NULL, NULL, NULL, 1); | |
2709 | if (ret == BCME_OK) | |
2710 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
2711 | ||
2712 | bus->ctrl_frame_stat = FALSE; | |
2713 | dhd_wait_event_wakeup(bus->dhd); | |
2714 | } | |
2715 | ||
2716 | int | |
2717 | dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen) | |
2718 | { | |
2719 | static int err_nodevice = 0; | |
2720 | uint8 *frame; | |
2721 | uint16 len; | |
2722 | uint32 swheader; | |
2723 | uint8 doff = 0; | |
2724 | int ret = -1; | |
2725 | uint8 sdpcm_hdrlen = bus->txglom_enable ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN; | |
2726 | ||
2727 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
2728 | ||
2729 | if (bus->dhd->dongle_reset) | |
2730 | return -EIO; | |
2731 | ||
2732 | /* Back the pointer to make a room for bus header */ | |
2733 | frame = msg - sdpcm_hdrlen; | |
2734 | len = (msglen += sdpcm_hdrlen); | |
2735 | ||
2736 | /* Add alignment padding (optional for ctl frames) */ | |
2737 | if (dhd_alignctl) { | |
2738 | if ((doff = ((uintptr)frame % DHD_SDALIGN))) { | |
2739 | frame -= doff; | |
2740 | len += doff; | |
2741 | msglen += doff; | |
2742 | bzero(frame, doff + sdpcm_hdrlen); | |
2743 | } | |
2744 | ASSERT(doff < DHD_SDALIGN); | |
2745 | } | |
2746 | doff += sdpcm_hdrlen; | |
2747 | ||
2748 | /* Round send length to next SDIO block */ | |
2749 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2750 | uint16 pad = bus->blocksize - (len % bus->blocksize); | |
2751 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | |
2752 | len += pad; | |
2753 | } else if (len % DHD_SDALIGN) { | |
2754 | len += DHD_SDALIGN - (len % DHD_SDALIGN); | |
2755 | } | |
2756 | ||
2757 | /* Satisfy length-alignment requirements */ | |
2758 | if (forcealign && (len & (ALIGNMENT - 1))) | |
2759 | len = ROUNDUP(len, ALIGNMENT); | |
2760 | ||
2761 | ASSERT(ISALIGNED((uintptr)frame, 2)); | |
2762 | ||
2763 | ||
2764 | /* Need to lock here to protect txseq and SDIO tx calls */ | |
32c27b7a | 2765 | dhd_os_sdlock(bus->dhd); |
dfb0f3ae RC |
2766 | if (bus->dhd->conf->txctl_tmo_fix > 0 && !TXCTLOK(bus)) { |
2767 | bus->ctrl_wait = TRUE; | |
32c27b7a | 2768 | dhd_os_sdunlock(bus->dhd); |
dfb0f3ae RC |
2769 | wait_event_interruptible_timeout(bus->ctrl_tx_wait, TXCTLOK(bus), |
2770 | msecs_to_jiffies(bus->dhd->conf->txctl_tmo_fix)); | |
32c27b7a | 2771 | dhd_os_sdlock(bus->dhd); |
dfb0f3ae | 2772 | bus->ctrl_wait = FALSE; |
ccd15baf | 2773 | } |
010c3a89 RC |
2774 | |
2775 | BUS_WAKE(bus); | |
2776 | ||
2777 | /* Make sure backplane clock is on */ | |
2778 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
2779 | ||
2780 | /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ | |
2781 | *(uint16*)frame = htol16((uint16)msglen); | |
2782 | *(((uint16*)frame) + 1) = htol16(~msglen); | |
2783 | ||
2784 | if (bus->txglom_enable) { | |
2785 | uint32 hwheader1, hwheader2; | |
2786 | /* Software tag: channel, sequence number, data offset */ | |
2787 | swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | |
2788 | | bus->tx_seq | |
2789 | | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK); | |
2790 | htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN + SDPCM_HWEXT_LEN); | |
2791 | htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN | |
2792 | + SDPCM_HWEXT_LEN + sizeof(swheader)); | |
2793 | ||
2794 | hwheader1 = (msglen - SDPCM_FRAMETAG_LEN) | (1 << 24); | |
2795 | hwheader2 = (len - (msglen)) << 16; | |
2796 | htol32_ua_store(hwheader1, frame + SDPCM_FRAMETAG_LEN); | |
2797 | htol32_ua_store(hwheader2, frame + SDPCM_FRAMETAG_LEN + 4); | |
2798 | ||
2799 | *(uint16*)frame = htol16(len); | |
2800 | *(((uint16*)frame) + 1) = htol16(~(len)); | |
2801 | } else { | |
2802 | /* Software tag: channel, sequence number, data offset */ | |
2803 | swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | |
2804 | | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK); | |
2805 | htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN); | |
2806 | htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader)); | |
2807 | } | |
2808 | ||
2809 | #ifdef DHD_ULP | |
2810 | dhd_ulp_set_path(bus->dhd, DHD_ULP_TX_CTRL); | |
2811 | ||
2812 | if (!TXCTLOK(bus) || !dhd_ulp_f2_ready(bus->dhd, bus->sdh)) | |
2813 | #else | |
2814 | if (!TXCTLOK(bus)) | |
2815 | #endif | |
2816 | { | |
2817 | DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n", | |
2818 | __FUNCTION__, bus->tx_max, bus->tx_seq)); | |
2819 | bus->ctrl_frame_stat = TRUE; | |
2820 | /* Send from dpc */ | |
2821 | bus->ctrl_frame_buf = frame; | |
2822 | bus->ctrl_frame_len = len; | |
2823 | ||
2824 | if (!bus->dpc_sched) { | |
2825 | bus->dpc_sched = TRUE; | |
2826 | dhd_sched_dpc(bus->dhd); | |
2827 | } | |
2828 | if (bus->ctrl_frame_stat) { | |
2829 | dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat); | |
2830 | } | |
2831 | ||
2832 | if (bus->ctrl_frame_stat == FALSE) { | |
2833 | DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __FUNCTION__)); | |
2834 | ret = 0; | |
2835 | } else { | |
2836 | bus->dhd->txcnt_timeout++; | |
2837 | if (!bus->dhd->hang_was_sent) { | |
2838 | #ifdef CUSTOMER_HW4_DEBUG | |
2839 | uint32 status, retry = 0; | |
2840 | R_SDREG(status, &bus->regs->intstatus, retry); | |
2841 | DHD_TRACE_HW4(("%s: txcnt_timeout, INT status=0x%08X\n", | |
2842 | __FUNCTION__, status)); | |
2843 | DHD_TRACE_HW4(("%s : tx_max : %d, tx_seq : %d, clkstate : %d \n", | |
2844 | __FUNCTION__, bus->tx_max, bus->tx_seq, bus->clkstate)); | |
2845 | #endif /* CUSTOMER_HW4_DEBUG */ | |
2846 | DHD_ERROR(("%s: ctrl_frame_stat == TRUE txcnt_timeout=%d\n", | |
2847 | __FUNCTION__, bus->dhd->txcnt_timeout)); | |
2848 | } | |
2849 | #ifdef DHD_FW_COREDUMP | |
2850 | /* Collect socram dump */ | |
2851 | if (bus->dhd->memdump_enabled) { | |
2852 | /* collect core dump */ | |
2853 | bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT_TX; | |
2854 | dhd_os_sdunlock(bus->dhd); | |
2855 | dhd_bus_mem_dump(bus->dhd); | |
2856 | dhd_os_sdlock(bus->dhd); | |
2857 | } | |
2858 | #endif /* DHD_FW_COREDUMP */ | |
2859 | ret = -1; | |
2860 | bus->ctrl_frame_stat = FALSE; | |
2861 | goto done; | |
2862 | } | |
2863 | } | |
2864 | ||
2865 | bus->dhd->txcnt_timeout = 0; | |
2866 | bus->ctrl_frame_stat = TRUE; | |
2867 | ||
2868 | if (ret == -1) { | |
2869 | #ifdef DHD_DEBUG | |
2870 | if (DHD_BYTES_ON() && DHD_CTL_ON()) { | |
2871 | prhex("Tx Frame", frame, len); | |
2872 | } else if (DHD_HDRS_ON()) { | |
2873 | prhex("TxHdr", frame, MIN(len, 16)); | |
2874 | } | |
2875 | #endif | |
2876 | #ifdef PKT_STATICS | |
2877 | tx_statics.ctrl_count++; | |
2878 | tx_statics.ctrl_size += len; | |
2879 | #endif | |
2880 | ret = dhd_bcmsdh_send_buffer(bus, frame, len); | |
2881 | } | |
2882 | bus->ctrl_frame_stat = FALSE; | |
2883 | #ifdef DHD_ULP | |
2884 | dhd_ulp_enable_cached_sbwad(bus->dhd, bus->sdh); | |
2885 | #endif /* DHD_ULP */ | |
2886 | ||
2887 | done: | |
2888 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched && | |
2889 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
2890 | bus->activity = FALSE; | |
2891 | dhdsdio_bussleep(bus, TRUE); | |
2892 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
2893 | } | |
2894 | ||
2895 | dhd_os_sdunlock(bus->dhd); | |
2896 | ||
2897 | if (ret) | |
2898 | bus->dhd->tx_ctlerrs++; | |
2899 | else | |
2900 | bus->dhd->tx_ctlpkts++; | |
2901 | ||
2902 | if (bus->dhd->txcnt_timeout >= MAX_CNTL_TX_TIMEOUT) { | |
2903 | return -ETIMEDOUT; | |
2904 | } | |
2905 | ||
2906 | if (ret == BCME_NODEVICE) | |
2907 | err_nodevice++; | |
2908 | else | |
2909 | err_nodevice = 0; | |
2910 | ||
2911 | return ret ? err_nodevice >= ERROR_BCME_NODEVICE_MAX ? -ETIMEDOUT : -EIO : 0; | |
2912 | } | |
2913 | ||
2914 | int | |
2915 | dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen) | |
2916 | { | |
2917 | int timeleft; | |
2918 | uint rxlen = 0; | |
91a2c117 | 2919 | static uint cnt = 0; |
010c3a89 RC |
2920 | |
2921 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
2922 | ||
2923 | if (bus->dhd->dongle_reset) | |
2924 | return -EIO; | |
2925 | ||
2926 | /* Wait until control frame is available */ | |
91a2c117 | 2927 | timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, false); |
010c3a89 RC |
2928 | |
2929 | dhd_os_sdlock(bus->dhd); | |
2930 | rxlen = bus->rxlen; | |
2931 | bcopy(bus->rxctl, msg, MIN(msglen, rxlen)); | |
2932 | bus->rxlen = 0; | |
2933 | dhd_os_sdunlock(bus->dhd); | |
2934 | ||
91a2c117 RC |
2935 | if (bus->dhd->conf->ctrl_resched > 0 && !rxlen && timeleft == 0) { |
2936 | cnt++; | |
2937 | if (cnt <= bus->dhd->conf->ctrl_resched) { | |
2938 | uint32 status, retry = 0; | |
2939 | R_SDREG(status, &bus->regs->intstatus, retry); | |
2940 | if ((status & I_HMB_HOST_INT) || PKT_AVAILABLE(bus, status)) { | |
2941 | DHD_ERROR(("%s: reschedule dhd_dpc, cnt=%d, status=0x%x\n", | |
2942 | __FUNCTION__, cnt, status)); | |
2943 | bus->ipend = TRUE; | |
2944 | bus->dpc_sched = TRUE; | |
2945 | dhd_sched_dpc(bus->dhd); | |
2946 | ||
2947 | /* Wait until control frame is available */ | |
2948 | timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, true); | |
2949 | ||
2950 | dhd_os_sdlock(bus->dhd); | |
2951 | rxlen = bus->rxlen; | |
2952 | bcopy(bus->rxctl, msg, MIN(msglen, rxlen)); | |
2953 | bus->rxlen = 0; | |
2954 | dhd_os_sdunlock(bus->dhd); | |
2955 | } | |
2956 | } | |
2957 | } else { | |
2958 | cnt = 0; | |
2959 | } | |
2960 | ||
010c3a89 RC |
2961 | if (rxlen) { |
2962 | DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n", | |
2963 | __FUNCTION__, rxlen, msglen)); | |
2964 | } else { | |
2965 | if (timeleft == 0) { | |
2966 | #ifdef DHD_DEBUG | |
2967 | uint32 status, retry = 0; | |
2968 | R_SDREG(status, &bus->regs->intstatus, retry); | |
2969 | DHD_ERROR(("%s: resumed on timeout, INT status=0x%08X\n", | |
2970 | __FUNCTION__, status)); | |
2971 | #else | |
2972 | DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__)); | |
2973 | #endif /* DHD_DEBUG */ | |
2974 | if (!bus->dhd->dongle_trap_occured) { | |
2975 | #ifdef DHD_FW_COREDUMP | |
2976 | bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT; | |
2977 | #endif /* DHD_FW_COREDUMP */ | |
2978 | dhd_os_sdlock(bus->dhd); | |
2979 | dhdsdio_checkdied(bus, NULL, 0); | |
2980 | dhd_os_sdunlock(bus->dhd); | |
2981 | } | |
2982 | } else { | |
2983 | DHD_CTL(("%s: resumed for unknown reason?\n", __FUNCTION__)); | |
2984 | if (!bus->dhd->dongle_trap_occured) { | |
2985 | #ifdef DHD_FW_COREDUMP | |
2986 | bus->dhd->memdump_type = DUMP_TYPE_RESUMED_UNKNOWN; | |
2987 | #endif /* DHD_FW_COREDUMP */ | |
2988 | dhd_os_sdlock(bus->dhd); | |
2989 | dhdsdio_checkdied(bus, NULL, 0); | |
2990 | dhd_os_sdunlock(bus->dhd); | |
2991 | } | |
2992 | } | |
2993 | #ifdef DHD_FW_COREDUMP | |
2994 | /* Dump the ram image */ | |
2995 | if (bus->dhd->memdump_enabled && !bus->dhd->dongle_trap_occured) | |
2996 | dhdsdio_mem_dump(bus); | |
2997 | #endif /* DHD_FW_COREDUMP */ | |
2998 | } | |
2999 | if (timeleft == 0) { | |
3000 | if (rxlen == 0) | |
3001 | bus->dhd->rxcnt_timeout++; | |
3002 | DHD_ERROR(("%s: rxcnt_timeout=%d, rxlen=%d\n", __FUNCTION__, | |
3003 | bus->dhd->rxcnt_timeout, rxlen)); | |
3004 | #ifdef DHD_FW_COREDUMP | |
3005 | /* collect socram dump */ | |
3006 | if (bus->dhd->memdump_enabled) { | |
3007 | bus->dhd->memdump_type = DUMP_TYPE_RESUMED_ON_TIMEOUT_RX; | |
3008 | dhd_bus_mem_dump(bus->dhd); | |
3009 | } | |
3010 | #endif /* DHD_FW_COREDUMP */ | |
3011 | } else { | |
3012 | bus->dhd->rxcnt_timeout = 0; | |
3013 | } | |
3014 | ||
3015 | if (rxlen) | |
3016 | bus->dhd->rx_ctlpkts++; | |
3017 | else | |
3018 | bus->dhd->rx_ctlerrs++; | |
3019 | ||
3020 | if (bus->dhd->rxcnt_timeout >= MAX_CNTL_RX_TIMEOUT) { | |
3021 | return -ETIMEDOUT; | |
3022 | } | |
3023 | ||
3024 | ||
3025 | if (bus->dhd->dongle_trap_occured) | |
3026 | return -EREMOTEIO; | |
3027 | ||
3028 | return rxlen ? (int)rxlen : -EIO; | |
3029 | } | |
3030 | ||
3031 | /* IOVar table */ | |
3032 | enum { | |
3033 | IOV_INTR = 1, | |
3034 | IOV_POLLRATE, | |
3035 | IOV_SDREG, | |
3036 | IOV_SBREG, | |
3037 | IOV_SDCIS, | |
3038 | IOV_RAMSIZE, | |
3039 | IOV_RAMSTART, | |
3040 | #ifdef DHD_DEBUG | |
3041 | IOV_CHECKDIED, | |
3042 | IOV_SERIALCONS, | |
3043 | #endif /* DHD_DEBUG */ | |
3044 | IOV_SET_DOWNLOAD_STATE, | |
3045 | IOV_SOCRAM_STATE, | |
3046 | IOV_FORCEEVEN, | |
3047 | IOV_SDIOD_DRIVE, | |
3048 | IOV_READAHEAD, | |
3049 | IOV_SDRXCHAIN, | |
3050 | IOV_ALIGNCTL, | |
3051 | IOV_SDALIGN, | |
3052 | IOV_DEVRESET, | |
3053 | IOV_CPU, | |
3054 | #if defined(USE_SDIOFIFO_IOVAR) | |
3055 | IOV_WATERMARK, | |
3056 | IOV_MESBUSYCTRL, | |
3057 | #endif /* USE_SDIOFIFO_IOVAR */ | |
3058 | #ifdef SDTEST | |
3059 | IOV_PKTGEN, | |
3060 | IOV_EXTLOOP, | |
3061 | #endif /* SDTEST */ | |
3062 | IOV_SPROM, | |
3063 | IOV_TXBOUND, | |
3064 | IOV_RXBOUND, | |
3065 | IOV_TXMINMAX, | |
3066 | IOV_IDLETIME, | |
3067 | IOV_IDLECLOCK, | |
3068 | IOV_SD1IDLE, | |
3069 | IOV_SLEEP, | |
3070 | IOV_DONGLEISOLATION, | |
3071 | IOV_KSO, | |
3072 | IOV_DEVSLEEP, | |
3073 | IOV_DEVCAP, | |
3074 | IOV_VARS, | |
3075 | #ifdef SOFTAP | |
3076 | IOV_FWPATH, | |
3077 | #endif | |
3078 | IOV_TXGLOMSIZE, | |
3079 | IOV_TXGLOMMODE, | |
3080 | IOV_HANGREPORT, | |
3081 | IOV_TXINRX_THRES, | |
3082 | IOV_SDIO_SUSPEND | |
3083 | }; | |
3084 | ||
3085 | const bcm_iovar_t dhdsdio_iovars[] = { | |
3086 | {"intr", IOV_INTR, 0, 0, IOVT_BOOL, 0 }, | |
3087 | {"sleep", IOV_SLEEP, 0, 0, IOVT_BOOL, 0 }, | |
3088 | {"pollrate", IOV_POLLRATE, 0, 0, IOVT_UINT32, 0 }, | |
3089 | {"idletime", IOV_IDLETIME, 0, 0, IOVT_INT32, 0 }, | |
3090 | {"idleclock", IOV_IDLECLOCK, 0, 0, IOVT_INT32, 0 }, | |
3091 | {"sd1idle", IOV_SD1IDLE, 0, 0, IOVT_BOOL, 0 }, | |
3092 | {"ramsize", IOV_RAMSIZE, 0, 0, IOVT_UINT32, 0 }, | |
3093 | {"ramstart", IOV_RAMSTART, 0, 0, IOVT_UINT32, 0 }, | |
3094 | {"dwnldstate", IOV_SET_DOWNLOAD_STATE, 0, 0, IOVT_BOOL, 0 }, | |
3095 | {"socram_state", IOV_SOCRAM_STATE, 0, 0, IOVT_BOOL, 0 }, | |
3096 | {"vars", IOV_VARS, 0, 0, IOVT_BUFFER, 0 }, | |
3097 | {"sdiod_drive", IOV_SDIOD_DRIVE, 0, 0, IOVT_UINT32, 0 }, | |
3098 | {"readahead", IOV_READAHEAD, 0, 0, IOVT_BOOL, 0 }, | |
3099 | {"sdrxchain", IOV_SDRXCHAIN, 0, 0, IOVT_BOOL, 0 }, | |
3100 | {"alignctl", IOV_ALIGNCTL, 0, 0, IOVT_BOOL, 0 }, | |
3101 | {"sdalign", IOV_SDALIGN, 0, 0, IOVT_BOOL, 0 }, | |
3102 | {"devreset", IOV_DEVRESET, 0, 0, IOVT_BOOL, 0 }, | |
3103 | #ifdef DHD_DEBUG | |
3104 | {"sdreg", IOV_SDREG, 0, 0, IOVT_BUFFER, sizeof(sdreg_t) }, | |
3105 | {"sbreg", IOV_SBREG, 0, 0, IOVT_BUFFER, sizeof(sdreg_t) }, | |
3106 | {"sd_cis", IOV_SDCIS, 0, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN }, | |
3107 | {"forcealign", IOV_FORCEEVEN, 0, 0, IOVT_BOOL, 0 }, | |
3108 | {"txbound", IOV_TXBOUND, 0, 0, IOVT_UINT32, 0 }, | |
3109 | {"rxbound", IOV_RXBOUND, 0, 0, IOVT_UINT32, 0 }, | |
3110 | {"txminmax", IOV_TXMINMAX, 0, 0, IOVT_UINT32, 0 }, | |
3111 | {"cpu", IOV_CPU, 0, 0, IOVT_BOOL, 0 }, | |
3112 | #ifdef DHD_DEBUG | |
3113 | {"checkdied", IOV_CHECKDIED, 0, 0, IOVT_BUFFER, 0 }, | |
3114 | {"serial", IOV_SERIALCONS, 0, 0, IOVT_UINT32, 0 }, | |
3115 | #endif /* DHD_DEBUG */ | |
3116 | #endif /* DHD_DEBUG */ | |
3117 | #ifdef SDTEST | |
3118 | {"extloop", IOV_EXTLOOP, 0, 0, IOVT_BOOL, 0 }, | |
3119 | {"pktgen", IOV_PKTGEN, 0, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t) }, | |
3120 | #endif /* SDTEST */ | |
3121 | #if defined(USE_SDIOFIFO_IOVAR) | |
3122 | {"watermark", IOV_WATERMARK, 0, 0, IOVT_UINT32, 0 }, | |
3123 | {"mesbusyctrl", IOV_MESBUSYCTRL, 0, 0, IOVT_UINT32, 0 }, | |
3124 | #endif /* USE_SDIOFIFO_IOVAR */ | |
3125 | {"devcap", IOV_DEVCAP, 0, 0, IOVT_UINT32, 0 }, | |
3126 | {"dngl_isolation", IOV_DONGLEISOLATION, 0, 0, IOVT_UINT32, 0 }, | |
3127 | {"kso", IOV_KSO, 0, 0, IOVT_UINT32, 0 }, | |
3128 | {"devsleep", IOV_DEVSLEEP, 0, 0, IOVT_UINT32, 0 }, | |
3129 | #ifdef SOFTAP | |
3130 | {"fwpath", IOV_FWPATH, 0, 0, IOVT_BUFFER, 0 }, | |
3131 | #endif | |
3132 | {"txglomsize", IOV_TXGLOMSIZE, 0, 0, IOVT_UINT32, 0 }, | |
3133 | {"fw_hang_report", IOV_HANGREPORT, 0, 0, IOVT_BOOL, 0 }, | |
3134 | {"txinrx_thres", IOV_TXINRX_THRES, 0, 0, IOVT_INT32, 0 }, | |
3135 | {"sdio_suspend", IOV_SDIO_SUSPEND, 0, 0, IOVT_UINT32, 0 }, | |
3136 | {NULL, 0, 0, 0, 0, 0 } | |
3137 | }; | |
3138 | ||
3139 | static void | |
3140 | dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div) | |
3141 | { | |
3142 | uint q1, q2; | |
3143 | ||
3144 | if (!div) { | |
3145 | bcm_bprintf(strbuf, "%s N/A", desc); | |
3146 | } else { | |
3147 | q1 = num / div; | |
3148 | q2 = (100 * (num - (q1 * div))) / div; | |
3149 | bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2); | |
3150 | } | |
3151 | } | |
3152 | ||
3153 | void | |
3154 | dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf) | |
3155 | { | |
3156 | dhd_bus_t *bus = dhdp->bus; | |
3157 | #if defined(DHD_WAKE_STATUS) && defined(DHD_WAKE_EVENT_STATUS) | |
3158 | int i; | |
3159 | #endif | |
3160 | ||
3161 | bcm_bprintf(strbuf, "Bus SDIO structure:\n"); | |
3162 | bcm_bprintf(strbuf, "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n", | |
3163 | bus->hostintmask, bus->intstatus, bus->sdpcm_ver); | |
3164 | bcm_bprintf(strbuf, "fcstate %d qlen %u tx_seq %d, max %d, rxskip %d rxlen %u rx_seq %d\n", | |
3165 | bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max, bus->rxskip, | |
3166 | bus->rxlen, bus->rx_seq); | |
3167 | bcm_bprintf(strbuf, "intr %d intrcount %u lastintrs %u spurious %u\n", | |
3168 | bus->intr, bus->intrcount, bus->lastintrs, bus->spurious); | |
3169 | ||
3170 | #ifdef DHD_WAKE_STATUS | |
3171 | bcm_bprintf(strbuf, "wake %u rxwake %u readctrlwake %u\n", | |
3172 | bcmsdh_get_total_wake(bus->sdh), bus->wake_counts.rxwake, | |
3173 | bus->wake_counts.rcwake); | |
3174 | #ifdef DHD_WAKE_RX_STATUS | |
3175 | bcm_bprintf(strbuf, " unicast %u multicast %u broadcast %u arp %u\n", | |
3176 | bus->wake_counts.rx_ucast, bus->wake_counts.rx_mcast, | |
3177 | bus->wake_counts.rx_bcast, bus->wake_counts.rx_arp); | |
3178 | bcm_bprintf(strbuf, " multi4 %u multi6 %u icmp6 %u multiother %u\n", | |
3179 | bus->wake_counts.rx_multi_ipv4, bus->wake_counts.rx_multi_ipv6, | |
3180 | bus->wake_counts.rx_icmpv6, bus->wake_counts.rx_multi_other); | |
3181 | bcm_bprintf(strbuf, " icmp6_ra %u, icmp6_na %u, icmp6_ns %u\n", | |
3182 | bus->wake_counts.rx_icmpv6_ra, bus->wake_counts.rx_icmpv6_na, | |
3183 | bus->wake_counts.rx_icmpv6_ns); | |
3184 | #endif /* DHD_WAKE_RX_STATUS */ | |
3185 | #ifdef DHD_WAKE_EVENT_STATUS | |
3186 | for (i = 0; i < WLC_E_LAST; i++) | |
3187 | if (bus->wake_counts.rc_event[i] != 0) | |
3188 | bcm_bprintf(strbuf, " %s = %u\n", bcmevent_get_name(i), | |
3189 | bus->wake_counts.rc_event[i]); | |
3190 | bcm_bprintf(strbuf, "\n"); | |
3191 | #endif /* DHD_WAKE_EVENT_STATUS */ | |
3192 | #endif /* DHD_WAKE_STATUS */ | |
3193 | ||
3194 | bcm_bprintf(strbuf, "pollrate %u pollcnt %u regfails %u\n", | |
3195 | bus->pollrate, bus->pollcnt, bus->regfails); | |
3196 | ||
3197 | bcm_bprintf(strbuf, "\nAdditional counters:\n"); | |
3198 | #ifdef DHDENABLE_TAILPAD | |
3199 | bcm_bprintf(strbuf, "tx_tailpad_chain %u tx_tailpad_pktget %u\n", | |
3200 | bus->tx_tailpad_chain, bus->tx_tailpad_pktget); | |
3201 | #endif /* DHDENABLE_TAILPAD */ | |
3202 | bcm_bprintf(strbuf, "tx_sderrs %u fcqueued %u rxrtx %u rx_toolong %u rxc_errors %u\n", | |
3203 | bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong, | |
3204 | bus->rxc_errors); | |
3205 | bcm_bprintf(strbuf, "rx_hdrfail %u badhdr %u badseq %u\n", | |
3206 | bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq); | |
3207 | bcm_bprintf(strbuf, "fc_rcvd %u, fc_xoff %u, fc_xon %u\n", | |
3208 | bus->fc_rcvd, bus->fc_xoff, bus->fc_xon); | |
3209 | bcm_bprintf(strbuf, "rxglomfail %u, rxglomframes %u, rxglompkts %u\n", | |
3210 | bus->rxglomfail, bus->rxglomframes, bus->rxglompkts); | |
3211 | bcm_bprintf(strbuf, "f2rx (hdrs/data) %u (%u/%u), f2tx %u f1regs %u\n", | |
3212 | (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs, bus->f2rxdata, | |
3213 | bus->f2txdata, bus->f1regdata); | |
3214 | { | |
3215 | dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets, | |
3216 | (bus->f2rxhdrs + bus->f2rxdata)); | |
3217 | dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets, bus->f1regdata); | |
3218 | dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets, | |
3219 | (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata)); | |
3220 | dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets, bus->intrcount); | |
3221 | bcm_bprintf(strbuf, "\n"); | |
3222 | ||
3223 | dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts), | |
3224 | bus->dhd->rx_packets); | |
3225 | dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts, bus->rxglomframes); | |
3226 | bcm_bprintf(strbuf, "\n"); | |
3227 | ||
3228 | dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets, bus->f2txdata); | |
3229 | dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets, bus->f1regdata); | |
3230 | dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets, | |
3231 | (bus->f2txdata + bus->f1regdata)); | |
3232 | dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets, bus->intrcount); | |
3233 | bcm_bprintf(strbuf, "\n"); | |
3234 | ||
3235 | dhd_dump_pct(strbuf, "Total: pkts/f2rw", | |
3236 | (bus->dhd->tx_packets + bus->dhd->rx_packets), | |
3237 | (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata)); | |
3238 | dhd_dump_pct(strbuf, ", pkts/f1sd", | |
3239 | (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->f1regdata); | |
3240 | dhd_dump_pct(strbuf, ", pkts/sd", | |
3241 | (bus->dhd->tx_packets + bus->dhd->rx_packets), | |
3242 | (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata)); | |
3243 | dhd_dump_pct(strbuf, ", pkts/int", | |
3244 | (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->intrcount); | |
3245 | bcm_bprintf(strbuf, "\n\n"); | |
3246 | } | |
3247 | ||
3248 | #ifdef SDTEST | |
3249 | if (bus->pktgen_count) { | |
3250 | bcm_bprintf(strbuf, "pktgen config and count:\n"); | |
3251 | bcm_bprintf(strbuf, "freq %u count %u print %u total %u min %u len %u\n", | |
3252 | bus->pktgen_freq, bus->pktgen_count, bus->pktgen_print, | |
3253 | bus->pktgen_total, bus->pktgen_minlen, bus->pktgen_maxlen); | |
3254 | bcm_bprintf(strbuf, "send attempts %u rcvd %u fail %u\n", | |
3255 | bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail); | |
3256 | } | |
3257 | #endif /* SDTEST */ | |
3258 | #ifdef DHD_DEBUG | |
3259 | bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n", | |
3260 | bus->dpc_sched, (bcmsdh_intr_pending(bus->sdh) ? " " : " not ")); | |
3261 | bcm_bprintf(strbuf, "blocksize %u roundup %u\n", bus->blocksize, bus->roundup); | |
3262 | #endif /* DHD_DEBUG */ | |
3263 | bcm_bprintf(strbuf, "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n", | |
3264 | bus->clkstate, bus->activity, bus->idletime, bus->idlecount, bus->sleeping); | |
3265 | dhd_dump_pct(strbuf, "Tx: glom pct", (100 * bus->txglompkts), bus->dhd->tx_packets); | |
3266 | dhd_dump_pct(strbuf, ", pkts/glom", bus->txglompkts, bus->txglomframes); | |
3267 | bcm_bprintf(strbuf, "\n"); | |
3268 | bcm_bprintf(strbuf, "txglomframes %u, txglompkts %u\n", bus->txglomframes, bus->txglompkts); | |
3269 | bcm_bprintf(strbuf, "\n"); | |
3270 | } | |
3271 | ||
3272 | void | |
3273 | dhd_bus_clearcounts(dhd_pub_t *dhdp) | |
3274 | { | |
3275 | dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus; | |
3276 | ||
3277 | bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0; | |
3278 | bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0; | |
3279 | bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0; | |
3280 | #ifdef DHDENABLE_TAILPAD | |
3281 | bus->tx_tailpad_chain = bus->tx_tailpad_pktget = 0; | |
3282 | #endif /* DHDENABLE_TAILPAD */ | |
3283 | bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0; | |
3284 | bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0; | |
3285 | bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0; | |
3286 | bus->txglomframes = bus->txglompkts = 0; | |
3287 | } | |
3288 | ||
3289 | #ifdef SDTEST | |
3290 | static int | |
3291 | dhdsdio_pktgen_get(dhd_bus_t *bus, uint8 *arg) | |
3292 | { | |
3293 | dhd_pktgen_t pktgen; | |
3294 | ||
3295 | pktgen.version = DHD_PKTGEN_VERSION; | |
3296 | pktgen.freq = bus->pktgen_freq; | |
3297 | pktgen.count = bus->pktgen_count; | |
3298 | pktgen.print = bus->pktgen_print; | |
3299 | pktgen.total = bus->pktgen_total; | |
3300 | pktgen.minlen = bus->pktgen_minlen; | |
3301 | pktgen.maxlen = bus->pktgen_maxlen; | |
3302 | pktgen.numsent = bus->pktgen_sent; | |
3303 | pktgen.numrcvd = bus->pktgen_rcvd; | |
3304 | pktgen.numfail = bus->pktgen_fail; | |
3305 | pktgen.mode = bus->pktgen_mode; | |
3306 | pktgen.stop = bus->pktgen_stop; | |
3307 | ||
3308 | bcopy(&pktgen, arg, sizeof(pktgen)); | |
3309 | ||
3310 | return 0; | |
3311 | } | |
3312 | ||
3313 | static int | |
3314 | dhdsdio_pktgen_set(dhd_bus_t *bus, uint8 *arg) | |
3315 | { | |
3316 | dhd_pktgen_t pktgen; | |
3317 | uint oldcnt, oldmode; | |
3318 | ||
3319 | bcopy(arg, &pktgen, sizeof(pktgen)); | |
3320 | if (pktgen.version != DHD_PKTGEN_VERSION) | |
3321 | return BCME_BADARG; | |
3322 | ||
3323 | oldcnt = bus->pktgen_count; | |
3324 | oldmode = bus->pktgen_mode; | |
3325 | ||
3326 | bus->pktgen_freq = pktgen.freq; | |
3327 | bus->pktgen_count = pktgen.count; | |
3328 | bus->pktgen_print = pktgen.print; | |
3329 | bus->pktgen_total = pktgen.total; | |
3330 | bus->pktgen_minlen = pktgen.minlen; | |
3331 | bus->pktgen_maxlen = pktgen.maxlen; | |
3332 | bus->pktgen_mode = pktgen.mode; | |
3333 | bus->pktgen_stop = pktgen.stop; | |
3334 | ||
3335 | bus->pktgen_tick = bus->pktgen_ptick = 0; | |
3336 | bus->pktgen_prev_time = jiffies; | |
3337 | bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen); | |
3338 | bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen); | |
3339 | ||
3340 | /* Clear counts for a new pktgen (mode change, or was stopped) */ | |
3341 | if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode)) { | |
3342 | bus->pktgen_sent = bus->pktgen_prev_sent = bus->pktgen_rcvd = 0; | |
3343 | bus->pktgen_prev_rcvd = bus->pktgen_fail = 0; | |
3344 | } | |
3345 | ||
3346 | return 0; | |
3347 | } | |
3348 | #endif /* SDTEST */ | |
3349 | ||
3350 | static void | |
3351 | dhdsdio_devram_remap(dhd_bus_t *bus, bool val) | |
3352 | { | |
3353 | uint8 enable, protect, remap; | |
3354 | ||
3355 | si_socdevram(bus->sih, FALSE, &enable, &protect, &remap); | |
3356 | remap = val ? TRUE : FALSE; | |
3357 | si_socdevram(bus->sih, TRUE, &enable, &protect, &remap); | |
3358 | } | |
3359 | ||
3360 | static int | |
3361 | dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, uint8 *data, uint size) | |
3362 | { | |
3363 | int bcmerror = 0; | |
3364 | uint32 sdaddr; | |
3365 | uint dsize; | |
32c27b7a | 3366 | uint8 *pdata; |
010c3a89 RC |
3367 | |
3368 | /* In remap mode, adjust address beyond socram and redirect | |
3369 | * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize | |
3370 | * is not backplane accessible | |
3371 | */ | |
3372 | if (REMAP_ENAB(bus) && REMAP_ISADDR(bus, address)) { | |
3373 | address -= bus->orig_ramsize; | |
3374 | address += SOCDEVRAM_BP_ADDR; | |
3375 | } | |
3376 | ||
3377 | /* Determine initial transfer parameters */ | |
3378 | sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK; | |
3379 | if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK) | |
3380 | dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr); | |
3381 | else | |
3382 | dsize = size; | |
3383 | ||
3384 | /* Set the backplane window to include the start address */ | |
3385 | if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) { | |
3386 | DHD_ERROR(("%s: window change failed\n", __FUNCTION__)); | |
3387 | goto xfer_done; | |
3388 | } | |
3389 | ||
3390 | /* Do the transfer(s) */ | |
3391 | while (size) { | |
3392 | DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n", | |
3393 | __FUNCTION__, (write ? "write" : "read"), dsize, sdaddr, | |
3394 | (address & SBSDIO_SBWINDOW_MASK))); | |
32c27b7a RC |
3395 | if (dsize <= MAX_MEM_BUF) { |
3396 | pdata = bus->membuf; | |
3397 | if (write) | |
3398 | memcpy(bus->membuf, data, dsize); | |
3399 | } else { | |
3400 | pdata = data; | |
3401 | } | |
3402 | if ((bcmerror = bcmsdh_rwdata(bus->sdh, write, sdaddr, pdata, dsize))) { | |
010c3a89 RC |
3403 | DHD_ERROR(("%s: membytes transfer failed\n", __FUNCTION__)); |
3404 | break; | |
3405 | } | |
32c27b7a | 3406 | if (dsize <= MAX_MEM_BUF && !write) { |
07d6b24a | 3407 | memcpy(data, bus->membuf, dsize); |
32c27b7a | 3408 | } |
010c3a89 RC |
3409 | |
3410 | /* Adjust for next transfer (if any) */ | |
3411 | if ((size -= dsize)) { | |
3412 | data += dsize; | |
3413 | address += dsize; | |
3414 | if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) { | |
3415 | DHD_ERROR(("%s: window change failed\n", __FUNCTION__)); | |
3416 | break; | |
3417 | } | |
3418 | sdaddr = 0; | |
3419 | dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size); | |
3420 | } | |
3421 | ||
3422 | } | |
3423 | ||
3424 | xfer_done: | |
3425 | /* Return the window to backplane enumeration space for core access */ | |
3426 | if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) { | |
3427 | DHD_ERROR(("%s: FAILED to set window back to 0x%x\n", __FUNCTION__, | |
3428 | bcmsdh_cur_sbwad(bus->sdh))); | |
3429 | } | |
3430 | ||
3431 | return bcmerror; | |
3432 | } | |
3433 | ||
3434 | static int | |
3435 | dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh) | |
3436 | { | |
3437 | uint32 addr; | |
3438 | int rv, i; | |
3439 | uint32 shaddr = 0; | |
3440 | ||
3441 | if (bus->sih == NULL) { | |
3442 | if (bus->dhd && bus->dhd->dongle_reset) { | |
3443 | DHD_ERROR(("%s: Dongle is in reset state\n", __FUNCTION__)); | |
3444 | return BCME_NOTREADY; | |
3445 | } else { | |
3446 | ASSERT(bus->dhd); | |
3447 | ASSERT(bus->sih); | |
3448 | DHD_ERROR(("%s: The address of sih is invalid\n", __FUNCTION__)); | |
3449 | return BCME_ERROR; | |
3450 | } | |
3451 | } | |
3452 | if ((CHIPID(bus->sih->chip) == BCM43430_CHIP_ID || | |
3453 | CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) && !dhdsdio_sr_cap(bus)) | |
3454 | bus->srmemsize = 0; | |
3455 | ||
3456 | shaddr = bus->dongle_ram_base + bus->ramsize - 4; | |
3457 | i = 0; | |
3458 | do { | |
3459 | /* Read last word in memory to determine address of sdpcm_shared structure */ | |
3460 | if ((rv = dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&addr, 4)) < 0) | |
3461 | return rv; | |
3462 | ||
3463 | addr = ltoh32(addr); | |
3464 | ||
3465 | DHD_INFO(("sdpcm_shared address 0x%08X\n", addr)); | |
3466 | ||
3467 | /* | |
3468 | * Check if addr is valid. | |
3469 | * NVRAM length at the end of memory should have been overwritten. | |
3470 | */ | |
3471 | if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) { | |
3472 | if ((bus->srmemsize > 0) && (i++ == 0)) { | |
3473 | shaddr -= bus->srmemsize; | |
3474 | } else { | |
3475 | DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n", | |
3476 | __FUNCTION__, addr)); | |
3477 | return BCME_ERROR; | |
3478 | } | |
3479 | } else | |
3480 | break; | |
3481 | } while (i < 2); | |
3482 | ||
3483 | /* Read hndrte_shared structure */ | |
3484 | if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)sh, sizeof(sdpcm_shared_t))) < 0) | |
3485 | return rv; | |
3486 | ||
3487 | /* Endianness */ | |
3488 | sh->flags = ltoh32(sh->flags); | |
3489 | sh->trap_addr = ltoh32(sh->trap_addr); | |
3490 | sh->assert_exp_addr = ltoh32(sh->assert_exp_addr); | |
3491 | sh->assert_file_addr = ltoh32(sh->assert_file_addr); | |
3492 | sh->assert_line = ltoh32(sh->assert_line); | |
3493 | sh->console_addr = ltoh32(sh->console_addr); | |
3494 | sh->msgtrace_addr = ltoh32(sh->msgtrace_addr); | |
3495 | ||
3496 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) == 3 && SDPCM_SHARED_VERSION == 1) | |
3497 | return BCME_OK; | |
3498 | ||
3499 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) { | |
3500 | DHD_ERROR(("%s: sdpcm_shared version %d in dhd " | |
3501 | "is different than sdpcm_shared version %d in dongle\n", | |
3502 | __FUNCTION__, SDPCM_SHARED_VERSION, | |
3503 | sh->flags & SDPCM_SHARED_VERSION_MASK)); | |
3504 | return BCME_ERROR; | |
3505 | } | |
3506 | ||
3507 | return BCME_OK; | |
3508 | } | |
3509 | ||
3510 | #define CONSOLE_LINE_MAX 192 | |
3511 | ||
3512 | #ifdef DHD_DEBUG | |
3513 | static int | |
3514 | dhdsdio_readconsole(dhd_bus_t *bus) | |
3515 | { | |
3516 | dhd_console_t *c = &bus->console; | |
3517 | uint8 line[CONSOLE_LINE_MAX], ch; | |
3518 | uint32 n, idx, addr; | |
3519 | int rv; | |
3520 | ||
3521 | /* Don't do anything until FWREADY updates console address */ | |
3522 | if (bus->console_addr == 0) | |
3523 | return 0; | |
3524 | ||
3525 | if (!KSO_ENAB(bus)) | |
3526 | return 0; | |
3527 | ||
3528 | /* Read console log struct */ | |
3529 | addr = bus->console_addr + OFFSETOF(hnd_cons_t, log); | |
3530 | if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0) | |
3531 | return rv; | |
3532 | ||
3533 | /* Allocate console buffer (one time only) */ | |
3534 | if (c->buf == NULL) { | |
3535 | c->bufsize = ltoh32(c->log.buf_size); | |
3536 | if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL) | |
3537 | return BCME_NOMEM; | |
3538 | } | |
3539 | ||
3540 | idx = ltoh32(c->log.idx); | |
3541 | ||
3542 | /* Protect against corrupt value */ | |
3543 | if (idx > c->bufsize) | |
3544 | return BCME_ERROR; | |
3545 | ||
3546 | /* Skip reading the console buffer if the index pointer has not moved */ | |
3547 | if (idx == c->last) | |
3548 | return BCME_OK; | |
3549 | ||
3550 | /* Read the console buffer */ | |
3551 | addr = ltoh32(c->log.buf); | |
3552 | if ((rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0) | |
3553 | return rv; | |
3554 | ||
3555 | while (c->last != idx) { | |
3556 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
3557 | if (c->last == idx) { | |
3558 | /* This would output a partial line. Instead, back up | |
3559 | * the buffer pointer and output this line next time around. | |
3560 | */ | |
3561 | if (c->last >= n) | |
3562 | c->last -= n; | |
3563 | else | |
3564 | c->last = c->bufsize - n; | |
3565 | goto break2; | |
3566 | } | |
3567 | ch = c->buf[c->last]; | |
3568 | c->last = (c->last + 1) % c->bufsize; | |
3569 | if (ch == '\n') | |
3570 | break; | |
3571 | line[n] = ch; | |
3572 | } | |
3573 | ||
3574 | if (n > 0) { | |
3575 | if (line[n - 1] == '\r') | |
3576 | n--; | |
3577 | line[n] = 0; | |
3578 | printf("CONSOLE: %s\n", line); | |
3579 | #ifdef LOG_INTO_TCPDUMP | |
3580 | dhd_sendup_log(bus->dhd, line, n); | |
3581 | #endif /* LOG_INTO_TCPDUMP */ | |
3582 | } | |
3583 | } | |
3584 | break2: | |
3585 | ||
3586 | return BCME_OK; | |
3587 | } | |
3588 | #endif /* DHD_DEBUG */ | |
3589 | ||
3590 | static int | |
3591 | dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size) | |
3592 | { | |
3593 | int bcmerror = 0; | |
3594 | uint msize = 512; | |
3595 | char *mbuffer = NULL; | |
3596 | char *console_buffer = NULL; | |
3597 | uint maxstrlen = 256; | |
3598 | char *str = NULL; | |
3599 | sdpcm_shared_t l_sdpcm_shared; | |
3600 | struct bcmstrbuf strbuf; | |
3601 | uint32 console_ptr, console_size, console_index; | |
3602 | uint8 line[CONSOLE_LINE_MAX], ch; | |
3603 | uint32 n, i, addr; | |
3604 | int rv; | |
3605 | ||
3606 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
3607 | ||
3608 | if (DHD_NOCHECKDIED_ON()) | |
3609 | return 0; | |
3610 | ||
3611 | if (data == NULL) { | |
3612 | /* | |
3613 | * Called after a rx ctrl timeout. "data" is NULL. | |
3614 | * allocate memory to trace the trap or assert. | |
3615 | */ | |
3616 | size = msize; | |
3617 | mbuffer = data = MALLOC(bus->dhd->osh, msize); | |
3618 | if (mbuffer == NULL) { | |
3619 | DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize)); | |
3620 | bcmerror = BCME_NOMEM; | |
3621 | goto done; | |
3622 | } | |
3623 | } | |
3624 | ||
3625 | if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) { | |
3626 | DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen)); | |
3627 | bcmerror = BCME_NOMEM; | |
3628 | goto done; | |
3629 | } | |
3630 | ||
3631 | if ((bcmerror = dhdsdio_readshared(bus, &l_sdpcm_shared)) < 0) | |
3632 | goto done; | |
3633 | ||
3634 | bcm_binit(&strbuf, data, size); | |
3635 | ||
3636 | bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address : 0x%08X\n", | |
3637 | l_sdpcm_shared.msgtrace_addr, l_sdpcm_shared.console_addr); | |
3638 | ||
3639 | if ((l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
3640 | /* NOTE: Misspelled assert is intentional - DO NOT FIX. | |
3641 | * (Avoids conflict with real asserts for programmatic parsing of output.) | |
3642 | */ | |
3643 | bcm_bprintf(&strbuf, "Assrt not built in dongle\n"); | |
3644 | } | |
3645 | ||
3646 | if ((l_sdpcm_shared.flags & (SDPCM_SHARED_ASSERT|SDPCM_SHARED_TRAP)) == 0) { | |
3647 | /* NOTE: Misspelled assert is intentional - DO NOT FIX. | |
3648 | * (Avoids conflict with real asserts for programmatic parsing of output.) | |
3649 | */ | |
3650 | bcm_bprintf(&strbuf, "No trap%s in dongle", | |
3651 | (l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) | |
3652 | ?"/assrt" :""); | |
3653 | } else { | |
3654 | if (l_sdpcm_shared.flags & SDPCM_SHARED_ASSERT) { | |
3655 | /* Download assert */ | |
3656 | bcm_bprintf(&strbuf, "Dongle assert"); | |
3657 | if (l_sdpcm_shared.assert_exp_addr != 0) { | |
3658 | str[0] = '\0'; | |
3659 | if ((bcmerror = dhdsdio_membytes(bus, FALSE, | |
3660 | l_sdpcm_shared.assert_exp_addr, | |
3661 | (uint8 *)str, maxstrlen)) < 0) | |
3662 | goto done; | |
3663 | ||
3664 | str[maxstrlen - 1] = '\0'; | |
3665 | bcm_bprintf(&strbuf, " expr \"%s\"", str); | |
3666 | } | |
3667 | ||
3668 | if (l_sdpcm_shared.assert_file_addr != 0) { | |
3669 | str[0] = '\0'; | |
3670 | if ((bcmerror = dhdsdio_membytes(bus, FALSE, | |
3671 | l_sdpcm_shared.assert_file_addr, | |
3672 | (uint8 *)str, maxstrlen)) < 0) | |
3673 | goto done; | |
3674 | ||
3675 | str[maxstrlen - 1] = '\0'; | |
3676 | bcm_bprintf(&strbuf, " file \"%s\"", str); | |
3677 | } | |
3678 | ||
3679 | bcm_bprintf(&strbuf, " line %d ", l_sdpcm_shared.assert_line); | |
3680 | } | |
3681 | ||
3682 | if (l_sdpcm_shared.flags & SDPCM_SHARED_TRAP) { | |
3683 | trap_t *tr = &bus->dhd->last_trap_info; | |
3684 | bus->dhd->dongle_trap_occured = TRUE; | |
3685 | if ((bcmerror = dhdsdio_membytes(bus, FALSE, | |
3686 | l_sdpcm_shared.trap_addr, | |
3687 | (uint8*)tr, sizeof(trap_t))) < 0) | |
3688 | goto done; | |
3689 | ||
3690 | bus->dongle_trap_addr = ltoh32(l_sdpcm_shared.trap_addr); | |
3691 | ||
3692 | dhd_bus_dump_trap_info(bus, &strbuf); | |
3693 | ||
3694 | addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log); | |
3695 | if ((rv = dhdsdio_membytes(bus, FALSE, addr, | |
3696 | (uint8 *)&console_ptr, sizeof(console_ptr))) < 0) | |
3697 | goto printbuf; | |
3698 | ||
3699 | addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.buf_size); | |
3700 | if ((rv = dhdsdio_membytes(bus, FALSE, addr, | |
3701 | (uint8 *)&console_size, sizeof(console_size))) < 0) | |
3702 | goto printbuf; | |
3703 | ||
3704 | addr = l_sdpcm_shared.console_addr + OFFSETOF(hnd_cons_t, log.idx); | |
3705 | if ((rv = dhdsdio_membytes(bus, FALSE, addr, | |
3706 | (uint8 *)&console_index, sizeof(console_index))) < 0) | |
3707 | goto printbuf; | |
3708 | ||
3709 | console_ptr = ltoh32(console_ptr); | |
3710 | console_size = ltoh32(console_size); | |
3711 | console_index = ltoh32(console_index); | |
3712 | ||
3713 | if (console_size > CONSOLE_BUFFER_MAX || | |
3714 | !(console_buffer = MALLOC(bus->dhd->osh, console_size))) | |
3715 | goto printbuf; | |
3716 | ||
3717 | if ((rv = dhdsdio_membytes(bus, FALSE, console_ptr, | |
3718 | (uint8 *)console_buffer, console_size)) < 0) | |
3719 | goto printbuf; | |
3720 | ||
3721 | for (i = 0, n = 0; i < console_size; i += n + 1) { | |
3722 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
3723 | ch = console_buffer[(console_index + i + n) % console_size]; | |
3724 | if (ch == '\n') | |
3725 | break; | |
3726 | line[n] = ch; | |
3727 | } | |
3728 | ||
3729 | ||
3730 | if (n > 0) { | |
3731 | if (line[n - 1] == '\r') | |
3732 | n--; | |
3733 | line[n] = 0; | |
3734 | /* Don't use DHD_ERROR macro since we print | |
3735 | * a lot of information quickly. The macro | |
3736 | * will truncate a lot of the printfs | |
3737 | */ | |
3738 | ||
3739 | if (dhd_msg_level & DHD_ERROR_VAL) | |
3740 | printf("CONSOLE: %s\n", line); | |
3741 | } | |
3742 | } | |
3743 | } | |
3744 | } | |
3745 | ||
3746 | printbuf: | |
3747 | if (l_sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) { | |
3748 | DHD_ERROR(("%s: %s\n", __FUNCTION__, strbuf.origbuf)); | |
3749 | } | |
3750 | ||
3751 | #if defined(DHD_FW_COREDUMP) | |
3752 | if (bus->dhd->memdump_enabled && (l_sdpcm_shared.flags & SDPCM_SHARED_TRAP)) { | |
3753 | /* Mem dump to a file on device */ | |
3754 | bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP; | |
3755 | dhd_os_sdunlock(bus->dhd); | |
3756 | dhdsdio_mem_dump(bus); | |
3757 | dhd_os_sdlock(bus->dhd); | |
3758 | } | |
3759 | #endif /* #if defined(DHD_FW_COREDUMP) */ | |
3760 | ||
3761 | done: | |
3762 | if (mbuffer) | |
3763 | MFREE(bus->dhd->osh, mbuffer, msize); | |
3764 | if (str) | |
3765 | MFREE(bus->dhd->osh, str, maxstrlen); | |
3766 | if (console_buffer) | |
3767 | MFREE(bus->dhd->osh, console_buffer, console_size); | |
3768 | ||
3769 | return bcmerror; | |
3770 | } | |
3771 | ||
3772 | #if defined(DHD_FW_COREDUMP) | |
3773 | int | |
3774 | dhd_bus_mem_dump(dhd_pub_t *dhdp) | |
3775 | { | |
3776 | dhd_bus_t *bus = dhdp->bus; | |
3777 | if (dhdp->busstate == DHD_BUS_SUSPEND) { | |
3778 | DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__)); | |
3779 | return 0; | |
3780 | } | |
3781 | return dhdsdio_mem_dump(bus); | |
3782 | } | |
3783 | ||
3784 | static int | |
3785 | dhdsdio_mem_dump(dhd_bus_t *bus) | |
3786 | { | |
3787 | int ret = 0; | |
3788 | int size; /* Full mem size */ | |
3789 | uint32 start = bus->dongle_ram_base; /* Start address */ | |
3790 | uint read_size = 0; /* Read size of each iteration */ | |
3791 | uint8 *buf = NULL, *databuf = NULL; | |
3792 | ||
3793 | /* Get full mem size */ | |
3794 | size = bus->ramsize; | |
3795 | buf = dhd_get_fwdump_buf(bus->dhd, size); | |
3796 | if (!buf) { | |
3797 | DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size)); | |
3798 | return -1; | |
3799 | } | |
3800 | ||
3801 | dhd_os_sdlock(bus->dhd); | |
3802 | BUS_WAKE(bus); | |
3803 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
3804 | ||
3805 | /* Read mem content */ | |
3806 | DHD_ERROR(("Dump dongle memory\n")); | |
3807 | databuf = buf; | |
3808 | while (size) | |
3809 | { | |
3810 | read_size = MIN(MEMBLOCK, size); | |
3811 | if ((ret = dhdsdio_membytes(bus, FALSE, start, databuf, read_size))) | |
3812 | { | |
3813 | DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret)); | |
3814 | ret = BCME_ERROR; | |
3815 | break; | |
3816 | } | |
3817 | /* Decrement size and increment start address */ | |
3818 | size -= read_size; | |
3819 | start += read_size; | |
3820 | databuf += read_size; | |
3821 | } | |
3822 | ||
3823 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched && | |
3824 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
3825 | bus->activity = FALSE; | |
3826 | dhdsdio_clkctl(bus, CLK_NONE, TRUE); | |
3827 | } | |
3828 | ||
3829 | dhd_os_sdunlock(bus->dhd); | |
3830 | ||
3831 | /* schedule a work queue to perform actual memdump. dhd_mem_dump() performs the job */ | |
3832 | if (!ret) { | |
3833 | /* buf, actually soc_ram free handled in dhd_{free,clear} */ | |
3834 | dhd_schedule_memdump(bus->dhd, buf, bus->ramsize); | |
3835 | } | |
3836 | ||
3837 | return ret; | |
3838 | } | |
3839 | #endif /* DHD_FW_COREDUMP */ | |
3840 | ||
3841 | int | |
3842 | dhd_socram_dump(dhd_bus_t * bus) | |
3843 | { | |
3844 | #if defined(DHD_FW_COREDUMP) | |
3845 | return (dhdsdio_mem_dump(bus)); | |
3846 | #else | |
3847 | return -1; | |
3848 | #endif | |
3849 | } | |
3850 | ||
3851 | int | |
3852 | dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len) | |
3853 | { | |
3854 | int bcmerror = BCME_OK; | |
3855 | ||
3856 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
3857 | ||
3858 | if (bus->dhd->up && | |
3859 | #ifdef DHD_ULP | |
3860 | (DHD_ULP_DISABLED == dhd_ulp_get_ulp_state(bus->dhd)) && | |
3861 | #endif /* DHD_ULP */ | |
3862 | 1) { | |
3863 | bcmerror = BCME_NOTDOWN; | |
3864 | goto err; | |
3865 | } | |
3866 | if (!len) { | |
3867 | bcmerror = BCME_BUFTOOSHORT; | |
3868 | goto err; | |
3869 | } | |
3870 | ||
3871 | /* Free the old ones and replace with passed variables */ | |
3872 | if (bus->vars) | |
3873 | MFREE(bus->dhd->osh, bus->vars, bus->varsz); | |
3874 | ||
3875 | bus->vars = MALLOC(bus->dhd->osh, len); | |
3876 | bus->varsz = bus->vars ? len : 0; | |
3877 | if (bus->vars == NULL) { | |
3878 | bcmerror = BCME_NOMEM; | |
3879 | goto err; | |
3880 | } | |
3881 | ||
3882 | /* Copy the passed variables, which should include the terminating double-null */ | |
3883 | bcopy(arg, bus->vars, bus->varsz); | |
3884 | err: | |
3885 | return bcmerror; | |
3886 | } | |
3887 | ||
3888 | #ifdef DHD_DEBUG | |
3889 | ||
3890 | #define CC_PLL_CHIPCTRL_SERIAL_ENAB (1 << 24) | |
3891 | #define CC_CHIPCTRL_JTAG_SEL (1 << 3) | |
3892 | #define CC_CHIPCTRL_GPIO_SEL (0x3) | |
3893 | #define CC_PLL_CHIPCTRL_SERIAL_ENAB_4334 (1 << 28) | |
3894 | ||
3895 | static int | |
3896 | dhd_serialconsole(dhd_bus_t *bus, bool set, bool enable, int *bcmerror) | |
3897 | { | |
3898 | int int_val; | |
3899 | uint32 addr, data, uart_enab = 0; | |
3900 | uint32 jtag_sel = CC_CHIPCTRL_JTAG_SEL; | |
3901 | uint32 gpio_sel = CC_CHIPCTRL_GPIO_SEL; | |
3902 | ||
3903 | addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr); | |
3904 | data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data); | |
3905 | *bcmerror = 0; | |
3906 | ||
3907 | bcmsdh_reg_write(bus->sdh, addr, 4, 1); | |
3908 | if (bcmsdh_regfail(bus->sdh)) { | |
3909 | *bcmerror = BCME_SDIO_ERROR; | |
3910 | return -1; | |
3911 | } | |
3912 | int_val = bcmsdh_reg_read(bus->sdh, data, 4); | |
3913 | if (bcmsdh_regfail(bus->sdh)) { | |
3914 | *bcmerror = BCME_SDIO_ERROR; | |
3915 | return -1; | |
3916 | } | |
3917 | ||
3918 | if (bus->sih->chip == BCM4330_CHIP_ID) { | |
3919 | uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB; | |
3920 | } else if (bus->sih->chip == BCM4334_CHIP_ID || | |
3921 | bus->sih->chip == BCM43340_CHIP_ID || | |
3922 | bus->sih->chip == BCM43341_CHIP_ID || | |
3923 | bus->sih->chip == BCM43342_CHIP_ID || | |
3924 | 0) { | |
3925 | if (enable) { | |
3926 | /* Moved to PMU chipcontrol 1 from 4330 */ | |
3927 | int_val &= ~gpio_sel; | |
3928 | int_val |= jtag_sel; | |
3929 | } else { | |
3930 | int_val |= gpio_sel; | |
3931 | int_val &= ~jtag_sel; | |
3932 | } | |
3933 | uart_enab = CC_PLL_CHIPCTRL_SERIAL_ENAB_4334; | |
3934 | } | |
3935 | ||
3936 | if (!set) | |
3937 | return (int_val & uart_enab); | |
3938 | if (enable) | |
3939 | int_val |= uart_enab; | |
3940 | else | |
3941 | int_val &= ~uart_enab; | |
3942 | bcmsdh_reg_write(bus->sdh, data, 4, int_val); | |
3943 | if (bcmsdh_regfail(bus->sdh)) { | |
3944 | *bcmerror = BCME_SDIO_ERROR; | |
3945 | return -1; | |
3946 | } | |
3947 | if (bus->sih->chip == BCM4330_CHIP_ID) { | |
3948 | uint32 chipcontrol; | |
3949 | addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol); | |
3950 | chipcontrol = bcmsdh_reg_read(bus->sdh, addr, 4); | |
3951 | chipcontrol &= ~jtag_sel; | |
3952 | if (enable) { | |
3953 | chipcontrol |= jtag_sel; | |
3954 | chipcontrol &= ~gpio_sel; | |
3955 | } | |
3956 | bcmsdh_reg_write(bus->sdh, addr, 4, chipcontrol); | |
3957 | } | |
3958 | ||
3959 | return (int_val & uart_enab); | |
3960 | } | |
3961 | #endif | |
3962 | ||
3963 | static int | |
3964 | dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name, | |
3965 | void *params, int plen, void *arg, int len, int val_size) | |
3966 | { | |
3967 | int bcmerror = 0; | |
3968 | int32 int_val = 0; | |
3969 | bool bool_val = 0; | |
3970 | ||
3971 | DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n", | |
3972 | __FUNCTION__, actionid, name, params, plen, arg, len, val_size)); | |
3973 | ||
3974 | if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0) | |
3975 | goto exit; | |
3976 | ||
3977 | if (plen >= (int)sizeof(int_val)) | |
3978 | bcopy(params, &int_val, sizeof(int_val)); | |
3979 | ||
3980 | bool_val = (int_val != 0) ? TRUE : FALSE; | |
3981 | ||
3982 | ||
3983 | /* Some ioctls use the bus */ | |
3984 | dhd_os_sdlock(bus->dhd); | |
3985 | ||
3986 | /* Check if dongle is in reset. If so, only allow DEVRESET iovars */ | |
3987 | if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) || | |
3988 | actionid == IOV_GVAL(IOV_DEVRESET))) { | |
3989 | bcmerror = BCME_NOTREADY; | |
3990 | goto exit; | |
3991 | } | |
3992 | ||
3993 | /* | |
3994 | * Special handling for keepSdioOn: New SDIO Wake-up Mechanism | |
3995 | */ | |
3996 | if ((vi->varid == IOV_KSO) && (IOV_ISSET(actionid))) { | |
3997 | dhdsdio_clk_kso_iovar(bus, bool_val); | |
3998 | goto exit; | |
3999 | } else if ((vi->varid == IOV_DEVSLEEP) && (IOV_ISSET(actionid))) { | |
4000 | { | |
4001 | dhdsdio_clk_devsleep_iovar(bus, bool_val); | |
4002 | if (!SLPAUTO_ENAB(bus) && (bool_val == FALSE) && (bus->ipend)) { | |
4003 | DHD_ERROR(("INT pending in devsleep 1, dpc_sched: %d\n", | |
4004 | bus->dpc_sched)); | |
4005 | if (!bus->dpc_sched) { | |
4006 | bus->dpc_sched = TRUE; | |
4007 | dhd_sched_dpc(bus->dhd); | |
4008 | } | |
4009 | } | |
4010 | } | |
4011 | goto exit; | |
4012 | } | |
4013 | ||
4014 | /* Handle sleep stuff before any clock mucking */ | |
4015 | if (vi->varid == IOV_SLEEP) { | |
4016 | if (IOV_ISSET(actionid)) { | |
4017 | bcmerror = dhdsdio_bussleep(bus, bool_val); | |
4018 | } else { | |
4019 | int_val = (int32)bus->sleeping; | |
4020 | bcopy(&int_val, arg, val_size); | |
4021 | } | |
4022 | goto exit; | |
4023 | } | |
4024 | ||
4025 | /* Request clock to allow SDIO accesses */ | |
4026 | if (!bus->dhd->dongle_reset) { | |
4027 | BUS_WAKE(bus); | |
4028 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
4029 | } | |
4030 | ||
4031 | switch (actionid) { | |
4032 | case IOV_GVAL(IOV_INTR): | |
4033 | int_val = (int32)bus->intr; | |
4034 | bcopy(&int_val, arg, val_size); | |
4035 | break; | |
4036 | ||
4037 | case IOV_SVAL(IOV_INTR): | |
4038 | bus->intr = bool_val; | |
4039 | bus->intdis = FALSE; | |
4040 | if (bus->dhd->up) { | |
4041 | if (bus->intr) { | |
4042 | DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__)); | |
4043 | // terence 20141207: enbale intdis | |
4044 | bus->intdis = TRUE; | |
4045 | bcmsdh_intr_enable(bus->sdh); | |
4046 | } else { | |
4047 | DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__)); | |
4048 | bcmsdh_intr_disable(bus->sdh); | |
4049 | } | |
4050 | } | |
4051 | break; | |
4052 | ||
4053 | case IOV_GVAL(IOV_POLLRATE): | |
4054 | int_val = (int32)bus->pollrate; | |
4055 | bcopy(&int_val, arg, val_size); | |
4056 | break; | |
4057 | ||
4058 | case IOV_SVAL(IOV_POLLRATE): | |
4059 | bus->pollrate = (uint)int_val; | |
4060 | bus->poll = (bus->pollrate != 0); | |
4061 | break; | |
4062 | ||
4063 | case IOV_GVAL(IOV_IDLETIME): | |
4064 | int_val = bus->idletime; | |
4065 | bcopy(&int_val, arg, val_size); | |
4066 | break; | |
4067 | ||
4068 | case IOV_SVAL(IOV_IDLETIME): | |
4069 | if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE)) { | |
4070 | bcmerror = BCME_BADARG; | |
4071 | } else { | |
4072 | bus->idletime = int_val; | |
4073 | } | |
4074 | break; | |
4075 | ||
4076 | case IOV_GVAL(IOV_IDLECLOCK): | |
4077 | int_val = (int32)bus->idleclock; | |
4078 | bcopy(&int_val, arg, val_size); | |
4079 | break; | |
4080 | ||
4081 | case IOV_SVAL(IOV_IDLECLOCK): | |
4082 | bus->idleclock = int_val; | |
4083 | break; | |
4084 | ||
4085 | case IOV_GVAL(IOV_SD1IDLE): | |
4086 | int_val = (int32)sd1idle; | |
4087 | bcopy(&int_val, arg, val_size); | |
4088 | break; | |
4089 | ||
4090 | case IOV_SVAL(IOV_SD1IDLE): | |
4091 | sd1idle = bool_val; | |
4092 | break; | |
4093 | ||
4094 | ||
4095 | ||
4096 | case IOV_GVAL(IOV_RAMSIZE): | |
4097 | int_val = (int32)bus->ramsize; | |
4098 | bcopy(&int_val, arg, val_size); | |
4099 | break; | |
4100 | ||
4101 | case IOV_GVAL(IOV_RAMSTART): | |
4102 | int_val = (int32)bus->dongle_ram_base; | |
4103 | bcopy(&int_val, arg, val_size); | |
4104 | break; | |
4105 | ||
4106 | case IOV_GVAL(IOV_SDIOD_DRIVE): | |
4107 | int_val = (int32)dhd_sdiod_drive_strength; | |
4108 | bcopy(&int_val, arg, val_size); | |
4109 | break; | |
4110 | ||
4111 | case IOV_SVAL(IOV_SDIOD_DRIVE): | |
4112 | dhd_sdiod_drive_strength = int_val; | |
4113 | si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh, dhd_sdiod_drive_strength); | |
4114 | break; | |
4115 | ||
4116 | case IOV_SVAL(IOV_SET_DOWNLOAD_STATE): | |
4117 | bcmerror = dhdsdio_download_state(bus, bool_val); | |
4118 | break; | |
4119 | ||
4120 | case IOV_SVAL(IOV_SOCRAM_STATE): | |
4121 | bcmerror = dhdsdio_download_state(bus, bool_val); | |
4122 | break; | |
4123 | ||
4124 | case IOV_SVAL(IOV_VARS): | |
4125 | bcmerror = dhdsdio_downloadvars(bus, arg, len); | |
4126 | break; | |
4127 | ||
4128 | case IOV_GVAL(IOV_READAHEAD): | |
4129 | int_val = (int32)dhd_readahead; | |
4130 | bcopy(&int_val, arg, val_size); | |
4131 | break; | |
4132 | ||
4133 | case IOV_SVAL(IOV_READAHEAD): | |
4134 | if (bool_val && !dhd_readahead) | |
4135 | bus->nextlen = 0; | |
4136 | dhd_readahead = bool_val; | |
4137 | break; | |
4138 | ||
4139 | case IOV_GVAL(IOV_SDRXCHAIN): | |
4140 | int_val = (int32)bus->use_rxchain; | |
4141 | bcopy(&int_val, arg, val_size); | |
4142 | break; | |
4143 | ||
4144 | case IOV_SVAL(IOV_SDRXCHAIN): | |
4145 | if (bool_val && !bus->sd_rxchain) | |
4146 | bcmerror = BCME_UNSUPPORTED; | |
4147 | else | |
4148 | bus->use_rxchain = bool_val; | |
4149 | break; | |
4150 | case IOV_GVAL(IOV_ALIGNCTL): | |
4151 | int_val = (int32)dhd_alignctl; | |
4152 | bcopy(&int_val, arg, val_size); | |
4153 | break; | |
4154 | ||
4155 | case IOV_SVAL(IOV_ALIGNCTL): | |
4156 | dhd_alignctl = bool_val; | |
4157 | break; | |
4158 | ||
4159 | case IOV_GVAL(IOV_SDALIGN): | |
4160 | int_val = DHD_SDALIGN; | |
4161 | bcopy(&int_val, arg, val_size); | |
4162 | break; | |
4163 | ||
4164 | #ifdef DHD_DEBUG | |
4165 | case IOV_GVAL(IOV_VARS): | |
4166 | if (bus->varsz < (uint)len) | |
4167 | bcopy(bus->vars, arg, bus->varsz); | |
4168 | else | |
4169 | bcmerror = BCME_BUFTOOSHORT; | |
4170 | break; | |
4171 | #endif /* DHD_DEBUG */ | |
4172 | ||
4173 | #ifdef DHD_DEBUG | |
4174 | case IOV_GVAL(IOV_SDREG): | |
4175 | { | |
4176 | sdreg_t *sd_ptr; | |
4177 | uintptr addr; | |
4178 | uint size; | |
4179 | ||
4180 | sd_ptr = (sdreg_t *)params; | |
4181 | ||
4182 | addr = ((uintptr)bus->regs + sd_ptr->offset); | |
4183 | size = sd_ptr->func; | |
4184 | int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size); | |
4185 | if (bcmsdh_regfail(bus->sdh)) | |
4186 | bcmerror = BCME_SDIO_ERROR; | |
4187 | bcopy(&int_val, arg, sizeof(int32)); | |
4188 | break; | |
4189 | } | |
4190 | ||
4191 | case IOV_SVAL(IOV_SDREG): | |
4192 | { | |
4193 | sdreg_t *sd_ptr; | |
4194 | uintptr addr; | |
4195 | uint size; | |
4196 | ||
4197 | sd_ptr = (sdreg_t *)params; | |
4198 | ||
4199 | addr = ((uintptr)bus->regs + sd_ptr->offset); | |
4200 | size = sd_ptr->func; | |
4201 | bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value); | |
4202 | if (bcmsdh_regfail(bus->sdh)) | |
4203 | bcmerror = BCME_SDIO_ERROR; | |
4204 | break; | |
4205 | } | |
4206 | ||
4207 | /* Same as above, but offset is not backplane (not SDIO core) */ | |
4208 | case IOV_GVAL(IOV_SBREG): | |
4209 | { | |
4210 | sdreg_t sdreg; | |
4211 | uint32 addr, size; | |
4212 | ||
4213 | bcopy(params, &sdreg, sizeof(sdreg)); | |
4214 | ||
4215 | addr = SI_ENUM_BASE + sdreg.offset; | |
4216 | size = sdreg.func; | |
4217 | int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size); | |
4218 | if (bcmsdh_regfail(bus->sdh)) | |
4219 | bcmerror = BCME_SDIO_ERROR; | |
4220 | bcopy(&int_val, arg, sizeof(int32)); | |
4221 | break; | |
4222 | } | |
4223 | ||
4224 | case IOV_SVAL(IOV_SBREG): | |
4225 | { | |
4226 | sdreg_t sdreg; | |
4227 | uint32 addr, size; | |
4228 | ||
4229 | bcopy(params, &sdreg, sizeof(sdreg)); | |
4230 | ||
4231 | addr = SI_ENUM_BASE + sdreg.offset; | |
4232 | size = sdreg.func; | |
4233 | bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value); | |
4234 | if (bcmsdh_regfail(bus->sdh)) | |
4235 | bcmerror = BCME_SDIO_ERROR; | |
4236 | break; | |
4237 | } | |
4238 | ||
4239 | case IOV_GVAL(IOV_SDCIS): | |
4240 | { | |
4241 | *(char *)arg = 0; | |
4242 | ||
4243 | bcmstrcat(arg, "\nFunc 0\n"); | |
4244 | bcmsdh_cis_read(bus->sdh, 0x10, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT); | |
4245 | bcmstrcat(arg, "\nFunc 1\n"); | |
4246 | bcmsdh_cis_read(bus->sdh, 0x11, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT); | |
4247 | bcmstrcat(arg, "\nFunc 2\n"); | |
4248 | bcmsdh_cis_read(bus->sdh, 0x12, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT); | |
4249 | break; | |
4250 | } | |
4251 | ||
4252 | case IOV_GVAL(IOV_FORCEEVEN): | |
4253 | int_val = (int32)forcealign; | |
4254 | bcopy(&int_val, arg, val_size); | |
4255 | break; | |
4256 | ||
4257 | case IOV_SVAL(IOV_FORCEEVEN): | |
4258 | forcealign = bool_val; | |
4259 | break; | |
4260 | ||
4261 | case IOV_GVAL(IOV_TXBOUND): | |
4262 | int_val = (int32)dhd_txbound; | |
4263 | bcopy(&int_val, arg, val_size); | |
4264 | break; | |
4265 | ||
4266 | case IOV_SVAL(IOV_TXBOUND): | |
4267 | dhd_txbound = (uint)int_val; | |
4268 | break; | |
4269 | ||
4270 | case IOV_GVAL(IOV_RXBOUND): | |
4271 | int_val = (int32)dhd_rxbound; | |
4272 | bcopy(&int_val, arg, val_size); | |
4273 | break; | |
4274 | ||
4275 | case IOV_SVAL(IOV_RXBOUND): | |
4276 | dhd_rxbound = (uint)int_val; | |
4277 | break; | |
4278 | ||
4279 | case IOV_GVAL(IOV_TXMINMAX): | |
4280 | int_val = (int32)dhd_txminmax; | |
4281 | bcopy(&int_val, arg, val_size); | |
4282 | break; | |
4283 | ||
4284 | case IOV_SVAL(IOV_TXMINMAX): | |
4285 | dhd_txminmax = (uint)int_val; | |
4286 | break; | |
4287 | ||
4288 | case IOV_GVAL(IOV_SERIALCONS): | |
4289 | int_val = dhd_serialconsole(bus, FALSE, 0, &bcmerror); | |
4290 | if (bcmerror != 0) | |
4291 | break; | |
4292 | ||
4293 | bcopy(&int_val, arg, val_size); | |
4294 | break; | |
4295 | ||
4296 | case IOV_SVAL(IOV_SERIALCONS): | |
4297 | dhd_serialconsole(bus, TRUE, bool_val, &bcmerror); | |
4298 | break; | |
4299 | ||
4300 | ||
4301 | #endif /* DHD_DEBUG */ | |
4302 | ||
4303 | ||
4304 | #ifdef SDTEST | |
4305 | case IOV_GVAL(IOV_EXTLOOP): | |
4306 | int_val = (int32)bus->ext_loop; | |
4307 | bcopy(&int_val, arg, val_size); | |
4308 | break; | |
4309 | ||
4310 | case IOV_SVAL(IOV_EXTLOOP): | |
4311 | bus->ext_loop = bool_val; | |
4312 | break; | |
4313 | ||
4314 | case IOV_GVAL(IOV_PKTGEN): | |
4315 | bcmerror = dhdsdio_pktgen_get(bus, arg); | |
4316 | break; | |
4317 | ||
4318 | case IOV_SVAL(IOV_PKTGEN): | |
4319 | bcmerror = dhdsdio_pktgen_set(bus, arg); | |
4320 | break; | |
4321 | #endif /* SDTEST */ | |
4322 | ||
4323 | #if defined(USE_SDIOFIFO_IOVAR) | |
4324 | case IOV_GVAL(IOV_WATERMARK): | |
4325 | int_val = (int32)watermark; | |
4326 | bcopy(&int_val, arg, val_size); | |
4327 | break; | |
4328 | ||
4329 | case IOV_SVAL(IOV_WATERMARK): | |
4330 | watermark = (uint)int_val; | |
4331 | watermark = (watermark > SBSDIO_WATERMARK_MASK) ? SBSDIO_WATERMARK_MASK : watermark; | |
4332 | DHD_ERROR(("Setting watermark as 0x%x.\n", watermark)); | |
4333 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, (uint8)watermark, NULL); | |
4334 | break; | |
4335 | ||
4336 | case IOV_GVAL(IOV_MESBUSYCTRL): | |
4337 | int_val = (int32)mesbusyctrl; | |
4338 | bcopy(&int_val, arg, val_size); | |
4339 | break; | |
4340 | ||
4341 | case IOV_SVAL(IOV_MESBUSYCTRL): | |
4342 | mesbusyctrl = (uint)int_val; | |
4343 | mesbusyctrl = (mesbusyctrl > SBSDIO_MESBUSYCTRL_MASK) | |
4344 | ? SBSDIO_MESBUSYCTRL_MASK : mesbusyctrl; | |
4345 | DHD_ERROR(("Setting mesbusyctrl as 0x%x.\n", mesbusyctrl)); | |
4346 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_MESBUSYCTRL, | |
4347 | ((uint8)mesbusyctrl | 0x80), NULL); | |
4348 | break; | |
4349 | #endif | |
4350 | ||
4351 | ||
4352 | case IOV_GVAL(IOV_DONGLEISOLATION): | |
4353 | int_val = bus->dhd->dongle_isolation; | |
4354 | bcopy(&int_val, arg, val_size); | |
4355 | break; | |
4356 | ||
4357 | case IOV_SVAL(IOV_DONGLEISOLATION): | |
4358 | bus->dhd->dongle_isolation = bool_val; | |
4359 | break; | |
4360 | ||
4361 | case IOV_SVAL(IOV_DEVRESET): | |
4362 | DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d busstate=%d\n", | |
4363 | __FUNCTION__, bool_val, bus->dhd->dongle_reset, | |
4364 | bus->dhd->busstate)); | |
4365 | ||
4366 | ASSERT(bus->dhd->osh); | |
4367 | /* ASSERT(bus->cl_devid); */ | |
4368 | ||
4369 | dhd_bus_devreset(bus->dhd, (uint8)bool_val); | |
4370 | ||
4371 | break; | |
4372 | /* | |
4373 | * softap firmware is updated through module parameter or android private command | |
4374 | */ | |
4375 | ||
4376 | case IOV_GVAL(IOV_DEVRESET): | |
4377 | DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __FUNCTION__)); | |
4378 | ||
4379 | /* Get its status */ | |
4380 | int_val = (bool) bus->dhd->dongle_reset; | |
4381 | bcopy(&int_val, arg, val_size); | |
4382 | ||
4383 | break; | |
4384 | ||
4385 | case IOV_GVAL(IOV_KSO): | |
4386 | int_val = dhdsdio_sleepcsr_get(bus); | |
4387 | bcopy(&int_val, arg, val_size); | |
4388 | break; | |
4389 | ||
4390 | case IOV_GVAL(IOV_DEVCAP): | |
4391 | int_val = dhdsdio_devcap_get(bus); | |
4392 | bcopy(&int_val, arg, val_size); | |
4393 | break; | |
4394 | ||
4395 | case IOV_SVAL(IOV_DEVCAP): | |
4396 | dhdsdio_devcap_set(bus, (uint8) int_val); | |
4397 | break; | |
4398 | case IOV_GVAL(IOV_TXGLOMSIZE): | |
4399 | int_val = (int32)bus->txglomsize; | |
4400 | bcopy(&int_val, arg, val_size); | |
4401 | break; | |
4402 | ||
4403 | case IOV_SVAL(IOV_TXGLOMSIZE): | |
4404 | if (int_val > SDPCM_MAXGLOM_SIZE) { | |
4405 | bcmerror = BCME_ERROR; | |
4406 | } else { | |
4407 | bus->txglomsize = (uint)int_val; | |
4408 | } | |
4409 | break; | |
4410 | case IOV_SVAL(IOV_HANGREPORT): | |
4411 | bus->dhd->hang_report = bool_val; | |
4412 | DHD_ERROR(("%s: Set hang_report as %d\n", __FUNCTION__, bus->dhd->hang_report)); | |
4413 | break; | |
4414 | ||
4415 | case IOV_GVAL(IOV_HANGREPORT): | |
4416 | int_val = (int32)bus->dhd->hang_report; | |
4417 | bcopy(&int_val, arg, val_size); | |
4418 | break; | |
4419 | ||
4420 | case IOV_GVAL(IOV_TXINRX_THRES): | |
4421 | int_val = bus->txinrx_thres; | |
4422 | bcopy(&int_val, arg, val_size); | |
4423 | break; | |
4424 | case IOV_SVAL(IOV_TXINRX_THRES): | |
4425 | if (int_val < 0) { | |
4426 | bcmerror = BCME_BADARG; | |
4427 | } else { | |
4428 | bus->txinrx_thres = int_val; | |
4429 | } | |
4430 | break; | |
4431 | ||
4432 | case IOV_GVAL(IOV_SDIO_SUSPEND): | |
4433 | int_val = (bus->dhd->busstate == DHD_BUS_SUSPEND) ? 1 : 0; | |
4434 | bcopy(&int_val, arg, val_size); | |
4435 | break; | |
4436 | ||
4437 | case IOV_SVAL(IOV_SDIO_SUSPEND): | |
4438 | if (bool_val) { /* Suspend */ | |
4439 | dhdsdio_suspend(bus); | |
4440 | } | |
4441 | else { /* Resume */ | |
4442 | dhdsdio_resume(bus); | |
4443 | } | |
4444 | break; | |
4445 | ||
4446 | default: | |
4447 | bcmerror = BCME_UNSUPPORTED; | |
4448 | break; | |
4449 | } | |
4450 | ||
4451 | exit: | |
4452 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched && | |
4453 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
4454 | bus->activity = FALSE; | |
4455 | dhdsdio_bussleep(bus, TRUE); | |
4456 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
4457 | } | |
4458 | ||
4459 | dhd_os_sdunlock(bus->dhd); | |
4460 | ||
4461 | return bcmerror; | |
4462 | } | |
4463 | ||
4464 | static int | |
4465 | dhdsdio_write_vars(dhd_bus_t *bus) | |
4466 | { | |
4467 | int bcmerror = 0; | |
4468 | uint32 varsize, phys_size; | |
4469 | uint32 varaddr; | |
4470 | uint8 *vbuffer; | |
4471 | uint32 varsizew; | |
4472 | #ifdef DHD_DEBUG | |
4473 | uint8 *nvram_ularray; | |
4474 | #endif /* DHD_DEBUG */ | |
4475 | ||
4476 | /* Even if there are no vars are to be written, we still need to set the ramsize. */ | |
4477 | varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0; | |
4478 | varaddr = (bus->ramsize - 4) - varsize; | |
4479 | ||
4480 | // terence 20150412: fix for nvram failed to download | |
4481 | if (bus->dhd->conf->chip == BCM43340_CHIP_ID || | |
4482 | bus->dhd->conf->chip == BCM43341_CHIP_ID) { | |
4483 | varsize = varsize ? ROUNDUP(varsize, 64) : 0; | |
4484 | varaddr = (bus->ramsize - 64) - varsize; | |
4485 | } | |
4486 | ||
4487 | varaddr += bus->dongle_ram_base; | |
4488 | ||
4489 | if (bus->vars) { | |
4490 | if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 7)) { | |
4491 | if (((varaddr & 0x3C) == 0x3C) && (varsize > 4)) { | |
4492 | DHD_ERROR(("PR85623WAR in place\n")); | |
4493 | varsize += 4; | |
4494 | varaddr -= 4; | |
4495 | } | |
4496 | } | |
4497 | ||
4498 | vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize); | |
4499 | if (!vbuffer) | |
4500 | return BCME_NOMEM; | |
4501 | ||
4502 | bzero(vbuffer, varsize); | |
4503 | bcopy(bus->vars, vbuffer, bus->varsz); | |
4504 | ||
4505 | /* Write the vars list */ | |
4506 | bcmerror = dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize); | |
4507 | if (bcmerror) { | |
4508 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
4509 | __FUNCTION__, bcmerror, varsize, varaddr)); | |
4510 | return bcmerror; | |
4511 | } | |
4512 | ||
4513 | #ifdef DHD_DEBUG | |
4514 | /* Verify NVRAM bytes */ | |
4515 | DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize)); | |
4516 | nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize); | |
4517 | if (!nvram_ularray) { | |
4518 | MFREE(bus->dhd->osh, vbuffer, varsize); | |
4519 | return BCME_NOMEM; | |
4520 | } | |
4521 | ||
4522 | /* Upload image to verify downloaded contents. */ | |
4523 | memset(nvram_ularray, 0xaa, varsize); | |
4524 | ||
4525 | /* Read the vars list to temp buffer for comparison */ | |
4526 | bcmerror = dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray, varsize); | |
4527 | if (bcmerror) { | |
4528 | DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n", | |
4529 | __FUNCTION__, bcmerror, varsize, varaddr)); | |
4530 | } | |
4531 | /* Compare the org NVRAM with the one read from RAM */ | |
4532 | if (memcmp(vbuffer, nvram_ularray, varsize)) { | |
4533 | DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__)); | |
4534 | } else | |
4535 | DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n", | |
4536 | __FUNCTION__)); | |
4537 | ||
4538 | MFREE(bus->dhd->osh, nvram_ularray, varsize); | |
4539 | #endif /* DHD_DEBUG */ | |
4540 | ||
4541 | MFREE(bus->dhd->osh, vbuffer, varsize); | |
4542 | } | |
4543 | ||
4544 | phys_size = REMAP_ENAB(bus) ? bus->ramsize : bus->orig_ramsize; | |
4545 | ||
4546 | phys_size += bus->dongle_ram_base; | |
4547 | ||
4548 | /* adjust to the user specified RAM */ | |
4549 | DHD_INFO(("Physical memory size: %d, usable memory size: %d\n", | |
4550 | phys_size, bus->ramsize)); | |
4551 | DHD_INFO(("Vars are at %d, orig varsize is %d\n", | |
4552 | varaddr, varsize)); | |
4553 | varsize = ((phys_size - 4) - varaddr); | |
4554 | ||
4555 | /* | |
4556 | * Determine the length token: | |
4557 | * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits. | |
4558 | */ | |
4559 | if (bcmerror) { | |
4560 | varsizew = 0; | |
4561 | } else { | |
4562 | varsizew = varsize / 4; | |
4563 | varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF); | |
4564 | varsizew = htol32(varsizew); | |
4565 | } | |
4566 | ||
4567 | DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew)); | |
4568 | ||
4569 | /* Write the length token to the last word */ | |
4570 | bcmerror = dhdsdio_membytes(bus, TRUE, (phys_size - 4), | |
4571 | (uint8*)&varsizew, 4); | |
4572 | ||
4573 | return bcmerror; | |
4574 | } | |
4575 | ||
4576 | static int | |
4577 | dhdsdio_download_state(dhd_bus_t *bus, bool enter) | |
4578 | { | |
4579 | uint retries; | |
4580 | int bcmerror = 0; | |
4581 | int foundcr4 = 0; | |
4582 | ||
4583 | if (!bus->sih) | |
4584 | return BCME_ERROR; | |
4585 | /* To enter download state, disable ARM and reset SOCRAM. | |
4586 | * To exit download state, simply reset ARM (default is RAM boot). | |
4587 | */ | |
4588 | if (enter) { | |
4589 | bus->alp_only = TRUE; | |
4590 | ||
4591 | if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && | |
4592 | !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) { | |
4593 | if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { | |
4594 | foundcr4 = 1; | |
4595 | } else { | |
4596 | DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); | |
4597 | bcmerror = BCME_ERROR; | |
4598 | goto fail; | |
4599 | } | |
4600 | } | |
4601 | ||
4602 | if (!foundcr4) { | |
4603 | si_core_disable(bus->sih, 0); | |
4604 | if (bcmsdh_regfail(bus->sdh)) { | |
4605 | bcmerror = BCME_SDIO_ERROR; | |
4606 | goto fail; | |
4607 | } | |
4608 | ||
4609 | if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { | |
4610 | DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); | |
4611 | bcmerror = BCME_ERROR; | |
4612 | goto fail; | |
4613 | } | |
4614 | ||
4615 | si_core_reset(bus->sih, 0, 0); | |
4616 | if (bcmsdh_regfail(bus->sdh)) { | |
4617 | DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n", | |
4618 | __FUNCTION__)); | |
4619 | bcmerror = BCME_SDIO_ERROR; | |
4620 | goto fail; | |
4621 | } | |
4622 | ||
4623 | /* Disable remap for download */ | |
4624 | if (REMAP_ENAB(bus) && si_socdevram_remap_isenb(bus->sih)) | |
4625 | dhdsdio_devram_remap(bus, FALSE); | |
4626 | ||
4627 | if (CHIPID(bus->sih->chip) == BCM43430_CHIP_ID || | |
4628 | CHIPID(bus->sih->chip) == BCM43018_CHIP_ID) { | |
4629 | /* Disabling Remap for SRAM_3 */ | |
4630 | si_socram_set_bankpda(bus->sih, 0x3, 0x0); | |
4631 | } | |
4632 | ||
4633 | /* Clear the top bit of memory */ | |
4634 | if (bus->ramsize) { | |
4635 | uint32 zeros = 0; | |
4636 | if (dhdsdio_membytes(bus, TRUE, bus->ramsize - 4, | |
4637 | (uint8*)&zeros, 4) < 0) { | |
4638 | bcmerror = BCME_SDIO_ERROR; | |
4639 | goto fail; | |
4640 | } | |
4641 | } | |
4642 | } else { | |
4643 | /* For CR4, | |
4644 | * Halt ARM | |
4645 | * Remove ARM reset | |
4646 | * Read RAM base address [0x18_0000] | |
4647 | * [next] Download firmware | |
4648 | * [done at else] Populate the reset vector | |
4649 | * [done at else] Remove ARM halt | |
4650 | */ | |
4651 | /* Halt ARM & remove reset */ | |
4652 | si_core_reset(bus->sih, SICF_CPUHALT, SICF_CPUHALT); | |
4653 | } | |
4654 | } else { | |
4655 | if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { | |
4656 | if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) { | |
4657 | DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__)); | |
4658 | bcmerror = BCME_ERROR; | |
4659 | goto fail; | |
4660 | } | |
4661 | ||
4662 | if (!si_iscoreup(bus->sih)) { | |
4663 | DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__)); | |
4664 | bcmerror = BCME_ERROR; | |
4665 | goto fail; | |
4666 | } | |
4667 | ||
4668 | if ((bcmerror = dhdsdio_write_vars(bus))) { | |
4669 | DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__)); | |
4670 | goto fail; | |
4671 | } | |
4672 | ||
4673 | /* Enable remap before ARM reset but after vars. | |
4674 | * No backplane access in remap mode | |
4675 | */ | |
4676 | if (REMAP_ENAB(bus) && !si_socdevram_remap_isenb(bus->sih)) | |
4677 | dhdsdio_devram_remap(bus, TRUE); | |
4678 | ||
4679 | if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) && | |
4680 | !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) { | |
4681 | DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__)); | |
4682 | bcmerror = BCME_ERROR; | |
4683 | goto fail; | |
4684 | } | |
4685 | W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries); | |
4686 | ||
4687 | ||
4688 | if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && | |
4689 | !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) { | |
4690 | DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__)); | |
4691 | bcmerror = BCME_ERROR; | |
4692 | goto fail; | |
4693 | } | |
4694 | } else { | |
4695 | /* cr4 has no socram, but tcm's */ | |
4696 | /* write vars */ | |
4697 | if ((bcmerror = dhdsdio_write_vars(bus))) { | |
4698 | DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__)); | |
4699 | goto fail; | |
4700 | } | |
4701 | ||
4702 | if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) && | |
4703 | !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) { | |
4704 | DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__)); | |
4705 | bcmerror = BCME_ERROR; | |
4706 | goto fail; | |
4707 | } | |
4708 | W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries); | |
4709 | ||
4710 | /* switch back to arm core again */ | |
4711 | if (!(si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) { | |
4712 | DHD_ERROR(("%s: Failed to find ARM CR4 core!\n", __FUNCTION__)); | |
4713 | bcmerror = BCME_ERROR; | |
4714 | goto fail; | |
4715 | } | |
4716 | /* write address 0 with reset instruction */ | |
4717 | bcmerror = dhdsdio_membytes(bus, TRUE, 0, | |
4718 | (uint8 *)&bus->resetinstr, sizeof(bus->resetinstr)); | |
4719 | ||
4720 | if (bcmerror == BCME_OK) { | |
4721 | uint32 tmp; | |
07d6b24a | 4722 | |
010c3a89 | 4723 | /* verify write */ |
565fad4d | 4724 | bcmerror = dhdsdio_membytes(bus, FALSE, 0, |
07d6b24a RC |
4725 | (uint8 *)&tmp, sizeof(tmp)); |
4726 | ||
4727 | if (bcmerror == BCME_OK && tmp != bus->resetinstr) { | |
4728 | DHD_ERROR(("%s: Failed to write 0x%08x to addr 0\n", | |
010c3a89 RC |
4729 | __FUNCTION__, bus->resetinstr)); |
4730 | DHD_ERROR(("%s: contents of addr 0 is 0x%08x\n", | |
07d6b24a | 4731 | __FUNCTION__, tmp)); |
010c3a89 RC |
4732 | bcmerror = BCME_SDIO_ERROR; |
4733 | goto fail; | |
4734 | } | |
4735 | } | |
4736 | ||
4737 | /* now remove reset and halt and continue to run CR4 */ | |
4738 | } | |
4739 | ||
4740 | si_core_reset(bus->sih, 0, 0); | |
4741 | if (bcmsdh_regfail(bus->sdh)) { | |
4742 | DHD_ERROR(("%s: Failure trying to reset ARM core?\n", __FUNCTION__)); | |
4743 | bcmerror = BCME_SDIO_ERROR; | |
4744 | goto fail; | |
4745 | } | |
4746 | ||
4747 | /* Allow HT Clock now that the ARM is running. */ | |
4748 | bus->alp_only = FALSE; | |
4749 | ||
4750 | bus->dhd->busstate = DHD_BUS_LOAD; | |
4751 | } | |
4752 | ||
4753 | fail: | |
4754 | /* Always return to SDIOD core */ | |
4755 | if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) | |
4756 | si_setcore(bus->sih, SDIOD_CORE_ID, 0); | |
4757 | ||
4758 | return bcmerror; | |
4759 | } | |
4760 | ||
4761 | int | |
4762 | dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name, | |
4763 | void *params, int plen, void *arg, int len, bool set) | |
4764 | { | |
4765 | dhd_bus_t *bus = dhdp->bus; | |
4766 | const bcm_iovar_t *vi = NULL; | |
4767 | int bcmerror = 0; | |
4768 | int val_size; | |
4769 | uint32 actionid; | |
4770 | ||
4771 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
4772 | ||
4773 | ASSERT(name); | |
4774 | ASSERT(len >= 0); | |
4775 | ||
4776 | /* Get MUST have return space */ | |
4777 | ASSERT(set || (arg && len)); | |
4778 | ||
4779 | /* Set does NOT take qualifiers */ | |
4780 | ASSERT(!set || (!params && !plen)); | |
4781 | ||
4782 | /* Look up var locally; if not found pass to host driver */ | |
4783 | if ((vi = bcm_iovar_lookup(dhdsdio_iovars, name)) == NULL) { | |
4784 | dhd_os_sdlock(bus->dhd); | |
4785 | ||
4786 | BUS_WAKE(bus); | |
4787 | ||
4788 | /* Turn on clock in case SD command needs backplane */ | |
4789 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
4790 | ||
4791 | bcmerror = bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len, set); | |
4792 | ||
4793 | /* Check for bus configuration changes of interest */ | |
4794 | ||
4795 | /* If it was divisor change, read the new one */ | |
4796 | if (set && strcmp(name, "sd_divisor") == 0) { | |
4797 | if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0, | |
4798 | &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) { | |
4799 | bus->sd_divisor = -1; | |
4800 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name)); | |
4801 | } else { | |
4802 | DHD_INFO(("%s: noted %s update, value now %d\n", | |
4803 | __FUNCTION__, name, bus->sd_divisor)); | |
4804 | } | |
4805 | } | |
4806 | /* If it was a mode change, read the new one */ | |
4807 | if (set && strcmp(name, "sd_mode") == 0) { | |
4808 | if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0, | |
4809 | &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) { | |
4810 | bus->sd_mode = -1; | |
4811 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name)); | |
4812 | } else { | |
4813 | DHD_INFO(("%s: noted %s update, value now %d\n", | |
4814 | __FUNCTION__, name, bus->sd_mode)); | |
4815 | } | |
4816 | } | |
4817 | /* Similar check for blocksize change */ | |
4818 | if (set && strcmp(name, "sd_blocksize") == 0) { | |
4819 | int32 fnum = 2; | |
4820 | if (bcmsdh_iovar_op(bus->sdh, "sd_blocksize", &fnum, sizeof(int32), | |
4821 | &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) { | |
4822 | bus->blocksize = 0; | |
4823 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize")); | |
4824 | } else { | |
4825 | DHD_INFO(("%s: noted %s update, value now %d\n", | |
4826 | __FUNCTION__, "sd_blocksize", bus->blocksize)); | |
4827 | ||
4828 | dhdsdio_tune_fifoparam(bus); | |
4829 | } | |
4830 | } | |
4831 | bus->roundup = MIN(max_roundup, bus->blocksize); | |
4832 | ||
4833 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched && | |
4834 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
4835 | bus->activity = FALSE; | |
4836 | dhdsdio_bussleep(bus, TRUE); | |
4837 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
4838 | } | |
4839 | ||
4840 | dhd_os_sdunlock(bus->dhd); | |
4841 | goto exit; | |
4842 | } | |
4843 | ||
4844 | DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__, | |
4845 | name, (set ? "set" : "get"), len, plen)); | |
4846 | ||
4847 | /* set up 'params' pointer in case this is a set command so that | |
4848 | * the convenience int and bool code can be common to set and get | |
4849 | */ | |
4850 | if (params == NULL) { | |
4851 | params = arg; | |
4852 | plen = len; | |
4853 | } | |
4854 | ||
4855 | if (vi->type == IOVT_VOID) | |
4856 | val_size = 0; | |
4857 | else if (vi->type == IOVT_BUFFER) | |
4858 | val_size = len; | |
4859 | else | |
4860 | /* all other types are integer sized */ | |
4861 | val_size = sizeof(int); | |
4862 | ||
4863 | actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid); | |
4864 | bcmerror = dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size); | |
4865 | ||
4866 | exit: | |
4867 | return bcmerror; | |
4868 | } | |
4869 | ||
4870 | void | |
4871 | dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex) | |
4872 | { | |
4873 | osl_t *osh; | |
4874 | uint32 local_hostintmask; | |
4875 | uint8 saveclk; | |
4876 | uint retries; | |
4877 | int err; | |
4878 | bool wlfc_enabled = FALSE; | |
4879 | unsigned long flags; | |
4880 | ||
4881 | if (!bus->dhd) | |
4882 | return; | |
4883 | ||
4884 | osh = bus->dhd->osh; | |
4885 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
4886 | ||
4887 | bcmsdh_waitlockfree(bus->sdh); | |
4888 | ||
4889 | if (enforce_mutex) | |
4890 | dhd_os_sdlock(bus->dhd); | |
4891 | ||
4892 | if ((bus->dhd->busstate == DHD_BUS_DOWN) || bus->dhd->hang_was_sent) { | |
4893 | /* if Firmware already hangs disbale any interrupt */ | |
4894 | bus->dhd->busstate = DHD_BUS_DOWN; | |
4895 | bus->hostintmask = 0; | |
4896 | bcmsdh_intr_disable(bus->sdh); | |
4897 | } else { | |
4898 | ||
4899 | BUS_WAKE(bus); | |
4900 | ||
4901 | if (KSO_ENAB(bus)) { | |
4902 | ||
4903 | /* Enable clock for device interrupts */ | |
4904 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
4905 | ||
4906 | /* Disable and clear interrupts at the chip level also */ | |
4907 | W_SDREG(0, &bus->regs->hostintmask, retries); | |
4908 | local_hostintmask = bus->hostintmask; | |
4909 | bus->hostintmask = 0; | |
4910 | ||
4911 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
4912 | saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
4913 | if (!err) { | |
4914 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
4915 | (saveclk | SBSDIO_FORCE_HT), &err); | |
4916 | } | |
4917 | if (err) { | |
4918 | DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", | |
4919 | __FUNCTION__, err)); | |
4920 | } | |
4921 | ||
4922 | /* Turn off the bus (F2), free any pending packets */ | |
4923 | DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__)); | |
4924 | bcmsdh_intr_disable(bus->sdh); | |
4925 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL); | |
4926 | ||
4927 | /* Clear any pending interrupts now that F2 is disabled */ | |
4928 | W_SDREG(local_hostintmask, &bus->regs->intstatus, retries); | |
4929 | } | |
4930 | ||
4931 | /* Turn off the backplane clock (only) */ | |
4932 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
4933 | ||
4934 | /* Change our idea of bus state */ | |
4935 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
4936 | bus->dhd->busstate = DHD_BUS_DOWN; | |
4937 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
4938 | } | |
4939 | ||
4940 | #ifdef PROP_TXSTATUS | |
4941 | wlfc_enabled = (dhd_wlfc_cleanup_txq(bus->dhd, NULL, 0) != WLFC_UNSUPPORTED); | |
4942 | #endif | |
4943 | if (!wlfc_enabled) { | |
4944 | #ifdef DHDTCPACK_SUPPRESS | |
4945 | /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt, | |
4946 | * when there is a newly coming packet from network stack. | |
4947 | */ | |
4948 | dhd_tcpack_info_tbl_clean(bus->dhd); | |
4949 | #endif /* DHDTCPACK_SUPPRESS */ | |
4950 | dhd_os_sdlock_txq(bus->dhd); | |
4951 | /* Clear the data packet queues */ | |
4952 | pktq_flush(osh, &bus->txq, TRUE); | |
4953 | dhd_os_sdunlock_txq(bus->dhd); | |
4954 | } | |
4955 | ||
4956 | /* Clear any held glomming stuff */ | |
4957 | if (bus->glomd) | |
4958 | PKTFREE(osh, bus->glomd, FALSE); | |
4959 | ||
4960 | if (bus->glom) | |
4961 | PKTFREE(osh, bus->glom, FALSE); | |
4962 | ||
4963 | bus->glom = bus->glomd = NULL; | |
4964 | ||
4965 | /* Clear rx control and wake any waiters */ | |
4966 | bus->rxlen = 0; | |
4967 | dhd_os_ioctl_resp_wake(bus->dhd); | |
4968 | ||
4969 | /* Reset some F2 state stuff */ | |
4970 | bus->rxskip = FALSE; | |
4971 | bus->tx_seq = bus->rx_seq = 0; | |
4972 | ||
4973 | bus->tx_max = 4; | |
4974 | ||
4975 | if (enforce_mutex) | |
4976 | dhd_os_sdunlock(bus->dhd); | |
4977 | } | |
4978 | ||
4979 | #if defined(BCMSDIOH_TXGLOM) && defined(BCMSDIOH_STD) | |
4980 | extern uint sd_txglom; | |
4981 | #endif | |
4982 | void | |
4983 | dhd_txglom_enable(dhd_pub_t *dhdp, bool enable) | |
4984 | { | |
4985 | /* can't enable host txglom by default, some platforms have no | |
4986 | * (or crappy) ADMA support and txglom will cause kernel assertions (e.g. | |
4987 | * panda board) | |
4988 | */ | |
4989 | dhd_bus_t *bus = dhdp->bus; | |
4990 | #ifdef BCMSDIOH_TXGLOM | |
4991 | uint32 rxglom; | |
4992 | int32 ret; | |
4993 | ||
4994 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
4995 | ||
4996 | #ifdef BCMSDIOH_STD | |
4997 | if (enable) | |
4998 | enable = sd_txglom; | |
4999 | #endif /* BCMSDIOH_STD */ | |
5000 | ||
5001 | if (enable) { | |
5002 | rxglom = 1; | |
5003 | ret = dhd_iovar(dhdp, 0, "bus:rxglom", (char *)&rxglom, sizeof(rxglom), NULL, 0, | |
5004 | TRUE); | |
5005 | if (ret >= 0) | |
5006 | bus->txglom_enable = TRUE; | |
5007 | else { | |
5008 | #ifdef BCMSDIOH_STD | |
5009 | sd_txglom = 0; | |
5010 | #endif /* BCMSDIOH_STD */ | |
5011 | bus->txglom_enable = FALSE; | |
5012 | } | |
5013 | } else | |
5014 | #endif /* BCMSDIOH_TXGLOM */ | |
5015 | bus->txglom_enable = FALSE; | |
5016 | printf("%s: enable %d\n", __FUNCTION__, bus->txglom_enable); | |
5017 | dhd_conf_set_txglom_params(bus->dhd, bus->txglom_enable); | |
5018 | bcmsdh_set_mode(bus->sdh, bus->dhd->conf->txglom_mode); | |
5019 | } | |
5020 | ||
5021 | int | |
5022 | dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex) | |
5023 | { | |
5024 | dhd_bus_t *bus = dhdp->bus; | |
5025 | dhd_timeout_t tmo; | |
5026 | uint retries = 0; | |
5027 | uint8 ready, enable; | |
5028 | int err, ret = 0; | |
5029 | uint8 saveclk; | |
5030 | ||
5031 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
5032 | ||
5033 | ASSERT(bus->dhd); | |
5034 | if (!bus->dhd) | |
5035 | return 0; | |
5036 | ||
5037 | if (enforce_mutex) | |
5038 | dhd_os_sdlock(bus->dhd); | |
5039 | ||
5040 | if (bus->sih->chip == BCM43362_CHIP_ID) { | |
5041 | printf("%s: delay 100ms for BCM43362\n", __FUNCTION__); | |
5042 | OSL_DELAY(100000); // terence 20131209: delay for 43362 | |
5043 | } | |
5044 | ||
5045 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
5046 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
5047 | if (bus->clkstate != CLK_AVAIL) { | |
5048 | DHD_ERROR(("%s: clock state is wrong. state = %d\n", __FUNCTION__, bus->clkstate)); | |
5049 | ret = -1; | |
5050 | goto exit; | |
5051 | } | |
5052 | ||
5053 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
5054 | saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5055 | ||
5056 | if (!err) { | |
5057 | if (bus->sih->chip == BCM43012_CHIP_ID) { | |
5058 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
5059 | (saveclk | SBSDIO_HT_AVAIL_REQ), &err); | |
5060 | } else { | |
5061 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
5062 | (saveclk | SBSDIO_FORCE_HT), &err); | |
5063 | } | |
5064 | } | |
5065 | ||
5066 | if (err) { | |
5067 | DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", __FUNCTION__, err)); | |
5068 | ret = -1; | |
5069 | goto exit; | |
5070 | } | |
5071 | ||
5072 | /* Enable function 2 (frame transfers) */ | |
5073 | W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT), | |
5074 | &bus->regs->tosbmailboxdata, retries); | |
5075 | enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2); | |
5076 | ||
5077 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL); | |
5078 | ||
5079 | /* Give the dongle some time to do its thing and set IOR2 */ | |
5080 | dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000); | |
5081 | ||
5082 | ready = 0; | |
5083 | while (ready != enable && !dhd_timeout_expired(&tmo)) | |
5084 | ready = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL); | |
5085 | ||
5086 | DHD_ERROR(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n", | |
5087 | __FUNCTION__, enable, ready, tmo.elapsed)); | |
5088 | ||
5089 | ||
5090 | /* If F2 successfully enabled, set core and enable interrupts */ | |
5091 | if (ready == enable) { | |
5092 | /* Make sure we're talking to the core. */ | |
5093 | if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0))) | |
5094 | bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0); | |
5095 | ASSERT(bus->regs != NULL); | |
5096 | ||
5097 | /* Set up the interrupt mask and enable interrupts */ | |
5098 | bus->hostintmask = HOSTINTMASK; | |
5099 | /* corerev 4 could use the newer interrupt logic to detect the frames */ | |
5100 | if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 4) && | |
5101 | (bus->rxint_mode != SDIO_DEVICE_HMB_RXINT)) { | |
5102 | bus->hostintmask &= ~I_HMB_FRAME_IND; | |
5103 | bus->hostintmask |= I_XMTDATA_AVAIL; | |
5104 | } | |
5105 | W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries); | |
5106 | ||
5107 | if (bus->sih->buscorerev < 15) { | |
5108 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, | |
5109 | (uint8)watermark, &err); | |
5110 | } | |
5111 | ||
5112 | /* Set bus state according to enable result */ | |
5113 | dhdp->busstate = DHD_BUS_DATA; | |
5114 | ||
5115 | /* Need to set fn2 block size to match fn1 block size. | |
5116 | * Requests to fn2 go thru fn1. * | |
5117 | * faltwig has this code contitioned with #if !BCMSPI_ANDROID. | |
5118 | * It would be cleaner to use the ->sdh->block_sz[fno] instead of | |
5119 | * 64, but this layer has no access to sdh types. | |
5120 | */ | |
5121 | ||
5122 | /* bcmsdh_intr_unmask(bus->sdh); */ | |
5123 | ||
5124 | bus->intdis = FALSE; | |
5125 | if (bus->intr) { | |
5126 | DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__)); | |
5127 | bcmsdh_intr_enable(bus->sdh); | |
5128 | } else { | |
5129 | DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__)); | |
5130 | bcmsdh_intr_disable(bus->sdh); | |
5131 | } | |
5132 | ||
5133 | } | |
5134 | ||
5135 | ||
5136 | else { | |
5137 | /* Disable F2 again */ | |
5138 | enable = SDIO_FUNC_ENABLE_1; | |
5139 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL); | |
5140 | } | |
5141 | ||
5142 | if (dhdsdio_sr_cap(bus)) { | |
5143 | dhdsdio_sr_init(bus); | |
5144 | /* Masking the chip active interrupt permanantly */ | |
5145 | bus->hostintmask &= ~I_CHIPACTIVE; | |
5146 | W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries); | |
5147 | DHD_INFO(("%s: disable I_CHIPACTIVE in hostintmask[0x%08x]\n", | |
5148 | __FUNCTION__, bus->hostintmask)); | |
5149 | } else { | |
5150 | bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, | |
5151 | SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err); | |
5152 | } | |
5153 | ||
5154 | /* If we didn't come up, turn off backplane clock */ | |
5155 | if (dhdp->busstate != DHD_BUS_DATA) | |
5156 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
5157 | ||
5158 | exit: | |
5159 | if (enforce_mutex) | |
5160 | dhd_os_sdunlock(bus->dhd); | |
5161 | ||
5162 | return ret; | |
5163 | } | |
5164 | ||
5165 | static void | |
5166 | dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx) | |
5167 | { | |
5168 | bcmsdh_info_t *sdh = bus->sdh; | |
5169 | sdpcmd_regs_t *regs = bus->regs; | |
5170 | uint retries = 0; | |
5171 | uint16 lastrbc; | |
5172 | uint8 hi, lo; | |
5173 | int err; | |
5174 | ||
5175 | DHD_ERROR(("%s: %sterminate frame%s\n", __FUNCTION__, | |
5176 | (abort ? "abort command, " : ""), (rtx ? ", send NAK" : ""))); | |
5177 | ||
5178 | if (!KSO_ENAB(bus)) { | |
5179 | DHD_ERROR(("%s: Device asleep\n", __FUNCTION__)); | |
5180 | return; | |
5181 | } | |
5182 | ||
5183 | if (abort) { | |
5184 | bcmsdh_abort(sdh, SDIO_FUNC_2); | |
5185 | } | |
5186 | ||
5187 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, &err); | |
5188 | if (err) { | |
5189 | DHD_ERROR(("%s: SBSDIO_FUNC1_FRAMECTRL cmd err\n", __FUNCTION__)); | |
5190 | goto fail; | |
5191 | } | |
5192 | bus->f1regdata++; | |
5193 | ||
5194 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
5195 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
5196 | hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI, NULL); | |
5197 | lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO, &err); | |
5198 | if (err) { | |
5199 | DHD_ERROR(("%s: SBSDIO_FUNC1_RFAMEBCLO cmd err\n", __FUNCTION__)); | |
5200 | goto fail; | |
5201 | } | |
5202 | ||
5203 | bus->f1regdata += 2; | |
5204 | ||
5205 | if ((hi == 0) && (lo == 0)) | |
5206 | break; | |
5207 | ||
5208 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5209 | DHD_ERROR(("%s: count growing: last 0x%04x now 0x%04x\n", | |
5210 | __FUNCTION__, lastrbc, ((hi << 8) + lo))); | |
5211 | } | |
5212 | lastrbc = (hi << 8) + lo; | |
5213 | } | |
5214 | ||
5215 | if (!retries) { | |
5216 | DHD_ERROR(("%s: count never zeroed: last 0x%04x\n", __FUNCTION__, lastrbc)); | |
5217 | } else { | |
5218 | DHD_INFO(("%s: flush took %d iterations\n", __FUNCTION__, (0xffff - retries))); | |
5219 | } | |
5220 | ||
5221 | if (rtx) { | |
5222 | bus->rxrtx++; | |
5223 | W_SDREG(SMB_NAK, ®s->tosbmailbox, retries); | |
5224 | bus->f1regdata++; | |
5225 | if (retries <= retry_limit) { | |
5226 | bus->rxskip = TRUE; | |
5227 | } | |
5228 | } | |
5229 | ||
5230 | /* Clear partial in any case */ | |
5231 | bus->nextlen = 0; | |
5232 | ||
5233 | fail: | |
5234 | /* If we can't reach the device, signal failure */ | |
5235 | if (err || bcmsdh_regfail(sdh)) | |
5236 | bus->dhd->busstate = DHD_BUS_DOWN; | |
5237 | } | |
5238 | ||
5239 | static void | |
5240 | dhdsdio_read_control(dhd_bus_t *bus, uint8 *hdr, uint len, uint doff) | |
5241 | { | |
5242 | bcmsdh_info_t *sdh = bus->sdh; | |
5243 | uint rdlen, pad; | |
5244 | ||
5245 | int sdret; | |
5246 | ||
5247 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
5248 | ||
5249 | /* Control data already received in aligned rxctl */ | |
5250 | if ((bus->bus == SPI_BUS) && (!bus->usebufpool)) | |
5251 | goto gotpkt; | |
5252 | ||
5253 | ASSERT(bus->rxbuf); | |
5254 | /* Set rxctl for frame (w/optional alignment) */ | |
5255 | bus->rxctl = bus->rxbuf; | |
5256 | if (dhd_alignctl) { | |
5257 | bus->rxctl += firstread; | |
5258 | if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN))) | |
5259 | bus->rxctl += (DHD_SDALIGN - pad); | |
5260 | bus->rxctl -= firstread; | |
5261 | } | |
5262 | ASSERT(bus->rxctl >= bus->rxbuf); | |
5263 | ||
5264 | /* Copy the already-read portion over */ | |
5265 | bcopy(hdr, bus->rxctl, firstread); | |
5266 | if (len <= firstread) | |
5267 | goto gotpkt; | |
5268 | ||
5269 | /* Copy the full data pkt in gSPI case and process ioctl. */ | |
5270 | if (bus->bus == SPI_BUS) { | |
5271 | bcopy(hdr, bus->rxctl, len); | |
5272 | goto gotpkt; | |
5273 | } | |
5274 | ||
5275 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
5276 | rdlen = len - firstread; | |
5277 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
5278 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
5279 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
5280 | ((len + pad) < bus->dhd->maxctl)) | |
5281 | rdlen += pad; | |
5282 | } else if (rdlen % DHD_SDALIGN) { | |
5283 | rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN); | |
5284 | } | |
5285 | ||
5286 | /* Satisfy length-alignment requirements */ | |
5287 | if (forcealign && (rdlen & (ALIGNMENT - 1))) | |
5288 | rdlen = ROUNDUP(rdlen, ALIGNMENT); | |
5289 | ||
5290 | /* Drop if the read is too big or it exceeds our maximum */ | |
5291 | if ((rdlen + firstread) > bus->dhd->maxctl) { | |
5292 | DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n", | |
5293 | __FUNCTION__, rdlen, bus->dhd->maxctl)); | |
5294 | bus->dhd->rx_errors++; | |
5295 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
5296 | goto done; | |
5297 | } | |
5298 | ||
5299 | if ((len - doff) > bus->dhd->maxctl) { | |
5300 | DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", | |
5301 | __FUNCTION__, len, (len - doff), bus->dhd->maxctl)); | |
5302 | bus->dhd->rx_errors++; bus->rx_toolong++; | |
5303 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
5304 | goto done; | |
5305 | } | |
5306 | ||
5307 | ||
5308 | /* Read remainder of frame body into the rxctl buffer */ | |
5309 | sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC, | |
5310 | (bus->rxctl + firstread), rdlen, NULL, NULL, NULL); | |
5311 | bus->f2rxdata++; | |
5312 | ASSERT(sdret != BCME_PENDING); | |
5313 | ||
5314 | /* Control frame failures need retransmission */ | |
5315 | if (sdret < 0) { | |
5316 | DHD_ERROR(("%s: read %d control bytes failed: %d\n", __FUNCTION__, rdlen, sdret)); | |
5317 | bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */ | |
5318 | dhdsdio_rxfail(bus, TRUE, TRUE); | |
5319 | goto done; | |
5320 | } | |
5321 | ||
5322 | gotpkt: | |
5323 | ||
5324 | #ifdef DHD_DEBUG | |
5325 | if (DHD_BYTES_ON() && DHD_CTL_ON()) { | |
5326 | prhex("RxCtrl", bus->rxctl, len); | |
5327 | } | |
5328 | #endif | |
5329 | ||
5330 | /* Point to valid data and indicate its length */ | |
5331 | bus->rxctl += doff; | |
5332 | bus->rxlen = len - doff; | |
5333 | ||
5334 | done: | |
5335 | /* Awake any waiters */ | |
5336 | dhd_os_ioctl_resp_wake(bus->dhd); | |
5337 | } | |
5338 | int | |
5339 | dhd_process_pkt_reorder_info(dhd_pub_t *dhd, uchar *reorder_info_buf, uint reorder_info_len, | |
5340 | void **pkt, uint32 *pkt_count); | |
5341 | ||
5342 | static uint8 | |
5343 | dhdsdio_rxglom(dhd_bus_t *bus, uint8 rxseq) | |
5344 | { | |
5345 | uint16 dlen, totlen; | |
5346 | uint8 *dptr, num = 0; | |
5347 | ||
5348 | uint16 sublen, check; | |
5349 | void *pfirst, *plast, *pnext; | |
5350 | void * list_tail[DHD_MAX_IFS] = { NULL }; | |
5351 | void * list_head[DHD_MAX_IFS] = { NULL }; | |
5352 | uint8 idx; | |
5353 | osl_t *osh = bus->dhd->osh; | |
5354 | ||
5355 | int errcode; | |
5356 | uint8 chan, seq, doff, sfdoff; | |
5357 | uint8 txmax; | |
5358 | uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN]; | |
5359 | uint reorder_info_len; | |
5360 | ||
5361 | int ifidx = 0; | |
5362 | bool usechain = bus->use_rxchain; | |
5363 | ||
5364 | /* If packets, issue read(s) and send up packet chain */ | |
5365 | /* Return sequence numbers consumed? */ | |
5366 | ||
5367 | DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd, bus->glom)); | |
5368 | ||
5369 | /* If there's a descriptor, generate the packet chain */ | |
5370 | if (bus->glomd) { | |
5371 | dhd_os_sdlock_rxq(bus->dhd); | |
5372 | ||
5373 | pfirst = plast = pnext = NULL; | |
5374 | dlen = (uint16)PKTLEN(osh, bus->glomd); | |
5375 | dptr = PKTDATA(osh, bus->glomd); | |
5376 | if (!dlen || (dlen & 1)) { | |
5377 | DHD_ERROR(("%s: bad glomd len (%d), ignore descriptor\n", | |
5378 | __FUNCTION__, dlen)); | |
5379 | dlen = 0; | |
5380 | } | |
5381 | ||
5382 | for (totlen = num = 0; dlen; num++) { | |
5383 | /* Get (and move past) next length */ | |
5384 | sublen = ltoh16_ua(dptr); | |
5385 | dlen -= sizeof(uint16); | |
5386 | dptr += sizeof(uint16); | |
5387 | if ((sublen < SDPCM_HDRLEN) || | |
5388 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5389 | DHD_ERROR(("%s: descriptor len %d bad: %d\n", | |
5390 | __FUNCTION__, num, sublen)); | |
5391 | pnext = NULL; | |
5392 | break; | |
5393 | } | |
5394 | if (sublen % DHD_SDALIGN) { | |
5395 | DHD_ERROR(("%s: sublen %d not a multiple of %d\n", | |
5396 | __FUNCTION__, sublen, DHD_SDALIGN)); | |
5397 | usechain = FALSE; | |
5398 | } | |
5399 | totlen += sublen; | |
5400 | ||
5401 | /* For last frame, adjust read len so total is a block multiple */ | |
5402 | if (!dlen) { | |
5403 | sublen += (ROUNDUP(totlen, bus->blocksize) - totlen); | |
5404 | totlen = ROUNDUP(totlen, bus->blocksize); | |
5405 | } | |
5406 | ||
5407 | /* Allocate/chain packet for next subframe */ | |
5408 | if ((pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE)) == NULL) { | |
5409 | DHD_ERROR(("%s: PKTGET failed, num %d len %d\n", | |
5410 | __FUNCTION__, num, sublen)); | |
5411 | break; | |
5412 | } | |
5413 | ASSERT(!PKTLINK(pnext)); | |
5414 | if (!pfirst) { | |
5415 | ASSERT(!plast); | |
5416 | pfirst = plast = pnext; | |
5417 | } else { | |
5418 | ASSERT(plast); | |
5419 | PKTSETNEXT(osh, plast, pnext); | |
5420 | plast = pnext; | |
5421 | } | |
5422 | ||
5423 | /* Adhere to start alignment requirements */ | |
5424 | PKTALIGN(osh, pnext, sublen, DHD_SDALIGN); | |
5425 | } | |
5426 | ||
5427 | /* If all allocations succeeded, save packet chain in bus structure */ | |
5428 | if (pnext) { | |
5429 | DHD_GLOM(("%s: allocated %d-byte packet chain for %d subframes\n", | |
5430 | __FUNCTION__, totlen, num)); | |
5431 | if (DHD_GLOM_ON() && bus->nextlen) { | |
5432 | if (totlen != bus->nextlen) { | |
5433 | DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " | |
5434 | "rxseq %d\n", __FUNCTION__, bus->nextlen, | |
5435 | totlen, rxseq)); | |
5436 | } | |
5437 | } | |
5438 | bus->glom = pfirst; | |
5439 | pfirst = pnext = NULL; | |
5440 | } else { | |
5441 | if (pfirst) | |
5442 | PKTFREE(osh, pfirst, FALSE); | |
5443 | bus->glom = NULL; | |
5444 | num = 0; | |
5445 | } | |
5446 | ||
5447 | /* Done with descriptor packet */ | |
5448 | PKTFREE(osh, bus->glomd, FALSE); | |
5449 | bus->glomd = NULL; | |
5450 | bus->nextlen = 0; | |
5451 | ||
5452 | dhd_os_sdunlock_rxq(bus->dhd); | |
5453 | } | |
5454 | ||
5455 | /* Ok -- either we just generated a packet chain, or had one from before */ | |
5456 | if (bus->glom) { | |
5457 | if (DHD_GLOM_ON()) { | |
5458 | DHD_GLOM(("%s: attempt superframe read, packet chain:\n", __FUNCTION__)); | |
5459 | for (pnext = bus->glom; pnext; pnext = PKTNEXT(osh, pnext)) { | |
5460 | DHD_GLOM((" %p: %p len 0x%04x (%d)\n", | |
5461 | pnext, (uint8*)PKTDATA(osh, pnext), | |
5462 | PKTLEN(osh, pnext), PKTLEN(osh, pnext))); | |
5463 | } | |
5464 | } | |
5465 | ||
5466 | pfirst = bus->glom; | |
5467 | dlen = (uint16)pkttotlen(osh, pfirst); | |
5468 | ||
5469 | /* Do an SDIO read for the superframe. Configurable iovar to | |
5470 | * read directly into the chained packet, or allocate a large | |
5471 | * packet and and copy into the chain. | |
5472 | */ | |
5473 | if (usechain) { | |
5474 | errcode = dhd_bcmsdh_recv_buf(bus, | |
5475 | bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2, | |
5476 | F2SYNC, (uint8*)PKTDATA(osh, pfirst), | |
5477 | dlen, pfirst, NULL, NULL); | |
5478 | } else if (bus->dataptr) { | |
5479 | errcode = dhd_bcmsdh_recv_buf(bus, | |
5480 | bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2, | |
5481 | F2SYNC, bus->dataptr, | |
5482 | dlen, NULL, NULL, NULL); | |
5483 | sublen = (uint16)pktfrombuf(osh, pfirst, 0, dlen, bus->dataptr); | |
5484 | if (sublen != dlen) { | |
5485 | DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n", | |
5486 | __FUNCTION__, dlen, sublen)); | |
5487 | errcode = -1; | |
5488 | } | |
5489 | pnext = NULL; | |
5490 | BCM_REFERENCE(pnext); | |
5491 | } else { | |
5492 | DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", dlen)); | |
5493 | errcode = -1; | |
5494 | } | |
5495 | bus->f2rxdata++; | |
5496 | ASSERT(errcode != BCME_PENDING); | |
5497 | ||
5498 | /* On failure, kill the superframe, allow a couple retries */ | |
5499 | if (errcode < 0) { | |
5500 | DHD_ERROR(("%s: glom read of %d bytes failed: %d\n", | |
5501 | __FUNCTION__, dlen, errcode)); | |
5502 | bus->dhd->rx_errors++; | |
5503 | ||
5504 | if (bus->glomerr++ < 3) { | |
5505 | dhdsdio_rxfail(bus, TRUE, TRUE); | |
5506 | } else { | |
5507 | bus->glomerr = 0; | |
5508 | dhdsdio_rxfail(bus, TRUE, FALSE); | |
5509 | dhd_os_sdlock_rxq(bus->dhd); | |
5510 | PKTFREE(osh, bus->glom, FALSE); | |
5511 | dhd_os_sdunlock_rxq(bus->dhd); | |
5512 | bus->rxglomfail++; | |
5513 | bus->glom = NULL; | |
5514 | } | |
5515 | return 0; | |
5516 | } | |
5517 | ||
5518 | #ifdef DHD_DEBUG | |
5519 | if (DHD_GLOM_ON()) { | |
5520 | prhex("SUPERFRAME", PKTDATA(osh, pfirst), | |
5521 | MIN(PKTLEN(osh, pfirst), 48)); | |
5522 | } | |
5523 | #endif | |
5524 | ||
5525 | ||
5526 | /* Validate the superframe header */ | |
5527 | dptr = (uint8 *)PKTDATA(osh, pfirst); | |
5528 | sublen = ltoh16_ua(dptr); | |
5529 | check = ltoh16_ua(dptr + sizeof(uint16)); | |
5530 | ||
5531 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
5532 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | |
5533 | bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
5534 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
5535 | DHD_INFO(("%s: got frame w/nextlen too large (%d) seq %d\n", | |
5536 | __FUNCTION__, bus->nextlen, seq)); | |
5537 | bus->nextlen = 0; | |
5538 | } | |
5539 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
5540 | txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
5541 | ||
5542 | errcode = 0; | |
5543 | if ((uint16)~(sublen^check)) { | |
5544 | DHD_ERROR(("%s (superframe): HW hdr error: len/check 0x%04x/0x%04x\n", | |
5545 | __FUNCTION__, sublen, check)); | |
5546 | errcode = -1; | |
5547 | } else if (ROUNDUP(sublen, bus->blocksize) != dlen) { | |
5548 | DHD_ERROR(("%s (superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n", | |
5549 | __FUNCTION__, sublen, ROUNDUP(sublen, bus->blocksize), dlen)); | |
5550 | errcode = -1; | |
5551 | } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != SDPCM_GLOM_CHANNEL) { | |
5552 | DHD_ERROR(("%s (superframe): bad channel %d\n", __FUNCTION__, | |
5553 | SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]))); | |
5554 | errcode = -1; | |
5555 | } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) { | |
5556 | DHD_ERROR(("%s (superframe): got second descriptor?\n", __FUNCTION__)); | |
5557 | errcode = -1; | |
5558 | } else if ((doff < SDPCM_HDRLEN) || | |
5559 | (doff > (PKTLEN(osh, pfirst) - SDPCM_HDRLEN))) { | |
5560 | DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d pkt %d min %d\n", | |
5561 | __FUNCTION__, doff, sublen, PKTLEN(osh, pfirst), | |
5562 | SDPCM_HDRLEN)); | |
5563 | errcode = -1; | |
5564 | } | |
5565 | ||
5566 | /* Check sequence number of superframe SW header */ | |
5567 | if (rxseq != seq) { | |
5568 | DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n", | |
5569 | __FUNCTION__, seq, rxseq)); | |
5570 | bus->rx_badseq++; | |
5571 | rxseq = seq; | |
5572 | } | |
5573 | ||
5574 | /* Check window for sanity */ | |
5575 | if ((uint8)(txmax - bus->tx_seq) > 0x70) { | |
5576 | DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n", | |
5577 | __FUNCTION__, txmax, bus->tx_seq)); | |
5578 | txmax = bus->tx_max; | |
5579 | } | |
5580 | bus->tx_max = txmax; | |
5581 | ||
5582 | /* Remove superframe header, remember offset */ | |
5583 | PKTPULL(osh, pfirst, doff); | |
5584 | sfdoff = doff; | |
5585 | ||
5586 | /* Validate all the subframe headers */ | |
5587 | for (num = 0, pnext = pfirst; pnext && !errcode; | |
5588 | num++, pnext = PKTNEXT(osh, pnext)) { | |
5589 | dptr = (uint8 *)PKTDATA(osh, pnext); | |
5590 | dlen = (uint16)PKTLEN(osh, pnext); | |
5591 | sublen = ltoh16_ua(dptr); | |
5592 | check = ltoh16_ua(dptr + sizeof(uint16)); | |
5593 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
5594 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
5595 | #ifdef DHD_DEBUG | |
5596 | if (DHD_GLOM_ON()) { | |
5597 | prhex("subframe", dptr, 32); | |
5598 | } | |
5599 | #endif | |
5600 | ||
5601 | if ((uint16)~(sublen^check)) { | |
5602 | DHD_ERROR(("%s (subframe %d): HW hdr error: " | |
5603 | "len/check 0x%04x/0x%04x\n", | |
5604 | __FUNCTION__, num, sublen, check)); | |
5605 | errcode = -1; | |
5606 | } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) { | |
5607 | DHD_ERROR(("%s (subframe %d): length mismatch: " | |
5608 | "len 0x%04x, expect 0x%04x\n", | |
5609 | __FUNCTION__, num, sublen, dlen)); | |
5610 | errcode = -1; | |
5611 | } else if ((chan != SDPCM_DATA_CHANNEL) && | |
5612 | (chan != SDPCM_EVENT_CHANNEL)) { | |
5613 | DHD_ERROR(("%s (subframe %d): bad channel %d\n", | |
5614 | __FUNCTION__, num, chan)); | |
5615 | errcode = -1; | |
5616 | } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) { | |
5617 | DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n", | |
5618 | __FUNCTION__, num, doff, sublen, SDPCM_HDRLEN)); | |
5619 | errcode = -1; | |
5620 | } | |
5621 | } | |
5622 | ||
5623 | if (errcode) { | |
5624 | /* Terminate frame on error, request a couple retries */ | |
5625 | if (bus->glomerr++ < 3) { | |
5626 | /* Restore superframe header space */ | |
5627 | PKTPUSH(osh, pfirst, sfdoff); | |
5628 | dhdsdio_rxfail(bus, TRUE, TRUE); | |
5629 | } else { | |
5630 | bus->glomerr = 0; | |
5631 | dhdsdio_rxfail(bus, TRUE, FALSE); | |
5632 | dhd_os_sdlock_rxq(bus->dhd); | |
5633 | PKTFREE(osh, bus->glom, FALSE); | |
5634 | dhd_os_sdunlock_rxq(bus->dhd); | |
5635 | bus->rxglomfail++; | |
5636 | bus->glom = NULL; | |
5637 | } | |
5638 | bus->nextlen = 0; | |
5639 | return 0; | |
5640 | } | |
5641 | ||
5642 | /* Basic SD framing looks ok - process each packet (header) */ | |
5643 | bus->glom = NULL; | |
5644 | plast = NULL; | |
5645 | ||
5646 | dhd_os_sdlock_rxq(bus->dhd); | |
5647 | for (num = 0; pfirst; rxseq++, pfirst = pnext) { | |
5648 | pnext = PKTNEXT(osh, pfirst); | |
5649 | PKTSETNEXT(osh, pfirst, NULL); | |
5650 | ||
5651 | dptr = (uint8 *)PKTDATA(osh, pfirst); | |
5652 | sublen = ltoh16_ua(dptr); | |
5653 | chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]); | |
5654 | seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]); | |
5655 | doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]); | |
5656 | ||
5657 | DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n", | |
5658 | __FUNCTION__, num, pfirst, PKTDATA(osh, pfirst), | |
5659 | PKTLEN(osh, pfirst), sublen, chan, seq)); | |
5660 | ||
5661 | ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL)); | |
5662 | ||
5663 | if (rxseq != seq) { | |
5664 | DHD_GLOM(("%s: rx_seq %d, expected %d\n", | |
5665 | __FUNCTION__, seq, rxseq)); | |
5666 | bus->rx_badseq++; | |
5667 | rxseq = seq; | |
5668 | } | |
5669 | ||
5670 | #ifdef DHD_DEBUG | |
5671 | if (DHD_BYTES_ON() && DHD_DATA_ON()) { | |
5672 | prhex("Rx Subframe Data", dptr, dlen); | |
5673 | } | |
5674 | #endif | |
5675 | ||
5676 | PKTSETLEN(osh, pfirst, sublen); | |
5677 | PKTPULL(osh, pfirst, doff); | |
5678 | ||
5679 | reorder_info_len = sizeof(reorder_info_buf); | |
5680 | ||
5681 | if (PKTLEN(osh, pfirst) == 0) { | |
5682 | PKTFREE(bus->dhd->osh, pfirst, FALSE); | |
5683 | continue; | |
5684 | } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst, reorder_info_buf, | |
5685 | &reorder_info_len) != 0) { | |
5686 | DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__)); | |
5687 | bus->dhd->rx_errors++; | |
5688 | PKTFREE(osh, pfirst, FALSE); | |
5689 | continue; | |
5690 | } | |
5691 | if (reorder_info_len) { | |
5692 | uint32 free_buf_count; | |
5693 | void *ppfirst; | |
5694 | ||
5695 | ppfirst = pfirst; | |
5696 | /* Reordering info from the firmware */ | |
5697 | dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf, | |
5698 | reorder_info_len, &ppfirst, &free_buf_count); | |
5699 | ||
5700 | if (free_buf_count == 0) { | |
5701 | continue; | |
5702 | } else { | |
5703 | void *temp; | |
5704 | ||
5705 | /* go to the end of the chain and attach the pnext there */ | |
5706 | temp = ppfirst; | |
5707 | while (PKTNEXT(osh, temp) != NULL) { | |
5708 | temp = PKTNEXT(osh, temp); | |
5709 | } | |
5710 | pfirst = temp; | |
5711 | if (list_tail[ifidx] == NULL) | |
5712 | list_head[ifidx] = ppfirst; | |
5713 | else | |
5714 | PKTSETNEXT(osh, list_tail[ifidx], ppfirst); | |
5715 | list_tail[ifidx] = pfirst; | |
5716 | } | |
5717 | ||
5718 | num += (uint8)free_buf_count; | |
5719 | } else { | |
5720 | /* this packet will go up, link back into chain and count it */ | |
5721 | ||
5722 | if (list_tail[ifidx] == NULL) { | |
5723 | list_head[ifidx] = list_tail[ifidx] = pfirst; | |
5724 | } else { | |
5725 | PKTSETNEXT(osh, list_tail[ifidx], pfirst); | |
5726 | list_tail[ifidx] = pfirst; | |
5727 | } | |
5728 | num++; | |
5729 | } | |
5730 | #ifdef DHD_DEBUG | |
5731 | if (DHD_GLOM_ON()) { | |
5732 | DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) nxt/lnk %p/%p\n", | |
5733 | __FUNCTION__, num, pfirst, | |
5734 | PKTDATA(osh, pfirst), PKTLEN(osh, pfirst), | |
5735 | PKTNEXT(osh, pfirst), PKTLINK(pfirst))); | |
5736 | prhex("", (uint8 *)PKTDATA(osh, pfirst), | |
5737 | MIN(PKTLEN(osh, pfirst), 32)); | |
5738 | } | |
5739 | #endif /* DHD_DEBUG */ | |
5740 | } | |
5741 | dhd_os_sdunlock_rxq(bus->dhd); | |
5742 | ||
5743 | for (idx = 0; idx < DHD_MAX_IFS; idx++) { | |
5744 | if (list_head[idx]) { | |
5745 | void *temp; | |
5746 | uint8 cnt = 0; | |
5747 | temp = list_head[idx]; | |
5748 | do { | |
5749 | temp = PKTNEXT(osh, temp); | |
5750 | cnt++; | |
5751 | } while (temp); | |
5752 | if (cnt) { | |
5753 | dhd_os_sdunlock(bus->dhd); | |
5754 | dhd_rx_frame(bus->dhd, idx, list_head[idx], cnt, 0); | |
5755 | dhd_os_sdlock(bus->dhd); | |
5756 | #if defined(SDIO_ISR_THREAD) | |
5757 | /* terence 20150615: fix for below error due to bussleep in watchdog after dhd_os_sdunlock here, | |
5758 | * so call BUS_WAKE to wake up bus again | |
5759 | * dhd_bcmsdh_recv_buf: Device asleep | |
5760 | * dhdsdio_readframes: RXHEADER FAILED: -40 | |
5761 | * dhdsdio_rxfail: abort command, terminate frame, send NAK | |
5762 | */ | |
5763 | BUS_WAKE(bus); | |
5764 | #endif | |
5765 | } | |
5766 | } | |
5767 | } | |
5768 | bus->rxglomframes++; | |
5769 | bus->rxglompkts += num; | |
5770 | } | |
5771 | return num; | |
5772 | } | |
5773 | ||
5774 | ||
5775 | /* Return TRUE if there may be more frames to read */ | |
5776 | static uint | |
5777 | dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) | |
5778 | { | |
5779 | osl_t *osh = bus->dhd->osh; | |
5780 | bcmsdh_info_t *sdh = bus->sdh; | |
5781 | ||
5782 | uint16 len, check; /* Extracted hardware header fields */ | |
5783 | uint8 chan, seq, doff; /* Extracted software header fields */ | |
5784 | uint8 fcbits; /* Extracted fcbits from software header */ | |
5785 | uint8 delta; | |
5786 | ||
5787 | void *pkt; /* Packet for event or data frames */ | |
5788 | uint16 pad; /* Number of pad bytes to read */ | |
5789 | uint16 rdlen; /* Total number of bytes to read */ | |
5790 | uint8 rxseq; /* Next sequence number to expect */ | |
5791 | uint rxleft = 0; /* Remaining number of frames allowed */ | |
5792 | int sdret; /* Return code from bcmsdh calls */ | |
5793 | uint8 txmax; /* Maximum tx sequence offered */ | |
5794 | bool len_consistent; /* Result of comparing readahead len and len from hw-hdr */ | |
5795 | uint8 *rxbuf; | |
5796 | int ifidx = 0; | |
5797 | uint rxcount = 0; /* Total frames read */ | |
5798 | uchar reorder_info_buf[WLHOST_REORDERDATA_TOTLEN]; | |
5799 | uint reorder_info_len; | |
5800 | uint pkt_count; | |
5801 | ||
5802 | #if defined(DHD_DEBUG) || defined(SDTEST) | |
5803 | bool sdtest = FALSE; /* To limit message spew from test mode */ | |
5804 | #endif | |
5805 | ||
5806 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
5807 | bus->readframes = TRUE; | |
5808 | ||
5809 | if (!KSO_ENAB(bus)) { | |
5810 | DHD_ERROR(("%s: KSO off\n", __FUNCTION__)); | |
5811 | bus->readframes = FALSE; | |
5812 | return 0; | |
5813 | } | |
5814 | ||
5815 | ASSERT(maxframes); | |
5816 | ||
5817 | #ifdef SDTEST | |
5818 | /* Allow pktgen to override maxframes */ | |
5819 | if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) { | |
5820 | maxframes = bus->pktgen_count; | |
5821 | sdtest = TRUE; | |
5822 | } | |
5823 | #endif | |
5824 | ||
5825 | /* Not finished unless we encounter no more frames indication */ | |
5826 | *finished = FALSE; | |
5827 | ||
5828 | ||
5829 | for (rxseq = bus->rx_seq, rxleft = maxframes; | |
5830 | !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN; | |
5831 | rxseq++, rxleft--) { | |
5832 | #ifdef DHDTCPACK_SUP_DBG | |
5833 | if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_DELAYTX) { | |
5834 | if (bus->dotxinrx == FALSE) | |
5835 | DHD_ERROR(("%s %d: dotxinrx FALSE with tcpack_sub_mode %d\n", | |
5836 | __FUNCTION__, __LINE__, bus->dhd->tcpack_sup_mode)); | |
5837 | } | |
5838 | #ifdef DEBUG_COUNTER | |
5839 | else if (pktq_mlen(&bus->txq, ~bus->flowcontrol) > 0) { | |
5840 | tack_tbl.cnt[bus->dotxinrx ? 6 : 7]++; | |
5841 | } | |
5842 | #endif /* DEBUG_COUNTER */ | |
5843 | #endif /* DHDTCPACK_SUP_DBG */ | |
5844 | /* tx more to improve rx performance */ | |
5845 | if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) { | |
5846 | dhdsdio_sendpendctl(bus); | |
5847 | } else if (bus->dotxinrx && (bus->clkstate == CLK_AVAIL) && | |
5848 | !bus->fcstate && DATAOK(bus) && | |
d964ce36 | 5849 | (pktq_mlen(&bus->txq, ~bus->flowcontrol) > bus->txinrx_thres)) { |
010c3a89 RC |
5850 | dhdsdio_sendfromq(bus, dhd_txbound); |
5851 | #ifdef DHDTCPACK_SUPPRESS | |
5852 | /* In TCPACK_SUP_DELAYTX mode, do txinrx only if | |
5853 | * 1. Any DATA packet to TX | |
5854 | * 2. TCPACK to TCPDATA PSH packets. | |
5855 | * in bus txq. | |
5856 | */ | |
5857 | bus->dotxinrx = (bus->dhd->tcpack_sup_mode == TCPACK_SUP_DELAYTX) ? | |
5858 | FALSE : TRUE; | |
5859 | #endif | |
5860 | } | |
5861 | ||
5862 | /* Handle glomming separately */ | |
5863 | if (bus->glom || bus->glomd) { | |
5864 | uint8 cnt; | |
5865 | DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n", | |
5866 | __FUNCTION__, bus->glomd, bus->glom)); | |
5867 | cnt = dhdsdio_rxglom(bus, rxseq); | |
5868 | DHD_GLOM(("%s: rxglom returned %d\n", __FUNCTION__, cnt)); | |
5869 | rxseq += cnt - 1; | |
5870 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; | |
5871 | continue; | |
5872 | } | |
5873 | ||
5874 | /* Try doing single read if we can */ | |
5875 | if (dhd_readahead && bus->nextlen) { | |
5876 | uint16 nextlen = bus->nextlen; | |
5877 | bus->nextlen = 0; | |
5878 | ||
5879 | if (bus->bus == SPI_BUS) { | |
5880 | rdlen = len = nextlen; | |
5881 | } else { | |
5882 | rdlen = len = nextlen << 4; | |
5883 | ||
5884 | /* Pad read to blocksize for efficiency */ | |
5885 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
5886 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
5887 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
5888 | ((rdlen + pad + firstread) < MAX_RX_DATASZ)) | |
5889 | rdlen += pad; | |
5890 | } else if (rdlen % DHD_SDALIGN) { | |
5891 | rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN); | |
5892 | } | |
5893 | } | |
5894 | ||
5895 | /* We use bus->rxctl buffer in WinXP for initial control pkt receives. | |
5896 | * Later we use buffer-poll for data as well as control packets. | |
5897 | * This is required because dhd receives full frame in gSPI unlike SDIO. | |
5898 | * After the frame is received we have to distinguish whether it is data | |
5899 | * or non-data frame. | |
5900 | */ | |
5901 | /* Allocate a packet buffer */ | |
5902 | dhd_os_sdlock_rxq(bus->dhd); | |
5903 | if (!(pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE))) { | |
5904 | if (bus->bus == SPI_BUS) { | |
5905 | bus->usebufpool = FALSE; | |
5906 | bus->rxctl = bus->rxbuf; | |
5907 | if (dhd_alignctl) { | |
5908 | bus->rxctl += firstread; | |
5909 | if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN))) | |
5910 | bus->rxctl += (DHD_SDALIGN - pad); | |
5911 | bus->rxctl -= firstread; | |
5912 | } | |
5913 | ASSERT(bus->rxctl >= bus->rxbuf); | |
5914 | rxbuf = bus->rxctl; | |
5915 | /* Read the entire frame */ | |
5916 | sdret = dhd_bcmsdh_recv_buf(bus, | |
5917 | bcmsdh_cur_sbwad(sdh), | |
5918 | SDIO_FUNC_2, | |
5919 | F2SYNC, rxbuf, rdlen, | |
5920 | NULL, NULL, NULL); | |
5921 | bus->f2rxdata++; | |
5922 | ASSERT(sdret != BCME_PENDING); | |
5923 | ||
5924 | ||
5925 | /* Control frame failures need retransmission */ | |
5926 | if (sdret < 0) { | |
5927 | DHD_ERROR(("%s: read %d control bytes failed: %d\n", | |
5928 | __FUNCTION__, rdlen, sdret)); | |
5929 | /* dhd.rx_ctlerrs is higher level */ | |
5930 | bus->rxc_errors++; | |
5931 | dhd_os_sdunlock_rxq(bus->dhd); | |
5932 | dhdsdio_rxfail(bus, TRUE, | |
5933 | (bus->bus == SPI_BUS) ? FALSE : TRUE); | |
5934 | continue; | |
5935 | } | |
5936 | } else { | |
5937 | /* Give up on data, request rtx of events */ | |
5938 | DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d " | |
5939 | "expected rxseq %d\n", | |
5940 | __FUNCTION__, len, rdlen, rxseq)); | |
5941 | /* Just go try again w/normal header read */ | |
5942 | dhd_os_sdunlock_rxq(bus->dhd); | |
5943 | continue; | |
5944 | } | |
5945 | } else { | |
5946 | if (bus->bus == SPI_BUS) | |
5947 | bus->usebufpool = TRUE; | |
5948 | ||
5949 | ASSERT(!PKTLINK(pkt)); | |
5950 | PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN); | |
5951 | rxbuf = (uint8 *)PKTDATA(osh, pkt); | |
5952 | /* Read the entire frame */ | |
5953 | sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), | |
5954 | SDIO_FUNC_2, | |
5955 | F2SYNC, rxbuf, rdlen, | |
5956 | pkt, NULL, NULL); | |
5957 | bus->f2rxdata++; | |
5958 | ASSERT(sdret != BCME_PENDING); | |
5959 | ||
5960 | if (sdret < 0) { | |
5961 | DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n", | |
5962 | __FUNCTION__, rdlen, sdret)); | |
5963 | PKTFREE(bus->dhd->osh, pkt, FALSE); | |
5964 | bus->dhd->rx_errors++; | |
5965 | dhd_os_sdunlock_rxq(bus->dhd); | |
5966 | /* Force retry w/normal header read. Don't attempt NAK for | |
5967 | * gSPI | |
5968 | */ | |
5969 | dhdsdio_rxfail(bus, TRUE, | |
5970 | (bus->bus == SPI_BUS) ? FALSE : TRUE); | |
5971 | continue; | |
5972 | } | |
5973 | } | |
5974 | dhd_os_sdunlock_rxq(bus->dhd); | |
5975 | ||
5976 | /* Now check the header */ | |
5977 | bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN); | |
5978 | ||
5979 | /* Extract hardware header fields */ | |
5980 | len = ltoh16_ua(bus->rxhdr); | |
5981 | check = ltoh16_ua(bus->rxhdr + sizeof(uint16)); | |
5982 | ||
5983 | /* All zeros means readahead info was bad */ | |
5984 | if (!(len|check)) { | |
5985 | DHD_INFO(("%s (nextlen): read zeros in HW header???\n", | |
5986 | __FUNCTION__)); | |
5987 | dhd_os_sdlock_rxq(bus->dhd); | |
5988 | PKTFREE2(); | |
5989 | dhd_os_sdunlock_rxq(bus->dhd); | |
5990 | GSPI_PR55150_BAILOUT; | |
5991 | continue; | |
5992 | } | |
5993 | ||
5994 | /* Validate check bytes */ | |
5995 | if ((uint16)~(len^check)) { | |
5996 | DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" | |
5997 | " 0x%04x/0x%04x/0x%04x\n", __FUNCTION__, nextlen, | |
5998 | len, check)); | |
5999 | dhd_os_sdlock_rxq(bus->dhd); | |
6000 | PKTFREE2(); | |
6001 | dhd_os_sdunlock_rxq(bus->dhd); | |
6002 | bus->rx_badhdr++; | |
6003 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
6004 | GSPI_PR55150_BAILOUT; | |
6005 | continue; | |
6006 | } | |
6007 | ||
6008 | /* Validate frame length */ | |
6009 | if (len < SDPCM_HDRLEN) { | |
6010 | DHD_ERROR(("%s (nextlen): HW hdr length invalid: %d\n", | |
6011 | __FUNCTION__, len)); | |
6012 | dhd_os_sdlock_rxq(bus->dhd); | |
6013 | PKTFREE2(); | |
6014 | dhd_os_sdunlock_rxq(bus->dhd); | |
6015 | GSPI_PR55150_BAILOUT; | |
6016 | continue; | |
6017 | } | |
6018 | ||
6019 | /* Check for consistency with readahead info */ | |
6020 | len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4)); | |
6021 | if (len_consistent) { | |
6022 | /* Mismatch, force retry w/normal header (may be >4K) */ | |
6023 | DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " | |
6024 | "expected rxseq %d\n", | |
6025 | __FUNCTION__, nextlen, len, ROUNDUP(len, 16), rxseq)); | |
6026 | dhd_os_sdlock_rxq(bus->dhd); | |
6027 | PKTFREE2(); | |
6028 | dhd_os_sdunlock_rxq(bus->dhd); | |
6029 | dhdsdio_rxfail(bus, TRUE, (bus->bus == SPI_BUS) ? FALSE : TRUE); | |
6030 | GSPI_PR55150_BAILOUT; | |
6031 | continue; | |
6032 | } | |
6033 | ||
6034 | ||
6035 | /* Extract software header fields */ | |
6036 | chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6037 | seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6038 | doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6039 | txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6040 | ||
6041 | bus->nextlen = | |
6042 | bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
6043 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
6044 | DHD_INFO(("%s (nextlen): got frame w/nextlen too large" | |
6045 | " (%d), seq %d\n", __FUNCTION__, bus->nextlen, | |
6046 | seq)); | |
6047 | bus->nextlen = 0; | |
6048 | } | |
6049 | ||
6050 | bus->dhd->rx_readahead_cnt ++; | |
6051 | /* Handle Flow Control */ | |
6052 | fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6053 | ||
6054 | delta = 0; | |
6055 | if (~bus->flowcontrol & fcbits) { | |
6056 | bus->fc_xoff++; | |
6057 | delta = 1; | |
6058 | } | |
6059 | if (bus->flowcontrol & ~fcbits) { | |
6060 | bus->fc_xon++; | |
6061 | delta = 1; | |
6062 | } | |
6063 | ||
6064 | if (delta) { | |
6065 | bus->fc_rcvd++; | |
6066 | bus->flowcontrol = fcbits; | |
6067 | } | |
6068 | ||
6069 | /* Check and update sequence number */ | |
6070 | if (rxseq != seq) { | |
6071 | DHD_INFO(("%s (nextlen): rx_seq %d, expected %d\n", | |
6072 | __FUNCTION__, seq, rxseq)); | |
6073 | bus->rx_badseq++; | |
6074 | rxseq = seq; | |
6075 | } | |
6076 | ||
6077 | /* Check window for sanity */ | |
6078 | if ((uint8)(txmax - bus->tx_seq) > 0x70) { | |
6079 | DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n", | |
6080 | __FUNCTION__, txmax, bus->tx_seq)); | |
6081 | txmax = bus->tx_max; | |
6082 | } | |
6083 | bus->tx_max = txmax; | |
6084 | ||
6085 | #ifdef DHD_DEBUG | |
6086 | if (DHD_BYTES_ON() && DHD_DATA_ON()) { | |
6087 | prhex("Rx Data", rxbuf, len); | |
6088 | } else if (DHD_HDRS_ON()) { | |
6089 | prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN); | |
6090 | } | |
6091 | #endif | |
6092 | ||
6093 | if (chan == SDPCM_CONTROL_CHANNEL) { | |
6094 | if (bus->bus == SPI_BUS) { | |
6095 | dhdsdio_read_control(bus, rxbuf, len, doff); | |
6096 | if (bus->usebufpool) { | |
6097 | dhd_os_sdlock_rxq(bus->dhd); | |
6098 | PKTFREE(bus->dhd->osh, pkt, FALSE); | |
6099 | dhd_os_sdunlock_rxq(bus->dhd); | |
6100 | } | |
6101 | continue; | |
6102 | } else { | |
6103 | DHD_ERROR(("%s (nextlen): readahead on control" | |
6104 | " packet %d?\n", __FUNCTION__, seq)); | |
6105 | /* Force retry w/normal header read */ | |
6106 | bus->nextlen = 0; | |
6107 | dhdsdio_rxfail(bus, FALSE, TRUE); | |
6108 | dhd_os_sdlock_rxq(bus->dhd); | |
6109 | PKTFREE2(); | |
6110 | dhd_os_sdunlock_rxq(bus->dhd); | |
6111 | continue; | |
6112 | } | |
6113 | } | |
6114 | ||
6115 | if ((bus->bus == SPI_BUS) && !bus->usebufpool) { | |
6116 | DHD_ERROR(("Received %d bytes on %d channel. Running out of " | |
6117 | "rx pktbuf's or not yet malloced.\n", len, chan)); | |
6118 | continue; | |
6119 | } | |
6120 | ||
6121 | /* Validate data offset */ | |
6122 | if ((doff < SDPCM_HDRLEN) || (doff > len)) { | |
6123 | DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n", | |
6124 | __FUNCTION__, doff, len, SDPCM_HDRLEN)); | |
6125 | dhd_os_sdlock_rxq(bus->dhd); | |
6126 | PKTFREE2(); | |
6127 | dhd_os_sdunlock_rxq(bus->dhd); | |
6128 | ASSERT(0); | |
6129 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
6130 | continue; | |
6131 | } | |
6132 | ||
6133 | /* All done with this one -- now deliver the packet */ | |
6134 | goto deliver; | |
6135 | } | |
6136 | /* gSPI frames should not be handled in fractions */ | |
6137 | if (bus->bus == SPI_BUS) { | |
6138 | break; | |
6139 | } | |
6140 | ||
6141 | /* Read frame header (hardware and software) */ | |
6142 | sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC, | |
6143 | bus->rxhdr, firstread, NULL, NULL, NULL); | |
6144 | bus->f2rxhdrs++; | |
6145 | ASSERT(sdret != BCME_PENDING); | |
6146 | ||
6147 | if (sdret < 0) { | |
6148 | DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __FUNCTION__, sdret)); | |
6149 | bus->rx_hdrfail++; | |
6150 | dhdsdio_rxfail(bus, TRUE, TRUE); | |
6151 | continue; | |
6152 | } | |
6153 | ||
6154 | #ifdef DHD_DEBUG | |
6155 | if (DHD_BYTES_ON() || DHD_HDRS_ON()) { | |
6156 | prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN); | |
6157 | } | |
6158 | #endif | |
6159 | ||
6160 | /* Extract hardware header fields */ | |
6161 | len = ltoh16_ua(bus->rxhdr); | |
6162 | check = ltoh16_ua(bus->rxhdr + sizeof(uint16)); | |
6163 | ||
6164 | /* All zeros means no more frames */ | |
6165 | if (!(len|check)) { | |
6166 | *finished = TRUE; | |
6167 | break; | |
6168 | } | |
6169 | ||
6170 | /* Validate check bytes */ | |
6171 | if ((uint16)~(len^check)) { | |
6172 | DHD_ERROR(("%s: HW hdr error: len/check 0x%04x/0x%04x\n", | |
6173 | __FUNCTION__, len, check)); | |
6174 | bus->rx_badhdr++; | |
6175 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
6176 | continue; | |
6177 | } | |
6178 | ||
6179 | /* Validate frame length */ | |
6180 | if (len < SDPCM_HDRLEN) { | |
6181 | DHD_ERROR(("%s: HW hdr length invalid: %d\n", __FUNCTION__, len)); | |
6182 | continue; | |
6183 | } | |
6184 | ||
6185 | /* Extract software header fields */ | |
6186 | chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6187 | seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6188 | doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6189 | txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6190 | ||
6191 | /* Validate data offset */ | |
6192 | if ((doff < SDPCM_HDRLEN) || (doff > len)) { | |
6193 | DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d seq %d\n", | |
6194 | __FUNCTION__, doff, len, SDPCM_HDRLEN, seq)); | |
6195 | bus->rx_badhdr++; | |
6196 | ASSERT(0); | |
6197 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
6198 | continue; | |
6199 | } | |
6200 | ||
6201 | /* Save the readahead length if there is one */ | |
6202 | bus->nextlen = bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET]; | |
6203 | if ((bus->nextlen << 4) > MAX_RX_DATASZ) { | |
6204 | DHD_INFO(("%s (nextlen): got frame w/nextlen too large (%d), seq %d\n", | |
6205 | __FUNCTION__, bus->nextlen, seq)); | |
6206 | bus->nextlen = 0; | |
6207 | } | |
6208 | ||
6209 | /* Handle Flow Control */ | |
6210 | fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]); | |
6211 | ||
6212 | delta = 0; | |
6213 | if (~bus->flowcontrol & fcbits) { | |
6214 | bus->fc_xoff++; | |
6215 | delta = 1; | |
6216 | } | |
6217 | if (bus->flowcontrol & ~fcbits) { | |
6218 | bus->fc_xon++; | |
6219 | delta = 1; | |
6220 | } | |
6221 | ||
6222 | if (delta) { | |
6223 | bus->fc_rcvd++; | |
6224 | bus->flowcontrol = fcbits; | |
6225 | } | |
6226 | ||
6227 | /* Check and update sequence number */ | |
6228 | if (rxseq != seq) { | |
6229 | DHD_INFO(("%s: rx_seq %d, expected %d\n", __FUNCTION__, seq, rxseq)); | |
6230 | bus->rx_badseq++; | |
6231 | rxseq = seq; | |
6232 | } | |
6233 | ||
6234 | /* Check window for sanity */ | |
6235 | if ((uint8)(txmax - bus->tx_seq) > 0x70) { | |
6236 | DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n", | |
6237 | __FUNCTION__, txmax, bus->tx_seq)); | |
6238 | txmax = bus->tx_max; | |
6239 | } | |
6240 | bus->tx_max = txmax; | |
6241 | ||
6242 | /* Call a separate function for control frames */ | |
6243 | if (chan == SDPCM_CONTROL_CHANNEL) { | |
6244 | dhdsdio_read_control(bus, bus->rxhdr, len, doff); | |
6245 | continue; | |
6246 | } | |
6247 | ||
6248 | ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL) || | |
6249 | (chan == SDPCM_TEST_CHANNEL) || (chan == SDPCM_GLOM_CHANNEL)); | |
6250 | ||
6251 | /* Length to read */ | |
6252 | rdlen = (len > firstread) ? (len - firstread) : 0; | |
6253 | ||
6254 | /* May pad read to blocksize for efficiency */ | |
6255 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
6256 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
6257 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
6258 | ((rdlen + pad + firstread) < MAX_RX_DATASZ)) | |
6259 | rdlen += pad; | |
6260 | } else if (rdlen % DHD_SDALIGN) { | |
6261 | rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN); | |
6262 | } | |
6263 | ||
6264 | /* Satisfy length-alignment requirements */ | |
6265 | if (forcealign && (rdlen & (ALIGNMENT - 1))) | |
6266 | rdlen = ROUNDUP(rdlen, ALIGNMENT); | |
6267 | ||
6268 | if ((rdlen + firstread) > MAX_RX_DATASZ) { | |
6269 | /* Too long -- skip this frame */ | |
6270 | DHD_ERROR(("%s: too long: len %d rdlen %d\n", __FUNCTION__, len, rdlen)); | |
6271 | bus->dhd->rx_errors++; bus->rx_toolong++; | |
6272 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
6273 | continue; | |
6274 | } | |
6275 | ||
6276 | dhd_os_sdlock_rxq(bus->dhd); | |
6277 | if (!(pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE))) { | |
6278 | /* Give up on data, request rtx of events */ | |
6279 | DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n", | |
6280 | __FUNCTION__, rdlen, chan)); | |
6281 | bus->dhd->rx_dropped++; | |
6282 | dhd_os_sdunlock_rxq(bus->dhd); | |
6283 | dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan)); | |
6284 | continue; | |
6285 | } | |
6286 | dhd_os_sdunlock_rxq(bus->dhd); | |
6287 | ||
6288 | ASSERT(!PKTLINK(pkt)); | |
6289 | ||
6290 | /* Leave room for what we already read, and align remainder */ | |
6291 | ASSERT(firstread < (PKTLEN(osh, pkt))); | |
6292 | PKTPULL(osh, pkt, firstread); | |
6293 | PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN); | |
6294 | ||
6295 | /* Read the remaining frame data */ | |
6296 | sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC, | |
6297 | ((uint8 *)PKTDATA(osh, pkt)), rdlen, pkt, NULL, NULL); | |
6298 | bus->f2rxdata++; | |
6299 | ASSERT(sdret != BCME_PENDING); | |
6300 | ||
6301 | if (sdret < 0) { | |
6302 | DHD_ERROR(("%s: read %d %s bytes failed: %d\n", __FUNCTION__, rdlen, | |
6303 | ((chan == SDPCM_EVENT_CHANNEL) ? "event" : | |
6304 | ((chan == SDPCM_DATA_CHANNEL) ? "data" : "test")), sdret)); | |
6305 | dhd_os_sdlock_rxq(bus->dhd); | |
6306 | PKTFREE(bus->dhd->osh, pkt, FALSE); | |
6307 | dhd_os_sdunlock_rxq(bus->dhd); | |
6308 | bus->dhd->rx_errors++; | |
6309 | dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan)); | |
6310 | continue; | |
6311 | } | |
6312 | ||
6313 | /* Copy the already-read portion */ | |
6314 | PKTPUSH(osh, pkt, firstread); | |
6315 | bcopy(bus->rxhdr, PKTDATA(osh, pkt), firstread); | |
6316 | ||
6317 | #ifdef DHD_DEBUG | |
6318 | if (DHD_BYTES_ON() && DHD_DATA_ON()) { | |
6319 | prhex("Rx Data", PKTDATA(osh, pkt), len); | |
6320 | } | |
6321 | #endif | |
6322 | ||
6323 | deliver: | |
6324 | /* Save superframe descriptor and allocate packet frame */ | |
6325 | if (chan == SDPCM_GLOM_CHANNEL) { | |
6326 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) { | |
6327 | DHD_GLOM(("%s: got glom descriptor, %d bytes:\n", | |
6328 | __FUNCTION__, len)); | |
6329 | #ifdef DHD_DEBUG | |
6330 | if (DHD_GLOM_ON()) { | |
6331 | prhex("Glom Data", PKTDATA(osh, pkt), len); | |
6332 | } | |
6333 | #endif | |
6334 | PKTSETLEN(osh, pkt, len); | |
6335 | ASSERT(doff == SDPCM_HDRLEN); | |
6336 | PKTPULL(osh, pkt, SDPCM_HDRLEN); | |
6337 | bus->glomd = pkt; | |
6338 | } else { | |
6339 | DHD_ERROR(("%s: glom superframe w/o descriptor!\n", __FUNCTION__)); | |
6340 | dhdsdio_rxfail(bus, FALSE, FALSE); | |
6341 | } | |
6342 | continue; | |
6343 | } | |
6344 | ||
6345 | /* Fill in packet len and prio, deliver upward */ | |
6346 | PKTSETLEN(osh, pkt, len); | |
6347 | PKTPULL(osh, pkt, doff); | |
6348 | ||
6349 | #ifdef SDTEST | |
6350 | /* Test channel packets are processed separately */ | |
6351 | if (chan == SDPCM_TEST_CHANNEL) { | |
6352 | dhdsdio_testrcv(bus, pkt, seq); | |
6353 | continue; | |
6354 | } | |
6355 | #endif /* SDTEST */ | |
6356 | ||
6357 | if (PKTLEN(osh, pkt) == 0) { | |
6358 | dhd_os_sdlock_rxq(bus->dhd); | |
6359 | PKTFREE(bus->dhd->osh, pkt, FALSE); | |
6360 | dhd_os_sdunlock_rxq(bus->dhd); | |
6361 | continue; | |
6362 | } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt, reorder_info_buf, | |
6363 | &reorder_info_len) != 0) { | |
6364 | DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__)); | |
6365 | dhd_os_sdlock_rxq(bus->dhd); | |
6366 | PKTFREE(bus->dhd->osh, pkt, FALSE); | |
6367 | dhd_os_sdunlock_rxq(bus->dhd); | |
6368 | bus->dhd->rx_errors++; | |
6369 | continue; | |
6370 | } | |
6371 | ||
6372 | if (reorder_info_len) { | |
6373 | /* Reordering info from the firmware */ | |
6374 | dhd_process_pkt_reorder_info(bus->dhd, reorder_info_buf, reorder_info_len, | |
6375 | &pkt, &pkt_count); | |
6376 | if (pkt_count == 0) | |
6377 | continue; | |
6378 | } else { | |
6379 | pkt_count = 1; | |
6380 | } | |
6381 | ||
6382 | /* Unlock during rx call */ | |
6383 | dhd_os_sdunlock(bus->dhd); | |
6384 | dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, chan); | |
6385 | dhd_os_sdlock(bus->dhd); | |
6386 | #if defined(SDIO_ISR_THREAD) | |
6387 | /* terence 20150615: fix for below error due to bussleep in watchdog after dhd_os_sdunlock here, | |
6388 | * so call BUS_WAKE to wake up bus again | |
6389 | * dhd_bcmsdh_recv_buf: Device asleep | |
6390 | * dhdsdio_readframes: RXHEADER FAILED: -40 | |
6391 | * dhdsdio_rxfail: abort command, terminate frame, send NAK | |
6392 | */ | |
6393 | BUS_WAKE(bus); | |
6394 | #endif | |
6395 | } | |
6396 | rxcount = maxframes - rxleft; | |
6397 | #ifdef DHD_DEBUG | |
6398 | /* Message if we hit the limit */ | |
6399 | if (!rxleft && !sdtest) | |
6400 | DHD_DATA(("%s: hit rx limit of %d frames\n", __FUNCTION__, maxframes)); | |
6401 | else | |
6402 | #endif /* DHD_DEBUG */ | |
6403 | DHD_DATA(("%s: processed %d frames\n", __FUNCTION__, rxcount)); | |
6404 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
6405 | if (bus->rxskip) | |
6406 | rxseq--; | |
6407 | bus->rx_seq = rxseq; | |
6408 | ||
6409 | if (bus->reqbussleep) | |
6410 | { | |
6411 | dhdsdio_bussleep(bus, TRUE); | |
6412 | bus->reqbussleep = FALSE; | |
6413 | } | |
6414 | bus->readframes = FALSE; | |
6415 | ||
6416 | return rxcount; | |
6417 | } | |
6418 | ||
6419 | static uint32 | |
6420 | dhdsdio_hostmail(dhd_bus_t *bus, uint32 *hmbd) | |
6421 | { | |
6422 | sdpcmd_regs_t *regs = bus->regs; | |
6423 | uint32 intstatus = 0; | |
6424 | uint32 hmb_data; | |
6425 | uint8 fcbits; | |
6426 | uint retries = 0; | |
6427 | ||
6428 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
6429 | ||
6430 | /* Read mailbox data and ack that we did so */ | |
6431 | R_SDREG(hmb_data, ®s->tohostmailboxdata, retries); | |
6432 | if (retries <= retry_limit) | |
6433 | W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries); | |
6434 | bus->f1regdata += 2; | |
6435 | ||
6436 | /* Dongle recomposed rx frames, accept them again */ | |
6437 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
6438 | DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n", bus->rx_seq)); | |
6439 | if (!bus->rxskip) { | |
6440 | DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __FUNCTION__)); | |
6441 | } | |
6442 | bus->rxskip = FALSE; | |
6443 | intstatus |= FRAME_AVAIL_MASK(bus); | |
6444 | } | |
6445 | ||
6446 | /* | |
6447 | * DEVREADY does not occur with gSPI. | |
6448 | */ | |
6449 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
6450 | bus->sdpcm_ver = (hmb_data & HMB_DATA_VERSION_MASK) >> HMB_DATA_VERSION_SHIFT; | |
6451 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
6452 | DHD_ERROR(("Version mismatch, dongle reports %d, expecting %d\n", | |
6453 | bus->sdpcm_ver, SDPCM_PROT_VERSION)); | |
6454 | else | |
6455 | DHD_INFO(("Dongle ready, protocol version %d\n", bus->sdpcm_ver)); | |
6456 | /* make sure for the SDIO_DEVICE_RXDATAINT_MODE_1 corecontrol is proper */ | |
6457 | if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) && | |
6458 | (bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_1)) { | |
6459 | uint32 val; | |
6460 | ||
6461 | val = R_REG(bus->dhd->osh, &bus->regs->corecontrol); | |
6462 | val &= ~CC_XMTDATAAVAIL_MODE; | |
6463 | val |= CC_XMTDATAAVAIL_CTRL; | |
6464 | W_REG(bus->dhd->osh, &bus->regs->corecontrol, val); | |
6465 | ||
6466 | val = R_REG(bus->dhd->osh, &bus->regs->corecontrol); | |
6467 | } | |
6468 | ||
6469 | #ifdef DHD_DEBUG | |
6470 | /* Retrieve console state address now that firmware should have updated it */ | |
6471 | { | |
6472 | sdpcm_shared_t shared; | |
6473 | if (dhdsdio_readshared(bus, &shared) == 0) | |
6474 | bus->console_addr = shared.console_addr; | |
6475 | } | |
6476 | #endif /* DHD_DEBUG */ | |
6477 | } | |
6478 | ||
6479 | /* | |
6480 | * Flow Control has been moved into the RX headers and this out of band | |
6481 | * method isn't used any more. Leave this here for possibly remaining backward | |
6482 | * compatible with older dongles | |
6483 | */ | |
6484 | if (hmb_data & HMB_DATA_FC) { | |
6485 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT; | |
6486 | ||
6487 | if (fcbits & ~bus->flowcontrol) | |
6488 | bus->fc_xoff++; | |
6489 | if (bus->flowcontrol & ~fcbits) | |
6490 | bus->fc_xon++; | |
6491 | ||
6492 | bus->fc_rcvd++; | |
6493 | bus->flowcontrol = fcbits; | |
6494 | } | |
6495 | ||
6496 | /* At least print a message if FW halted */ | |
6497 | if (hmb_data & HMB_DATA_FWHALT) { | |
6498 | DHD_ERROR(("INTERNAL ERROR: FIRMWARE HALTED : set BUS DOWN\n")); | |
6499 | dhdsdio_checkdied(bus, NULL, 0); | |
6500 | bus->dhd->busstate = DHD_BUS_DOWN; | |
6501 | } | |
6502 | ||
6503 | /* Shouldn't be any others */ | |
6504 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
6505 | HMB_DATA_FWHALT | | |
6506 | HMB_DATA_NAKHANDLED | | |
6507 | HMB_DATA_FC | | |
6508 | HMB_DATA_FWREADY | | |
6509 | HMB_DATA_FCDATA_MASK | | |
6510 | HMB_DATA_VERSION_MASK)) { | |
6511 | DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data)); | |
6512 | } | |
6513 | ||
6514 | if (hmbd) { | |
6515 | *hmbd = hmb_data; | |
6516 | } | |
6517 | ||
6518 | return intstatus; | |
6519 | } | |
6520 | ||
6521 | static bool | |
6522 | dhdsdio_dpc(dhd_bus_t *bus) | |
6523 | { | |
6524 | bcmsdh_info_t *sdh = bus->sdh; | |
6525 | sdpcmd_regs_t *regs = bus->regs; | |
6526 | uint32 intstatus, newstatus = 0; | |
6527 | uint retries = 0; | |
6528 | uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */ | |
6529 | uint txlimit = dhd_txbound; /* Tx frames to send before resched */ | |
6530 | uint framecnt = 0; /* Temporary counter of tx/rx frames */ | |
6531 | bool rxdone = TRUE; /* Flag for no more read data */ | |
6532 | bool resched = FALSE; /* Flag indicating resched wanted */ | |
6533 | unsigned long flags; | |
6534 | #ifdef DEBUG_DPC_THREAD_WATCHDOG | |
6535 | bool is_resched_by_readframe = FALSE; | |
6536 | #endif /* DEBUG_DPC_THREAD_WATCHDOG */ | |
6537 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
6538 | ||
6539 | dhd_os_sdlock(bus->dhd); | |
6540 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
6541 | if (bus->dhd->busstate == DHD_BUS_DOWN) { | |
6542 | DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__)); | |
6543 | bus->intstatus = 0; | |
6544 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
6545 | dhd_os_sdunlock(bus->dhd); | |
6546 | return 0; | |
6547 | } | |
6548 | ||
6549 | DHD_BUS_BUSY_SET_IN_DPC(bus->dhd); | |
6550 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
6551 | ||
6552 | /* Start with leftover status bits */ | |
6553 | intstatus = bus->intstatus; | |
6554 | ||
6555 | if (!SLPAUTO_ENAB(bus) && !KSO_ENAB(bus)) { | |
6556 | DHD_ERROR(("%s: Device asleep\n", __FUNCTION__)); | |
6557 | goto exit; | |
6558 | } | |
6559 | ||
6560 | /* If waiting for HTAVAIL, check status */ | |
6561 | if (!SLPAUTO_ENAB(bus) && (bus->clkstate == CLK_PENDING)) { | |
6562 | int err; | |
6563 | uint8 clkctl, devctl = 0; | |
6564 | ||
6565 | #ifdef DHD_DEBUG | |
6566 | /* Check for inconsistent device control */ | |
6567 | devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err); | |
6568 | if (err) { | |
6569 | DHD_ERROR(("%s: error reading DEVCTL: %d\n", __FUNCTION__, err)); | |
6570 | bus->dhd->busstate = DHD_BUS_DOWN; | |
6571 | } else { | |
6572 | ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY); | |
6573 | } | |
6574 | #endif /* DHD_DEBUG */ | |
6575 | ||
6576 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
6577 | clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
6578 | if (err) { | |
6579 | DHD_ERROR(("%s: error reading CSR: %d\n", __FUNCTION__, err)); | |
6580 | bus->dhd->busstate = DHD_BUS_DOWN; | |
6581 | } | |
6582 | ||
6583 | DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl, clkctl)); | |
6584 | ||
6585 | if (SBSDIO_HTAV(clkctl)) { | |
6586 | devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err); | |
6587 | if (err) { | |
6588 | DHD_ERROR(("%s: error reading DEVCTL: %d\n", | |
6589 | __FUNCTION__, err)); | |
6590 | bus->dhd->busstate = DHD_BUS_DOWN; | |
6591 | } | |
6592 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
6593 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err); | |
6594 | if (err) { | |
6595 | DHD_ERROR(("%s: error writing DEVCTL: %d\n", | |
6596 | __FUNCTION__, err)); | |
6597 | bus->dhd->busstate = DHD_BUS_DOWN; | |
6598 | } | |
6599 | bus->clkstate = CLK_AVAIL; | |
6600 | } else { | |
6601 | goto clkwait; | |
6602 | } | |
6603 | } | |
6604 | ||
6605 | BUS_WAKE(bus); | |
6606 | ||
6607 | /* Make sure backplane clock is on */ | |
6608 | dhdsdio_clkctl(bus, CLK_AVAIL, TRUE); | |
6609 | if (bus->clkstate != CLK_AVAIL) | |
6610 | goto clkwait; | |
6611 | ||
6612 | /* Pending interrupt indicates new device status */ | |
47fa5ad5 | 6613 | if (bus->ipend) { |
010c3a89 RC |
6614 | bus->ipend = FALSE; |
6615 | #if defined(BT_OVER_SDIO) | |
6616 | bcmsdh_btsdio_process_f3_intr(); | |
6617 | #endif /* defined (BT_OVER_SDIO) */ | |
6618 | ||
6619 | R_SDREG(newstatus, ®s->intstatus, retries); | |
6620 | bus->f1regdata++; | |
6621 | if (bcmsdh_regfail(bus->sdh)) | |
6622 | newstatus = 0; | |
6623 | newstatus &= bus->hostintmask; | |
6624 | bus->fcstate = !!(newstatus & I_HMB_FC_STATE); | |
6625 | if (newstatus) { | |
6626 | bus->f1regdata++; | |
6627 | if ((bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_0) && | |
6628 | (newstatus == I_XMTDATA_AVAIL)) { | |
6629 | } else | |
6630 | W_SDREG(newstatus, ®s->intstatus, retries); | |
6631 | } | |
6632 | } | |
6633 | ||
6634 | /* Merge new bits with previous */ | |
6635 | intstatus |= newstatus; | |
6636 | bus->intstatus = 0; | |
6637 | ||
6638 | /* Handle flow-control change: read new state in case our ack | |
6639 | * crossed another change interrupt. If change still set, assume | |
6640 | * FC ON for safety, let next loop through do the debounce. | |
6641 | */ | |
6642 | if (intstatus & I_HMB_FC_CHANGE) { | |
6643 | intstatus &= ~I_HMB_FC_CHANGE; | |
6644 | W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries); | |
6645 | R_SDREG(newstatus, ®s->intstatus, retries); | |
6646 | bus->f1regdata += 2; | |
6647 | bus->fcstate = !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)); | |
6648 | intstatus |= (newstatus & bus->hostintmask); | |
6649 | } | |
6650 | ||
6651 | /* Handle host mailbox indication */ | |
6652 | if (intstatus & I_HMB_HOST_INT) { | |
6653 | uint32 hmbdata = 0; | |
6654 | ||
6655 | intstatus &= ~I_HMB_HOST_INT; | |
6656 | intstatus |= dhdsdio_hostmail(bus, &hmbdata); | |
6657 | ||
6658 | #ifdef DHD_ULP | |
6659 | /* ULP prototyping. Redowload fw on oob interupt */ | |
6660 | ||
6661 | /* all the writes after this point CAN use cached sbwad value */ | |
6662 | bcmsdh_force_sbwad_calc(bus->sdh, FALSE); | |
6663 | ||
6664 | if (dhd_ulp_pre_redownload_check(bus->dhd, bus->sdh, hmbdata)) { | |
6665 | if (dhd_bus_ulp_reinit_fw(bus) < 0) { | |
6666 | DHD_ERROR(("%s:%d FW redownload failed\n", | |
6667 | __FUNCTION__, __LINE__)); | |
6668 | goto exit; | |
6669 | } | |
6670 | } | |
6671 | #endif | |
6672 | ||
6673 | } | |
6674 | ||
6675 | /* Just being here means nothing more to do for chipactive */ | |
6676 | if (intstatus & I_CHIPACTIVE) { | |
6677 | /* ASSERT(bus->clkstate == CLK_AVAIL); */ | |
6678 | intstatus &= ~I_CHIPACTIVE; | |
6679 | } | |
6680 | ||
6681 | /* Handle host mailbox indication */ | |
6682 | if (intstatus & I_HMB_HOST_INT) { | |
6683 | intstatus &= ~I_HMB_HOST_INT; | |
6684 | intstatus |= dhdsdio_hostmail(bus, NULL); | |
6685 | } | |
6686 | ||
6687 | /* Generally don't ask for these, can get CRC errors... */ | |
6688 | if (intstatus & I_WR_OOSYNC) { | |
6689 | DHD_ERROR(("Dongle reports WR_OOSYNC\n")); | |
6690 | intstatus &= ~I_WR_OOSYNC; | |
6691 | } | |
6692 | ||
6693 | if (intstatus & I_RD_OOSYNC) { | |
6694 | DHD_ERROR(("Dongle reports RD_OOSYNC\n")); | |
6695 | intstatus &= ~I_RD_OOSYNC; | |
6696 | } | |
6697 | ||
6698 | if (intstatus & I_SBINT) { | |
6699 | DHD_ERROR(("Dongle reports SBINT\n")); | |
6700 | intstatus &= ~I_SBINT; | |
6701 | } | |
6702 | ||
6703 | /* Would be active due to wake-wlan in gSPI */ | |
6704 | if (intstatus & I_CHIPACTIVE) { | |
6705 | DHD_INFO(("Dongle reports CHIPACTIVE\n")); | |
6706 | intstatus &= ~I_CHIPACTIVE; | |
6707 | } | |
6708 | ||
6709 | if (intstatus & I_HMB_FC_STATE) { | |
6710 | DHD_INFO(("Dongle reports HMB_FC_STATE\n")); | |
6711 | intstatus &= ~I_HMB_FC_STATE; | |
6712 | } | |
6713 | ||
6714 | /* Ignore frame indications if rxskip is set */ | |
6715 | if (bus->rxskip) { | |
6716 | intstatus &= ~FRAME_AVAIL_MASK(bus); | |
6717 | } | |
6718 | ||
6719 | /* On frame indication, read available frames */ | |
6720 | if (PKT_AVAILABLE(bus, intstatus)) { | |
6721 | ||
6722 | framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone); | |
6723 | if (rxdone || bus->rxskip) | |
6724 | intstatus &= ~FRAME_AVAIL_MASK(bus); | |
6725 | rxlimit -= MIN(framecnt, rxlimit); | |
6726 | } | |
6727 | ||
6728 | /* Keep still-pending events for next scheduling */ | |
6729 | bus->intstatus = intstatus; | |
6730 | ||
6731 | clkwait: | |
6732 | /* Re-enable interrupts to detect new device events (mailbox, rx frame) | |
6733 | * or clock availability. (Allows tx loop to check ipend if desired.) | |
6734 | * (Unless register access seems hosed, as we may not be able to ACK...) | |
6735 | */ | |
32c27b7a RC |
6736 | if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh) && |
6737 | !(bus->dhd->conf->oob_enabled_later && !bus->ctrl_frame_stat)) { | |
010c3a89 RC |
6738 | DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n", |
6739 | __FUNCTION__, rxdone, framecnt)); | |
6740 | bus->intdis = FALSE; | |
6741 | #if defined(OOB_INTR_ONLY) | |
6742 | bcmsdh_oob_intr_set(bus->sdh, TRUE); | |
6743 | #endif /* defined(OOB_INTR_ONLY) */ | |
6744 | bcmsdh_intr_enable(sdh); | |
6745 | } | |
6746 | ||
6747 | #if defined(OOB_INTR_ONLY) && !defined(HW_OOB) | |
6748 | /* In case of SW-OOB(using edge trigger), | |
6749 | * Check interrupt status in the dongle again after enable irq on the host. | |
6750 | * and rechedule dpc if interrupt is pended in the dongle. | |
6751 | * There is a chance to miss OOB interrupt while irq is disabled on the host. | |
6752 | * No need to do this with HW-OOB(level trigger) | |
6753 | */ | |
6754 | R_SDREG(newstatus, ®s->intstatus, retries); | |
6755 | if (bcmsdh_regfail(bus->sdh)) | |
6756 | newstatus = 0; | |
6757 | if (newstatus & bus->hostintmask) { | |
6758 | bus->ipend = TRUE; | |
6759 | resched = TRUE; | |
6760 | } | |
6761 | #endif /* defined(OOB_INTR_ONLY) && !defined(HW_OOB) */ | |
6762 | ||
6763 | #ifdef PROP_TXSTATUS | |
6764 | dhd_wlfc_commit_packets(bus->dhd, (f_commitpkt_t)dhd_bus_txdata, (void *)bus, NULL, FALSE); | |
6765 | #endif | |
6766 | ||
6767 | if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) | |
6768 | dhdsdio_sendpendctl(bus); | |
6769 | ||
6770 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
6771 | else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate && | |
6772 | pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && DATAOK(bus)) { | |
6773 | ||
6774 | #ifdef DHD_ULP | |
6775 | if (dhd_ulp_f2_ready(bus->dhd, bus->sdh)) { | |
6776 | #endif /* DHD_ULP */ | |
6777 | if (bus->dhd->conf->dhd_txminmax < 0) | |
6778 | framecnt = rxdone ? txlimit : MIN(txlimit, DATABUFCNT(bus)); | |
6779 | else | |
6780 | framecnt = rxdone ? txlimit : MIN(txlimit, bus->dhd->conf->dhd_txminmax); | |
6781 | framecnt = dhdsdio_sendfromq(bus, framecnt); | |
6782 | txlimit -= framecnt; | |
6783 | #ifdef DHD_ULP | |
6784 | } else { | |
6785 | /* In other transient states like DHD_ULP_, after the states are | |
6786 | * DHD_ULP_F2ENAB_CLEARING and DHD_ULP_F2ENAB_SETTING, | |
6787 | * dpc is scheduled after steady-state and dhdsdio_sendfromq() will | |
6788 | * execute again | |
6789 | */ | |
6790 | } | |
6791 | #endif /* DHD_ULP */ | |
6792 | } | |
6793 | /* Resched the DPC if ctrl cmd is pending on bus credit */ | |
6794 | if (bus->ctrl_frame_stat) { | |
32c27b7a | 6795 | if (bus->dhd->conf->txctl_tmo_fix) { |
010c3a89 RC |
6796 | set_current_state(TASK_INTERRUPTIBLE); |
6797 | if (!kthread_should_stop()) | |
6798 | schedule_timeout(1); | |
6799 | set_current_state(TASK_RUNNING); | |
6800 | } | |
6801 | resched = TRUE; | |
6802 | } | |
6803 | ||
6804 | /* Resched if events or tx frames are pending, else await next interrupt */ | |
6805 | /* On failed register access, all bets are off: no resched or interrupts */ | |
6806 | if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) { | |
6807 | if ((bus->sih && bus->sih->buscorerev >= 12) && !(dhdsdio_sleepcsr_get(bus) & | |
6808 | SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
6809 | /* Bus failed because of KSO */ | |
6810 | DHD_ERROR(("%s: Bus failed due to KSO\n", __FUNCTION__)); | |
6811 | bus->kso = FALSE; | |
6812 | } else { | |
6813 | DHD_ERROR(("%s: failed backplane access over SDIO, halting operation\n", | |
6814 | __FUNCTION__)); | |
6815 | bus->dhd->busstate = DHD_BUS_DOWN; | |
6816 | bus->intstatus = 0; | |
6817 | } | |
6818 | } else if (bus->clkstate == CLK_PENDING) { | |
6819 | /* Awaiting I_CHIPACTIVE; don't resched */ | |
6820 | } else if (bus->intstatus || bus->ipend || | |
6821 | (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) && DATAOK(bus)) || | |
6822 | PKT_AVAILABLE(bus, bus->intstatus)) { /* Read multiple frames */ | |
6823 | resched = TRUE; | |
6824 | } | |
6825 | ||
6826 | bus->dpc_sched = resched; | |
6827 | ||
6828 | /* If we're done for now, turn off clock request. */ | |
6829 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && (bus->clkstate != CLK_PENDING) && | |
6830 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
6831 | bus->activity = FALSE; | |
6832 | dhdsdio_bussleep(bus, TRUE); | |
6833 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
6834 | } | |
6835 | ||
6836 | exit: | |
6837 | ||
6838 | if (!resched) { | |
6839 | /* Re-enable interrupts to detect new device events (mailbox, rx frame) | |
6840 | * or clock availability. (Allows tx loop to check ipend if desired.) | |
6841 | * (Unless register access seems hosed, as we may not be able to ACK...) | |
6842 | */ | |
32c27b7a RC |
6843 | if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh) && |
6844 | (bus->dhd->conf->oob_enabled_later && !bus->ctrl_frame_stat)) { | |
010c3a89 RC |
6845 | DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n", |
6846 | __FUNCTION__, rxdone, framecnt)); | |
6847 | bus->intdis = FALSE; | |
6848 | #if defined(OOB_INTR_ONLY) | |
6849 | bcmsdh_oob_intr_set(bus->sdh, TRUE); | |
6850 | #endif /* defined(OOB_INTR_ONLY) */ | |
6851 | bcmsdh_intr_enable(sdh); | |
6852 | } | |
6853 | if (dhd_dpcpoll) { | |
6854 | if (dhdsdio_readframes(bus, dhd_rxbound, &rxdone) != 0) { | |
6855 | resched = TRUE; | |
6856 | #ifdef DEBUG_DPC_THREAD_WATCHDOG | |
6857 | is_resched_by_readframe = TRUE; | |
6858 | #endif /* DEBUG_DPC_THREAD_WATCHDOG */ | |
6859 | } | |
6860 | } | |
6861 | } | |
6862 | ||
dfb0f3ae RC |
6863 | if (bus->ctrl_wait && TXCTLOK(bus)) |
6864 | wake_up_interruptible(&bus->ctrl_tx_wait); | |
010c3a89 RC |
6865 | dhd_os_sdunlock(bus->dhd); |
6866 | #ifdef DEBUG_DPC_THREAD_WATCHDOG | |
6867 | if (bus->dhd->dhd_bug_on) { | |
6868 | DHD_INFO(("%s: resched = %d ctrl_frame_stat = %d intstatus 0x%08x" | |
6869 | " ipend = %d pktq_mlen = %d is_resched_by_readframe = %d \n", | |
6870 | __FUNCTION__, resched, bus->ctrl_frame_stat, | |
6871 | bus->intstatus, bus->ipend, | |
6872 | pktq_mlen(&bus->txq, ~bus->flowcontrol), is_resched_by_readframe)); | |
6873 | ||
6874 | bus->dhd->dhd_bug_on = FALSE; | |
6875 | } | |
6876 | #endif /* DEBUG_DPC_THREAD_WATCHDOG */ | |
6877 | ||
6878 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
6879 | DHD_BUS_BUSY_CLEAR_IN_DPC(bus->dhd); | |
6880 | dhd_os_busbusy_wake(bus->dhd); | |
6881 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
6882 | ||
6883 | return resched; | |
6884 | } | |
6885 | ||
6886 | bool | |
6887 | dhd_bus_dpc(struct dhd_bus *bus) | |
6888 | { | |
6889 | bool resched; | |
6890 | ||
6891 | /* Call the DPC directly. */ | |
6892 | DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__)); | |
6893 | resched = dhdsdio_dpc(bus); | |
6894 | ||
6895 | return resched; | |
6896 | } | |
6897 | ||
6898 | void | |
6899 | dhdsdio_isr(void *arg) | |
6900 | { | |
6901 | dhd_bus_t *bus = (dhd_bus_t*)arg; | |
6902 | bcmsdh_info_t *sdh; | |
6903 | ||
6904 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
6905 | ||
6906 | if (!bus) { | |
6907 | DHD_ERROR(("%s : bus is null pointer , exit \n", __FUNCTION__)); | |
6908 | return; | |
6909 | } | |
6910 | sdh = bus->sdh; | |
6911 | ||
6912 | if (bus->dhd->busstate == DHD_BUS_DOWN) { | |
6913 | DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__)); | |
6914 | return; | |
6915 | } | |
6916 | ||
6917 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
6918 | ||
6919 | /* Count the interrupt call */ | |
6920 | bus->intrcount++; | |
6921 | bus->ipend = TRUE; | |
6922 | ||
6923 | /* Shouldn't get this interrupt if we're sleeping? */ | |
6924 | if (!SLPAUTO_ENAB(bus)) { | |
6925 | if (bus->sleeping) { | |
6926 | DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n")); | |
6927 | return; | |
6928 | } else if (!KSO_ENAB(bus)) { | |
6929 | DHD_ERROR(("ISR in devsleep 1\n")); | |
6930 | } | |
6931 | } | |
6932 | ||
6933 | /* Disable additional interrupts (is this needed now)? */ | |
6934 | if (bus->intr) { | |
6935 | DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__)); | |
6936 | } else { | |
6937 | DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n")); | |
6938 | } | |
6939 | ||
6940 | bcmsdh_intr_disable(sdh); | |
6941 | bus->intdis = TRUE; | |
6942 | ||
6943 | #if defined(SDIO_ISR_THREAD) | |
6944 | DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__)); | |
6945 | DHD_OS_WAKE_LOCK(bus->dhd); | |
6946 | /* terence 20150209: dpc should be scheded again if dpc_sched is TRUE or dhd_bus_txdata can | |
6947 | not schedule anymore because dpc_sched is TRUE now. | |
6948 | */ | |
6949 | if (dhdsdio_dpc(bus)) { | |
6950 | bus->dpc_sched = TRUE; | |
6951 | dhd_sched_dpc(bus->dhd); | |
6952 | } | |
6953 | DHD_OS_WAKE_UNLOCK(bus->dhd); | |
6954 | #else | |
6955 | bus->dpc_sched = TRUE; | |
6956 | dhd_sched_dpc(bus->dhd); | |
6957 | #endif /* defined(SDIO_ISR_THREAD) */ | |
6958 | ||
6959 | } | |
6960 | ||
6961 | #ifdef PKT_STATICS | |
6962 | void dhdsdio_txpktstatics(void) | |
6963 | { | |
6964 | uint i, total = 0; | |
6965 | ||
6966 | printf("%s: TYPE EVENT: %d pkts (size=%d) transfered\n", | |
6967 | __FUNCTION__, tx_statics.event_count, tx_statics.event_size); | |
6968 | printf("%s: TYPE CTRL: %d pkts (size=%d) transfered\n", | |
6969 | __FUNCTION__, tx_statics.ctrl_count, tx_statics.ctrl_size); | |
6970 | printf("%s: TYPE DATA: %d pkts (size=%d) transfered\n", | |
6971 | __FUNCTION__, tx_statics.data_count, tx_statics.data_size); | |
6972 | printf("%s: Glom size distribution:\n", __FUNCTION__); | |
6973 | for (i=0;i<tx_statics.glom_max;i++) { | |
6974 | total += tx_statics.glom_cnt[i]; | |
6975 | } | |
6976 | for (i=0;i<tx_statics.glom_max;i++) { | |
6977 | printf("%02d: %d", i+1, tx_statics.glom_cnt[i]); | |
6978 | if ((i+1)%8) | |
6979 | printf(", "); | |
6980 | else | |
6981 | printf("\n"); | |
6982 | } | |
6983 | printf("\n"); | |
6984 | for (i=0;i<tx_statics.glom_max;i++) { | |
6985 | printf("%02d:%3d%%", i+1, (tx_statics.glom_cnt[i]*100)/total); | |
6986 | if ((i+1)%8) | |
6987 | printf(", "); | |
6988 | else | |
6989 | printf("\n"); | |
6990 | } | |
6991 | printf("\n"); | |
6992 | printf("%s: data/glom=%d, glom_max=%d\n", | |
6993 | __FUNCTION__, tx_statics.data_count/total, tx_statics.glom_max); | |
6994 | printf("%s: TYPE RX GLOM: %d pkts (size=%d) transfered\n", | |
6995 | __FUNCTION__, tx_statics.glom_count, tx_statics.glom_size); | |
6996 | printf("%s: TYPE TEST: %d pkts (size=%d) transfered\n\n\n", | |
6997 | __FUNCTION__, tx_statics.test_count, tx_statics.test_size); | |
6998 | } | |
6999 | #endif | |
7000 | ||
7001 | #ifdef SDTEST | |
7002 | static void | |
7003 | dhdsdio_pktgen_init(dhd_bus_t *bus) | |
7004 | { | |
7005 | /* Default to specified length, or full range */ | |
7006 | if (dhd_pktgen_len) { | |
7007 | bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN); | |
7008 | bus->pktgen_minlen = bus->pktgen_maxlen; | |
7009 | } else { | |
7010 | bus->pktgen_maxlen = MAX_PKTGEN_LEN; | |
7011 | bus->pktgen_minlen = 0; | |
7012 | } | |
7013 | bus->pktgen_len = (uint16)bus->pktgen_minlen; | |
7014 | ||
7015 | /* Default to per-watchdog burst with 10s print time */ | |
7016 | bus->pktgen_freq = 1; | |
7017 | bus->pktgen_print = dhd_watchdog_ms ? (10000 / dhd_watchdog_ms) : 0; | |
7018 | bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000; | |
7019 | ||
7020 | /* Default to echo mode */ | |
7021 | bus->pktgen_mode = DHD_PKTGEN_ECHO; | |
7022 | bus->pktgen_stop = 1; | |
7023 | } | |
7024 | ||
7025 | static void | |
7026 | dhdsdio_pktgen(dhd_bus_t *bus) | |
7027 | { | |
7028 | void *pkt; | |
7029 | uint8 *data; | |
7030 | uint pktcount; | |
7031 | uint fillbyte; | |
7032 | osl_t *osh = bus->dhd->osh; | |
7033 | uint16 len; | |
7034 | ulong time_lapse; | |
7035 | uint sent_pkts; | |
7036 | uint rcvd_pkts; | |
7037 | ||
7038 | /* Display current count if appropriate */ | |
7039 | if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) { | |
7040 | bus->pktgen_ptick = 0; | |
7041 | printf("%s: send attempts %d, rcvd %d, errors %d\n", | |
7042 | __FUNCTION__, bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail); | |
7043 | ||
7044 | /* Print throughput stats only for constant length packet runs */ | |
7045 | if (bus->pktgen_minlen == bus->pktgen_maxlen) { | |
7046 | time_lapse = jiffies - bus->pktgen_prev_time; | |
7047 | bus->pktgen_prev_time = jiffies; | |
7048 | sent_pkts = bus->pktgen_sent - bus->pktgen_prev_sent; | |
7049 | bus->pktgen_prev_sent = bus->pktgen_sent; | |
7050 | rcvd_pkts = bus->pktgen_rcvd - bus->pktgen_prev_rcvd; | |
7051 | bus->pktgen_prev_rcvd = bus->pktgen_rcvd; | |
7052 | ||
7053 | printf("%s: Tx Throughput %d kbps, Rx Throughput %d kbps\n", | |
7054 | __FUNCTION__, | |
7055 | (sent_pkts * bus->pktgen_len / jiffies_to_msecs(time_lapse)) * 8, | |
7056 | (rcvd_pkts * bus->pktgen_len / jiffies_to_msecs(time_lapse)) * 8); | |
7057 | } | |
7058 | } | |
7059 | ||
7060 | /* For recv mode, just make sure dongle has started sending */ | |
7061 | if (bus->pktgen_mode == DHD_PKTGEN_RECV) { | |
7062 | if (bus->pktgen_rcv_state == PKTGEN_RCV_IDLE) { | |
7063 | bus->pktgen_rcv_state = PKTGEN_RCV_ONGOING; | |
7064 | dhdsdio_sdtest_set(bus, bus->pktgen_total); | |
7065 | } | |
7066 | return; | |
7067 | } | |
7068 | ||
7069 | /* Otherwise, generate or request the specified number of packets */ | |
7070 | for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) { | |
7071 | /* Stop if total has been reached */ | |
7072 | if (bus->pktgen_total && (bus->pktgen_sent >= bus->pktgen_total)) { | |
7073 | bus->pktgen_count = 0; | |
7074 | break; | |
7075 | } | |
7076 | ||
7077 | /* Allocate an appropriate-sized packet */ | |
7078 | if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) { | |
7079 | len = SDPCM_TEST_PKT_CNT_FLD_LEN; | |
7080 | } else { | |
7081 | len = bus->pktgen_len; | |
7082 | } | |
7083 | if (!(pkt = PKTGET(osh, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN), | |
7084 | TRUE))) {; | |
7085 | DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__)); | |
7086 | break; | |
7087 | } | |
7088 | PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN); | |
7089 | data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN; | |
7090 | ||
7091 | /* Write test header cmd and extra based on mode */ | |
7092 | switch (bus->pktgen_mode) { | |
7093 | case DHD_PKTGEN_ECHO: | |
7094 | *data++ = SDPCM_TEST_ECHOREQ; | |
7095 | *data++ = (uint8)bus->pktgen_sent; | |
7096 | break; | |
7097 | ||
7098 | case DHD_PKTGEN_SEND: | |
7099 | *data++ = SDPCM_TEST_DISCARD; | |
7100 | *data++ = (uint8)bus->pktgen_sent; | |
7101 | break; | |
7102 | ||
7103 | case DHD_PKTGEN_RXBURST: | |
7104 | *data++ = SDPCM_TEST_BURST; | |
7105 | *data++ = (uint8)bus->pktgen_count; /* Just for backward compatability */ | |
7106 | break; | |
7107 | ||
7108 | default: | |
7109 | DHD_ERROR(("Unrecognized pktgen mode %d\n", bus->pktgen_mode)); | |
7110 | PKTFREE(osh, pkt, TRUE); | |
7111 | bus->pktgen_count = 0; | |
7112 | return; | |
7113 | } | |
7114 | ||
7115 | /* Write test header length field */ | |
7116 | *data++ = (bus->pktgen_len >> 0); | |
7117 | *data++ = (bus->pktgen_len >> 8); | |
7118 | ||
7119 | /* Write frame count in a 4 byte field adjucent to SDPCM test header for | |
7120 | * burst mode | |
7121 | */ | |
7122 | if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) { | |
7123 | *data++ = (uint8)(bus->pktgen_count >> 0); | |
7124 | *data++ = (uint8)(bus->pktgen_count >> 8); | |
7125 | *data++ = (uint8)(bus->pktgen_count >> 16); | |
7126 | *data++ = (uint8)(bus->pktgen_count >> 24); | |
7127 | } else { | |
7128 | ||
7129 | /* Then fill in the remainder -- N/A for burst */ | |
7130 | for (fillbyte = 0; fillbyte < len; fillbyte++) | |
7131 | *data++ = SDPCM_TEST_FILL(fillbyte, (uint8)bus->pktgen_sent); | |
7132 | } | |
7133 | ||
7134 | #ifdef DHD_DEBUG | |
7135 | if (DHD_BYTES_ON() && DHD_DATA_ON()) { | |
7136 | data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN; | |
7137 | prhex("dhdsdio_pktgen: Tx Data", data, PKTLEN(osh, pkt) - SDPCM_HDRLEN); | |
7138 | } | |
7139 | #endif | |
7140 | ||
7141 | /* Send it */ | |
7142 | if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK) { | |
7143 | bus->pktgen_fail++; | |
7144 | if (bus->pktgen_stop && bus->pktgen_stop == bus->pktgen_fail) | |
7145 | bus->pktgen_count = 0; | |
7146 | } | |
7147 | bus->pktgen_sent++; | |
7148 | ||
7149 | /* Bump length if not fixed, wrap at max */ | |
7150 | if (++bus->pktgen_len > bus->pktgen_maxlen) | |
7151 | bus->pktgen_len = (uint16)bus->pktgen_minlen; | |
7152 | ||
7153 | /* Special case for burst mode: just send one request! */ | |
7154 | if (bus->pktgen_mode == DHD_PKTGEN_RXBURST) | |
7155 | break; | |
7156 | } | |
7157 | } | |
7158 | ||
7159 | static void | |
7160 | dhdsdio_sdtest_set(dhd_bus_t *bus, uint count) | |
7161 | { | |
7162 | void *pkt; | |
7163 | uint8 *data; | |
7164 | osl_t *osh = bus->dhd->osh; | |
7165 | ||
7166 | /* Allocate the packet */ | |
7167 | if (!(pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + | |
7168 | SDPCM_TEST_PKT_CNT_FLD_LEN + DHD_SDALIGN, TRUE))) { | |
7169 | DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__)); | |
7170 | return; | |
7171 | } | |
7172 | PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + | |
7173 | SDPCM_TEST_PKT_CNT_FLD_LEN), DHD_SDALIGN); | |
7174 | data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN; | |
7175 | ||
7176 | /* Fill in the test header */ | |
7177 | *data++ = SDPCM_TEST_SEND; | |
7178 | *data++ = (count > 0)?TRUE:FALSE; | |
7179 | *data++ = (bus->pktgen_maxlen >> 0); | |
7180 | *data++ = (bus->pktgen_maxlen >> 8); | |
7181 | *data++ = (uint8)(count >> 0); | |
7182 | *data++ = (uint8)(count >> 8); | |
7183 | *data++ = (uint8)(count >> 16); | |
7184 | *data++ = (uint8)(count >> 24); | |
7185 | ||
7186 | /* Send it */ | |
7187 | if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) != BCME_OK) | |
7188 | bus->pktgen_fail++; | |
7189 | } | |
7190 | ||
7191 | ||
7192 | static void | |
7193 | dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq) | |
7194 | { | |
7195 | osl_t *osh = bus->dhd->osh; | |
7196 | uint8 *data; | |
7197 | uint pktlen; | |
7198 | ||
7199 | uint8 cmd; | |
7200 | uint8 extra; | |
7201 | uint16 len; | |
7202 | uint16 offset; | |
7203 | ||
7204 | /* Check for min length */ | |
7205 | if ((pktlen = PKTLEN(osh, pkt)) < SDPCM_TEST_HDRLEN) { | |
7206 | DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n", pktlen)); | |
7207 | PKTFREE(osh, pkt, FALSE); | |
7208 | return; | |
7209 | } | |
7210 | ||
7211 | /* Extract header fields */ | |
7212 | data = PKTDATA(osh, pkt); | |
7213 | cmd = *data++; | |
7214 | extra = *data++; | |
7215 | len = *data++; len += *data++ << 8; | |
7216 | DHD_TRACE(("%s:cmd:%d, xtra:%d,len:%d\n", __FUNCTION__, cmd, extra, len)); | |
7217 | /* Check length for relevant commands */ | |
7218 | if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ || cmd == SDPCM_TEST_ECHORSP) { | |
7219 | if (pktlen != len + SDPCM_TEST_HDRLEN) { | |
7220 | DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, pktlen %d seq %d" | |
7221 | " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len)); | |
7222 | PKTFREE(osh, pkt, FALSE); | |
7223 | return; | |
7224 | } | |
7225 | } | |
7226 | ||
7227 | /* Process as per command */ | |
7228 | switch (cmd) { | |
7229 | case SDPCM_TEST_ECHOREQ: | |
7230 | /* Rx->Tx turnaround ok (even on NDIS w/current implementation) */ | |
7231 | *(uint8 *)(PKTDATA(osh, pkt)) = SDPCM_TEST_ECHORSP; | |
7232 | if (dhdsdio_txpkt(bus, SDPCM_TEST_CHANNEL, &pkt, 1, TRUE) == BCME_OK) { | |
7233 | bus->pktgen_sent++; | |
7234 | } else { | |
7235 | bus->pktgen_fail++; | |
7236 | PKTFREE(osh, pkt, FALSE); | |
7237 | } | |
7238 | bus->pktgen_rcvd++; | |
7239 | break; | |
7240 | ||
7241 | case SDPCM_TEST_ECHORSP: | |
7242 | if (bus->ext_loop) { | |
7243 | PKTFREE(osh, pkt, FALSE); | |
7244 | bus->pktgen_rcvd++; | |
7245 | break; | |
7246 | } | |
7247 | ||
7248 | for (offset = 0; offset < len; offset++, data++) { | |
7249 | if (*data != SDPCM_TEST_FILL(offset, extra)) { | |
7250 | DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " | |
7251 | "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n", | |
7252 | offset, len, SDPCM_TEST_FILL(offset, extra), *data)); | |
7253 | break; | |
7254 | } | |
7255 | } | |
7256 | PKTFREE(osh, pkt, FALSE); | |
7257 | bus->pktgen_rcvd++; | |
7258 | break; | |
7259 | ||
7260 | case SDPCM_TEST_DISCARD: | |
7261 | { | |
7262 | int i = 0; | |
7263 | uint8 *prn = data; | |
7264 | uint8 testval = extra; | |
7265 | for (i = 0; i < len; i++) { | |
7266 | if (*prn != testval) { | |
7267 | DHD_ERROR(("DIErr@Pkt#:%d,Ix:%d, expected:0x%x, got:0x%x\n", | |
7268 | i, bus->pktgen_rcvd_rcvsession, testval, *prn)); | |
7269 | prn++; testval++; | |
7270 | } | |
7271 | } | |
7272 | } | |
7273 | PKTFREE(osh, pkt, FALSE); | |
7274 | bus->pktgen_rcvd++; | |
7275 | break; | |
7276 | ||
7277 | case SDPCM_TEST_BURST: | |
7278 | case SDPCM_TEST_SEND: | |
7279 | default: | |
7280 | DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, pktlen %d seq %d" | |
7281 | " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len)); | |
7282 | PKTFREE(osh, pkt, FALSE); | |
7283 | break; | |
7284 | } | |
7285 | ||
7286 | /* For recv mode, stop at limit (and tell dongle to stop sending) */ | |
7287 | if (bus->pktgen_mode == DHD_PKTGEN_RECV) { | |
7288 | if (bus->pktgen_rcv_state != PKTGEN_RCV_IDLE) { | |
7289 | bus->pktgen_rcvd_rcvsession++; | |
7290 | ||
7291 | if (bus->pktgen_total && | |
7292 | (bus->pktgen_rcvd_rcvsession >= bus->pktgen_total)) { | |
7293 | bus->pktgen_count = 0; | |
7294 | DHD_ERROR(("Pktgen:rcv test complete!\n")); | |
7295 | bus->pktgen_rcv_state = PKTGEN_RCV_IDLE; | |
7296 | dhdsdio_sdtest_set(bus, FALSE); | |
7297 | bus->pktgen_rcvd_rcvsession = 0; | |
7298 | } | |
7299 | } | |
7300 | } | |
7301 | } | |
7302 | #endif /* SDTEST */ | |
7303 | ||
7304 | int dhd_bus_oob_intr_register(dhd_pub_t *dhdp) | |
7305 | { | |
7306 | int err = 0; | |
7307 | ||
7308 | #if defined(OOB_INTR_ONLY) | |
7309 | err = bcmsdh_oob_intr_register(dhdp->bus->sdh, dhdsdio_isr, dhdp->bus); | |
7310 | #endif | |
7311 | return err; | |
7312 | } | |
7313 | ||
7314 | void dhd_bus_oob_intr_unregister(dhd_pub_t *dhdp) | |
7315 | { | |
7316 | #if defined(OOB_INTR_ONLY) | |
7317 | bcmsdh_oob_intr_unregister(dhdp->bus->sdh); | |
7318 | #endif | |
7319 | } | |
7320 | ||
7321 | void dhd_bus_oob_intr_set(dhd_pub_t *dhdp, bool enable) | |
7322 | { | |
7323 | #if defined(OOB_INTR_ONLY) | |
7324 | bcmsdh_oob_intr_set(dhdp->bus->sdh, enable); | |
7325 | #endif | |
7326 | } | |
7327 | ||
7328 | void dhd_bus_dev_pm_stay_awake(dhd_pub_t *dhdpub) | |
7329 | { | |
7330 | bcmsdh_dev_pm_stay_awake(dhdpub->bus->sdh); | |
7331 | } | |
7332 | ||
7333 | void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub) | |
7334 | { | |
7335 | bcmsdh_dev_relax(dhdpub->bus->sdh); | |
7336 | } | |
7337 | ||
7338 | bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub) | |
7339 | { | |
7340 | bool enabled = FALSE; | |
7341 | ||
7342 | enabled = bcmsdh_dev_pm_enabled(dhdpub->bus->sdh); | |
7343 | return enabled; | |
7344 | } | |
7345 | ||
7346 | extern bool | |
7347 | dhd_bus_watchdog(dhd_pub_t *dhdp) | |
7348 | { | |
7349 | dhd_bus_t *bus; | |
7350 | unsigned long flags; | |
7351 | ||
7352 | DHD_TIMER(("%s: Enter\n", __FUNCTION__)); | |
7353 | ||
7354 | bus = dhdp->bus; | |
7355 | ||
7356 | if (bus->dhd->dongle_reset) | |
7357 | return FALSE; | |
7358 | ||
7359 | if (bus->dhd->hang_was_sent) { | |
7360 | dhd_os_wd_timer(bus->dhd, 0); | |
7361 | return FALSE; | |
7362 | } | |
7363 | ||
7364 | /* Ignore the timer if simulating bus down */ | |
7365 | if (!SLPAUTO_ENAB(bus) && bus->sleeping) | |
7366 | return FALSE; | |
7367 | ||
7368 | DHD_LINUX_GENERAL_LOCK(dhdp, flags); | |
7369 | if (DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhdp) || | |
7370 | DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp)) { | |
7371 | DHD_LINUX_GENERAL_UNLOCK(dhdp, flags); | |
7372 | return FALSE; | |
7373 | } | |
7374 | DHD_BUS_BUSY_SET_IN_WD(dhdp); | |
7375 | DHD_LINUX_GENERAL_UNLOCK(dhdp, flags); | |
7376 | ||
7377 | dhd_os_sdlock(bus->dhd); | |
7378 | ||
7379 | /* Poll period: check device if appropriate. */ | |
7380 | // terence 20160615: remove !SLPAUTO_ENAB(bus) to fix not able to polling if sr supported | |
7381 | if (1 && (bus->poll && (++bus->polltick >= bus->pollrate))) { | |
7382 | uint32 intstatus = 0; | |
7383 | ||
7384 | /* Reset poll tick */ | |
7385 | bus->polltick = 0; | |
7386 | ||
7387 | /* Check device if no interrupts */ | |
7388 | if (!bus->intr || (bus->intrcount == bus->lastintrs)) { | |
7389 | ||
7390 | if (!bus->dpc_sched) { | |
7391 | uint8 devpend; | |
7392 | devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, | |
7393 | SDIOD_CCCR_INTPEND, NULL); | |
7394 | intstatus = devpend & (INTR_STATUS_FUNC1 | INTR_STATUS_FUNC2); | |
7395 | } | |
7396 | ||
7397 | /* If there is something, make like the ISR and schedule the DPC */ | |
7398 | if (intstatus) { | |
7399 | bus->pollcnt++; | |
7400 | bus->ipend = TRUE; | |
7401 | if (bus->intr) { | |
7402 | bcmsdh_intr_disable(bus->sdh); | |
7403 | } | |
7404 | bus->dpc_sched = TRUE; | |
7405 | dhd_sched_dpc(bus->dhd); | |
7406 | } | |
7407 | } | |
7408 | ||
7409 | /* Update interrupt tracking */ | |
7410 | bus->lastintrs = bus->intrcount; | |
7411 | } | |
7412 | ||
7413 | if ((!bus->dpc_sched) && pktq_len(&bus->txq)) { | |
7414 | bus->dpc_sched = TRUE; | |
7415 | dhd_sched_dpc(bus->dhd); | |
7416 | } | |
7417 | ||
7418 | #ifdef DHD_DEBUG | |
7419 | /* Poll for console output periodically */ | |
7420 | if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) { | |
7421 | bus->console.count += dhd_watchdog_ms; | |
7422 | if (bus->console.count >= dhd_console_ms) { | |
7423 | bus->console.count -= dhd_console_ms; | |
7424 | /* Make sure backplane clock is on */ | |
7425 | if (SLPAUTO_ENAB(bus)) | |
7426 | dhdsdio_bussleep(bus, FALSE); | |
7427 | else | |
7428 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
7429 | if (dhdsdio_readconsole(bus) < 0) | |
7430 | dhd_console_ms = 0; /* On error, stop trying */ | |
7431 | } | |
7432 | } | |
7433 | #endif /* DHD_DEBUG */ | |
7434 | ||
7435 | #ifdef SDTEST | |
7436 | /* Generate packets if configured */ | |
7437 | if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) { | |
7438 | /* Make sure backplane clock is on */ | |
7439 | if (SLPAUTO_ENAB(bus)) | |
7440 | dhdsdio_bussleep(bus, FALSE); | |
7441 | else | |
7442 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
7443 | bus->pktgen_tick = 0; | |
7444 | dhdsdio_pktgen(bus); | |
7445 | } | |
7446 | #endif | |
7447 | ||
7448 | /* On idle timeout clear activity flag and/or turn off clock */ | |
7449 | #ifdef DHD_USE_IDLECOUNT | |
7450 | if (bus->activity) | |
7451 | bus->activity = FALSE; | |
7452 | else { | |
7453 | bus->idlecount++; | |
7454 | ||
7455 | /* | |
7456 | * If the condition to switch off the clock is reached And if | |
7457 | * BT is inactive (in case of BT_OVER_SDIO build) turn off clk. | |
7458 | * | |
7459 | * Consider the following case, DHD is configured with | |
7460 | * 1) idletime == DHD_IDLE_IMMEDIATE | |
7461 | * 2) BT is the last user of the clock | |
7462 | * We cannot disable the clock from __dhdsdio_clk_disable | |
7463 | * since WLAN might be using it. If WLAN is active then | |
7464 | * from the respective function/context after doing the job | |
7465 | * the clk is turned off. | |
7466 | * But if WLAN is actually inactive then the watchdog should | |
7467 | * disable the clock. So the condition check below should be | |
7468 | * bus->idletime != 0 instead of idletime == 0 | |
7469 | */ | |
7470 | if ((bus->idletime != 0) && (bus->idlecount >= bus->idletime) && | |
7471 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
7472 | DHD_TIMER(("%s: DHD Idle state!!\n", __FUNCTION__)); | |
7473 | if (!bus->poll && SLPAUTO_ENAB(bus)) { | |
7474 | if (dhdsdio_bussleep(bus, TRUE) != BCME_BUSY) | |
7475 | dhd_os_wd_timer(bus->dhd, 0); | |
7476 | } else | |
7477 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
7478 | ||
7479 | bus->idlecount = 0; | |
7480 | } | |
7481 | } | |
7482 | #else | |
7483 | if ((bus->idletime != 0) && (bus->clkstate == CLK_AVAIL) && | |
7484 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
7485 | if (++bus->idlecount >= bus->idletime) { | |
7486 | bus->idlecount = 0; | |
7487 | if (bus->activity) { | |
7488 | bus->activity = FALSE; | |
7489 | if (!bus->poll && SLPAUTO_ENAB(bus)) { | |
7490 | if (!bus->readframes) | |
7491 | dhdsdio_bussleep(bus, TRUE); | |
7492 | else | |
7493 | bus->reqbussleep = TRUE; | |
7494 | } else { | |
7495 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
7496 | } | |
7497 | } | |
7498 | } | |
7499 | } | |
7500 | #endif /* DHD_USE_IDLECOUNT */ | |
7501 | ||
7502 | dhd_os_sdunlock(bus->dhd); | |
7503 | ||
7504 | DHD_LINUX_GENERAL_LOCK(dhdp, flags); | |
7505 | DHD_BUS_BUSY_CLEAR_IN_WD(dhdp); | |
7506 | dhd_os_busbusy_wake(dhdp); | |
7507 | DHD_LINUX_GENERAL_UNLOCK(dhdp, flags); | |
7508 | ||
7509 | return bus->ipend; | |
7510 | } | |
7511 | ||
7512 | extern int | |
7513 | dhd_bus_console_in(dhd_pub_t *dhdp, uchar *msg, uint msglen) | |
7514 | { | |
7515 | dhd_bus_t *bus = dhdp->bus; | |
7516 | uint32 addr, val; | |
7517 | int rv; | |
7518 | void *pkt; | |
7519 | ||
7520 | /* Address could be zero if CONSOLE := 0 in dongle Makefile */ | |
7521 | if (bus->console_addr == 0) | |
7522 | return BCME_UNSUPPORTED; | |
7523 | ||
7524 | /* Exclusive bus access */ | |
7525 | dhd_os_sdlock(bus->dhd); | |
7526 | ||
7527 | /* Don't allow input if dongle is in reset */ | |
7528 | if (bus->dhd->dongle_reset) { | |
7529 | dhd_os_sdunlock(bus->dhd); | |
7530 | return BCME_NOTREADY; | |
7531 | } | |
7532 | ||
7533 | /* Request clock to allow SDIO accesses */ | |
7534 | BUS_WAKE(bus); | |
7535 | /* No pend allowed since txpkt is called later, ht clk has to be on */ | |
7536 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
7537 | ||
7538 | /* Zero cbuf_index */ | |
7539 | addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx); | |
7540 | val = htol32(0); | |
7541 | if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) | |
7542 | goto done; | |
7543 | ||
7544 | /* Write message into cbuf */ | |
7545 | addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf); | |
7546 | if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0) | |
7547 | goto done; | |
7548 | ||
7549 | /* Write length into vcons_in */ | |
7550 | addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in); | |
7551 | val = htol32(msglen); | |
7552 | if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) | |
7553 | goto done; | |
7554 | ||
47fa5ad5 RC |
7555 | if (!DATAOK(bus)) { |
7556 | rv = BCME_NOTREADY; | |
7557 | goto done; | |
7558 | } | |
7559 | ||
010c3a89 RC |
7560 | /* Bump dongle by sending an empty packet on the event channel. |
7561 | * sdpcm_sendup (RX) checks for virtual console input. | |
7562 | */ | |
7563 | if ((pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE)) != NULL) | |
7564 | rv = dhdsdio_txpkt(bus, SDPCM_EVENT_CHANNEL, &pkt, 1, TRUE); | |
7565 | ||
7566 | done: | |
7567 | if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched && | |
7568 | NO_OTHER_ACTIVE_BUS_USER(bus)) { | |
7569 | bus->activity = FALSE; | |
7570 | dhdsdio_bussleep(bus, TRUE); | |
7571 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
7572 | } | |
7573 | ||
7574 | dhd_os_sdunlock(bus->dhd); | |
7575 | ||
7576 | return rv; | |
7577 | } | |
7578 | ||
7579 | #ifdef DHD_DEBUG | |
7580 | static void | |
7581 | dhd_dump_cis(uint fn, uint8 *cis) | |
7582 | { | |
7583 | uint byte, tag, tdata; | |
7584 | DHD_INFO(("Function %d CIS:\n", fn)); | |
7585 | ||
7586 | for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) { | |
7587 | if ((byte % 16) == 0) | |
7588 | DHD_INFO((" ")); | |
7589 | DHD_INFO(("%02x ", cis[byte])); | |
7590 | if ((byte % 16) == 15) | |
7591 | DHD_INFO(("\n")); | |
7592 | if (!tdata--) { | |
7593 | tag = cis[byte]; | |
7594 | if (tag == 0xff) | |
7595 | break; | |
7596 | else if (!tag) | |
7597 | tdata = 0; | |
7598 | else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT) | |
7599 | tdata = cis[byte + 1] + 1; | |
7600 | else | |
7601 | DHD_INFO(("]")); | |
7602 | } | |
7603 | } | |
7604 | if ((byte % 16) != 15) | |
7605 | DHD_INFO(("\n")); | |
7606 | } | |
7607 | #endif /* DHD_DEBUG */ | |
7608 | ||
7609 | static bool | |
7610 | dhdsdio_chipmatch(uint16 chipid) | |
7611 | { | |
7612 | if (chipid == BCM4336_CHIP_ID) | |
7613 | return TRUE; | |
7614 | if (chipid == BCM4330_CHIP_ID) | |
7615 | return TRUE; | |
7616 | if (chipid == BCM43237_CHIP_ID) | |
7617 | return TRUE; | |
7618 | if (chipid == BCM43362_CHIP_ID) | |
7619 | return TRUE; | |
7620 | if (chipid == BCM4314_CHIP_ID) | |
7621 | return TRUE; | |
7622 | if (chipid == BCM43242_CHIP_ID) | |
7623 | return TRUE; | |
7624 | if (chipid == BCM43340_CHIP_ID) | |
7625 | return TRUE; | |
7626 | if (chipid == BCM43341_CHIP_ID) | |
7627 | return TRUE; | |
7628 | if (chipid == BCM43143_CHIP_ID) | |
7629 | return TRUE; | |
7630 | if (chipid == BCM43342_CHIP_ID) | |
7631 | return TRUE; | |
7632 | if (chipid == BCM4334_CHIP_ID) | |
7633 | return TRUE; | |
7634 | if (chipid == BCM43239_CHIP_ID) | |
7635 | return TRUE; | |
7636 | if (chipid == BCM4324_CHIP_ID) | |
7637 | return TRUE; | |
7638 | if (chipid == BCM4335_CHIP_ID) | |
7639 | return TRUE; | |
7640 | if (chipid == BCM4339_CHIP_ID) | |
7641 | return TRUE; | |
7642 | if (chipid == BCM43349_CHIP_ID) | |
7643 | return TRUE; | |
7644 | if (BCM4345_CHIP(chipid)) | |
7645 | return TRUE; | |
7646 | if (chipid == BCM4350_CHIP_ID) | |
7647 | return TRUE; | |
7648 | if (chipid == BCM4354_CHIP_ID) | |
7649 | return TRUE; | |
7650 | if (chipid == BCM4358_CHIP_ID) | |
7651 | return TRUE; | |
7652 | if (chipid == BCM43569_CHIP_ID) | |
7653 | return TRUE; | |
7654 | if (chipid == BCM4371_CHIP_ID) | |
7655 | return TRUE; | |
7656 | if (chipid == BCM43430_CHIP_ID) | |
7657 | return TRUE; | |
7658 | if (chipid == BCM43018_CHIP_ID) | |
7659 | return TRUE; | |
7660 | if (BCM4349_CHIP(chipid)) | |
7661 | return TRUE; | |
7662 | if (BCM4347_CHIP(chipid)) | |
7663 | return TRUE; | |
7664 | if (chipid == BCM4364_CHIP_ID) | |
7665 | return TRUE; | |
7666 | ||
7667 | if (chipid == BCM43012_CHIP_ID) | |
7668 | return TRUE; | |
dfb0f3ae | 7669 | if (chipid == BCM4362_CHIP_ID) |
210a9a5c W |
7670 | return TRUE; |
7671 | ||
010c3a89 RC |
7672 | return FALSE; |
7673 | } | |
7674 | ||
010c3a89 RC |
7675 | static void * |
7676 | dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, uint16 slot, | |
7677 | uint16 func, uint bustype, void *regsva, osl_t * osh, void *sdh) | |
7678 | { | |
7679 | int ret; | |
7680 | dhd_bus_t *bus; | |
7681 | #ifdef GET_OTP_MAC_ENABLE | |
7682 | struct ether_addr ea_addr; | |
7683 | #endif | |
7684 | ||
d964ce36 | 7685 | DHD_MUTEX_LOCK(); |
010c3a89 RC |
7686 | |
7687 | /* Init global variables at run-time, not as part of the declaration. | |
7688 | * This is required to support init/de-init of the driver. Initialization | |
7689 | * of globals as part of the declaration results in non-deterministic | |
7690 | * behavior since the value of the globals may be different on the | |
7691 | * first time that the driver is initialized vs subsequent initializations. | |
7692 | */ | |
7693 | dhd_txbound = DHD_TXBOUND; | |
7694 | dhd_rxbound = DHD_RXBOUND; | |
7695 | dhd_alignctl = TRUE; | |
7696 | sd1idle = TRUE; | |
7697 | dhd_readahead = TRUE; | |
7698 | retrydata = FALSE; | |
7699 | ||
7700 | #ifdef DISABLE_FLOW_CONTROL | |
7701 | dhd_doflow = FALSE; | |
7702 | #endif /* DISABLE_FLOW_CONTROL */ | |
7703 | dhd_dongle_ramsize = 0; | |
7704 | dhd_txminmax = DHD_TXMINMAX; | |
7705 | ||
7706 | forcealign = TRUE; | |
7707 | ||
7708 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
7709 | DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __FUNCTION__, venid, devid)); | |
7710 | ||
7711 | /* We make assumptions about address window mappings */ | |
7712 | ASSERT((uintptr)regsva == SI_ENUM_BASE); | |
7713 | ||
7714 | /* BCMSDH passes venid and devid based on CIS parsing -- but low-power start | |
7715 | * means early parse could fail, so here we should get either an ID | |
7716 | * we recognize OR (-1) indicating we must request power first. | |
7717 | */ | |
7718 | /* Check the Vendor ID */ | |
7719 | switch (venid) { | |
7720 | case 0x0000: | |
7721 | case VENDOR_BROADCOM: | |
7722 | break; | |
7723 | default: | |
7724 | DHD_ERROR(("%s: unknown vendor: 0x%04x\n", | |
7725 | __FUNCTION__, venid)); | |
7726 | goto forcereturn; | |
7727 | } | |
7728 | ||
7729 | /* Check the Device ID and make sure it's one that we support */ | |
7730 | switch (devid) { | |
7731 | case 0: | |
7732 | DHD_INFO(("%s: allow device id 0, will check chip internals\n", | |
7733 | __FUNCTION__)); | |
7734 | break; | |
7735 | ||
7736 | default: | |
7737 | DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n", | |
7738 | __FUNCTION__, venid, devid)); | |
7739 | goto forcereturn; | |
7740 | } | |
7741 | ||
7742 | if (osh == NULL) { | |
7743 | DHD_ERROR(("%s: osh is NULL!\n", __FUNCTION__)); | |
7744 | goto forcereturn; | |
7745 | } | |
7746 | ||
7747 | /* Allocate private bus interface state */ | |
7748 | if (!(bus = MALLOC(osh, sizeof(dhd_bus_t)))) { | |
7749 | DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__)); | |
7750 | goto fail; | |
7751 | } | |
7752 | bzero(bus, sizeof(dhd_bus_t)); | |
7753 | bus->sdh = sdh; | |
7754 | bus->cl_devid = (uint16)devid; | |
7755 | bus->bus = DHD_BUS; | |
7756 | bus->bus_num = bus_no; | |
7757 | bus->slot_num = slot; | |
7758 | bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1; | |
7759 | bus->usebufpool = FALSE; /* Use bufpool if allocated, else use locally malloced rxbuf */ | |
7760 | #ifdef BT_OVER_SDIO | |
7761 | bus->bt_use_count = 0; | |
7762 | #endif | |
7763 | ||
7764 | #if defined(SUPPORT_P2P_GO_PS) | |
7765 | init_waitqueue_head(&bus->bus_sleep); | |
7766 | #endif /* LINUX && SUPPORT_P2P_GO_PS */ | |
dfb0f3ae | 7767 | init_waitqueue_head(&bus->ctrl_tx_wait); |
010c3a89 RC |
7768 | |
7769 | /* attempt to attach to the dongle */ | |
7770 | if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) { | |
7771 | DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __FUNCTION__)); | |
7772 | goto fail; | |
7773 | } | |
7774 | ||
7775 | /* Attach to the dhd/OS/network interface */ | |
7776 | if (!(bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE))) { | |
7777 | DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__)); | |
7778 | goto fail; | |
7779 | } | |
7780 | #if defined(BT_OVER_SDIO) | |
7781 | g_dhd_pub = bus->dhd; | |
7782 | DHD_ERROR(("%s: g_dhd_pub %p\n", __FUNCTION__, g_dhd_pub)); | |
7783 | #endif /* defined (BT_OVER_SDIO) */ | |
7784 | ||
7785 | /* Allocate buffers */ | |
7786 | if (!(dhdsdio_probe_malloc(bus, osh, sdh))) { | |
7787 | DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __FUNCTION__)); | |
7788 | goto fail; | |
7789 | } | |
7790 | ||
7791 | if (!(dhdsdio_probe_init(bus, osh, sdh))) { | |
7792 | DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __FUNCTION__)); | |
7793 | goto fail; | |
7794 | } | |
7795 | ||
7796 | if (bus->intr) { | |
7797 | /* Register interrupt callback, but mask it (not operational yet). */ | |
7798 | DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n", __FUNCTION__)); | |
7799 | bcmsdh_intr_disable(sdh); | |
7800 | if ((ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus)) != 0) { | |
7801 | DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n", | |
7802 | __FUNCTION__, ret)); | |
7803 | goto fail; | |
7804 | } | |
7805 | DHD_INTR(("%s: registered SDIO interrupt function ok\n", __FUNCTION__)); | |
7806 | } else { | |
7807 | DHD_INFO(("%s: SDIO interrupt function is NOT registered due to polling mode\n", | |
7808 | __FUNCTION__)); | |
7809 | } | |
7810 | ||
7811 | DHD_INFO(("%s: completed!!\n", __FUNCTION__)); | |
7812 | ||
7813 | /* if firmware path present try to download and bring up bus */ | |
7814 | bus->dhd->hang_report = TRUE; | |
7815 | #if 0 // terence 20150325: fix for WPA/WPA2 4-way handshake fail in hostapd | |
7816 | if (dhd_download_fw_on_driverload) { | |
7817 | if ((ret = dhd_bus_start(bus->dhd)) != 0) { | |
7818 | DHD_ERROR(("%s: dhd_bus_start failed\n", __FUNCTION__)); | |
7819 | goto fail; | |
7820 | } | |
7821 | } | |
7822 | else { | |
7823 | /* Set random MAC address during boot time */ | |
7824 | get_random_bytes(&bus->dhd->mac.octet[3], 3); | |
7825 | /* Adding BRCM OUI */ | |
7826 | bus->dhd->mac.octet[0] = 0; | |
7827 | bus->dhd->mac.octet[1] = 0x90; | |
7828 | bus->dhd->mac.octet[2] = 0x4C; | |
7829 | } | |
7830 | #endif | |
7831 | #if defined(BT_OVER_SDIO) | |
7832 | /* At this point Regulators are turned on and iconditionaly sdio bus is started | |
7833 | * based upon dhd_download_fw_on_driverload check, so | |
7834 | * increase the bus user count, this count will only be disabled inside | |
7835 | * dhd_register_if() function if flag dhd_download_fw_on_driverload is set to false, | |
7836 | * i.e FW download during insmod is not needed, otherwise it will not be decremented | |
7837 | * so that WALN will always hold the bus untill rmmod is done. | |
7838 | */ | |
7839 | dhdsdio_bus_usr_cnt_inc(bus->dhd); | |
7840 | #endif /* BT_OVER_SDIO */ | |
7841 | ||
7842 | #ifdef GET_OTP_MAC_ENABLE | |
7843 | if (dhd_conf_get_mac(bus->dhd, sdh, ea_addr.octet)) { | |
7844 | DHD_TRACE(("%s: Can not read MAC address\n", __FUNCTION__)); | |
7845 | } else | |
7846 | memcpy(bus->dhd->mac.octet, (void *)&ea_addr, ETHER_ADDR_LEN); | |
7847 | #endif /* GET_CUSTOM_MAC_ENABLE */ | |
7848 | ||
7849 | /* Ok, have the per-port tell the stack we're open for business */ | |
7850 | if (dhd_register_if(bus->dhd, 0, TRUE) != 0) { | |
7851 | DHD_ERROR(("%s: Net attach failed!!\n", __FUNCTION__)); | |
7852 | goto fail; | |
7853 | } | |
7854 | ||
7855 | #ifdef BCMHOST_XTAL_PU_TIME_MOD | |
7856 | bcmsdh_reg_write(bus->sdh, 0x18000620, 2, 11); | |
7857 | #ifdef BCM4330_CHIP | |
7858 | bcmsdh_reg_write(bus->sdh, 0x18000628, 4, 0x0000F801); | |
7859 | #else | |
7860 | bcmsdh_reg_write(bus->sdh, 0x18000628, 4, 0x00F80001); | |
7861 | #endif /* BCM4330_CHIP */ | |
7862 | #endif /* BCMHOST_XTAL_PU_TIME_MOD */ | |
7863 | ||
7864 | #if defined(MULTIPLE_SUPPLICANT) | |
7865 | wl_android_post_init(); // terence 20120530: fix critical section in dhd_open and dhdsdio_probe | |
d964ce36 | 7866 | #endif /* MULTIPLE_SUPPLICANT */ |
7867 | DHD_MUTEX_UNLOCK(); | |
010c3a89 RC |
7868 | |
7869 | return bus; | |
7870 | ||
7871 | fail: | |
7872 | dhdsdio_release(bus, osh); | |
7873 | ||
7874 | forcereturn: | |
d964ce36 | 7875 | DHD_MUTEX_UNLOCK(); |
010c3a89 RC |
7876 | |
7877 | return NULL; | |
7878 | } | |
7879 | ||
7880 | static bool | |
7881 | dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva, | |
7882 | uint16 devid) | |
7883 | { | |
7884 | uint8 clkctl = 0; | |
7885 | uint fn, numfn; | |
7886 | uint8 *cis[SDIOD_MAX_IOFUNCS]; | |
7887 | int err = 0; | |
7888 | ||
7889 | ||
7890 | bus->alp_only = TRUE; | |
7891 | bus->sih = NULL; | |
7892 | ||
7893 | /* Return the window to backplane enumeration space for core access */ | |
7894 | if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE)) { | |
7895 | DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __FUNCTION__)); | |
7896 | } | |
7897 | ||
7898 | #if defined(DHD_DEBUG) && !defined(CUSTOMER_HW4_DEBUG) | |
7899 | DHD_ERROR(("F1 signature read @0x18000000=0x%4x\n", | |
7900 | bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4))); | |
7901 | #endif /* DHD_DEBUG && !CUSTOMER_HW4_DEBUG */ | |
7902 | ||
7903 | ||
7904 | /* Force PLL off until si_attach() programs PLL control regs */ | |
7905 | ||
7906 | ||
7907 | ||
7908 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, DHD_INIT_CLKCTL1, &err); | |
7909 | if (!err) | |
7910 | clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
7911 | ||
7912 | if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) { | |
7913 | DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", | |
7914 | err, DHD_INIT_CLKCTL1, clkctl)); | |
7915 | goto fail; | |
7916 | } | |
7917 | numfn = bcmsdh_query_iofnum(sdh); | |
7918 | ASSERT(numfn <= SDIOD_MAX_IOFUNCS); | |
7919 | ||
7920 | /* Make sure ALP is available before trying to read CIS */ | |
7921 | SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, | |
7922 | SBSDIO_FUNC1_CHIPCLKCSR, NULL)), | |
7923 | !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY); | |
7924 | ||
7925 | /* Now request ALP be put on the bus */ | |
7926 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, | |
7927 | DHD_INIT_CLKCTL2, &err); | |
7928 | OSL_DELAY(200); | |
dfb0f3ae | 7929 | |
010c3a89 RC |
7930 | if (DHD_INFO_ON()) { |
7931 | for (fn = 0; fn <= numfn; fn++) { | |
7932 | if (!(cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT))) { | |
7933 | DHD_INFO(("dhdsdio_probe: fn %d cis malloc failed\n", fn)); | |
7934 | break; | |
7935 | } | |
7936 | bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT); | |
7937 | ||
7938 | if ((err = bcmsdh_cis_read(sdh, fn, cis[fn], | |
7939 | SBSDIO_CIS_SIZE_LIMIT))) { | |
7940 | DHD_INFO(("dhdsdio_probe: fn %d cis read err %d\n", fn, err)); | |
7941 | MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT); | |
7942 | break; | |
7943 | } | |
7944 | #if 0 | |
7945 | /* Reading the F1, F2 and F3 max blocksize values from CIS | |
7946 | * and writing into the F1, F2 and F3 block size registers. | |
7947 | * There is no max block size register value available for F0 in CIS register. | |
7948 | * So, setting default value for F0 block size as 32 (which was set earlier | |
7949 | * in iovar). IOVAR takes only one arguement. | |
7950 | * So, we are passing the function number alongwith the value (fn<<16) | |
7951 | */ | |
7952 | if (!fn) | |
7953 | value = F0_BLOCK_SIZE; | |
7954 | else | |
7955 | value = (cis[fn][25]<<8) | cis[fn][24] | (fn<<16); | |
7956 | printf("%s: fn=%d, value=%d\n", __FUNCTION__, fn, value); | |
7957 | if (bcmsdh_iovar_op(sdh, "sd_blocksize", NULL, 0, &value, | |
7958 | sizeof(value), TRUE) != BCME_OK) { | |
7959 | bus->blocksize = 0; | |
7960 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, | |
7961 | "sd_blocksize")); | |
7962 | } | |
7963 | #endif | |
7964 | #ifdef DHD_DEBUG | |
7965 | if (DHD_INFO_ON()) { | |
7966 | dhd_dump_cis(fn, cis[fn]); | |
7967 | } | |
7968 | #endif /* DHD_DEBUG */ | |
7969 | } | |
7970 | while (fn-- > 0) { | |
7971 | ASSERT(cis[fn]); | |
7972 | MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT); | |
7973 | } | |
7974 | } | |
7975 | #if 0 | |
7976 | if (dhd_conf_set_blksize(sdh)) { | |
7977 | bus->blocksize = 0; | |
7978 | } | |
7979 | #endif | |
7980 | if (err) { | |
7981 | DHD_ERROR(("dhdsdio_probe: failure reading or parsing CIS\n")); | |
7982 | goto fail; | |
7983 | } | |
7984 | /* si_attach() will provide an SI handle and scan the backplane */ | |
7985 | if (!(bus->sih = si_attach((uint)devid, osh, regsva, DHD_BUS, sdh, | |
7986 | &bus->vars, &bus->varsz))) { | |
7987 | DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__)); | |
7988 | goto fail; | |
7989 | } | |
7990 | ||
7991 | #ifdef DHD_DEBUG | |
7992 | DHD_ERROR(("F1 signature OK, socitype:0x%x chip:0x%4x rev:0x%x pkg:0x%x\n", | |
7993 | bus->sih->socitype, bus->sih->chip, bus->sih->chiprev, bus->sih->chippkg)); | |
7994 | #endif /* DHD_DEBUG */ | |
7995 | ||
7996 | ||
7997 | bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev); | |
7998 | ||
7999 | if (!dhdsdio_chipmatch((uint16)bus->sih->chip)) { | |
8000 | DHD_ERROR(("%s: unsupported chip: 0x%04x\n", | |
8001 | __FUNCTION__, bus->sih->chip)); | |
8002 | goto fail; | |
8003 | } | |
8004 | ||
8005 | if (bus->sih->buscorerev >= 12) | |
8006 | dhdsdio_clk_kso_init(bus); | |
8007 | else | |
8008 | bus->kso = TRUE; | |
8009 | ||
8010 | if (CST4330_CHIPMODE_SDIOD(bus->sih->chipst)) { | |
8011 | } | |
8012 | ||
8013 | si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength); | |
8014 | ||
8015 | ||
8016 | /* Get info on the ARM and SOCRAM cores... */ | |
8017 | if (!DHD_NOPMU(bus)) { | |
8018 | if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) || | |
8019 | (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) || | |
8020 | (si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) { | |
8021 | bus->armrev = si_corerev(bus->sih); | |
8022 | } else { | |
8023 | DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__)); | |
8024 | goto fail; | |
8025 | } | |
8026 | ||
8027 | if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { | |
8028 | if (!(bus->orig_ramsize = si_socram_size(bus->sih))) { | |
8029 | DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__)); | |
8030 | goto fail; | |
8031 | } | |
8032 | } else { | |
8033 | /* cr4 has a different way to find the RAM size from TCM's */ | |
8034 | if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) { | |
8035 | DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__)); | |
8036 | goto fail; | |
8037 | } | |
8038 | /* also populate base address */ | |
8039 | switch ((uint16)bus->sih->chip) { | |
8040 | case BCM4335_CHIP_ID: | |
8041 | case BCM4339_CHIP_ID: | |
8042 | case BCM43349_CHIP_ID: | |
8043 | bus->dongle_ram_base = CR4_4335_RAM_BASE; | |
8044 | break; | |
8045 | case BCM4350_CHIP_ID: | |
8046 | case BCM4354_CHIP_ID: | |
8047 | case BCM4358_CHIP_ID: | |
8048 | case BCM43569_CHIP_ID: | |
8049 | case BCM4371_CHIP_ID: | |
8050 | bus->dongle_ram_base = CR4_4350_RAM_BASE; | |
8051 | break; | |
8052 | case BCM4360_CHIP_ID: | |
8053 | bus->dongle_ram_base = CR4_4360_RAM_BASE; | |
8054 | break; | |
8055 | CASE_BCM4345_CHIP: | |
8056 | bus->dongle_ram_base = (bus->sih->chiprev < 6) /* from 4345C0 */ | |
8057 | ? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE; | |
8058 | break; | |
8059 | case BCM4349_CHIP_GRPID: | |
8060 | /* RAM based changed from 4349c0(revid=9) onwards */ | |
8061 | bus->dongle_ram_base = ((bus->sih->chiprev < 9) ? | |
8062 | CR4_4349_RAM_BASE: CR4_4349_RAM_BASE_FROM_REV_9); | |
8063 | break; | |
8064 | case BCM4364_CHIP_ID: | |
8065 | bus->dongle_ram_base = CR4_4364_RAM_BASE; | |
8066 | break; | |
8067 | case BCM4347_CHIP_GRPID: | |
8068 | bus->dongle_ram_base = CR4_4347_RAM_BASE; | |
8069 | break; | |
dfb0f3ae RC |
8070 | case BCM4362_CHIP_ID: |
8071 | bus->dongle_ram_base = CR4_4362_RAM_BASE; | |
210a9a5c | 8072 | break; |
010c3a89 RC |
8073 | default: |
8074 | bus->dongle_ram_base = 0; | |
8075 | DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n", | |
8076 | __FUNCTION__, bus->dongle_ram_base)); | |
8077 | } | |
8078 | } | |
8079 | bus->ramsize = bus->orig_ramsize; | |
8080 | if (dhd_dongle_ramsize) | |
8081 | dhd_dongle_setramsize(bus, dhd_dongle_ramsize); | |
8082 | ||
8083 | DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n", | |
8084 | bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base)); | |
8085 | ||
8086 | bus->srmemsize = si_socram_srmem_size(bus->sih); | |
8087 | } | |
8088 | ||
8089 | /* ...but normally deal with the SDPCMDEV core */ | |
8090 | if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) && | |
8091 | !(bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0))) { | |
8092 | DHD_ERROR(("%s: failed to find SDIODEV core!\n", __FUNCTION__)); | |
8093 | goto fail; | |
8094 | } | |
8095 | bus->sdpcmrev = si_corerev(bus->sih); | |
8096 | ||
8097 | /* Set core control so an SDIO reset does a backplane reset */ | |
8098 | OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN); | |
8099 | bus->rxint_mode = SDIO_DEVICE_HMB_RXINT; | |
8100 | ||
8101 | if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) && | |
8102 | (bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_1)) | |
8103 | { | |
8104 | uint32 val; | |
8105 | ||
8106 | val = R_REG(osh, &bus->regs->corecontrol); | |
8107 | val &= ~CC_XMTDATAAVAIL_MODE; | |
8108 | val |= CC_XMTDATAAVAIL_CTRL; | |
8109 | W_REG(osh, &bus->regs->corecontrol, val); | |
8110 | } | |
8111 | ||
8112 | ||
8113 | pktq_init(&bus->txq, (PRIOMASK + 1), QLEN); | |
8114 | ||
8115 | /* Locate an appropriately-aligned portion of hdrbuf */ | |
8116 | bus->rxhdr = (uint8 *)ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN); | |
8117 | ||
8118 | /* Set the poll and/or interrupt flags */ | |
8119 | bus->intr = (bool)dhd_intr; | |
8120 | if ((bus->poll = (bool)dhd_poll)) | |
8121 | bus->pollrate = 1; | |
8122 | ||
8123 | /* Setting default Glom size */ | |
8124 | bus->txglomsize = SDPCM_DEFGLOM_SIZE; | |
8125 | ||
8126 | return TRUE; | |
8127 | ||
8128 | fail: | |
8129 | if (bus->sih != NULL) { | |
8130 | si_detach(bus->sih); | |
8131 | bus->sih = NULL; | |
8132 | } | |
8133 | return FALSE; | |
8134 | } | |
8135 | ||
8136 | static bool | |
8137 | dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh) | |
8138 | { | |
8139 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8140 | ||
8141 | if (bus->dhd->maxctl) { | |
8142 | bus->rxblen = ROUNDUP((bus->dhd->maxctl+SDPCM_HDRLEN), ALIGNMENT) + DHD_SDALIGN; | |
8143 | if (!(bus->rxbuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_RXBUF, bus->rxblen))) { | |
8144 | DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n", | |
8145 | __FUNCTION__, bus->rxblen)); | |
8146 | goto fail; | |
8147 | } | |
8148 | } | |
8149 | /* Allocate buffer to receive glomed packet */ | |
8150 | if (!(bus->databuf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_DATABUF, MAX_DATA_BUF))) { | |
8151 | DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n", | |
8152 | __FUNCTION__, MAX_DATA_BUF)); | |
8153 | /* release rxbuf which was already located as above */ | |
8154 | if (!bus->rxblen) | |
8155 | DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen); | |
8156 | goto fail; | |
8157 | } | |
07d6b24a RC |
8158 | /* Allocate buffer to membuf */ |
8159 | bus->membuf = MALLOC(osh, MAX_MEM_BUF); | |
8160 | if (bus->membuf == NULL) { | |
8161 | DHD_ERROR(("%s: MALLOC of %d-byte membuf failed\n", | |
8162 | __FUNCTION__, MAX_MEM_BUF)); | |
8163 | if (bus->databuf) { | |
8164 | #ifndef CONFIG_DHD_USE_STATIC_BUF | |
8165 | MFREE(osh, bus->databuf, MAX_DATA_BUF); | |
8166 | #endif | |
8167 | bus->databuf = NULL; | |
8168 | } | |
8169 | /* release rxbuf which was already located as above */ | |
8170 | if (!bus->rxblen) | |
8171 | DHD_OS_PREFREE(bus->dhd, bus->rxbuf, bus->rxblen); | |
8172 | goto fail; | |
8173 | } | |
8174 | memset(bus->membuf, 0, MAX_MEM_BUF); | |
010c3a89 RC |
8175 | |
8176 | /* Align the buffer */ | |
8177 | if ((uintptr)bus->databuf % DHD_SDALIGN) | |
8178 | bus->dataptr = bus->databuf + (DHD_SDALIGN - ((uintptr)bus->databuf % DHD_SDALIGN)); | |
8179 | else | |
8180 | bus->dataptr = bus->databuf; | |
8181 | ||
8182 | return TRUE; | |
8183 | ||
8184 | fail: | |
8185 | return FALSE; | |
8186 | } | |
8187 | ||
8188 | static bool | |
8189 | dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh) | |
8190 | { | |
8191 | int32 fnum; | |
8192 | ||
8193 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8194 | ||
8195 | bus->_srenab = FALSE; | |
8196 | ||
8197 | #ifdef SDTEST | |
8198 | dhdsdio_pktgen_init(bus); | |
8199 | #endif /* SDTEST */ | |
8200 | ||
8201 | /* set PMU minimum resource mask to default */ | |
8202 | dhd_bus_set_default_min_res_mask(bus); | |
8203 | /* Disable F2 to clear any intermediate frame state on the dongle */ | |
8204 | bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL); | |
8205 | ||
8206 | bus->dhd->busstate = DHD_BUS_DOWN; | |
8207 | bus->sleeping = FALSE; | |
8208 | bus->rxflow = FALSE; | |
8209 | bus->prev_rxlim_hit = 0; | |
8210 | ||
8211 | /* Done with backplane-dependent accesses, can drop clock... */ | |
8212 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); | |
8213 | ||
8214 | /* ...and initialize clock/power states */ | |
8215 | bus->clkstate = CLK_SDONLY; | |
8216 | bus->idletime = (int32)dhd_idletime; | |
8217 | bus->idleclock = DHD_IDLE_ACTIVE; | |
8218 | ||
8219 | /* Query the SD clock speed */ | |
8220 | if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0, | |
8221 | &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) { | |
8222 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_divisor")); | |
8223 | bus->sd_divisor = -1; | |
8224 | } else { | |
8225 | DHD_INFO(("%s: Initial value for %s is %d\n", | |
8226 | __FUNCTION__, "sd_divisor", bus->sd_divisor)); | |
8227 | } | |
8228 | ||
8229 | /* Query the SD bus mode */ | |
8230 | if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0, | |
8231 | &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) { | |
8232 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_mode")); | |
8233 | bus->sd_mode = -1; | |
8234 | } else { | |
8235 | DHD_INFO(("%s: Initial value for %s is %d\n", | |
8236 | __FUNCTION__, "sd_mode", bus->sd_mode)); | |
8237 | } | |
8238 | ||
8239 | /* Query the F2 block size, set roundup accordingly */ | |
8240 | fnum = 2; | |
8241 | if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(int32), | |
8242 | &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) { | |
8243 | bus->blocksize = 0; | |
8244 | DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize")); | |
8245 | } else { | |
8246 | DHD_INFO(("%s: Initial value for %s is %d\n", | |
8247 | __FUNCTION__, "sd_blocksize", bus->blocksize)); | |
8248 | ||
8249 | dhdsdio_tune_fifoparam(bus); | |
8250 | } | |
8251 | bus->roundup = MIN(max_roundup, bus->blocksize); | |
8252 | ||
8253 | #ifdef DHDENABLE_TAILPAD | |
8254 | if (bus->pad_pkt) | |
8255 | PKTFREE(osh, bus->pad_pkt, FALSE); | |
8256 | bus->pad_pkt = PKTGET(osh, SDIO_MAX_BLOCK_SIZE, FALSE); | |
8257 | if (bus->pad_pkt == NULL) | |
8258 | DHD_ERROR(("failed to allocate padding packet\n")); | |
8259 | else { | |
8260 | int alignment_offset = 0; | |
8261 | uintptr pktprt = (uintptr)PKTDATA(osh, bus->pad_pkt); | |
8262 | if (!(pktprt&1) && (pktprt = (pktprt % DHD_SDALIGN))) | |
8263 | PKTPUSH(osh, bus->pad_pkt, alignment_offset); | |
8264 | PKTSETNEXT(osh, bus->pad_pkt, NULL); | |
8265 | } | |
8266 | #endif /* DHDENABLE_TAILPAD */ | |
8267 | ||
8268 | /* Query if bus module supports packet chaining, default to use if supported */ | |
8269 | if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0, | |
8270 | &bus->sd_rxchain, sizeof(int32), FALSE) != BCME_OK) { | |
8271 | bus->sd_rxchain = FALSE; | |
8272 | } else { | |
8273 | DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n", | |
8274 | __FUNCTION__, (bus->sd_rxchain ? "supports" : "does not support"))); | |
8275 | } | |
8276 | bus->use_rxchain = (bool)bus->sd_rxchain; | |
8277 | bus->txinrx_thres = CUSTOM_TXINRX_THRES; | |
8278 | /* TX first in dhdsdio_readframes() */ | |
8279 | bus->dotxinrx = TRUE; | |
8280 | ||
8281 | #ifdef PKT_STATICS | |
8282 | memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t)); | |
8283 | #endif | |
8284 | ||
8285 | return TRUE; | |
8286 | } | |
8287 | ||
8288 | int | |
8289 | dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh, | |
8290 | char *pfw_path, char *pnv_path, | |
8291 | char *pclm_path, char *pconf_path) | |
8292 | { | |
8293 | int ret; | |
8294 | ||
8295 | bus->fw_path = pfw_path; | |
8296 | bus->nv_path = pnv_path; | |
8297 | bus->dhd->clm_path = pclm_path; | |
8298 | bus->dhd->conf_path = pconf_path; | |
8299 | ||
8300 | ret = dhdsdio_download_firmware(bus, osh, bus->sdh); | |
8301 | ||
8302 | return ret; | |
8303 | } | |
8304 | ||
8305 | void | |
8306 | dhd_set_path_params(struct dhd_bus *bus) | |
8307 | { | |
8308 | /* External conf takes precedence if specified */ | |
8309 | dhd_conf_preinit(bus->dhd); | |
8310 | ||
8311 | if (bus->dhd->conf_path[0] == '\0') { | |
8312 | dhd_conf_set_path(bus->dhd, "config.txt", bus->dhd->conf_path, bus->nv_path); | |
8313 | } | |
8314 | if (bus->dhd->clm_path[0] == '\0') { | |
8315 | dhd_conf_set_path(bus->dhd, "clm.blob", bus->dhd->clm_path, bus->fw_path); | |
8316 | } | |
8317 | #ifdef CONFIG_PATH_AUTO_SELECT | |
8318 | dhd_conf_set_conf_name_by_chip(bus->dhd, bus->dhd->conf_path); | |
8319 | #endif | |
8320 | ||
8321 | dhd_conf_read_config(bus->dhd, bus->dhd->conf_path); | |
8322 | ||
8323 | dhd_conf_set_fw_name_by_chip(bus->dhd, bus->fw_path); | |
8324 | dhd_conf_set_nv_name_by_chip(bus->dhd, bus->nv_path); | |
8325 | dhd_conf_set_clm_name_by_chip(bus->dhd, bus->dhd->clm_path); | |
8326 | ||
8327 | dhd_conf_set_fw_name_by_mac(bus->dhd, bus->sdh, bus->fw_path); | |
8328 | dhd_conf_set_nv_name_by_mac(bus->dhd, bus->sdh, bus->nv_path); | |
8329 | ||
8330 | printf("Final fw_path=%s\n", bus->fw_path); | |
8331 | printf("Final nv_path=%s\n", bus->nv_path); | |
8332 | printf("Final clm_path=%s\n", bus->dhd->clm_path); | |
8333 | printf("Final conf_path=%s\n", bus->dhd->conf_path); | |
8334 | ||
8335 | } | |
8336 | ||
8337 | void | |
8338 | dhd_set_bus_params(struct dhd_bus *bus) | |
8339 | { | |
8340 | if (bus->dhd->conf->dhd_poll >= 0) { | |
8341 | bus->poll = bus->dhd->conf->dhd_poll; | |
8342 | if (!bus->pollrate) | |
8343 | bus->pollrate = 1; | |
8344 | printf("%s: set polling mode %d\n", __FUNCTION__, bus->dhd->conf->dhd_poll); | |
8345 | } | |
8346 | if (bus->dhd->conf->use_rxchain >= 0) { | |
8347 | bus->use_rxchain = (bool)bus->dhd->conf->use_rxchain; | |
010c3a89 RC |
8348 | } |
8349 | if (bus->dhd->conf->txinrx_thres >= 0) { | |
8350 | bus->txinrx_thres = bus->dhd->conf->txinrx_thres; | |
010c3a89 RC |
8351 | } |
8352 | if (bus->dhd->conf->txglomsize >= 0) { | |
8353 | bus->txglomsize = bus->dhd->conf->txglomsize; | |
010c3a89 RC |
8354 | } |
8355 | } | |
8356 | ||
8357 | static int | |
8358 | dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh) | |
8359 | { | |
8360 | int ret; | |
8361 | ||
8362 | ||
8363 | #if defined(DHD_BLOB_EXISTENCE_CHECK) | |
8364 | dhd_set_blob_support(bus->dhd, bus->fw_path); | |
8365 | #endif /* DHD_BLOB_EXISTENCE_CHECK */ | |
8366 | ||
8367 | DHD_TRACE_HW4(("%s: firmware path=%s, nvram path=%s\n", | |
8368 | __FUNCTION__, bus->fw_path, bus->nv_path)); | |
8369 | DHD_OS_WAKE_LOCK(bus->dhd); | |
8370 | ||
8371 | /* Download the firmware */ | |
8372 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
8373 | ||
8374 | dhd_set_path_params(bus); | |
8375 | dhd_set_bus_params(bus); | |
8376 | ||
8377 | ret = _dhdsdio_download_firmware(bus); | |
8378 | ||
8379 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
8380 | ||
8381 | DHD_OS_WAKE_UNLOCK(bus->dhd); | |
8382 | return ret; | |
8383 | } | |
8384 | ||
8385 | /* Detach and free everything */ | |
8386 | static void | |
8387 | dhdsdio_release(dhd_bus_t *bus, osl_t *osh) | |
8388 | { | |
8389 | bool dongle_isolation = FALSE; | |
8390 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8391 | ||
8392 | if (bus) { | |
8393 | ASSERT(osh); | |
8394 | ||
8395 | if (bus->dhd) { | |
8396 | dongle_isolation = bus->dhd->dongle_isolation; | |
8397 | dhd_detach(bus->dhd); | |
8398 | } | |
8399 | ||
8400 | /* De-register interrupt handler */ | |
8401 | bcmsdh_intr_disable(bus->sdh); | |
8402 | bcmsdh_intr_dereg(bus->sdh); | |
8403 | ||
8404 | if (bus->dhd) { | |
8405 | dhdsdio_release_dongle(bus, osh, dongle_isolation, TRUE); | |
8406 | dhd_free(bus->dhd); | |
8407 | bus->dhd = NULL; | |
8408 | } | |
8409 | ||
8410 | dhdsdio_release_malloc(bus, osh); | |
8411 | ||
8412 | #ifdef DHD_DEBUG | |
8413 | if (bus->console.buf != NULL) | |
8414 | MFREE(osh, bus->console.buf, bus->console.bufsize); | |
8415 | #endif | |
8416 | ||
8417 | #ifdef DHDENABLE_TAILPAD | |
8418 | if (bus->pad_pkt) | |
8419 | PKTFREE(osh, bus->pad_pkt, FALSE); | |
8420 | #endif /* DHDENABLE_TAILPAD */ | |
8421 | ||
8422 | MFREE(osh, bus, sizeof(dhd_bus_t)); | |
8423 | } | |
8424 | ||
8425 | DHD_TRACE(("%s: Disconnected\n", __FUNCTION__)); | |
8426 | } | |
8427 | ||
8428 | static void | |
8429 | dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh) | |
8430 | { | |
8431 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8432 | ||
8433 | if (bus->dhd && bus->dhd->dongle_reset) | |
8434 | return; | |
8435 | ||
8436 | if (bus->rxbuf) { | |
8437 | #ifndef CONFIG_DHD_USE_STATIC_BUF | |
8438 | MFREE(osh, bus->rxbuf, bus->rxblen); | |
8439 | #endif | |
8440 | bus->rxctl = bus->rxbuf = NULL; | |
8441 | bus->rxlen = 0; | |
8442 | } | |
8443 | ||
8444 | if (bus->databuf) { | |
8445 | #ifndef CONFIG_DHD_USE_STATIC_BUF | |
8446 | MFREE(osh, bus->databuf, MAX_DATA_BUF); | |
8447 | #endif | |
8448 | bus->databuf = NULL; | |
8449 | } | |
8450 | ||
07d6b24a RC |
8451 | if (bus->membuf) { |
8452 | MFREE(osh, bus->membuf, MAX_DATA_BUF); | |
8453 | bus->membuf = NULL; | |
8454 | } | |
8455 | ||
010c3a89 RC |
8456 | if (bus->vars && bus->varsz) { |
8457 | MFREE(osh, bus->vars, bus->varsz); | |
8458 | bus->vars = NULL; | |
8459 | } | |
8460 | ||
8461 | } | |
8462 | ||
8463 | ||
8464 | static void | |
8465 | dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag) | |
8466 | { | |
8467 | DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__, | |
8468 | bus->dhd, bus->dhd->dongle_reset)); | |
8469 | ||
8470 | if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) | |
8471 | return; | |
8472 | ||
8473 | if (bus->sih) { | |
8474 | /* In Win10, system will be BSOD if using "sysprep" to do OS image */ | |
8475 | /* Skip this will not cause the BSOD. */ | |
8476 | #if !defined(BCMLXSDMMC) | |
8477 | if (bus->dhd) { | |
8478 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
8479 | } | |
8480 | if (KSO_ENAB(bus) && (dongle_isolation == FALSE)) | |
8481 | si_watchdog(bus->sih, 4); | |
8482 | #endif /* !defined(BCMLXSDMMC) */ | |
8483 | if (bus->dhd) { | |
8484 | dhdsdio_clkctl(bus, CLK_NONE, FALSE); | |
8485 | } | |
8486 | si_detach(bus->sih); | |
8487 | bus->sih = NULL; | |
8488 | if (bus->vars && bus->varsz) | |
8489 | MFREE(osh, bus->vars, bus->varsz); | |
8490 | bus->vars = NULL; | |
8491 | } | |
8492 | ||
8493 | DHD_TRACE(("%s: Disconnected\n", __FUNCTION__)); | |
8494 | } | |
8495 | ||
8496 | static void | |
8497 | dhdsdio_disconnect(void *ptr) | |
8498 | { | |
8499 | dhd_bus_t *bus = (dhd_bus_t *)ptr; | |
8500 | ||
8501 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8502 | ||
d964ce36 | 8503 | DHD_MUTEX_LOCK(); |
010c3a89 RC |
8504 | if (bus) { |
8505 | ASSERT(bus->dhd); | |
ccd15baf RC |
8506 | /* Advertise bus remove during rmmod */ |
8507 | dhdsdio_advertise_bus_remove(bus->dhd); | |
010c3a89 RC |
8508 | dhdsdio_release(bus, bus->dhd->osh); |
8509 | } | |
d964ce36 | 8510 | DHD_MUTEX_UNLOCK(); |
010c3a89 RC |
8511 | |
8512 | DHD_TRACE(("%s: Disconnected\n", __FUNCTION__)); | |
8513 | } | |
8514 | ||
8515 | static int | |
8516 | dhdsdio_suspend(void *context) | |
8517 | { | |
8518 | int ret = 0; | |
8519 | #ifdef SUPPORT_P2P_GO_PS | |
8520 | int wait_time = 0; | |
8521 | #endif /* SUPPORT_P2P_GO_PS */ | |
8522 | ||
8523 | dhd_bus_t *bus = (dhd_bus_t*)context; | |
8524 | unsigned long flags; | |
8525 | ||
8526 | DHD_ERROR(("%s Enter\n", __FUNCTION__)); | |
8527 | if (bus->dhd == NULL) { | |
8528 | DHD_ERROR(("bus not inited\n")); | |
8529 | return BCME_ERROR; | |
8530 | } | |
8531 | if (bus->dhd->prot == NULL) { | |
8532 | DHD_ERROR(("prot is not inited\n")); | |
8533 | return BCME_ERROR; | |
8534 | } | |
8535 | ||
8536 | if (bus->dhd->up == FALSE) { | |
8537 | return BCME_OK; | |
8538 | } | |
8539 | ||
8540 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
8541 | if (bus->dhd->busstate != DHD_BUS_DATA && bus->dhd->busstate != DHD_BUS_SUSPEND) { | |
8542 | DHD_ERROR(("not in a readystate to LPBK is not inited\n")); | |
8543 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8544 | return BCME_ERROR; | |
8545 | } | |
8546 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8547 | if (bus->dhd->dongle_reset) { | |
8548 | DHD_ERROR(("Dongle is in reset state.\n")); | |
8549 | return -EIO; | |
8550 | } | |
8551 | ||
8552 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
8553 | bus->dhd->busstate = DHD_BUS_SUSPEND; | |
8554 | if (DHD_BUS_BUSY_CHECK_IN_TX(bus->dhd)) { | |
8555 | DHD_ERROR(("Tx Request is not ended\n")); | |
8556 | bus->dhd->busstate = DHD_BUS_DATA; | |
8557 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8558 | return -EBUSY; | |
8559 | } | |
8560 | DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd); | |
8561 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8562 | ||
8563 | #ifdef SUPPORT_P2P_GO_PS | |
8564 | if (bus->idletime > 0) { | |
8565 | wait_time = msecs_to_jiffies(bus->idletime * dhd_watchdog_ms); | |
8566 | } | |
8567 | #endif /* SUPPORT_P2P_GO_PS */ | |
8568 | ret = dhd_os_check_wakelock(bus->dhd); | |
8569 | #ifdef SUPPORT_P2P_GO_PS | |
8570 | // terence 20141124: fix for suspend issue | |
8571 | if (SLPAUTO_ENAB(bus) && (!ret) && (bus->dhd->up) && (bus->dhd->op_mode != DHD_FLAG_HOSTAP_MODE)) { | |
8572 | if (wait_event_timeout(bus->bus_sleep, bus->sleeping, wait_time) == 0) { | |
8573 | if (!bus->sleeping) { | |
8574 | ret = 1; | |
8575 | } | |
8576 | } | |
8577 | } | |
8578 | #endif /* SUPPORT_P2P_GO_PS */ | |
8579 | ||
8580 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
8581 | if (ret) { | |
8582 | bus->dhd->busstate = DHD_BUS_DATA; | |
8583 | } | |
8584 | DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd); | |
8585 | dhd_os_busbusy_wake(bus->dhd); | |
8586 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8587 | return ret; | |
8588 | } | |
8589 | ||
8590 | static int | |
8591 | dhdsdio_resume(void *context) | |
8592 | { | |
8593 | dhd_bus_t *bus = (dhd_bus_t*)context; | |
8594 | ulong flags; | |
8595 | ||
8596 | DHD_ERROR(("%s Enter\n", __FUNCTION__)); | |
8597 | ||
8598 | if (bus->dhd->up == FALSE) { | |
8599 | return BCME_OK; | |
8600 | } | |
8601 | ||
8602 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
8603 | DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd); | |
8604 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8605 | ||
8606 | #if defined(OOB_INTR_ONLY) | |
8607 | if (dhd_os_check_if_up(bus->dhd)) | |
8608 | bcmsdh_oob_intr_set(bus->sdh, TRUE); | |
8609 | #endif | |
8610 | ||
8611 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
8612 | DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd); | |
8613 | bus->dhd->busstate = DHD_BUS_DATA; | |
8614 | dhd_os_busbusy_wake(bus->dhd); | |
8615 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
8616 | ||
8617 | return 0; | |
8618 | } | |
8619 | ||
8620 | ||
8621 | /* Register/Unregister functions are called by the main DHD entry | |
8622 | * point (e.g. module insertion) to link with the bus driver, in | |
8623 | * order to look for or await the device. | |
8624 | */ | |
8625 | ||
8626 | static bcmsdh_driver_t dhd_sdio = { | |
8627 | dhdsdio_probe, | |
8628 | dhdsdio_disconnect, | |
8629 | dhdsdio_suspend, | |
8630 | dhdsdio_resume | |
8631 | }; | |
8632 | ||
8633 | int | |
8634 | dhd_bus_register(void) | |
8635 | { | |
8636 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8637 | ||
8638 | return bcmsdh_register(&dhd_sdio); | |
8639 | } | |
8640 | ||
8641 | void | |
8642 | dhd_bus_unregister(void) | |
8643 | { | |
8644 | DHD_TRACE(("%s: Enter\n", __FUNCTION__)); | |
8645 | ||
8646 | bcmsdh_unregister(); | |
8647 | } | |
8648 | ||
8649 | #if defined(BCMLXSDMMC) | |
8650 | /* Register a dummy SDIO client driver in order to be notified of new SDIO device */ | |
8651 | int dhd_bus_reg_sdio_notify(void* semaphore) | |
8652 | { | |
8653 | return bcmsdh_reg_sdio_notify(semaphore); | |
8654 | } | |
8655 | ||
8656 | void dhd_bus_unreg_sdio_notify(void) | |
8657 | { | |
8658 | bcmsdh_unreg_sdio_notify(); | |
8659 | } | |
8660 | #endif /* defined(BCMLXSDMMC) */ | |
8661 | ||
8662 | #ifdef BCMEMBEDIMAGE | |
8663 | static int | |
8664 | dhdsdio_download_code_array(struct dhd_bus *bus) | |
8665 | { | |
8666 | int bcmerror = -1; | |
8667 | int offset = 0; | |
8668 | unsigned char *ularray = NULL; | |
8669 | ||
8670 | DHD_INFO(("%s: download embedded firmware...\n", __FUNCTION__)); | |
8671 | ||
8672 | /* Download image */ | |
8673 | while ((offset + MEMBLOCK) < sizeof(dlarray)) { | |
8674 | /* check if CR4 */ | |
8675 | if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { | |
8676 | /* if address is 0, store the reset instruction to be written in 0 */ | |
8677 | ||
8678 | if (offset == 0) { | |
8679 | bus->resetinstr = *(((uint32*)dlarray)); | |
8680 | /* Add start of RAM address to the address given by user */ | |
8681 | offset += bus->dongle_ram_base; | |
8682 | } | |
8683 | } | |
8684 | ||
8685 | bcmerror = dhdsdio_membytes(bus, TRUE, offset, | |
8686 | (uint8 *) (dlarray + offset), MEMBLOCK); | |
8687 | if (bcmerror) { | |
8688 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
8689 | __FUNCTION__, bcmerror, MEMBLOCK, offset)); | |
8690 | goto err; | |
8691 | } | |
8692 | ||
8693 | offset += MEMBLOCK; | |
8694 | } | |
8695 | ||
8696 | if (offset < sizeof(dlarray)) { | |
8697 | bcmerror = dhdsdio_membytes(bus, TRUE, offset, | |
8698 | (uint8 *) (dlarray + offset), sizeof(dlarray) - offset); | |
8699 | if (bcmerror) { | |
8700 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
8701 | __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset)); | |
8702 | goto err; | |
8703 | } | |
8704 | } | |
8705 | ||
8706 | #ifdef DHD_DEBUG | |
8707 | /* Upload and compare the downloaded code */ | |
8708 | { | |
8709 | ularray = MALLOC(bus->dhd->osh, bus->ramsize); | |
8710 | /* Upload image to verify downloaded contents. */ | |
8711 | offset = 0; | |
8712 | memset(ularray, 0xaa, bus->ramsize); | |
8713 | while ((offset + MEMBLOCK) < sizeof(dlarray)) { | |
8714 | bcmerror = dhdsdio_membytes(bus, FALSE, offset, ularray + offset, MEMBLOCK); | |
8715 | if (bcmerror) { | |
8716 | DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n", | |
8717 | __FUNCTION__, bcmerror, MEMBLOCK, offset)); | |
8718 | goto err; | |
8719 | } | |
8720 | ||
8721 | offset += MEMBLOCK; | |
8722 | } | |
8723 | ||
8724 | if (offset < sizeof(dlarray)) { | |
8725 | bcmerror = dhdsdio_membytes(bus, FALSE, offset, | |
8726 | ularray + offset, sizeof(dlarray) - offset); | |
8727 | if (bcmerror) { | |
8728 | DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n", | |
8729 | __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset)); | |
8730 | goto err; | |
8731 | } | |
8732 | } | |
8733 | ||
8734 | if (memcmp(dlarray, ularray, sizeof(dlarray))) { | |
8735 | DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n", | |
8736 | __FUNCTION__, dlimagename, dlimagever, dlimagedate)); | |
8737 | goto err; | |
8738 | } else | |
8739 | DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n", | |
8740 | __FUNCTION__, dlimagename, dlimagever, dlimagedate)); | |
8741 | ||
8742 | } | |
8743 | #endif /* DHD_DEBUG */ | |
8744 | ||
8745 | err: | |
8746 | if (ularray) | |
8747 | MFREE(bus->dhd->osh, ularray, bus->ramsize); | |
8748 | return bcmerror; | |
8749 | } | |
8750 | #endif /* BCMEMBEDIMAGE */ | |
8751 | ||
8752 | static int | |
8753 | dhdsdio_download_code_file(struct dhd_bus *bus, char *pfw_path) | |
8754 | { | |
8755 | int bcmerror = -1; | |
8756 | int offset = 0; | |
8757 | int len; | |
8758 | void *image = NULL; | |
8759 | uint8 *memblock = NULL, *memptr; | |
8760 | uint8 *memptr_tmp = NULL; // terence: check downloaded firmware is correct | |
8761 | uint memblock_size = MEMBLOCK; | |
8762 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8763 | unsigned long initial_jiffies = 0; | |
8764 | uint firmware_sz = 0; | |
8765 | #endif | |
8766 | ||
8767 | DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, pfw_path)); | |
8768 | ||
8769 | image = dhd_os_open_image(pfw_path); | |
8770 | if (image == NULL) { | |
8771 | printf("%s: Open firmware file failed %s\n", __FUNCTION__, pfw_path); | |
8772 | goto err; | |
8773 | } | |
8774 | ||
8775 | /* Update the dongle image download block size depending on the F1 block size */ | |
8776 | if (sd_f1_blocksize == 512) | |
8777 | memblock_size = MAX_MEMBLOCK; | |
8778 | ||
8779 | memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN); | |
8780 | if (memblock == NULL) { | |
8781 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, | |
8782 | memblock_size)); | |
8783 | goto err; | |
8784 | } | |
8785 | if (dhd_msg_level & DHD_TRACE_VAL) { | |
8786 | memptr_tmp = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); | |
8787 | if (memptr_tmp == NULL) { | |
8788 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); | |
8789 | goto err; | |
8790 | } | |
8791 | } | |
8792 | if ((uint32)(uintptr)memblock % DHD_SDALIGN) | |
8793 | memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN)); | |
8794 | ||
8795 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8796 | initial_jiffies = jiffies; | |
8797 | #endif | |
8798 | ||
8799 | /* Download image */ | |
8800 | while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) { | |
8801 | // terence 20150412: fix for firmware failed to download | |
8802 | if (bus->dhd->conf->chip == BCM43340_CHIP_ID || | |
8803 | bus->dhd->conf->chip == BCM43341_CHIP_ID) { | |
8804 | if (len % 64 != 0) { | |
8805 | memset(memptr+len, 0, len%64); | |
8806 | len += (64 - len%64); | |
8807 | } | |
8808 | } | |
8809 | if (len < 0) { | |
8810 | DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len)); | |
8811 | bcmerror = BCME_ERROR; | |
8812 | goto err; | |
8813 | } | |
8814 | /* check if CR4 */ | |
8815 | if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { | |
8816 | /* if address is 0, store the reset instruction to be written in 0 */ | |
8817 | ||
8818 | if (offset == 0) { | |
8819 | bus->resetinstr = *(((uint32*)memptr)); | |
8820 | /* Add start of RAM address to the address given by user */ | |
8821 | offset += bus->dongle_ram_base; | |
8822 | } | |
8823 | } | |
8824 | ||
8825 | bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len); | |
8826 | if (bcmerror) { | |
8827 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
8828 | __FUNCTION__, bcmerror, memblock_size, offset)); | |
8829 | goto err; | |
8830 | } | |
8831 | ||
8832 | if (dhd_msg_level & DHD_TRACE_VAL) { | |
8833 | bcmerror = dhdsdio_membytes(bus, FALSE, offset, memptr_tmp, len); | |
8834 | if (bcmerror) { | |
8835 | DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n", | |
8836 | __FUNCTION__, bcmerror, MEMBLOCK, offset)); | |
8837 | goto err; | |
8838 | } | |
8839 | if (memcmp(memptr_tmp, memptr, len)) { | |
8840 | DHD_ERROR(("%s: Downloaded image is corrupted.\n", __FUNCTION__)); | |
8841 | goto err; | |
8842 | } else | |
8843 | DHD_INFO(("%s: Download, Upload and compare succeeded.\n", __FUNCTION__)); | |
8844 | } | |
8845 | ||
8846 | offset += memblock_size; | |
8847 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8848 | firmware_sz += len; | |
8849 | #endif | |
8850 | } | |
8851 | ||
8852 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8853 | DHD_ERROR(("Firmware download time for %u bytes: %u ms\n", | |
8854 | firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies))); | |
8855 | #endif | |
8856 | ||
8857 | err: | |
8858 | if (memblock) | |
8859 | MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN); | |
8860 | if (dhd_msg_level & DHD_TRACE_VAL) { | |
8861 | if (memptr_tmp) | |
8862 | MFREE(bus->dhd->osh, memptr_tmp, MEMBLOCK + DHD_SDALIGN); | |
8863 | } | |
8864 | ||
8865 | if (image) | |
8866 | dhd_os_close_image(image); | |
8867 | ||
8868 | return bcmerror; | |
8869 | } | |
8870 | ||
8871 | #ifdef DHD_UCODE_DOWNLOAD | |
8872 | /* Currently supported only for the chips in which ucode RAM is AXI addressable */ | |
8873 | static uint32 | |
8874 | dhdsdio_ucode_base(struct dhd_bus *bus) | |
8875 | { | |
8876 | uint32 ucode_base = 0; | |
8877 | ||
8878 | switch ((uint16)bus->sih->chip) { | |
8879 | case BCM43012_CHIP_ID: | |
8880 | ucode_base = 0xE8020000; | |
8881 | break; | |
8882 | default: | |
8883 | DHD_ERROR(("%s: Unsupported!\n", __func__)); | |
8884 | break; | |
8885 | } | |
8886 | ||
8887 | return ucode_base; | |
8888 | } | |
8889 | ||
8890 | static int | |
8891 | dhdsdio_download_ucode_file(struct dhd_bus *bus, char *ucode_path) | |
8892 | { | |
8893 | int bcmerror = -1; | |
8894 | int offset = 0; | |
8895 | int len; | |
8896 | uint32 ucode_base; | |
8897 | void *image = NULL; | |
8898 | uint8 *memblock = NULL, *memptr; | |
8899 | uint memblock_size = MEMBLOCK; | |
8900 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8901 | unsigned long initial_jiffies = 0; | |
8902 | uint firmware_sz = 0; | |
8903 | #endif | |
8904 | ||
8905 | DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, ucode_path)); | |
8906 | ||
8907 | ucode_base = dhdsdio_ucode_base(bus); | |
8908 | ||
8909 | image = dhd_os_open_image(ucode_path); | |
8910 | if (image == NULL) | |
8911 | goto err; | |
8912 | ||
8913 | /* Update the dongle image download block size depending on the F1 block size */ | |
8914 | if (sd_f1_blocksize == 512) | |
8915 | memblock_size = MAX_MEMBLOCK; | |
8916 | ||
8917 | memptr = memblock = MALLOC(bus->dhd->osh, memblock_size + DHD_SDALIGN); | |
8918 | if (memblock == NULL) { | |
8919 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, | |
8920 | memblock_size)); | |
8921 | goto err; | |
8922 | } | |
8923 | if ((uint32)(uintptr)memblock % DHD_SDALIGN) | |
8924 | memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN)); | |
8925 | ||
8926 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8927 | initial_jiffies = jiffies; | |
8928 | #endif | |
8929 | ||
8930 | /* Download image */ | |
8931 | while ((len = dhd_os_get_image_block((char*)memptr, memblock_size, image))) { | |
8932 | if (len < 0) { | |
8933 | DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len)); | |
8934 | bcmerror = BCME_ERROR; | |
8935 | goto err; | |
8936 | } | |
8937 | ||
8938 | bcmerror = dhdsdio_membytes(bus, TRUE, (ucode_base + offset), memptr, len); | |
8939 | if (bcmerror) { | |
8940 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
8941 | __FUNCTION__, bcmerror, memblock_size, offset)); | |
8942 | goto err; | |
8943 | } | |
8944 | ||
8945 | offset += memblock_size; | |
8946 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8947 | firmware_sz += len; | |
8948 | #endif | |
8949 | } | |
8950 | ||
8951 | #ifdef DHD_DEBUG_DOWNLOADTIME | |
8952 | DHD_ERROR(("ucode download time for %u bytes: %u ms\n", | |
8953 | firmware_sz, jiffies_to_msecs(jiffies - initial_jiffies))); | |
8954 | #endif | |
8955 | ||
8956 | err: | |
8957 | if (memblock) | |
8958 | MFREE(bus->dhd->osh, memblock, memblock_size + DHD_SDALIGN); | |
8959 | ||
8960 | if (image) | |
8961 | dhd_os_close_image(image); | |
8962 | ||
8963 | return bcmerror; | |
8964 | } | |
8965 | ||
8966 | void | |
8967 | dhd_bus_ucode_download(struct dhd_bus *bus) | |
8968 | { | |
8969 | uint32 shaddr = 0, shdata = 0; | |
8970 | ||
8971 | shaddr = bus->dongle_ram_base + bus->ramsize - 4; | |
8972 | dhdsdio_membytes(bus, FALSE, shaddr, (uint8 *)&shdata, 4); | |
8973 | ||
8974 | DHD_TRACE(("%s: shdata:[0x%08x :0x%08x]\n", __func__, shaddr, shdata)); | |
8975 | ||
8976 | if (shdata == UCODE_DOWNLOAD_REQUEST) | |
8977 | { | |
8978 | DHD_ERROR(("%s: Received ucode download request!\n", __func__)); | |
8979 | ||
8980 | /* Download the ucode */ | |
8981 | if (!dhd_get_ucode_path(bus->dhd)) { | |
8982 | DHD_ERROR(("%s: bus->uc_path not set!\n", __func__)); | |
8983 | return; | |
8984 | } | |
8985 | dhdsdio_download_ucode_file(bus, dhd_get_ucode_path(bus->dhd)); | |
8986 | ||
8987 | DHD_ERROR(("%s: Ucode downloaded successfully!\n", __func__)); | |
8988 | ||
8989 | shdata = UCODE_DOWNLOAD_COMPLETE; | |
8990 | dhdsdio_membytes(bus, TRUE, shaddr, (uint8 *)&shdata, 4); | |
8991 | } | |
8992 | } | |
8993 | ||
8994 | #endif /* DHD_UCODE_DOWNLOAD */ | |
8995 | ||
8996 | static int | |
8997 | dhdsdio_download_nvram(struct dhd_bus *bus) | |
8998 | { | |
8999 | int bcmerror = -1; | |
9000 | uint len; | |
9001 | void * image = NULL; | |
9002 | char * memblock = NULL; | |
9003 | char *bufp; | |
9004 | char *pnv_path; | |
9005 | bool nvram_file_exists; | |
9006 | ||
9007 | pnv_path = bus->nv_path; | |
9008 | ||
9009 | nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0')); | |
9010 | ||
9011 | /* For Get nvram from UEFI */ | |
9012 | if (nvram_file_exists) { | |
9013 | image = dhd_os_open_image(pnv_path); | |
9014 | if (image == NULL) { | |
9015 | printf("%s: Open nvram file failed %s\n", __FUNCTION__, pnv_path); | |
9016 | goto err; | |
9017 | } | |
9018 | } | |
9019 | ||
9020 | memblock = MALLOC(bus->dhd->osh, MAX_NVRAMBUF_SIZE); | |
9021 | if (memblock == NULL) { | |
9022 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", | |
9023 | __FUNCTION__, MAX_NVRAMBUF_SIZE)); | |
9024 | goto err; | |
9025 | } | |
9026 | ||
9027 | /* For Get nvram from image or UEFI (when image == NULL ) */ | |
9028 | len = dhd_os_get_image_block(memblock, MAX_NVRAMBUF_SIZE, image); | |
9029 | ||
9030 | if (len > 0 && len < MAX_NVRAMBUF_SIZE) { | |
9031 | bufp = (char *)memblock; | |
9032 | bufp[len] = 0; | |
9033 | len = process_nvram_vars(bufp, len); | |
9034 | if (len % 4) { | |
9035 | len += 4 - (len % 4); | |
9036 | } | |
9037 | bufp += len; | |
9038 | *bufp++ = 0; | |
9039 | if (len) | |
9040 | bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1); | |
9041 | if (bcmerror) { | |
9042 | DHD_ERROR(("%s: error downloading vars: %d\n", | |
9043 | __FUNCTION__, bcmerror)); | |
9044 | } | |
9045 | } else { | |
9046 | DHD_ERROR(("%s: error reading nvram file: %d\n", | |
9047 | __FUNCTION__, len)); | |
9048 | bcmerror = BCME_SDIO_ERROR; | |
9049 | } | |
9050 | ||
9051 | err: | |
9052 | if (memblock) | |
9053 | MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE); | |
9054 | ||
9055 | if (image) | |
9056 | dhd_os_close_image(image); | |
9057 | ||
9058 | return bcmerror; | |
9059 | } | |
9060 | ||
9061 | static int | |
9062 | _dhdsdio_download_firmware(struct dhd_bus *bus) | |
9063 | { | |
9064 | int bcmerror = -1; | |
9065 | ||
9066 | bool embed = FALSE; /* download embedded firmware */ | |
9067 | bool dlok = FALSE; /* download firmware succeeded */ | |
9068 | ||
9069 | /* Out immediately if no image to download */ | |
9070 | if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) { | |
9071 | #ifdef BCMEMBEDIMAGE | |
9072 | embed = TRUE; | |
9073 | #else | |
9074 | return 0; | |
9075 | #endif | |
9076 | } | |
9077 | ||
9078 | /* Keep arm in reset */ | |
9079 | if (dhdsdio_download_state(bus, TRUE)) { | |
9080 | DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__)); | |
9081 | goto err; | |
9082 | } | |
9083 | ||
9084 | /* External image takes precedence if specified */ | |
9085 | if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) { | |
9086 | if (dhdsdio_download_code_file(bus, bus->fw_path)) { | |
9087 | DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__)); | |
9088 | #ifdef BCMEMBEDIMAGE | |
9089 | embed = TRUE; | |
9090 | #else | |
9091 | goto err; | |
9092 | #endif | |
9093 | } else { | |
9094 | embed = FALSE; | |
9095 | dlok = TRUE; | |
9096 | } | |
9097 | } | |
9098 | ||
9099 | #ifdef BCMEMBEDIMAGE | |
9100 | if (embed) { | |
9101 | if (dhdsdio_download_code_array(bus)) { | |
9102 | DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__)); | |
9103 | goto err; | |
9104 | } else { | |
9105 | dlok = TRUE; | |
9106 | } | |
9107 | } | |
9108 | #else | |
9109 | BCM_REFERENCE(embed); | |
9110 | #endif | |
9111 | if (!dlok) { | |
9112 | DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__)); | |
9113 | goto err; | |
9114 | } | |
9115 | ||
9116 | /* External nvram takes precedence if specified */ | |
9117 | if (dhdsdio_download_nvram(bus)) { | |
9118 | DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__)); | |
9119 | goto err; | |
9120 | } | |
9121 | ||
9122 | /* Take arm out of reset */ | |
9123 | if (dhdsdio_download_state(bus, FALSE)) { | |
9124 | DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__)); | |
9125 | goto err; | |
9126 | } | |
9127 | ||
9128 | bcmerror = 0; | |
9129 | ||
9130 | err: | |
9131 | return bcmerror; | |
9132 | } | |
9133 | ||
9134 | static int | |
9135 | dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes, | |
9136 | void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle) | |
9137 | { | |
9138 | int status; | |
9139 | ||
9140 | if (!KSO_ENAB(bus)) { | |
9141 | DHD_ERROR(("%s: Device asleep\n", __FUNCTION__)); | |
9142 | return BCME_NODEVICE; | |
9143 | } | |
9144 | ||
9145 | status = bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete_fn, handle); | |
9146 | ||
9147 | return status; | |
9148 | } | |
9149 | ||
9150 | static int | |
9151 | dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes, | |
9152 | void *pkt, bcmsdh_cmplt_fn_t complete_fn, void *handle, int max_retry) | |
9153 | { | |
9154 | int ret; | |
9155 | int i = 0; | |
9156 | int retries = 0; | |
9157 | bcmsdh_info_t *sdh; | |
9158 | ||
9159 | if (!KSO_ENAB(bus)) { | |
9160 | DHD_ERROR(("%s: Device asleep\n", __FUNCTION__)); | |
9161 | return BCME_NODEVICE; | |
9162 | } | |
9163 | ||
9164 | sdh = bus->sdh; | |
9165 | do { | |
9166 | ret = bcmsdh_send_buf(bus->sdh, addr, fn, flags, buf, nbytes, | |
9167 | pkt, complete_fn, handle); | |
9168 | ||
9169 | bus->f2txdata++; | |
9170 | ASSERT(ret != BCME_PENDING); | |
9171 | ||
9172 | if (ret == BCME_NODEVICE) { | |
9173 | DHD_ERROR(("%s: Device asleep already\n", __FUNCTION__)); | |
9174 | } else if (ret < 0) { | |
9175 | /* On failure, abort the command and terminate the frame */ | |
9176 | DHD_ERROR(("%s: sdio error %d, abort command and terminate frame.\n", | |
9177 | __FUNCTION__, ret)); | |
9178 | bus->tx_sderrs++; | |
9179 | bus->f1regdata++; | |
9180 | bus->dhd->tx_errors++; | |
9181 | bcmsdh_abort(sdh, SDIO_FUNC_2); | |
9182 | bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, | |
9183 | SFC_WF_TERM, NULL); | |
9184 | for (i = 0; i < READ_FRM_CNT_RETRIES; i++) { | |
9185 | uint8 hi, lo; | |
9186 | hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCHI, | |
9187 | NULL); | |
9188 | lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_WFRAMEBCLO, | |
9189 | NULL); | |
9190 | bus->f1regdata += 2; | |
9191 | if ((hi == 0) && (lo == 0)) | |
9192 | break; | |
9193 | } | |
9194 | } | |
9195 | } while ((ret < 0) && retrydata && ++retries < max_retry); | |
9196 | ||
9197 | return ret; | |
9198 | } | |
9199 | ||
9200 | uint8 | |
9201 | dhd_bus_is_ioready(struct dhd_bus *bus) | |
9202 | { | |
9203 | uint8 enable; | |
9204 | bcmsdh_info_t *sdh; | |
9205 | ASSERT(bus); | |
9206 | ASSERT(bus->sih != NULL); | |
9207 | enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2); | |
9208 | sdh = bus->sdh; | |
9209 | return (enable == bcmsdh_cfg_read(sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL)); | |
9210 | } | |
9211 | ||
9212 | uint | |
9213 | dhd_bus_chip(struct dhd_bus *bus) | |
9214 | { | |
9215 | ASSERT(bus->sih != NULL); | |
9216 | return bus->sih->chip; | |
9217 | } | |
9218 | ||
9219 | uint | |
9220 | dhd_bus_chiprev(struct dhd_bus *bus) | |
9221 | { | |
9222 | ASSERT(bus); | |
9223 | ASSERT(bus->sih != NULL); | |
9224 | return bus->sih->chiprev; | |
9225 | } | |
9226 | ||
9227 | void * | |
9228 | dhd_bus_pub(struct dhd_bus *bus) | |
9229 | { | |
9230 | return bus->dhd; | |
9231 | } | |
9232 | ||
9233 | const void * | |
9234 | dhd_bus_sih(struct dhd_bus *bus) | |
9235 | { | |
9236 | return (const void *)bus->sih; | |
9237 | } | |
9238 | ||
9239 | void * | |
9240 | dhd_bus_txq(struct dhd_bus *bus) | |
9241 | { | |
9242 | return &bus->txq; | |
9243 | } | |
9244 | ||
9245 | uint | |
9246 | dhd_bus_hdrlen(struct dhd_bus *bus) | |
9247 | { | |
9248 | return (bus->txglom_enable) ? SDPCM_HDRLEN_TXGLOM : SDPCM_HDRLEN; | |
9249 | } | |
9250 | ||
9251 | void | |
9252 | dhd_bus_set_dotxinrx(struct dhd_bus *bus, bool val) | |
9253 | { | |
9254 | bus->dotxinrx = val; | |
9255 | } | |
9256 | ||
9257 | /* | |
9258 | * dhdsdio_advertise_bus_cleanup advertises that clean up is under progress | |
9259 | * to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts | |
9260 | * to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for | |
9261 | * whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so | |
9262 | * they will exit from there itself without marking dhd_bus_busy_state as BUSY. | |
9263 | */ | |
9264 | static void | |
9265 | dhdsdio_advertise_bus_cleanup(dhd_pub_t *dhdp) | |
9266 | { | |
9267 | unsigned long flags; | |
9268 | int timeleft; | |
9269 | ||
9270 | DHD_LINUX_GENERAL_LOCK(dhdp, flags); | |
9271 | dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS; | |
9272 | DHD_LINUX_GENERAL_UNLOCK(dhdp, flags); | |
9273 | ||
9274 | timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state); | |
9275 | if ((timeleft == 0) || (timeleft == 1)) { | |
9276 | DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n", | |
9277 | __FUNCTION__, dhdp->dhd_bus_busy_state)); | |
9278 | ASSERT(0); | |
9279 | } | |
9280 | ||
9281 | return; | |
9282 | } | |
9283 | ||
ccd15baf RC |
9284 | static void |
9285 | dhdsdio_advertise_bus_remove(dhd_pub_t *dhdp) | |
9286 | { | |
9287 | unsigned long flags; | |
9288 | int timeleft; | |
9289 | ||
9290 | DHD_LINUX_GENERAL_LOCK(dhdp, flags); | |
9291 | dhdp->busstate = DHD_BUS_REMOVE; | |
9292 | DHD_LINUX_GENERAL_UNLOCK(dhdp, flags); | |
9293 | ||
9294 | timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state); | |
9295 | if ((timeleft == 0) || (timeleft == 1)) { | |
9296 | DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n", | |
9297 | __FUNCTION__, dhdp->dhd_bus_busy_state)); | |
9298 | ASSERT(0); | |
9299 | } | |
9300 | ||
9301 | return; | |
9302 | } | |
9303 | ||
9304 | ||
010c3a89 RC |
9305 | int |
9306 | dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag) | |
9307 | { | |
9308 | int bcmerror = 0; | |
9309 | dhd_bus_t *bus; | |
9310 | unsigned long flags; | |
9311 | ||
9312 | bus = dhdp->bus; | |
9313 | ||
9314 | if (flag == TRUE) { | |
9315 | if (!bus->dhd->dongle_reset) { | |
9316 | DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__)); | |
9317 | dhdsdio_advertise_bus_cleanup(bus->dhd); | |
9318 | dhd_os_sdlock(dhdp); | |
9319 | dhd_os_wd_timer(dhdp, 0); | |
9320 | #if !defined(IGNORE_ETH0_DOWN) | |
9321 | /* Force flow control as protection when stop come before ifconfig_down */ | |
9322 | dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON); | |
9323 | #endif /* !defined(IGNORE_ETH0_DOWN) */ | |
9324 | /* Expect app to have torn down any connection before calling */ | |
9325 | /* Stop the bus, disable F2 */ | |
9326 | dhd_bus_stop(bus, FALSE); | |
9327 | ||
9328 | #if defined(OOB_INTR_ONLY) | |
9329 | /* Clean up any pending IRQ */ | |
9330 | dhd_enable_oob_intr(bus, FALSE); | |
9331 | bcmsdh_oob_intr_set(bus->sdh, FALSE); | |
9332 | bcmsdh_oob_intr_unregister(bus->sdh); | |
9333 | #endif | |
9334 | ||
9335 | /* Clean tx/rx buffer pointers, detach from the dongle */ | |
9336 | dhdsdio_release_dongle(bus, bus->dhd->osh, TRUE, TRUE); | |
9337 | ||
9338 | bus->dhd->dongle_reset = TRUE; | |
9339 | bus->dhd->up = FALSE; | |
9340 | dhd_txglom_enable(dhdp, FALSE); | |
9341 | dhd_os_sdunlock(dhdp); | |
9342 | ||
9343 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
9344 | bus->dhd->busstate = DHD_BUS_DOWN; | |
9345 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
9346 | ||
9347 | printf("%s: WLAN OFF DONE\n", __FUNCTION__); | |
9348 | /* App can now remove power from device */ | |
9349 | } else | |
9350 | bcmerror = BCME_SDIO_ERROR; | |
9351 | } else { | |
9352 | /* App must have restored power to device before calling */ | |
9353 | ||
9354 | printf("\n\n%s: == WLAN ON ==\n", __FUNCTION__); | |
9355 | ||
9356 | if (bus->dhd->dongle_reset) { | |
9357 | /* Turn on WLAN */ | |
9358 | dhd_os_sdlock(dhdp); | |
9359 | /* Reset SD client */ | |
9360 | bcmsdh_reset(bus->sdh); | |
9361 | ||
9362 | /* Attempt to re-attach & download */ | |
9363 | if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh, | |
9364 | (uint32 *)SI_ENUM_BASE, | |
9365 | bus->cl_devid)) { | |
9366 | ||
9367 | DHD_LINUX_GENERAL_LOCK(bus->dhd, flags); | |
9368 | bus->dhd->busstate = DHD_BUS_DOWN; | |
9369 | DHD_LINUX_GENERAL_UNLOCK(bus->dhd, flags); | |
9370 | /* Attempt to download binary to the dongle */ | |
9371 | if (dhdsdio_probe_init(bus, bus->dhd->osh, bus->sdh) && | |
9372 | dhdsdio_download_firmware(bus, bus->dhd->osh, bus->sdh) >= 0) { | |
9373 | ||
9374 | /* Re-init bus, enable F2 transfer */ | |
9375 | bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE); | |
9376 | if (bcmerror == BCME_OK) { | |
9377 | #if defined(OOB_INTR_ONLY) | |
9378 | dhd_enable_oob_intr(bus, TRUE); | |
9379 | bcmsdh_oob_intr_register(bus->sdh, | |
9380 | dhdsdio_isr, bus); | |
9381 | bcmsdh_oob_intr_set(bus->sdh, TRUE); | |
9382 | #elif defined(FORCE_WOWLAN) | |
9383 | dhd_enable_oob_intr(bus, TRUE); | |
9384 | #endif | |
9385 | ||
9386 | bus->dhd->dongle_reset = FALSE; | |
9387 | bus->dhd->up = TRUE; | |
9388 | ||
9389 | #if !defined(IGNORE_ETH0_DOWN) | |
9390 | /* Restore flow control */ | |
9391 | dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF); | |
9392 | #endif | |
9393 | dhd_os_wd_timer(dhdp, dhd_watchdog_ms); | |
9394 | ||
9395 | DHD_TRACE(("%s: WLAN ON DONE\n", __FUNCTION__)); | |
9396 | } else { | |
9397 | dhd_bus_stop(bus, FALSE); | |
9398 | dhdsdio_release_dongle(bus, bus->dhd->osh, | |
9399 | TRUE, FALSE); | |
9400 | } | |
9401 | } else { | |
9402 | DHD_ERROR(("%s Failed to download binary to the dongle\n", | |
9403 | __FUNCTION__)); | |
9404 | if (bus->sih != NULL) { | |
9405 | si_detach(bus->sih); | |
9406 | bus->sih = NULL; | |
9407 | } | |
9408 | bcmerror = BCME_SDIO_ERROR; | |
9409 | } | |
9410 | } else | |
9411 | bcmerror = BCME_SDIO_ERROR; | |
9412 | ||
9413 | dhd_os_sdunlock(dhdp); | |
9414 | } else { | |
9415 | printf("%s called when dongle is not in reset\n", | |
9416 | __FUNCTION__); | |
9417 | printf("Will call dhd_bus_start instead\n"); | |
9418 | dhd_bus_resume(dhdp, 1); | |
9419 | #if defined(HW_OOB) || defined(FORCE_WOWLAN) | |
9420 | dhd_conf_set_hw_oob_intr(bus->sdh, bus->sih->chip); // terence 20120615: fix for OOB initial issue | |
9421 | #endif | |
9422 | if ((bcmerror = dhd_bus_start(dhdp)) != 0) | |
9423 | DHD_ERROR(("%s: dhd_bus_start fail with %d\n", | |
9424 | __FUNCTION__, bcmerror)); | |
9425 | } | |
9426 | } | |
9427 | ||
9428 | #ifdef PKT_STATICS | |
9429 | memset((uint8*) &tx_statics, 0, sizeof(pkt_statics_t)); | |
9430 | #endif | |
9431 | return bcmerror; | |
9432 | } | |
9433 | ||
9434 | int dhd_bus_suspend(dhd_pub_t *dhdpub) | |
9435 | { | |
9436 | return bcmsdh_stop(dhdpub->bus->sdh); | |
9437 | } | |
9438 | ||
9439 | int dhd_bus_resume(dhd_pub_t *dhdpub, int stage) | |
9440 | { | |
9441 | return bcmsdh_start(dhdpub->bus->sdh, stage); | |
9442 | } | |
9443 | ||
9444 | /* Get Chip ID version */ | |
9445 | uint dhd_bus_chip_id(dhd_pub_t *dhdp) | |
9446 | { | |
9447 | dhd_bus_t *bus = dhdp->bus; | |
9448 | ||
9449 | if (bus && bus->sih) | |
9450 | return bus->sih->chip; | |
9451 | else | |
9452 | return 0; | |
9453 | } | |
9454 | ||
9455 | /* Get Chip Rev ID version */ | |
9456 | uint dhd_bus_chiprev_id(dhd_pub_t *dhdp) | |
9457 | { | |
9458 | dhd_bus_t *bus = dhdp->bus; | |
9459 | ||
9460 | if (bus && bus->sih) | |
9461 | return bus->sih->chiprev; | |
9462 | else | |
9463 | return 0; | |
9464 | } | |
9465 | ||
9466 | /* Get Chip Pkg ID version */ | |
9467 | uint dhd_bus_chippkg_id(dhd_pub_t *dhdp) | |
9468 | { | |
9469 | dhd_bus_t *bus = dhdp->bus; | |
9470 | ||
9471 | return bus->sih->chippkg; | |
9472 | } | |
9473 | ||
9474 | int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num, uint32 *slot_num) | |
9475 | { | |
9476 | *bus_type = bus->bus; | |
9477 | *bus_num = bus->bus_num; | |
9478 | *slot_num = bus->slot_num; | |
9479 | return 0; | |
9480 | } | |
9481 | ||
9482 | int | |
9483 | dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size) | |
9484 | { | |
9485 | dhd_bus_t *bus; | |
9486 | ||
9487 | bus = dhdp->bus; | |
9488 | return dhdsdio_membytes(bus, set, address, data, size); | |
9489 | } | |
9490 | ||
9491 | ||
9492 | void | |
9493 | dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path, | |
9494 | char *pclm_path, char *pconf_path) | |
9495 | { | |
9496 | bus->fw_path = pfw_path; | |
9497 | bus->nv_path = pnv_path; | |
9498 | bus->dhd->clm_path = pclm_path; | |
9499 | bus->dhd->conf_path = pconf_path; | |
9500 | } | |
9501 | ||
9502 | int | |
9503 | dhd_enableOOB(dhd_pub_t *dhd, bool sleep) | |
9504 | { | |
9505 | dhd_bus_t *bus = dhd->bus; | |
9506 | sdpcmd_regs_t *regs = bus->regs; | |
9507 | uint retries = 0; | |
9508 | ||
9509 | if (sleep) { | |
9510 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
9511 | /* Tell device to start using OOB wakeup */ | |
9512 | W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries); | |
9513 | if (retries > retry_limit) { | |
9514 | DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n")); | |
9515 | return BCME_BUSY; | |
9516 | } | |
9517 | /* Turn off our contribution to the HT clock request */ | |
9518 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
9519 | } else { | |
9520 | /* Make sure the controller has the bus up */ | |
9521 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
9522 | ||
9523 | /* Send misc interrupt to indicate OOB not needed */ | |
9524 | W_SDREG(0, ®s->tosbmailboxdata, retries); | |
9525 | if (retries <= retry_limit) | |
9526 | W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries); | |
9527 | ||
9528 | if (retries > retry_limit) | |
9529 | DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n")); | |
9530 | ||
9531 | /* Make sure we have SD bus access */ | |
9532 | dhdsdio_clkctl(bus, CLK_SDONLY, FALSE); | |
9533 | } | |
9534 | return BCME_OK; | |
9535 | } | |
9536 | ||
9537 | void | |
9538 | dhd_bus_pktq_flush(dhd_pub_t *dhdp) | |
9539 | { | |
9540 | dhd_bus_t *bus = dhdp->bus; | |
9541 | bool wlfc_enabled = FALSE; | |
9542 | ||
9543 | #ifdef PROP_TXSTATUS | |
9544 | wlfc_enabled = (dhd_wlfc_cleanup_txq(dhdp, NULL, 0) != WLFC_UNSUPPORTED); | |
9545 | #endif | |
9546 | if (!wlfc_enabled) { | |
9547 | #ifdef DHDTCPACK_SUPPRESS | |
9548 | /* Clean tcp_ack_info_tbl in order to prevent access to flushed pkt, | |
9549 | * when there is a newly coming packet from network stack. | |
9550 | */ | |
9551 | dhd_tcpack_info_tbl_clean(bus->dhd); | |
9552 | #endif /* DHDTCPACK_SUPPRESS */ | |
9553 | /* Clear the data packet queues */ | |
9554 | pktq_flush(dhdp->osh, &bus->txq, TRUE); | |
9555 | } | |
9556 | } | |
9557 | ||
9558 | #ifdef BCMSDIO | |
9559 | int | |
9560 | dhd_sr_config(dhd_pub_t *dhd, bool on) | |
9561 | { | |
9562 | dhd_bus_t *bus = dhd->bus; | |
9563 | ||
9564 | if (!bus->_srenab) | |
9565 | return -1; | |
9566 | ||
9567 | return dhdsdio_clk_devsleep_iovar(bus, on); | |
9568 | } | |
9569 | ||
9570 | uint16 | |
9571 | dhd_get_chipid(dhd_pub_t *dhd) | |
9572 | { | |
9573 | dhd_bus_t *bus = dhd->bus; | |
9574 | ||
9575 | if (bus && bus->sih) | |
9576 | return (uint16)bus->sih->chip; | |
9577 | else | |
9578 | return 0; | |
9579 | } | |
9580 | #endif /* BCMSDIO */ | |
9581 | ||
9582 | #ifdef DEBUGGER | |
9583 | uint32 dhd_sdio_reg_read(void *h, uint32 addr) | |
9584 | { | |
9585 | uint32 rval; | |
9586 | struct dhd_bus *bus = (struct dhd_bus *) h; | |
9587 | ||
9588 | dhd_os_sdlock(bus->dhd); | |
9589 | ||
9590 | BUS_WAKE(bus); | |
9591 | ||
9592 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
9593 | ||
9594 | rval = bcmsdh_reg_read(bus->sdh, addr, 4); | |
9595 | ||
9596 | dhd_os_sdunlock(bus->dhd); | |
9597 | ||
9598 | return rval; | |
9599 | } | |
9600 | ||
9601 | void dhd_sdio_reg_write(void *h, uint32 addr, uint32 val) | |
9602 | { | |
9603 | struct dhd_bus *bus = (struct dhd_bus *) h; | |
9604 | ||
9605 | dhd_os_sdlock(bus->dhd); | |
9606 | ||
9607 | BUS_WAKE(bus); | |
9608 | ||
9609 | dhdsdio_clkctl(bus, CLK_AVAIL, FALSE); | |
9610 | ||
9611 | bcmsdh_reg_write(bus->sdh, addr, 4, val); | |
9612 | ||
9613 | dhd_os_sdunlock(bus->dhd); | |
9614 | } | |
9615 | ||
9616 | #endif /* DEBUGGER */ | |
9617 | ||
9618 | ||
9619 | #if defined(BT_OVER_SDIO) | |
9620 | uint8 dhd_bus_cfg_read(void *h, uint fun_num, uint32 addr, int *err) | |
9621 | { | |
9622 | uint8 intrd; | |
9623 | dhd_pub_t *dhdp = (dhd_pub_t *)h; | |
9624 | dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus; | |
9625 | ||
9626 | dhd_os_sdlock(bus->dhd); | |
9627 | ||
9628 | intrd = bcmsdh_cfg_read(bus->sdh, fun_num, addr, err); | |
9629 | ||
9630 | dhd_os_sdunlock(bus->dhd); | |
9631 | ||
9632 | return intrd; | |
9633 | } EXPORT_SYMBOL(dhd_bus_cfg_read); | |
9634 | ||
9635 | void dhd_bus_cfg_write(void *h, uint fun_num, uint32 addr, uint8 val, int *err) | |
9636 | { | |
9637 | dhd_pub_t *dhdp = (dhd_pub_t *)h; | |
9638 | dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus; | |
9639 | ||
9640 | dhd_os_sdlock(bus->dhd); | |
9641 | ||
9642 | bcmsdh_cfg_write(bus->sdh, fun_num, addr, val, err); | |
9643 | ||
9644 | dhd_os_sdunlock(bus->dhd); | |
9645 | ||
9646 | } EXPORT_SYMBOL(dhd_bus_cfg_write); | |
9647 | ||
9648 | static int | |
9649 | extract_hex_field(char * line, uint16 start_pos, uint16 num_chars, uint16 * value) | |
9650 | { | |
9651 | char field [8]; | |
9652 | ||
9653 | strncpy(field, line + start_pos, num_chars); | |
9654 | field [num_chars] = '\0'; | |
9655 | ||
9656 | return (sscanf (field, "%hX", value) == 1); | |
9657 | } | |
9658 | ||
9659 | static int | |
9660 | read_more_btbytes(struct dhd_bus *bus, void * file, char *line, int * addr_mode, uint16 * hi_addr, | |
9661 | uint32 * dest_addr, uint8 *data_bytes, uint32 * num_bytes) | |
9662 | { | |
9663 | int str_len; | |
9664 | uint16 num_data_bytes, addr, data_pos, type, w, i; | |
9665 | uint32 abs_base_addr32 = 0; | |
9666 | *num_bytes = 0; | |
9667 | ||
9668 | while (!*num_bytes) | |
9669 | { | |
9670 | str_len = dhd_os_gets_image(bus->dhd, line, BTFW_MAX_STR_LEN, file); | |
9671 | ||
9672 | DHD_TRACE(("%s: Len :0x%x %s\n", __FUNCTION__, str_len, line)); | |
9673 | ||
9674 | if (str_len == 0) { | |
9675 | break; | |
9676 | } else if (str_len > 9) { | |
9677 | extract_hex_field(line, 1, 2, &num_data_bytes); | |
9678 | extract_hex_field(line, 3, 4, &addr); | |
9679 | extract_hex_field(line, 7, 2, &type); | |
9680 | ||
9681 | data_pos = 9; | |
9682 | for (i = 0; i < num_data_bytes; i++) { | |
9683 | extract_hex_field(line, data_pos, 2, &w); | |
9684 | data_bytes [i] = (uint8)(w & 0x00FF); | |
9685 | data_pos += 2; | |
9686 | } | |
9687 | ||
9688 | if (type == BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS) { | |
9689 | *hi_addr = (data_bytes [0] << 8) | data_bytes [1]; | |
9690 | *addr_mode = BTFW_ADDR_MODE_EXTENDED; | |
9691 | } else if (type == BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS) { | |
9692 | *hi_addr = (data_bytes [0] << 8) | data_bytes [1]; | |
9693 | *addr_mode = BTFW_ADDR_MODE_SEGMENT; | |
9694 | } else if (type == BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS) { | |
9695 | abs_base_addr32 = (data_bytes [0] << 24) | (data_bytes [1] << 16) | | |
9696 | (data_bytes [2] << 8) | data_bytes [3]; | |
9697 | *addr_mode = BTFW_ADDR_MODE_LINEAR32; | |
9698 | } else if (type == BTFW_HEX_LINE_TYPE_DATA) { | |
9699 | *dest_addr = addr; | |
9700 | if (*addr_mode == BTFW_ADDR_MODE_EXTENDED) | |
9701 | *dest_addr += (*hi_addr << 16); | |
9702 | else if (*addr_mode == BTFW_ADDR_MODE_SEGMENT) | |
9703 | *dest_addr += (*hi_addr << 4); | |
9704 | else if (*addr_mode == BTFW_ADDR_MODE_LINEAR32) | |
9705 | *dest_addr += abs_base_addr32; | |
9706 | *num_bytes = num_data_bytes; | |
9707 | } | |
9708 | } | |
9709 | } | |
9710 | return (*num_bytes > 0); | |
9711 | } | |
9712 | ||
9713 | static int | |
9714 | _dhdsdio_download_btfw(struct dhd_bus *bus) | |
9715 | { | |
9716 | int bcm_error = -1; | |
9717 | void *image = NULL; | |
9718 | uint8 *mem_blk = NULL, *mem_ptr = NULL, *data_ptr = NULL; | |
9719 | ||
9720 | ||
9721 | uint32 offset_addr = 0, offset_len = 0, bytes_to_write = 0; | |
9722 | ||
9723 | char *line = NULL; | |
9724 | uint32 dest_addr = 0, num_bytes; | |
9725 | uint16 hiAddress = 0; | |
9726 | uint32 start_addr, start_data, end_addr, end_data, i, index, pad; | |
9727 | uint32 bt2wlan_pwrup_adr; | |
9728 | ||
9729 | int addr_mode = BTFW_ADDR_MODE_EXTENDED; | |
9730 | ||
9731 | /* Out immediately if no image to download */ | |
9732 | if ((bus->btfw_path == NULL) || (bus->btfw_path[0] == '\0')) { | |
9733 | return 0; | |
9734 | } | |
9735 | ||
9736 | image = dhd_os_open_image(bus->btfw_path); | |
9737 | if (image == NULL) | |
9738 | goto err; | |
9739 | ||
9740 | mem_ptr = mem_blk = MALLOC(bus->dhd->osh, BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN); | |
9741 | if (mem_blk == NULL) { | |
9742 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, | |
9743 | BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN)); | |
9744 | goto err; | |
9745 | } | |
9746 | if ((uint32)(uintptr)mem_blk % DHD_SDALIGN) | |
9747 | mem_ptr += (DHD_SDALIGN - ((uint32)(uintptr)mem_blk % DHD_SDALIGN)); | |
9748 | ||
9749 | data_ptr = MALLOC(bus->dhd->osh, BTFW_DOWNLOAD_BLK_SIZE - 8); | |
9750 | if (data_ptr == NULL) { | |
9751 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, | |
9752 | BTFW_DOWNLOAD_BLK_SIZE - 8)); | |
9753 | goto err; | |
9754 | } | |
9755 | /* Write to BT register to hold WLAN wake high during BT FW download */ | |
9756 | bt2wlan_pwrup_adr = BTMEM_OFFSET + BT2WLAN_PWRUP_ADDR; | |
9757 | bcmsdh_reg_write(bus->sdh, bt2wlan_pwrup_adr, 4, BT2WLAN_PWRUP_WAKE); | |
9758 | /* | |
9759 | * Wait for at least 2msec for the clock to be ready/Available. | |
9760 | */ | |
9761 | OSL_DELAY(2000); | |
9762 | ||
9763 | line = MALLOC(bus->dhd->osh, BTFW_MAX_STR_LEN); | |
9764 | if (line == NULL) { | |
9765 | DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", | |
9766 | __FUNCTION__, BTFW_MAX_STR_LEN)); | |
9767 | goto err; | |
9768 | } | |
9769 | memset(line, 0, BTFW_MAX_STR_LEN); | |
9770 | ||
9771 | while (read_more_btbytes (bus, image, line, &addr_mode, &hiAddress, &dest_addr, | |
9772 | data_ptr, &num_bytes)) { | |
9773 | ||
9774 | DHD_TRACE(("read %d bytes at address %08X\n", num_bytes, dest_addr)); | |
9775 | ||
9776 | start_addr = BTMEM_OFFSET + dest_addr; | |
9777 | index = 0; | |
9778 | ||
9779 | /* Make sure the start address is 4 byte aligned to avoid alignment issues | |
9780 | * with SD host controllers | |
9781 | */ | |
9782 | if (!ISALIGNED(start_addr, 4)) { | |
9783 | pad = start_addr % 4; | |
9784 | start_addr = ROUNDDN(start_addr, 4); | |
9785 | start_data = bcmsdh_reg_read(bus->sdh, start_addr, 4); | |
9786 | for (i = 0; i < pad; i++, index++) { | |
9787 | mem_ptr[index] = (uint8)((uint8 *)&start_data)[i]; | |
9788 | } | |
9789 | } | |
9790 | bcopy(data_ptr, &(mem_ptr[index]), num_bytes); | |
9791 | index += num_bytes; | |
9792 | ||
9793 | /* Make sure the length is multiple of 4bytes to avoid alignment issues | |
9794 | * with SD host controllers | |
9795 | */ | |
9796 | end_addr = start_addr + index; | |
9797 | if (!ISALIGNED(end_addr, 4)) { | |
9798 | end_addr = ROUNDDN(end_addr, 4); | |
9799 | end_data = bcmsdh_reg_read(bus->sdh, end_addr, 4); | |
9800 | for (i = (index % 4); i < 4; i++, index++) { | |
9801 | mem_ptr[index] = (uint8)((uint8 *)&end_data)[i]; | |
9802 | } | |
9803 | } | |
9804 | ||
9805 | offset_addr = start_addr & 0xFFF; | |
9806 | offset_len = offset_addr + index; | |
9807 | if (offset_len <= 0x1000) { | |
9808 | bcm_error = dhdsdio_membytes(bus, TRUE, start_addr, mem_ptr, index); | |
9809 | if (bcm_error) { | |
9810 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
9811 | __FUNCTION__, bcm_error, num_bytes, start_addr)); | |
9812 | goto err; | |
9813 | } | |
9814 | } | |
9815 | else { | |
9816 | bytes_to_write = 0x1000 - offset_addr; | |
9817 | bcm_error = dhdsdio_membytes(bus, TRUE, start_addr, mem_ptr, | |
9818 | bytes_to_write); | |
9819 | if (bcm_error) { | |
9820 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
9821 | __FUNCTION__, bcm_error, num_bytes, start_addr)); | |
9822 | goto err; | |
9823 | } | |
9824 | ||
9825 | OSL_DELAY(10000); | |
9826 | ||
9827 | bcm_error = dhdsdio_membytes(bus, TRUE, (start_addr + bytes_to_write), | |
9828 | (mem_ptr + bytes_to_write), (index - bytes_to_write)); | |
9829 | if (bcm_error) { | |
9830 | DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", | |
9831 | __FUNCTION__, bcm_error, num_bytes, start_addr)); | |
9832 | goto err; | |
9833 | } | |
9834 | } | |
9835 | memset(line, 0, BTFW_MAX_STR_LEN); | |
9836 | } | |
9837 | ||
9838 | bcm_error = 0; | |
9839 | err: | |
9840 | if (mem_blk) | |
9841 | MFREE(bus->dhd->osh, mem_blk, BTFW_DOWNLOAD_BLK_SIZE + DHD_SDALIGN); | |
9842 | ||
9843 | if (data_ptr) | |
9844 | MFREE(bus->dhd->osh, data_ptr, BTFW_DOWNLOAD_BLK_SIZE - 8); | |
9845 | ||
9846 | if (line) | |
9847 | MFREE(bus->dhd->osh, line, BTFW_MAX_STR_LEN); | |
9848 | ||
9849 | if (image) | |
9850 | dhd_os_close_image(image); | |
9851 | ||
9852 | return bcm_error; | |
9853 | } | |
9854 | ||
9855 | static int | |
9856 | dhdsdio_download_btfw(struct dhd_bus *bus, osl_t *osh, void *sdh) | |
9857 | { | |
9858 | int ret; | |
9859 | ||
9860 | DHD_TRACE(("%s: btfw path=%s\n", | |
9861 | __FUNCTION__, bus->btfw_path)); | |
9862 | DHD_OS_WAKE_LOCK(bus->dhd); | |
9863 | dhd_os_sdlock(bus->dhd); | |
9864 | ||
9865 | /* Download the firmware */ | |
9866 | ret = _dhdsdio_download_btfw(bus); | |
9867 | ||
9868 | dhd_os_sdunlock(bus->dhd); | |
9869 | DHD_OS_WAKE_UNLOCK(bus->dhd); | |
9870 | ||
9871 | return ret; | |
9872 | } | |
9873 | ||
9874 | int | |
9875 | dhd_bus_download_btfw(struct dhd_bus *bus, osl_t *osh, | |
9876 | char *pbtfw_path) | |
9877 | { | |
9878 | int ret; | |
9879 | ||
9880 | bus->btfw_path = pbtfw_path; | |
9881 | ||
9882 | ret = dhdsdio_download_btfw(bus, osh, bus->sdh); | |
9883 | ||
9884 | return ret; | |
9885 | } | |
9886 | #endif /* defined (BT_OVER_SDIO) */ | |
9887 | ||
9888 | void | |
9889 | dhd_bus_dump_trap_info(dhd_bus_t *bus, struct bcmstrbuf *strbuf) | |
9890 | { | |
9891 | trap_t *tr = &bus->dhd->last_trap_info; | |
9892 | ||
9893 | bcm_bprintf(strbuf, | |
9894 | "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x," | |
9895 | "lp 0x%x, rpc 0x%x Trap offset 0x%x, " | |
9896 | "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, " | |
9897 | "r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n", | |
9898 | ltoh32(tr->type), ltoh32(tr->epc), ltoh32(tr->cpsr), ltoh32(tr->spsr), | |
9899 | ltoh32(tr->r13), ltoh32(tr->r14), ltoh32(tr->pc), | |
9900 | ltoh32(bus->dongle_trap_addr), | |
9901 | ltoh32(tr->r0), ltoh32(tr->r1), ltoh32(tr->r2), ltoh32(tr->r3), | |
9902 | ltoh32(tr->r4), ltoh32(tr->r5), ltoh32(tr->r6), ltoh32(tr->r7)); | |
9903 | ||
9904 | } | |
9905 | ||
9906 | static int | |
9907 | dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len) | |
9908 | { | |
9909 | int ret = -1; | |
9910 | ||
9911 | ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(((dhd_bus_t*)bus)->sdh), | |
9912 | SDIO_FUNC_2, F2SYNC, frame, len, NULL, NULL, NULL, TXRETRIES); | |
9913 | ||
9914 | if (ret == BCME_OK) | |
9915 | ((dhd_bus_t*)bus)->tx_seq = (((dhd_bus_t*)bus)->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; | |
9916 | ||
9917 | return ret; | |
9918 | } | |
9919 | ||
9920 | /* Function to set the min res mask depending on the chip ID used */ | |
9921 | bool | |
9922 | dhd_bus_set_default_min_res_mask(struct dhd_bus *bus) | |
9923 | { | |
9924 | if ((bus == NULL) || (bus->sih == NULL)) { | |
9925 | DHD_ERROR(("%s(): Invalid Arguments \r\n", __FUNCTION__)); | |
9926 | return FALSE; | |
9927 | } | |
9928 | ||
9929 | switch (bus->sih->chip) { | |
9930 | case BCM4339_CHIP_ID: | |
9931 | bcmsdh_reg_write(bus->sdh, SI_ENUM_BASE + 0x618, 4, 0x3fcaf377); | |
9932 | if (bcmsdh_regfail(bus->sdh)) { | |
9933 | DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__)); | |
9934 | return FALSE; | |
9935 | } | |
9936 | break; | |
9937 | ||
9938 | case BCM43012_CHIP_ID: | |
9939 | bcmsdh_reg_write(bus->sdh, | |
9940 | si_get_pmu_reg_addr(bus->sih, OFFSETOF(pmuregs_t, min_res_mask)), | |
9941 | 4, DEFAULT_43012_MIN_RES_MASK); | |
9942 | if (bcmsdh_regfail(bus->sdh)) { | |
9943 | DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__)); | |
9944 | return FALSE; | |
9945 | } | |
9946 | break; | |
9947 | ||
9948 | default: | |
9949 | DHD_ERROR(("%s: Unhandled chip id\n", __FUNCTION__)); | |
9950 | return FALSE; | |
9951 | } | |
9952 | ||
9953 | return TRUE; | |
9954 | } | |
9955 | ||
9956 | /* Function to reset PMU registers */ | |
9957 | void | |
9958 | dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp) | |
9959 | { | |
9960 | struct dhd_bus *bus = dhdp->bus; | |
9961 | bcmsdh_reg_write(bus->sdh, si_get_pmu_reg_addr(bus->sih, | |
9962 | OFFSETOF(pmuregs_t, swscratch)), 4, 0x0); | |
9963 | if (bcmsdh_regfail(bus->sdh)) { | |
9964 | DHD_ERROR(("%s:%d Setting min_res_mask failed\n", __FUNCTION__, __LINE__)); | |
9965 | } | |
9966 | } | |
9967 | ||
9968 | ||
9969 | #ifdef DHD_ULP | |
9970 | /* Function to disable console messages on entering ULP mode */ | |
9971 | void | |
9972 | dhd_bus_ulp_disable_console(dhd_pub_t *dhdp) | |
9973 | { | |
9974 | #ifdef DHD_DEBUG | |
9975 | DHD_ERROR(("Flushing and disabling console messages\n")); | |
9976 | ||
9977 | /* Save the console print interval */ | |
9978 | dhd_ulp_save_console_interval(dhdp); | |
9979 | ||
9980 | /* Flush the console buffer before disabling */ | |
9981 | dhdsdio_readconsole(dhdp->bus); | |
9982 | dhd_console_ms = 0; | |
9983 | #endif /* DHD_DEBUG */ | |
9984 | } | |
9985 | ||
9986 | /* Function for redownloading firmaware */ | |
9987 | static int | |
9988 | dhd_bus_ulp_reinit_fw(dhd_bus_t *bus) | |
9989 | { | |
9990 | int bcmerror = 0; | |
9991 | ||
9992 | /* After firmware redownload tx/rx seq are reset accordingly these values are | |
9993 | reset on DHD side tx_max is initially set to 4, which later is updated by FW | |
9994 | */ | |
9995 | bus->tx_seq = bus->rx_seq = 0; | |
9996 | bus->tx_max = 4; | |
9997 | ||
9998 | if (dhd_bus_download_firmware(bus, bus->dhd->osh, | |
9999 | bus->fw_path, bus->nv_path) >= 0) { | |
10000 | ||
10001 | /* Re-init bus, enable F2 transfer */ | |
10002 | bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE); | |
10003 | if (bcmerror == BCME_OK) { | |
10004 | bus->dhd->up = TRUE; | |
10005 | dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms); | |
10006 | ||
10007 | dhd_ulp_set_ulp_state(bus->dhd, DHD_ULP_READY); | |
10008 | #if defined(OOB_INTR_ONLY) | |
10009 | dhd_enable_oob_intr(bus, TRUE); | |
10010 | bcmsdh_oob_intr_set(bus->sdh, TRUE); | |
10011 | #endif | |
10012 | #ifdef DHD_DEBUG | |
10013 | /* Re-enable the console messages on FW redownload to default value */ | |
10014 | dhd_ulp_restore_console_interval(bus->dhd); | |
10015 | #endif /* DHD_DEBUG */ | |
10016 | } else { | |
10017 | DHD_ERROR(("bus init failed\n")); | |
10018 | dhd_bus_stop(bus, FALSE); | |
10019 | dhdsdio_release_dongle(bus, bus->dhd->osh, | |
10020 | TRUE, FALSE); | |
10021 | } | |
10022 | } else | |
10023 | bcmerror = BCME_SDIO_ERROR; | |
10024 | ||
10025 | return bcmerror; | |
10026 | } | |
10027 | #endif /* DHD_ULP */ | |
10028 | ||
10029 | int | |
10030 | dhd_bus_readwrite_bp_addr(dhd_pub_t *dhdp, uint addr, uint size, uint* data, bool read) | |
10031 | { | |
10032 | int bcmerror = 0; | |
10033 | struct dhd_bus *bus = dhdp->bus; | |
10034 | ||
10035 | if (read) { | |
10036 | *data = (int32)bcmsdh_reg_read(bus->sdh, addr, size); | |
10037 | } else { | |
10038 | bcmsdh_reg_write(bus->sdh, addr, size, *data); | |
10039 | } | |
10040 | ||
10041 | if (bcmsdh_regfail(bus->sdh)) | |
10042 | bcmerror = BCME_SDIO_ERROR; | |
10043 | ||
10044 | return bcmerror; | |
10045 | } | |
10046 | ||
10047 | int dhd_get_idletime(dhd_pub_t *dhd) | |
10048 | { | |
10049 | return dhd->bus->idletime; | |
10050 | } | |
10051 | ||
10052 | #ifdef DHD_WAKE_STATUS | |
10053 | wake_counts_t* | |
10054 | dhd_bus_get_wakecount(dhd_pub_t *dhd) | |
10055 | { | |
10056 | if (!dhd->bus) { | |
10057 | return NULL; | |
10058 | } | |
10059 | return &dhd->bus->wake_counts; | |
10060 | } | |
10061 | int | |
10062 | dhd_bus_get_bus_wake(dhd_pub_t *dhd) | |
10063 | { | |
10064 | return bcmsdh_set_get_wake(dhd->bus->sdh, 0); | |
10065 | } | |
10066 | #endif /* DHD_WAKE_STATUS */ |