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[PATCH] Remove some unneeded ACPI externs in mpparse.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / mpparse.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
1da177e4
LT		 17#include <linux/init.h>
18#include <linux/delay.h>
1da177e4
LT		 19#include <linux/bootmem.h>
20#include <linux/smp_lock.h>
21#include <linux/kernel_stat.h>
22#include <linux/mc146818rtc.h>
23#include <linux/acpi.h>
8c5a0908 24#include <linux/module.h>
1da177e4
LT		 25
26#include <asm/smp.h>
27#include <asm/mtrr.h>
28#include <asm/mpspec.h>
29#include <asm/pgalloc.h>
30#include <asm/io_apic.h>
31#include <asm/proto.h>
8d916406 32#include <asm/acpi.h>
1da177e4
LT		 33
34/* Have we found an MP table */
35int smp_found_config;
36unsigned int __initdata maxcpus = NR_CPUS;
37
38int acpi_found_madt;
39
40/*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
8893166f 44unsigned char apic_version [MAX_APICS];
55f05ffa 45DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
1da177e4 46int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
1da177e4
LT		 47
48static int mp_current_pci_id = 0;
49/* I/O APIC entries */
50struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
51
52/* # of MP IRQ source entries */
53struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
54
55/* MP IRQ source entries */
56int mp_irq_entries;
57
58int nr_ioapics;
1da177e4
LT		 59unsigned long mp_lapic_addr = 0;
60
61
62
63/* Processor that is doing the boot up */
64unsigned int boot_cpu_id = -1U;
65/* Internal processor count */
420f8f68
AK		 66unsigned int num_processors __initdata = 0;
67
68unsigned disabled_cpus __initdata;
1da177e4
LT		 69
70/* Bitmask of physically existing CPUs */
71physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
72
1da177e4
LT		 73u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
74
75
76/*
77 * Intel MP BIOS table parsing routines:
78 */
79
80/*
81 * Checksum an MP configuration block.
82 */
83
84static int __init mpf_checksum(unsigned char *mp, int len)
85{
86 int sum = 0;
87
88 while (len--)
89 sum += *mp++;
90
91 return sum & 0xFF;
92}
93
51f62e18 94static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
1da177e4 95{
8893166f
AK		 96 int cpu;
97 unsigned char ver;
51f62e18 98 cpumask_t tmp_map;
1da177e4 99
420f8f68
AK		 100 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
101 disabled_cpus++;
1da177e4 102 return;
420f8f68 103 }
1da177e4
LT		 104
105 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
106 m->mpc_apicid,
107 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
108 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
109 m->mpc_apicver);
110
111 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
112 Dprintk(" Bootup CPU\n");
113 boot_cpu_id = m->mpc_apicid;
114 }
115 if (num_processors >= NR_CPUS) {
116 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
117 " Processor ignored.\n", NR_CPUS);
118 return;
119 }
1da177e4 120
51f62e18
AR		 121 num_processors++;
122 cpus_complement(tmp_map, cpu_present_map);
123 cpu = first_cpu(tmp_map);
124
8893166f
AK		 125#if MAX_APICS < 255
126 if ((int)m->mpc_apicid > MAX_APICS) {
1da177e4
LT		 127 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
128 m->mpc_apicid, MAX_APICS);
129 return;
130 }
8893166f 131#endif
1da177e4
LT		 132 ver = m->mpc_apicver;
133
134 physid_set(m->mpc_apicid, phys_cpu_present_map);
135 /*
136 * Validate version
137 */
138 if (ver == 0x0) {
139 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
140 ver = 0x10;
141 }
142 apic_version[m->mpc_apicid] = ver;
18a2b647
AK		 143 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
144 /*
145 * bios_cpu_apicid is required to have processors listed
146 * in same order as logical cpu numbers. Hence the first
147 * entry is BSP, and so on.
148 */
61b1b2d0 149 cpu = 0;
51f62e18 150 }
61b1b2d0
AK		 151 bios_cpu_apicid[cpu] = m->mpc_apicid;
152 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
153
154 cpu_set(cpu, cpu_possible_map);
155 cpu_set(cpu, cpu_present_map);
1da177e4
LT		 156}
157
158static void __init MP_bus_info (struct mpc_config_bus *m)
159{
160 char str[7];
161
162 memcpy(str, m->mpc_bustype, 6);
163 str[6] = 0;
164 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
165
166 if (strncmp(str, "ISA", 3) == 0) {
55f05ffa 167 set_bit(m->mpc_busid, mp_bus_not_pci);
1da177e4 168 } else if (strncmp(str, "PCI", 3) == 0) {
55f05ffa 169 clear_bit(m->mpc_busid, mp_bus_not_pci);
1da177e4
LT		 170 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
171 mp_current_pci_id++;
1da177e4
LT		 172 } else {
173 printk(KERN_ERR "Unknown bustype %s\n", str);
174 }
175}
176
177static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
178{
179 if (!(m->mpc_flags & MPC_APIC_USABLE))
180 return;
181
182 printk("I/O APIC #%d Version %d at 0x%X.\n",
183 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
184 if (nr_ioapics >= MAX_IO_APICS) {
185 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
186 MAX_IO_APICS, nr_ioapics);
187 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
188 }
189 if (!m->mpc_apicaddr) {
190 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
191 " found in MP table, skipping!\n");
192 return;
193 }
194 mp_ioapics[nr_ioapics] = *m;
195 nr_ioapics++;
196}
197
198static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
199{
200 mp_irqs [mp_irq_entries] = *m;
201 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
202 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
203 m->mpc_irqtype, m->mpc_irqflag & 3,
204 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
205 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
6004e1b7 206 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
1da177e4
LT		 207 panic("Max # of irq sources exceeded!!\n");
208}
209
210static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
211{
212 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
213 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
214 m->mpc_irqtype, m->mpc_irqflag & 3,
215 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
216 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
1da177e4
LT		 217}
218
219/*
220 * Read/parse the MPC
221 */
222
223static int __init smp_read_mpc(struct mp_config_table *mpc)
224{
225 char str[16];
226 int count=sizeof(*mpc);
227 unsigned char *mpt=((unsigned char *)mpc)+count;
228
229 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
230 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
231 mpc->mpc_signature[0],
232 mpc->mpc_signature[1],
233 mpc->mpc_signature[2],
234 mpc->mpc_signature[3]);
235 return 0;
236 }
237 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
238 printk("SMP mptable: checksum error!\n");
239 return 0;
240 }
241 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
242 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
243 mpc->mpc_spec);
244 return 0;
245 }
246 if (!mpc->mpc_lapic) {
247 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
248 return 0;
249 }
250 memcpy(str,mpc->mpc_oem,8);
251 str[8]=0;
252 printk(KERN_INFO "OEM ID: %s ",str);
253
254 memcpy(str,mpc->mpc_productid,12);
255 str[12]=0;
9ff4ced4 256 printk("Product ID: %s ",str);
1da177e4 257
9ff4ced4 258 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
1da177e4
LT		 259
260 /* save the local APIC address, it might be non-default */
261 if (!acpi_lapic)
262 mp_lapic_addr = mpc->mpc_lapic;
263
264 /*
265 * Now process the configuration blocks.
266 */
267 while (count < mpc->mpc_length) {
268 switch(*mpt) {
269 case MP_PROCESSOR:
270 {
271 struct mpc_config_processor *m=
272 (struct mpc_config_processor *)mpt;
273 if (!acpi_lapic)
274 MP_processor_info(m);
275 mpt += sizeof(*m);
276 count += sizeof(*m);
277 break;
278 }
279 case MP_BUS:
280 {
281 struct mpc_config_bus *m=
282 (struct mpc_config_bus *)mpt;
283 MP_bus_info(m);
284 mpt += sizeof(*m);
285 count += sizeof(*m);
286 break;
287 }
288 case MP_IOAPIC:
289 {
290 struct mpc_config_ioapic *m=
291 (struct mpc_config_ioapic *)mpt;
292 MP_ioapic_info(m);
293 mpt+=sizeof(*m);
294 count+=sizeof(*m);
295 break;
296 }
297 case MP_INTSRC:
298 {
299 struct mpc_config_intsrc *m=
300 (struct mpc_config_intsrc *)mpt;
301
302 MP_intsrc_info(m);
303 mpt+=sizeof(*m);
304 count+=sizeof(*m);
305 break;
306 }
307 case MP_LINTSRC:
308 {
309 struct mpc_config_lintsrc *m=
310 (struct mpc_config_lintsrc *)mpt;
311 MP_lintsrc_info(m);
312 mpt+=sizeof(*m);
313 count+=sizeof(*m);
314 break;
315 }
316 }
317 }
318 clustered_apic_check();
319 if (!num_processors)
320 printk(KERN_ERR "SMP mptable: no processors registered!\n");
321 return num_processors;
322}
323
324static int __init ELCR_trigger(unsigned int irq)
325{
326 unsigned int port;
327
328 port = 0x4d0 + (irq >> 3);
329 return (inb(port) >> (irq & 7)) & 1;
330}
331
332static void __init construct_default_ioirq_mptable(int mpc_default_type)
333{
334 struct mpc_config_intsrc intsrc;
335 int i;
336 int ELCR_fallback = 0;
337
338 intsrc.mpc_type = MP_INTSRC;
339 intsrc.mpc_irqflag = 0; /* conforming */
340 intsrc.mpc_srcbus = 0;
341 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
342
343 intsrc.mpc_irqtype = mp_INT;
344
345 /*
346 * If true, we have an ISA/PCI system with no IRQ entries
347 * in the MP table. To prevent the PCI interrupts from being set up
348 * incorrectly, we try to use the ELCR. The sanity check to see if
349 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
350 * never be level sensitive, so we simply see if the ELCR agrees.
351 * If it does, we assume it's valid.
352 */
353 if (mpc_default_type == 5) {
354 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
355
356 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
357 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
358 else {
359 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
360 ELCR_fallback = 1;
361 }
362 }
363
364 for (i = 0; i < 16; i++) {
365 switch (mpc_default_type) {
366 case 2:
367 if (i == 0 || i == 13)
368 continue; /* IRQ0 & IRQ13 not connected */
369 /* fall through */
370 default:
371 if (i == 2)
372 continue; /* IRQ2 is never connected */
373 }
374
375 if (ELCR_fallback) {
376 /*
377 * If the ELCR indicates a level-sensitive interrupt, we
378 * copy that information over to the MP table in the
379 * irqflag field (level sensitive, active high polarity).
380 */
381 if (ELCR_trigger(i))
382 intsrc.mpc_irqflag = 13;
383 else
384 intsrc.mpc_irqflag = 0;
385 }
386
387 intsrc.mpc_srcbusirq = i;
388 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
389 MP_intsrc_info(&intsrc);
390 }
391
392 intsrc.mpc_irqtype = mp_ExtINT;
393 intsrc.mpc_srcbusirq = 0;
394 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
395 MP_intsrc_info(&intsrc);
396}
397
398static inline void __init construct_default_ISA_mptable(int mpc_default_type)
399{
400 struct mpc_config_processor processor;
401 struct mpc_config_bus bus;
402 struct mpc_config_ioapic ioapic;
403 struct mpc_config_lintsrc lintsrc;
404 int linttypes[2] = { mp_ExtINT, mp_NMI };
405 int i;
406
407 /*
408 * local APIC has default address
409 */
410 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
411
412 /*
413 * 2 CPUs, numbered 0 & 1.
414 */
415 processor.mpc_type = MP_PROCESSOR;
416 /* Either an integrated APIC or a discrete 82489DX. */
417 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
418 processor.mpc_cpuflag = CPU_ENABLED;
419 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
420 (boot_cpu_data.x86_model << 4) |
421 boot_cpu_data.x86_mask;
422 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
423 processor.mpc_reserved[0] = 0;
424 processor.mpc_reserved[1] = 0;
425 for (i = 0; i < 2; i++) {
426 processor.mpc_apicid = i;
427 MP_processor_info(&processor);
428 }
429
430 bus.mpc_type = MP_BUS;
431 bus.mpc_busid = 0;
432 switch (mpc_default_type) {
433 default:
434 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
435 mpc_default_type);
436 /* fall through */
437 case 1:
438 case 5:
439 memcpy(bus.mpc_bustype, "ISA ", 6);
440 break;
1da177e4
LT		 441 }
442 MP_bus_info(&bus);
443 if (mpc_default_type > 4) {
444 bus.mpc_busid = 1;
445 memcpy(bus.mpc_bustype, "PCI ", 6);
446 MP_bus_info(&bus);
447 }
448
449 ioapic.mpc_type = MP_IOAPIC;
450 ioapic.mpc_apicid = 2;
451 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
452 ioapic.mpc_flags = MPC_APIC_USABLE;
453 ioapic.mpc_apicaddr = 0xFEC00000;
454 MP_ioapic_info(&ioapic);
455
456 /*
457 * We set up most of the low 16 IO-APIC pins according to MPS rules.
458 */
459 construct_default_ioirq_mptable(mpc_default_type);
460
461 lintsrc.mpc_type = MP_LINTSRC;
462 lintsrc.mpc_irqflag = 0; /* conforming */
463 lintsrc.mpc_srcbusid = 0;
464 lintsrc.mpc_srcbusirq = 0;
465 lintsrc.mpc_destapic = MP_APIC_ALL;
466 for (i = 0; i < 2; i++) {
467 lintsrc.mpc_irqtype = linttypes[i];
468 lintsrc.mpc_destapiclint = i;
469 MP_lintsrc_info(&lintsrc);
470 }
471}
472
473static struct intel_mp_floating *mpf_found;
474
475/*
476 * Scan the memory blocks for an SMP configuration block.
477 */
478void __init get_smp_config (void)
479{
480 struct intel_mp_floating *mpf = mpf_found;
481
482 /*
1da177e4
LT		 483 * ACPI supports both logical (e.g. Hyper-Threading) and physical
484 * processors, where MPS only supports physical.
485 */
486 if (acpi_lapic && acpi_ioapic) {
487 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
488 return;
489 }
490 else if (acpi_lapic)
491 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
492
493 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
1da177e4
LT		 494
495 /*
496 * Now see if we need to read further.
497 */
498 if (mpf->mpf_feature1 != 0) {
499
500 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
501 construct_default_ISA_mptable(mpf->mpf_feature1);
502
503 } else if (mpf->mpf_physptr) {
504
505 /*
506 * Read the physical hardware table. Anything here will
507 * override the defaults.
508 */
f6c2e333 509 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
1da177e4
LT		 510 smp_found_config = 0;
511 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
512 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
513 return;
514 }
515 /*
516 * If there are no explicit MP IRQ entries, then we are
517 * broken. We set up most of the low 16 IO-APIC pins to
518 * ISA defaults and hope it will work.
519 */
520 if (!mp_irq_entries) {
521 struct mpc_config_bus bus;
522
523 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
524
525 bus.mpc_type = MP_BUS;
526 bus.mpc_busid = 0;
527 memcpy(bus.mpc_bustype, "ISA ", 6);
528 MP_bus_info(&bus);
529
530 construct_default_ioirq_mptable(0);
531 }
532
533 } else
534 BUG();
535
536 printk(KERN_INFO "Processors: %d\n", num_processors);
537 /*
538 * Only use the first configuration found.
539 */
540}
541
542static int __init smp_scan_config (unsigned long base, unsigned long length)
543{
544 extern void __bad_mpf_size(void);
545 unsigned int *bp = phys_to_virt(base);
546 struct intel_mp_floating *mpf;
547
548 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
549 if (sizeof(*mpf) != 16)
550 __bad_mpf_size();
551
552 while (length > 0) {
553 mpf = (struct intel_mp_floating *)bp;
554 if ((*bp == SMP_MAGIC_IDENT) &&
555 (mpf->mpf_length == 1) &&
556 !mpf_checksum((unsigned char *)bp, 16) &&
557 ((mpf->mpf_specification == 1)
558 || (mpf->mpf_specification == 4)) ) {
559
560 smp_found_config = 1;
561 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
562 if (mpf->mpf_physptr)
563 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
564 mpf_found = mpf;
565 return 1;
566 }
567 bp += 4;
568 length -= 16;
569 }
570 return 0;
571}
572
a01fd3ba 573void __init find_smp_config(void)
1da177e4
LT		 574{
575 unsigned int address;
576
577 /*
578 * FIXME: Linux assumes you have 640K of base ram..
579 * this continues the error...
580 *
581 * 1) Scan the bottom 1K for a signature
582 * 2) Scan the top 1K of base RAM
583 * 3) Scan the 64K of bios
584 */
585 if (smp_scan_config(0x0,0x400) ||
586 smp_scan_config(639*0x400,0x400) ||
587 smp_scan_config(0xF0000,0x10000))
588 return;
589 /*
e5099134 590 * If it is an SMP machine we should know now.
1da177e4
LT		 591 *
592 * there is a real-mode segmented pointer pointing to the
593 * 4K EBDA area at 0x40E, calculate and scan it here.
594 *
595 * NOTE! There are Linux loaders that will corrupt the EBDA
596 * area, and as such this kind of SMP config may be less
597 * trustworthy, simply because the SMP table may have been
598 * stomped on during early boot. These loaders are buggy and
599 * should be fixed.
600 */
601
602 address = *(unsigned short *)phys_to_virt(0x40E);
603 address <<= 4;
604 if (smp_scan_config(address, 0x1000))
605 return;
606
607 /* If we have come this far, we did not find an MP table */
608 printk(KERN_INFO "No mptable found.\n");
609}
610
1da177e4
LT		 611/* --------------------------------------------------------------------------
612 ACPI-based MP Configuration
613 -------------------------------------------------------------------------- */
614
888ba6c6 615#ifdef CONFIG_ACPI
1da177e4
LT		 616
617void __init mp_register_lapic_address (
618 u64 address)
619{
620 mp_lapic_addr = (unsigned long) address;
621
622 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
623
624 if (boot_cpu_id == -1U)
625 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
626
627 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
628}
629
630
51f62e18 631void __cpuinit mp_register_lapic (
1da177e4
LT		 632 u8 id,
633 u8 enabled)
634{
635 struct mpc_config_processor processor;
636 int boot_cpu = 0;
637
638 if (id >= MAX_APICS) {
639 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
640 id, MAX_APICS);
641 return;
642 }
643
644 if (id == boot_cpu_physical_apicid)
645 boot_cpu = 1;
646
647 processor.mpc_type = MP_PROCESSOR;
648 processor.mpc_apicid = id;
8675b1a4 649 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
1da177e4
LT		 650 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
651 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
652 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
653 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
654 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
655 processor.mpc_reserved[0] = 0;
656 processor.mpc_reserved[1] = 0;
657
658 MP_processor_info(&processor);
659}
660
1da177e4
LT		 661#define MP_ISA_BUS 0
662#define MP_MAX_IOAPIC_PIN 127
663
664static struct mp_ioapic_routing {
665 int apic_id;
666 int gsi_start;
667 int gsi_end;
668 u32 pin_programmed[4];
669} mp_ioapic_routing[MAX_IO_APICS];
670
671
672static int mp_find_ioapic (
673 int gsi)
674{
675 int i = 0;
676
677 /* Find the IOAPIC that manages this GSI. */
678 for (i = 0; i < nr_ioapics; i++) {
679 if ((gsi >= mp_ioapic_routing[i].gsi_start)
680 && (gsi <= mp_ioapic_routing[i].gsi_end))
681 return i;
682 }
683
684 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
685
686 return -1;
687}
688
689
690void __init mp_register_ioapic (
691 u8 id,
692 u32 address,
693 u32 gsi_base)
694{
695 int idx = 0;
696
697 if (nr_ioapics >= MAX_IO_APICS) {
698 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
699 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
700 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
701 }
702 if (!address) {
703 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
704 " found in MADT table, skipping!\n");
705 return;
706 }
707
708 idx = nr_ioapics++;
709
710 mp_ioapics[idx].mpc_type = MP_IOAPIC;
711 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
712 mp_ioapics[idx].mpc_apicaddr = address;
713
714 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
0af2be0b 715 mp_ioapics[idx].mpc_apicid = id;
1da177e4
LT		 716 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
717
718 /*
719 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
720 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
721 */
722 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
723 mp_ioapic_routing[idx].gsi_start = gsi_base;
724 mp_ioapic_routing[idx].gsi_end = gsi_base +
725 io_apic_get_redir_entries(idx);
726
727 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
728 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
729 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
730 mp_ioapic_routing[idx].gsi_start,
731 mp_ioapic_routing[idx].gsi_end);
732
733 return;
734}
735
736
737void __init mp_override_legacy_irq (
738 u8 bus_irq,
739 u8 polarity,
740 u8 trigger,
741 u32 gsi)
742{
743 struct mpc_config_intsrc intsrc;
744 int ioapic = -1;
745 int pin = -1;
746
747 /*
748 * Convert 'gsi' to 'ioapic.pin'.
749 */
750 ioapic = mp_find_ioapic(gsi);
751 if (ioapic < 0)
752 return;
753 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
754
755 /*
756 * TBD: This check is for faulty timer entries, where the override
757 * erroneously sets the trigger to level, resulting in a HUGE
758 * increase of timer interrupts!
759 */
760 if ((bus_irq == 0) && (trigger == 3))
761 trigger = 1;
762
763 intsrc.mpc_type = MP_INTSRC;
764 intsrc.mpc_irqtype = mp_INT;
765 intsrc.mpc_irqflag = (trigger << 2) | polarity;
766 intsrc.mpc_srcbus = MP_ISA_BUS;
767 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
768 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
769 intsrc.mpc_dstirq = pin; /* INTIN# */
770
771 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
772 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
773 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
774 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
775
776 mp_irqs[mp_irq_entries] = intsrc;
777 if (++mp_irq_entries == MAX_IRQ_SOURCES)
778 panic("Max # of irq sources exceeded!\n");
779
780 return;
781}
782
783
784void __init mp_config_acpi_legacy_irqs (void)
785{
786 struct mpc_config_intsrc intsrc;
787 int i = 0;
788 int ioapic = -1;
789
790 /*
791 * Fabricate the legacy ISA bus (bus #31).
792 */
55f05ffa 793 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1da177e4
LT		 794
795 /*
796 * Locate the IOAPIC that manages the ISA IRQs (0-15).
797 */
798 ioapic = mp_find_ioapic(0);
799 if (ioapic < 0)
800 return;
801
802 intsrc.mpc_type = MP_INTSRC;
803 intsrc.mpc_irqflag = 0; /* Conforming */
804 intsrc.mpc_srcbus = MP_ISA_BUS;
805 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
806
807 /*
808 * Use the default configuration for the IRQs 0-15. Unless
809 * overridden by (MADT) interrupt source override entries.
810 */
811 for (i = 0; i < 16; i++) {
812 int idx;
813
814 for (idx = 0; idx < mp_irq_entries; idx++) {
815 struct mpc_config_intsrc *irq = mp_irqs + idx;
816
817 /* Do we already have a mapping for this ISA IRQ? */
818 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
819 break;
820
821 /* Do we already have a mapping for this IOAPIC pin */
822 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
823 (irq->mpc_dstirq == i))
824 break;
825 }
826
827 if (idx != mp_irq_entries) {
828 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
829 continue; /* IRQ already used */
830 }
831
832 intsrc.mpc_irqtype = mp_INT;
833 intsrc.mpc_srcbusirq = i; /* Identity mapped */
834 intsrc.mpc_dstirq = i;
835
836 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
837 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
838 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
839 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
840 intsrc.mpc_dstirq);
841
842 mp_irqs[mp_irq_entries] = intsrc;
843 if (++mp_irq_entries == MAX_IRQ_SOURCES)
844 panic("Max # of irq sources exceeded!\n");
845 }
846
847 return;
848}
849
701067c4
NP		 850#define MAX_GSI_NUM 4096
851
50eca3eb 852int mp_register_gsi(u32 gsi, int triggering, int polarity)
1da177e4
LT		 853{
854 int ioapic = -1;
855 int ioapic_pin = 0;
856 int idx, bit = 0;
701067c4
NP		 857 static int pci_irq = 16;
858 /*
859 * Mapping between Global System Interrupts, which
860 * represent all possible interrupts, to the IRQs
861 * assigned to actual devices.
862 */
863 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4
LT		 864
865 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
866 return gsi;
867
1da177e4
LT		 868 /* Don't set up the ACPI SCI because it's already set up */
869 if (acpi_fadt.sci_int == gsi)
870 return gsi;
1da177e4
LT		 871
872 ioapic = mp_find_ioapic(gsi);
873 if (ioapic < 0) {
874 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
875 return gsi;
876 }
877
878 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
879
880 /*
881 * Avoid pin reprogramming. PRTs typically include entries
882 * with redundant pin->gsi mappings (but unique PCI devices);
883 * we only program the IOAPIC on the first.
884 */
885 bit = ioapic_pin % 32;
886 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
887 if (idx > 3) {
888 printk(KERN_ERR "Invalid reference to IOAPIC pin "
889 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
890 ioapic_pin);
891 return gsi;
892 }
893 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
894 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
895 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
701067c4 896 return gsi_to_irq[gsi];
1da177e4
LT		 897 }
898
899 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
900
cb654695 901 if (triggering == ACPI_LEVEL_SENSITIVE) {
701067c4
NP		 902 /*
903 * For PCI devices assign IRQs in order, avoiding gaps
904 * due to unused I/O APIC pins.
905 */
906 int irq = gsi;
6a1caa21 907 if (gsi < MAX_GSI_NUM) {
e0c1e9bf
KM		 908 /*
909 * Retain the VIA chipset work-around (gsi > 15), but
910 * avoid a problem where the 8254 timer (IRQ0) is setup
911 * via an override (so it's not on pin 0 of the ioapic),
912 * and at the same time, the pin 0 interrupt is a PCI
913 * type. The gsi > 15 test could cause these two pins
914 * to be shared as IRQ0, and they are not shareable.
915 * So test for this condition, and if necessary, avoid
916 * the pin collision.
917 */
918 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
6a1caa21 919 gsi = pci_irq++;
6a1caa21
NP		 920 /*
921 * Don't assign IRQ used by ACPI SCI
922 */
923 if (gsi == acpi_fadt.sci_int)
924 gsi = pci_irq++;
6a1caa21
NP		 925 gsi_to_irq[irq] = gsi;
926 } else {
927 printk(KERN_ERR "GSI %u is too high\n", gsi);
928 return gsi;
929 }
701067c4
NP		 930 }
931
1da177e4 932 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
50eca3eb
BM		 933 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
934 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1da177e4
LT		 935 return gsi;
936}
937
888ba6c6 938#endif /*CONFIG_ACPI*/
kernel source for telekom puls (alcatel/mediatek)