Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
8a8f422d | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
136d249e | 67 | |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
263b5e86 JR |
71 | #ifdef CONFIG_IRQ_REMAP |
72 | static void irq_remap_modify_chip_defaults(struct irq_chip *chip); | |
73 | static inline bool irq_remapped(struct irq_cfg *cfg) | |
74 | { | |
75 | return cfg->irq_2_iommu.iommu != NULL; | |
76 | } | |
77 | #else | |
78 | static inline bool irq_remapped(struct irq_cfg *cfg) | |
79 | { | |
80 | return false; | |
81 | } | |
82 | static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip) | |
83 | { | |
84 | } | |
85 | #endif | |
86 | ||
1da177e4 | 87 | /* |
54168ed7 IM |
88 | * Is the SiS APIC rmw bug present ? |
89 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
90 | */ |
91 | int sis_apic_bug = -1; | |
92 | ||
dade7716 TG |
93 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
94 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 95 | |
b69c6c3b SS |
96 | static struct ioapic { |
97 | /* | |
98 | * # of IRQ routing registers | |
99 | */ | |
100 | int nr_registers; | |
57a6f740 SS |
101 | /* |
102 | * Saved state during suspend/resume, or while enabling intr-remap. | |
103 | */ | |
104 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
105 | /* I/O APIC config */ |
106 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
107 | /* IO APIC gsi routing info */ |
108 | struct mp_ioapic_gsi gsi_config; | |
8f18c971 | 109 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
b69c6c3b | 110 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 111 | |
6f50d45f | 112 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 113 | |
6f50d45f | 114 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 115 | { |
6f50d45f | 116 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
117 | } |
118 | ||
6f50d45f | 119 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 120 | { |
6f50d45f | 121 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
122 | } |
123 | ||
6f50d45f | 124 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 125 | { |
6f50d45f | 126 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 127 | } |
9f640ccb | 128 | |
c040aaeb | 129 | int nr_ioapics; |
2a4ab640 | 130 | |
a4384df3 EB |
131 | /* The one past the highest gsi number used */ |
132 | u32 gsi_top; | |
5777372a | 133 | |
584f734d | 134 | /* MP IRQ source entries */ |
c2c21745 | 135 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
136 | |
137 | /* # of MP IRQ source entries */ | |
138 | int mp_irq_entries; | |
139 | ||
bc07844a TG |
140 | /* GSI interrupts */ |
141 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
142 | ||
bb8187d3 | 143 | #ifdef CONFIG_EISA |
8732fc4b AS |
144 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
145 | #endif | |
146 | ||
147 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
148 | ||
efa2559f YL |
149 | int skip_ioapic_setup; |
150 | ||
7167d08e HK |
151 | /** |
152 | * disable_ioapic_support() - disables ioapic support at runtime | |
153 | */ | |
154 | void disable_ioapic_support(void) | |
65a4e574 IM |
155 | { |
156 | #ifdef CONFIG_PCI | |
157 | noioapicquirk = 1; | |
158 | noioapicreroute = -1; | |
159 | #endif | |
160 | skip_ioapic_setup = 1; | |
161 | } | |
162 | ||
54168ed7 | 163 | static int __init parse_noapic(char *str) |
efa2559f YL |
164 | { |
165 | /* disable IO-APIC */ | |
7167d08e | 166 | disable_ioapic_support(); |
efa2559f YL |
167 | return 0; |
168 | } | |
169 | early_param("noapic", parse_noapic); | |
66759a01 | 170 | |
20443598 SAS |
171 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
172 | struct io_apic_irq_attr *attr); | |
710dcda6 | 173 | |
2d8009ba FT |
174 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
175 | void mp_save_irq(struct mpc_intsrc *m) | |
176 | { | |
177 | int i; | |
178 | ||
179 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
180 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
181 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
182 | m->srcbusirq, m->dstapic, m->dstirq); | |
183 | ||
184 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 185 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
186 | return; |
187 | } | |
188 | ||
0e3fa13f | 189 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
190 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
191 | panic("Max # of irq sources exceeded!!\n"); | |
192 | } | |
193 | ||
0b8f1efa YL |
194 | struct irq_pin_list { |
195 | int apic, pin; | |
196 | struct irq_pin_list *next; | |
197 | }; | |
198 | ||
7e495529 | 199 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 200 | { |
2ee39065 | 201 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
202 | } |
203 | ||
2d8009ba | 204 | |
a1420f39 | 205 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
97943390 | 206 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
a1420f39 | 207 | |
13a0c3c2 | 208 | int __init arch_early_irq_init(void) |
8f09cd20 | 209 | { |
0b8f1efa | 210 | struct irq_cfg *cfg; |
60c69948 | 211 | int count, node, i; |
d6c88a50 | 212 | |
bb84ac2d | 213 | if (!legacy_pic->nr_legacy_irqs) |
1f91233c | 214 | io_apic_irqs = ~0UL; |
1f91233c | 215 | |
4c79185c | 216 | for (i = 0; i < nr_ioapics; i++) { |
57a6f740 | 217 | ioapics[i].saved_registers = |
4c79185c | 218 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 219 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 220 | if (!ioapics[i].saved_registers) |
4c79185c SS |
221 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
222 | } | |
223 | ||
0b8f1efa YL |
224 | cfg = irq_cfgx; |
225 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 226 | node = cpu_to_node(0); |
8f09cd20 | 227 | |
fbc6bff0 TG |
228 | /* Make sure the legacy interrupts are marked in the bitmap */ |
229 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
230 | ||
0b8f1efa | 231 | for (i = 0; i < count; i++) { |
2c778651 | 232 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
233 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
234 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
235 | /* |
236 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
237 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
238 | */ | |
54b56170 | 239 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
240 | cfg[i].vector = IRQ0_VECTOR + i; |
241 | cpumask_set_cpu(0, cfg[i].domain); | |
242 | } | |
0b8f1efa | 243 | } |
13a0c3c2 YL |
244 | |
245 | return 0; | |
0b8f1efa | 246 | } |
8f09cd20 | 247 | |
48b26501 | 248 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 249 | { |
2c778651 | 250 | return irq_get_chip_data(irq); |
8f09cd20 | 251 | } |
d6c88a50 | 252 | |
f981a3dc | 253 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 254 | { |
0b8f1efa | 255 | struct irq_cfg *cfg; |
0f978f45 | 256 | |
2ee39065 | 257 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
258 | if (!cfg) |
259 | return NULL; | |
2ee39065 | 260 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 261 | goto out_cfg; |
2ee39065 | 262 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 263 | goto out_domain; |
0b8f1efa | 264 | return cfg; |
6e2fff50 TG |
265 | out_domain: |
266 | free_cpumask_var(cfg->domain); | |
267 | out_cfg: | |
268 | kfree(cfg); | |
269 | return NULL; | |
8f09cd20 YL |
270 | } |
271 | ||
f981a3dc | 272 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 273 | { |
fbc6bff0 TG |
274 | if (!cfg) |
275 | return; | |
2c778651 | 276 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
277 | free_cpumask_var(cfg->domain); |
278 | free_cpumask_var(cfg->old_domain); | |
279 | kfree(cfg); | |
280 | } | |
281 | ||
08c33db6 TG |
282 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
283 | { | |
284 | int res = irq_alloc_desc_at(at, node); | |
285 | struct irq_cfg *cfg; | |
286 | ||
287 | if (res < 0) { | |
288 | if (res != -EEXIST) | |
289 | return NULL; | |
2c778651 | 290 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
291 | if (cfg) |
292 | return cfg; | |
293 | } | |
294 | ||
f981a3dc | 295 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 296 | if (cfg) |
2c778651 | 297 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
298 | else |
299 | irq_free_desc(at); | |
300 | return cfg; | |
301 | } | |
302 | ||
303 | static int alloc_irq_from(unsigned int from, int node) | |
304 | { | |
305 | return irq_alloc_desc_from(from, node); | |
306 | } | |
307 | ||
308 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
309 | { | |
f981a3dc | 310 | free_irq_cfg(at, cfg); |
08c33db6 TG |
311 | irq_free_desc(at); |
312 | } | |
313 | ||
136d249e | 314 | |
130fe05d LT |
315 | struct io_apic { |
316 | unsigned int index; | |
317 | unsigned int unused[3]; | |
318 | unsigned int data; | |
0280f7c4 SS |
319 | unsigned int unused2[11]; |
320 | unsigned int eoi; | |
130fe05d LT |
321 | }; |
322 | ||
323 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
324 | { | |
325 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 326 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
327 | } |
328 | ||
0280f7c4 SS |
329 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
330 | { | |
331 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
332 | writel(vector, &io_apic->eoi); | |
333 | } | |
334 | ||
4a8e2a31 | 335 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
336 | { |
337 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
338 | writel(reg, &io_apic->index); | |
339 | return readl(&io_apic->data); | |
340 | } | |
341 | ||
4a8e2a31 | 342 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
343 | { |
344 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 345 | |
130fe05d LT |
346 | writel(reg, &io_apic->index); |
347 | writel(value, &io_apic->data); | |
348 | } | |
349 | ||
350 | /* | |
351 | * Re-write a value: to be used for read-modify-write | |
352 | * cycles where the read already set up the index register. | |
353 | * | |
354 | * Older SiS APIC requires we rewrite the index register | |
355 | */ | |
4a8e2a31 | 356 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 357 | { |
54168ed7 | 358 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
359 | |
360 | if (sis_apic_bug) | |
361 | writel(reg, &io_apic->index); | |
130fe05d LT |
362 | writel(value, &io_apic->data); |
363 | } | |
364 | ||
cf4c6a2f AK |
365 | union entry_union { |
366 | struct { u32 w1, w2; }; | |
367 | struct IO_APIC_route_entry entry; | |
368 | }; | |
369 | ||
e57253a8 SS |
370 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
371 | { | |
372 | union entry_union eu; | |
373 | ||
374 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
375 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 376 | |
e57253a8 SS |
377 | return eu.entry; |
378 | } | |
379 | ||
cf4c6a2f AK |
380 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
381 | { | |
382 | union entry_union eu; | |
383 | unsigned long flags; | |
136d249e | 384 | |
dade7716 | 385 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 386 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 387 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 388 | |
cf4c6a2f AK |
389 | return eu.entry; |
390 | } | |
391 | ||
f9dadfa7 LT |
392 | /* |
393 | * When we write a new IO APIC routing entry, we need to write the high | |
394 | * word first! If the mask bit in the low word is clear, we will enable | |
395 | * the interrupt, and we need to make sure the entry is fully populated | |
396 | * before that happens. | |
397 | */ | |
136d249e | 398 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 399 | { |
50a8d4d2 F |
400 | union entry_union eu = {{0, 0}}; |
401 | ||
cf4c6a2f | 402 | eu.entry = e; |
f9dadfa7 LT |
403 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
404 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
405 | } |
406 | ||
1a8ce7ff | 407 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
408 | { |
409 | unsigned long flags; | |
136d249e | 410 | |
dade7716 | 411 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 412 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 413 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
414 | } |
415 | ||
416 | /* | |
417 | * When we mask an IO APIC routing entry, we need to write the low | |
418 | * word first, in order to set the mask bit before we change the | |
419 | * high bits! | |
420 | */ | |
421 | static void ioapic_mask_entry(int apic, int pin) | |
422 | { | |
423 | unsigned long flags; | |
424 | union entry_union eu = { .entry.mask = 1 }; | |
425 | ||
dade7716 | 426 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
427 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
428 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 429 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
430 | } |
431 | ||
1da177e4 LT |
432 | /* |
433 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
434 | * shared ISA-space IRQs, so we have to support them. We are super | |
435 | * fast in the common case, and fast for shared ISA-space IRQs. | |
436 | */ | |
136d249e | 437 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 438 | { |
2977fb3f | 439 | struct irq_pin_list **last, *entry; |
0f978f45 | 440 | |
2977fb3f CG |
441 | /* don't allow duplicates */ |
442 | last = &cfg->irq_2_pin; | |
443 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 444 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 445 | return 0; |
2977fb3f | 446 | last = &entry->next; |
1da177e4 | 447 | } |
0f978f45 | 448 | |
7e495529 | 449 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 450 | if (!entry) { |
c767a54b JP |
451 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
452 | node, apic, pin); | |
f3d1915a | 453 | return -ENOMEM; |
a7428cd2 | 454 | } |
1da177e4 LT |
455 | entry->apic = apic; |
456 | entry->pin = pin; | |
875e68ec | 457 | |
2977fb3f | 458 | *last = entry; |
f3d1915a CG |
459 | return 0; |
460 | } | |
461 | ||
462 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
463 | { | |
7e495529 | 464 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 465 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
466 | } |
467 | ||
468 | /* | |
469 | * Reroute an IRQ to a different pin. | |
470 | */ | |
85ac16d0 | 471 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
472 | int oldapic, int oldpin, |
473 | int newapic, int newpin) | |
1da177e4 | 474 | { |
535b6429 | 475 | struct irq_pin_list *entry; |
1da177e4 | 476 | |
2977fb3f | 477 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
478 | if (entry->apic == oldapic && entry->pin == oldpin) { |
479 | entry->apic = newapic; | |
480 | entry->pin = newpin; | |
0f978f45 | 481 | /* every one is different, right? */ |
4eea6fff | 482 | return; |
0f978f45 | 483 | } |
1da177e4 | 484 | } |
0f978f45 | 485 | |
4eea6fff JF |
486 | /* old apic/pin didn't exist, so just add new ones */ |
487 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
488 | } |
489 | ||
c29d9db3 SS |
490 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
491 | int mask_and, int mask_or, | |
492 | void (*final)(struct irq_pin_list *entry)) | |
493 | { | |
494 | unsigned int reg, pin; | |
495 | ||
496 | pin = entry->pin; | |
497 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
498 | reg &= mask_and; | |
499 | reg |= mask_or; | |
500 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
501 | if (final) | |
502 | final(entry); | |
503 | } | |
504 | ||
2f210deb JF |
505 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
506 | int mask_and, int mask_or, | |
507 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 508 | { |
87783be4 | 509 | struct irq_pin_list *entry; |
047c8fdb | 510 | |
c29d9db3 SS |
511 | for_each_irq_pin(entry, cfg->irq_2_pin) |
512 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
513 | } | |
514 | ||
7f3e632f | 515 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 516 | { |
87783be4 CG |
517 | /* |
518 | * Synchronize the IO-APIC and the CPU by doing | |
519 | * a dummy read from the IO-APIC | |
520 | */ | |
521 | struct io_apic __iomem *io_apic; | |
136d249e | 522 | |
87783be4 | 523 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 524 | readl(&io_apic->data); |
1da177e4 LT |
525 | } |
526 | ||
dd5f15e5 | 527 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 528 | { |
dd5f15e5 TG |
529 | unsigned long flags; |
530 | ||
531 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 532 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 533 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 534 | } |
1da177e4 | 535 | |
90297c5f | 536 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 537 | { |
90297c5f | 538 | mask_ioapic(data->chip_data); |
dd5f15e5 | 539 | } |
3145e941 | 540 | |
dd5f15e5 TG |
541 | static void __unmask_ioapic(struct irq_cfg *cfg) |
542 | { | |
543 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
544 | } |
545 | ||
dd5f15e5 | 546 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
547 | { |
548 | unsigned long flags; | |
549 | ||
dade7716 | 550 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 551 | __unmask_ioapic(cfg); |
dade7716 | 552 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
553 | } |
554 | ||
90297c5f | 555 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 556 | { |
90297c5f | 557 | unmask_ioapic(data->chip_data); |
3145e941 YL |
558 | } |
559 | ||
c0205701 SS |
560 | /* |
561 | * IO-APIC versions below 0x20 don't support EOI register. | |
562 | * For the record, here is the information about various versions: | |
563 | * 0Xh 82489DX | |
564 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
565 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
566 | * 30h-FFh Reserved | |
567 | * | |
568 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
569 | * version as 0x2. This is an error with documentation and these ICH chips | |
570 | * use io-apic's of version 0x20. | |
571 | * | |
572 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
573 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
574 | * mode to edge and then back to level, with RTE being masked during this. | |
575 | */ | |
576 | static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg) | |
577 | { | |
578 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
579 | /* | |
580 | * Intr-remapping uses pin number as the virtual vector | |
581 | * in the RTE. Actual vector is programmed in | |
582 | * intr-remapping table entry. Hence for the io-apic | |
583 | * EOI we use the pin number. | |
584 | */ | |
585 | if (cfg && irq_remapped(cfg)) | |
586 | io_apic_eoi(apic, pin); | |
587 | else | |
588 | io_apic_eoi(apic, vector); | |
589 | } else { | |
590 | struct IO_APIC_route_entry entry, entry1; | |
591 | ||
592 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
593 | ||
594 | /* | |
595 | * Mask the entry and change the trigger mode to edge. | |
596 | */ | |
597 | entry1.mask = 1; | |
598 | entry1.trigger = IOAPIC_EDGE; | |
599 | ||
600 | __ioapic_write_entry(apic, pin, entry1); | |
601 | ||
602 | /* | |
603 | * Restore the previous level triggered entry. | |
604 | */ | |
605 | __ioapic_write_entry(apic, pin, entry); | |
606 | } | |
607 | } | |
608 | ||
609 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) | |
610 | { | |
611 | struct irq_pin_list *entry; | |
612 | unsigned long flags; | |
613 | ||
614 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
615 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
616 | __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg); | |
617 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
618 | } | |
619 | ||
1da177e4 LT |
620 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
621 | { | |
622 | struct IO_APIC_route_entry entry; | |
36062448 | 623 | |
1da177e4 | 624 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 625 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
626 | if (entry.delivery_mode == dest_SMI) |
627 | return; | |
1e75b31d | 628 | |
1da177e4 | 629 | /* |
1e75b31d SS |
630 | * Make sure the entry is masked and re-read the contents to check |
631 | * if it is a level triggered pin and if the remote-IRR is set. | |
632 | */ | |
633 | if (!entry.mask) { | |
634 | entry.mask = 1; | |
635 | ioapic_write_entry(apic, pin, entry); | |
636 | entry = ioapic_read_entry(apic, pin); | |
637 | } | |
638 | ||
639 | if (entry.irr) { | |
c0205701 SS |
640 | unsigned long flags; |
641 | ||
1e75b31d SS |
642 | /* |
643 | * Make sure the trigger mode is set to level. Explicit EOI | |
644 | * doesn't clear the remote-IRR if the trigger mode is not | |
645 | * set to level. | |
646 | */ | |
647 | if (!entry.trigger) { | |
648 | entry.trigger = IOAPIC_LEVEL; | |
649 | ioapic_write_entry(apic, pin, entry); | |
650 | } | |
651 | ||
c0205701 SS |
652 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
653 | __eoi_ioapic_pin(apic, pin, entry.vector, NULL); | |
654 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1e75b31d SS |
655 | } |
656 | ||
657 | /* | |
658 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
659 | * bit. | |
1da177e4 | 660 | */ |
f9dadfa7 | 661 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
662 | entry = ioapic_read_entry(apic, pin); |
663 | if (entry.irr) | |
c767a54b | 664 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 665 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
666 | } |
667 | ||
54168ed7 | 668 | static void clear_IO_APIC (void) |
1da177e4 LT |
669 | { |
670 | int apic, pin; | |
671 | ||
672 | for (apic = 0; apic < nr_ioapics; apic++) | |
b69c6c3b | 673 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
1da177e4 LT |
674 | clear_IO_APIC_pin(apic, pin); |
675 | } | |
676 | ||
54168ed7 | 677 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
678 | /* |
679 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
680 | * specific CPU-side IRQs. | |
681 | */ | |
682 | ||
683 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
684 | static int pirq_entries[MAX_PIRQS] = { |
685 | [0 ... MAX_PIRQS - 1] = -1 | |
686 | }; | |
1da177e4 | 687 | |
1da177e4 LT |
688 | static int __init ioapic_pirq_setup(char *str) |
689 | { | |
690 | int i, max; | |
691 | int ints[MAX_PIRQS+1]; | |
692 | ||
693 | get_options(str, ARRAY_SIZE(ints), ints); | |
694 | ||
1da177e4 LT |
695 | apic_printk(APIC_VERBOSE, KERN_INFO |
696 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
697 | max = MAX_PIRQS; | |
698 | if (ints[0] < MAX_PIRQS) | |
699 | max = ints[0]; | |
700 | ||
701 | for (i = 0; i < max; i++) { | |
702 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
703 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
704 | /* | |
705 | * PIRQs are mapped upside down, usually. | |
706 | */ | |
707 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
708 | } | |
709 | return 1; | |
710 | } | |
711 | ||
712 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
713 | #endif /* CONFIG_X86_32 */ |
714 | ||
54168ed7 | 715 | /* |
05c3dc2c | 716 | * Saves all the IO-APIC RTE's |
54168ed7 | 717 | */ |
31dce14a | 718 | int save_ioapic_entries(void) |
54168ed7 | 719 | { |
54168ed7 | 720 | int apic, pin; |
31dce14a | 721 | int err = 0; |
54168ed7 IM |
722 | |
723 | for (apic = 0; apic < nr_ioapics; apic++) { | |
57a6f740 | 724 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
725 | err = -ENOMEM; |
726 | continue; | |
727 | } | |
54168ed7 | 728 | |
b69c6c3b | 729 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
57a6f740 | 730 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 731 | ioapic_read_entry(apic, pin); |
b24696bc | 732 | } |
5ffa4eb2 | 733 | |
31dce14a | 734 | return err; |
54168ed7 IM |
735 | } |
736 | ||
b24696bc FY |
737 | /* |
738 | * Mask all IO APIC entries. | |
739 | */ | |
31dce14a | 740 | void mask_ioapic_entries(void) |
05c3dc2c SS |
741 | { |
742 | int apic, pin; | |
743 | ||
744 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2f344d2e | 745 | if (!ioapics[apic].saved_registers) |
31dce14a | 746 | continue; |
b24696bc | 747 | |
b69c6c3b | 748 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
05c3dc2c SS |
749 | struct IO_APIC_route_entry entry; |
750 | ||
57a6f740 | 751 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
752 | if (!entry.mask) { |
753 | entry.mask = 1; | |
754 | ioapic_write_entry(apic, pin, entry); | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
b24696bc | 760 | /* |
57a6f740 | 761 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 762 | */ |
31dce14a | 763 | int restore_ioapic_entries(void) |
54168ed7 IM |
764 | { |
765 | int apic, pin; | |
766 | ||
5ffa4eb2 | 767 | for (apic = 0; apic < nr_ioapics; apic++) { |
2f344d2e | 768 | if (!ioapics[apic].saved_registers) |
31dce14a | 769 | continue; |
b24696bc | 770 | |
b69c6c3b | 771 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
54168ed7 | 772 | ioapic_write_entry(apic, pin, |
57a6f740 | 773 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 774 | } |
b24696bc | 775 | return 0; |
54168ed7 IM |
776 | } |
777 | ||
1da177e4 LT |
778 | /* |
779 | * Find the IRQ entry number of a certain pin. | |
780 | */ | |
6f50d45f | 781 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
782 | { |
783 | int i; | |
784 | ||
785 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 786 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 787 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
788 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
789 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
790 | return i; |
791 | ||
792 | return -1; | |
793 | } | |
794 | ||
795 | /* | |
796 | * Find the pin to which IRQ[irq] (ISA) is connected | |
797 | */ | |
fcfd636a | 798 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
799 | { |
800 | int i; | |
801 | ||
802 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 803 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 804 | |
d27e2b8e | 805 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
806 | (mp_irqs[i].irqtype == type) && |
807 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 808 | |
c2c21745 | 809 | return mp_irqs[i].dstirq; |
1da177e4 LT |
810 | } |
811 | return -1; | |
812 | } | |
813 | ||
fcfd636a EB |
814 | static int __init find_isa_irq_apic(int irq, int type) |
815 | { | |
816 | int i; | |
817 | ||
818 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 819 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 820 | |
73b2961b | 821 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
822 | (mp_irqs[i].irqtype == type) && |
823 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
824 | break; |
825 | } | |
6f50d45f | 826 | |
fcfd636a | 827 | if (i < mp_irq_entries) { |
6f50d45f YL |
828 | int ioapic_idx; |
829 | ||
830 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) | |
831 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) | |
832 | return ioapic_idx; | |
fcfd636a EB |
833 | } |
834 | ||
835 | return -1; | |
836 | } | |
837 | ||
bb8187d3 | 838 | #ifdef CONFIG_EISA |
1da177e4 LT |
839 | /* |
840 | * EISA Edge/Level control register, ELCR | |
841 | */ | |
842 | static int EISA_ELCR(unsigned int irq) | |
843 | { | |
b81bb373 | 844 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
845 | unsigned int port = 0x4d0 + (irq >> 3); |
846 | return (inb(port) >> (irq & 7)) & 1; | |
847 | } | |
848 | apic_printk(APIC_VERBOSE, KERN_INFO | |
849 | "Broken MPtable reports ISA irq %d\n", irq); | |
850 | return 0; | |
851 | } | |
54168ed7 | 852 | |
c0a282c2 | 853 | #endif |
1da177e4 | 854 | |
6728801d AS |
855 | /* ISA interrupts are always polarity zero edge triggered, |
856 | * when listed as conforming in the MP table. */ | |
857 | ||
858 | #define default_ISA_trigger(idx) (0) | |
859 | #define default_ISA_polarity(idx) (0) | |
860 | ||
1da177e4 LT |
861 | /* EISA interrupts are always polarity zero and can be edge or level |
862 | * trigger depending on the ELCR value. If an interrupt is listed as | |
863 | * EISA conforming in the MP table, that means its trigger type must | |
864 | * be read in from the ELCR */ | |
865 | ||
c2c21745 | 866 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 867 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
868 | |
869 | /* PCI interrupts are always polarity one level triggered, | |
870 | * when listed as conforming in the MP table. */ | |
871 | ||
872 | #define default_PCI_trigger(idx) (1) | |
873 | #define default_PCI_polarity(idx) (1) | |
874 | ||
b77cf6a8 | 875 | static int irq_polarity(int idx) |
1da177e4 | 876 | { |
c2c21745 | 877 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
878 | int polarity; |
879 | ||
880 | /* | |
881 | * Determine IRQ line polarity (high active or low active): | |
882 | */ | |
c2c21745 | 883 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 884 | { |
54168ed7 IM |
885 | case 0: /* conforms, ie. bus-type dependent polarity */ |
886 | if (test_bit(bus, mp_bus_not_pci)) | |
887 | polarity = default_ISA_polarity(idx); | |
888 | else | |
889 | polarity = default_PCI_polarity(idx); | |
890 | break; | |
891 | case 1: /* high active */ | |
892 | { | |
893 | polarity = 0; | |
894 | break; | |
895 | } | |
896 | case 2: /* reserved */ | |
897 | { | |
c767a54b | 898 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
899 | polarity = 1; |
900 | break; | |
901 | } | |
902 | case 3: /* low active */ | |
903 | { | |
904 | polarity = 1; | |
905 | break; | |
906 | } | |
907 | default: /* invalid */ | |
908 | { | |
c767a54b | 909 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
910 | polarity = 1; |
911 | break; | |
912 | } | |
1da177e4 LT |
913 | } |
914 | return polarity; | |
915 | } | |
916 | ||
b77cf6a8 | 917 | static int irq_trigger(int idx) |
1da177e4 | 918 | { |
c2c21745 | 919 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
920 | int trigger; |
921 | ||
922 | /* | |
923 | * Determine IRQ trigger mode (edge or level sensitive): | |
924 | */ | |
c2c21745 | 925 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 926 | { |
54168ed7 IM |
927 | case 0: /* conforms, ie. bus-type dependent */ |
928 | if (test_bit(bus, mp_bus_not_pci)) | |
929 | trigger = default_ISA_trigger(idx); | |
930 | else | |
931 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 932 | #ifdef CONFIG_EISA |
54168ed7 IM |
933 | switch (mp_bus_id_to_type[bus]) { |
934 | case MP_BUS_ISA: /* ISA pin */ | |
935 | { | |
936 | /* set before the switch */ | |
937 | break; | |
938 | } | |
939 | case MP_BUS_EISA: /* EISA pin */ | |
940 | { | |
941 | trigger = default_EISA_trigger(idx); | |
942 | break; | |
943 | } | |
944 | case MP_BUS_PCI: /* PCI pin */ | |
945 | { | |
946 | /* set before the switch */ | |
947 | break; | |
948 | } | |
54168ed7 IM |
949 | default: |
950 | { | |
c767a54b | 951 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
952 | trigger = 1; |
953 | break; | |
954 | } | |
955 | } | |
956 | #endif | |
1da177e4 | 957 | break; |
54168ed7 | 958 | case 1: /* edge */ |
1da177e4 | 959 | { |
54168ed7 | 960 | trigger = 0; |
1da177e4 LT |
961 | break; |
962 | } | |
54168ed7 | 963 | case 2: /* reserved */ |
1da177e4 | 964 | { |
c767a54b | 965 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 966 | trigger = 1; |
1da177e4 LT |
967 | break; |
968 | } | |
54168ed7 | 969 | case 3: /* level */ |
1da177e4 | 970 | { |
54168ed7 | 971 | trigger = 1; |
1da177e4 LT |
972 | break; |
973 | } | |
54168ed7 | 974 | default: /* invalid */ |
1da177e4 | 975 | { |
c767a54b | 976 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 977 | trigger = 0; |
1da177e4 LT |
978 | break; |
979 | } | |
980 | } | |
981 | return trigger; | |
982 | } | |
983 | ||
1da177e4 LT |
984 | static int pin_2_irq(int idx, int apic, int pin) |
985 | { | |
d464207c | 986 | int irq; |
c2c21745 | 987 | int bus = mp_irqs[idx].srcbus; |
c040aaeb | 988 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
1da177e4 LT |
989 | |
990 | /* | |
991 | * Debugging check, we are in big trouble if this message pops up! | |
992 | */ | |
c2c21745 | 993 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 994 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 995 | |
54168ed7 | 996 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 997 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 998 | } else { |
c040aaeb | 999 | u32 gsi = gsi_cfg->gsi_base + pin; |
988856ee EB |
1000 | |
1001 | if (gsi >= NR_IRQS_LEGACY) | |
1002 | irq = gsi; | |
1003 | else | |
a4384df3 | 1004 | irq = gsi_top + gsi; |
1da177e4 LT |
1005 | } |
1006 | ||
54168ed7 | 1007 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1008 | /* |
1009 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1010 | */ | |
1011 | if ((pin >= 16) && (pin <= 23)) { | |
1012 | if (pirq_entries[pin-16] != -1) { | |
1013 | if (!pirq_entries[pin-16]) { | |
1014 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1015 | "disabling PIRQ%d\n", pin-16); | |
1016 | } else { | |
1017 | irq = pirq_entries[pin-16]; | |
1018 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1019 | "using PIRQ%d -> IRQ %d\n", | |
1020 | pin-16, irq); | |
1021 | } | |
1022 | } | |
1023 | } | |
54168ed7 IM |
1024 | #endif |
1025 | ||
1da177e4 LT |
1026 | return irq; |
1027 | } | |
1028 | ||
e20c06fd YL |
1029 | /* |
1030 | * Find a specific PCI IRQ entry. | |
1031 | * Not an __init, possibly needed by modules | |
1032 | */ | |
1033 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1034 | struct io_apic_irq_attr *irq_attr) |
e20c06fd | 1035 | { |
6f50d45f | 1036 | int ioapic_idx, i, best_guess = -1; |
e20c06fd YL |
1037 | |
1038 | apic_printk(APIC_DEBUG, | |
1039 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1040 | bus, slot, pin); | |
1041 | if (test_bit(bus, mp_bus_not_pci)) { | |
1042 | apic_printk(APIC_VERBOSE, | |
1043 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1044 | return -1; | |
1045 | } | |
1046 | for (i = 0; i < mp_irq_entries; i++) { | |
1047 | int lbus = mp_irqs[i].srcbus; | |
1048 | ||
6f50d45f YL |
1049 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1050 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || | |
e20c06fd YL |
1051 | mp_irqs[i].dstapic == MP_APIC_ALL) |
1052 | break; | |
1053 | ||
1054 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1055 | !mp_irqs[i].irqtype && | |
1056 | (bus == lbus) && | |
1057 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
6f50d45f | 1058 | int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); |
e20c06fd | 1059 | |
6f50d45f | 1060 | if (!(ioapic_idx || IO_APIC_IRQ(irq))) |
e20c06fd YL |
1061 | continue; |
1062 | ||
1063 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
6f50d45f | 1064 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1065 | mp_irqs[i].dstirq, |
1066 | irq_trigger(i), | |
1067 | irq_polarity(i)); | |
e20c06fd YL |
1068 | return irq; |
1069 | } | |
1070 | /* | |
1071 | * Use the first all-but-pin matching entry as a | |
1072 | * best-guess fuzzy result for broken mptables. | |
1073 | */ | |
1074 | if (best_guess < 0) { | |
6f50d45f | 1075 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1076 | mp_irqs[i].dstirq, |
1077 | irq_trigger(i), | |
1078 | irq_polarity(i)); | |
e20c06fd YL |
1079 | best_guess = irq; |
1080 | } | |
1081 | } | |
1082 | } | |
1083 | return best_guess; | |
1084 | } | |
1085 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1086 | ||
497c9a19 YL |
1087 | void lock_vector_lock(void) |
1088 | { | |
1089 | /* Used to the online set of cpus does not change | |
1090 | * during assign_irq_vector. | |
1091 | */ | |
dade7716 | 1092 | raw_spin_lock(&vector_lock); |
497c9a19 | 1093 | } |
1da177e4 | 1094 | |
497c9a19 | 1095 | void unlock_vector_lock(void) |
1da177e4 | 1096 | { |
dade7716 | 1097 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1098 | } |
1da177e4 | 1099 | |
e7986739 MT |
1100 | static int |
1101 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1102 | { |
047c8fdb YL |
1103 | /* |
1104 | * NOTE! The local APIC isn't very good at handling | |
1105 | * multiple interrupts at the same interrupt level. | |
1106 | * As the interrupt level is determined by taking the | |
1107 | * vector number and shifting that right by 4, we | |
1108 | * want to spread these out a bit so that they don't | |
1109 | * all fall in the same interrupt level. | |
1110 | * | |
1111 | * Also, we've got to be careful not to trash gate | |
1112 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1113 | */ | |
6579b474 | 1114 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
1bccd58b | 1115 | static int current_offset = VECTOR_OFFSET_START % 16; |
22f65d31 MT |
1116 | int cpu, err; |
1117 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1118 | |
23359a88 | 1119 | if (cfg->move_in_progress) |
54168ed7 | 1120 | return -EBUSY; |
0a1ad60d | 1121 | |
22f65d31 MT |
1122 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1123 | return -ENOMEM; | |
ace80ab7 | 1124 | |
e7986739 | 1125 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 | 1126 | err = -ENOSPC; |
b39f25a8 SS |
1127 | cpumask_clear(cfg->old_domain); |
1128 | cpu = cpumask_first_and(mask, cpu_online_mask); | |
1129 | while (cpu < nr_cpu_ids) { | |
1ac322d0 | 1130 | int new_cpu, vector, offset; |
497c9a19 | 1131 | |
1ac322d0 | 1132 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
497c9a19 | 1133 | |
332afa65 | 1134 | if (cpumask_subset(tmp_mask, cfg->domain)) { |
1ac322d0 SS |
1135 | err = 0; |
1136 | if (cpumask_equal(tmp_mask, cfg->domain)) | |
1137 | break; | |
1138 | /* | |
1139 | * New cpumask using the vector is a proper subset of | |
1140 | * the current in use mask. So cleanup the vector | |
1141 | * allocation for the members that are not used anymore. | |
1142 | */ | |
1143 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | |
1144 | cfg->move_in_progress = 1; | |
1145 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); | |
1146 | break; | |
332afa65 | 1147 | } |
497c9a19 | 1148 | |
54168ed7 IM |
1149 | vector = current_vector; |
1150 | offset = current_offset; | |
497c9a19 | 1151 | next: |
1bccd58b | 1152 | vector += 16; |
54168ed7 | 1153 | if (vector >= first_system_vector) { |
1bccd58b | 1154 | offset = (offset + 1) % 16; |
6579b474 | 1155 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 | 1156 | } |
8637e38a AG |
1157 | |
1158 | if (unlikely(current_vector == vector)) { | |
b39f25a8 SS |
1159 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); |
1160 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | |
1161 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | |
54168ed7 | 1162 | continue; |
8637e38a | 1163 | } |
b77b881f YL |
1164 | |
1165 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1166 | goto next; |
b77b881f | 1167 | |
22f65d31 | 1168 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1169 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1170 | goto next; | |
1171 | /* Found one! */ | |
1172 | current_vector = vector; | |
1173 | current_offset = offset; | |
1ac322d0 | 1174 | if (cfg->vector) { |
54168ed7 | 1175 | cfg->move_in_progress = 1; |
22f65d31 | 1176 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1177 | } |
22f65d31 | 1178 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1179 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1180 | cfg->vector = vector; | |
22f65d31 MT |
1181 | cpumask_copy(cfg->domain, tmp_mask); |
1182 | err = 0; | |
1183 | break; | |
54168ed7 | 1184 | } |
22f65d31 MT |
1185 | free_cpumask_var(tmp_mask); |
1186 | return err; | |
497c9a19 YL |
1187 | } |
1188 | ||
9338ad6f | 1189 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1190 | { |
1191 | int err; | |
ace80ab7 | 1192 | unsigned long flags; |
ace80ab7 | 1193 | |
dade7716 | 1194 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1195 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1196 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1197 | return err; |
1198 | } | |
1199 | ||
3145e941 | 1200 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1201 | { |
497c9a19 YL |
1202 | int cpu, vector; |
1203 | ||
497c9a19 YL |
1204 | BUG_ON(!cfg->vector); |
1205 | ||
1206 | vector = cfg->vector; | |
1d44b30f | 1207 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1208 | per_cpu(vector_irq, cpu)[vector] = -1; |
1209 | ||
1210 | cfg->vector = 0; | |
22f65d31 | 1211 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1212 | |
1213 | if (likely(!cfg->move_in_progress)) | |
1214 | return; | |
1d44b30f | 1215 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1216 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1217 | vector++) { | |
1218 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1219 | continue; | |
1220 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1221 | break; | |
1222 | } | |
1223 | } | |
1224 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1225 | } |
1226 | ||
1227 | void __setup_vector_irq(int cpu) | |
1228 | { | |
1229 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1230 | int irq, vector; |
1231 | struct irq_cfg *cfg; | |
1232 | ||
9d133e5d SS |
1233 | /* |
1234 | * vector_lock will make sure that we don't run into irq vector | |
1235 | * assignments that might be happening on another cpu in parallel, | |
1236 | * while we setup our initial vector to irq mappings. | |
1237 | */ | |
dade7716 | 1238 | raw_spin_lock(&vector_lock); |
497c9a19 | 1239 | /* Mark the inuse vectors */ |
ad9f4334 | 1240 | for_each_active_irq(irq) { |
2c778651 | 1241 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1242 | if (!cfg) |
1243 | continue; | |
36e9e1ea SS |
1244 | /* |
1245 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1246 | * will be part of the irq_cfg's domain. | |
1247 | */ | |
1248 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1249 | cpumask_set_cpu(cpu, cfg->domain); | |
1250 | ||
22f65d31 | 1251 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1252 | continue; |
1253 | vector = cfg->vector; | |
497c9a19 YL |
1254 | per_cpu(vector_irq, cpu)[vector] = irq; |
1255 | } | |
1256 | /* Mark the free vectors */ | |
1257 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1258 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1259 | if (irq < 0) | |
1260 | continue; | |
1261 | ||
1262 | cfg = irq_cfg(irq); | |
22f65d31 | 1263 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1264 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1265 | } |
dade7716 | 1266 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1267 | } |
3fde6900 | 1268 | |
f5b9ed7a | 1269 | static struct irq_chip ioapic_chip; |
1da177e4 | 1270 | |
047c8fdb | 1271 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1272 | static inline int IO_APIC_irq_trigger(int irq) |
1273 | { | |
d6c88a50 | 1274 | int apic, idx, pin; |
1d025192 | 1275 | |
d6c88a50 | 1276 | for (apic = 0; apic < nr_ioapics; apic++) { |
b69c6c3b | 1277 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
d6c88a50 TG |
1278 | idx = find_irq_entry(apic, pin, mp_INT); |
1279 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1280 | return irq_trigger(idx); | |
1281 | } | |
1282 | } | |
1283 | /* | |
54168ed7 IM |
1284 | * nonexistent IRQs are edge default |
1285 | */ | |
d6c88a50 | 1286 | return 0; |
1d025192 | 1287 | } |
047c8fdb YL |
1288 | #else |
1289 | static inline int IO_APIC_irq_trigger(int irq) | |
1290 | { | |
54168ed7 | 1291 | return 1; |
047c8fdb YL |
1292 | } |
1293 | #endif | |
1d025192 | 1294 | |
1a0e62a4 TG |
1295 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1296 | unsigned long trigger) | |
1da177e4 | 1297 | { |
c60eaf25 TG |
1298 | struct irq_chip *chip = &ioapic_chip; |
1299 | irq_flow_handler_t hdl; | |
1300 | bool fasteoi; | |
199751d7 | 1301 | |
6ebcc00e | 1302 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1303 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1304 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1305 | fasteoi = true; |
1306 | } else { | |
60c69948 | 1307 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1308 | fasteoi = false; |
1309 | } | |
047c8fdb | 1310 | |
1a0e62a4 | 1311 | if (irq_remapped(cfg)) { |
60c69948 | 1312 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c39d77ff | 1313 | irq_remap_modify_chip_defaults(chip); |
c60eaf25 | 1314 | fasteoi = trigger != 0; |
54168ed7 | 1315 | } |
29b61be6 | 1316 | |
c60eaf25 TG |
1317 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1318 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1319 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1320 | } |
1321 | ||
c5b4712c YL |
1322 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1323 | unsigned int destination, int vector, | |
1324 | struct io_apic_irq_attr *attr) | |
1325 | { | |
95a02e97 SS |
1326 | if (irq_remapping_enabled) |
1327 | return setup_ioapic_remapped_entry(irq, entry, destination, | |
1328 | vector, attr); | |
497c9a19 | 1329 | |
c5b4712c YL |
1330 | memset(entry, 0, sizeof(*entry)); |
1331 | ||
1332 | entry->delivery_mode = apic->irq_delivery_mode; | |
1333 | entry->dest_mode = apic->irq_dest_mode; | |
1334 | entry->dest = destination; | |
1335 | entry->vector = vector; | |
1336 | entry->mask = 0; /* enable IRQ */ | |
1337 | entry->trigger = attr->trigger; | |
1338 | entry->polarity = attr->polarity; | |
1339 | ||
1340 | /* | |
1341 | * Mask level triggered irqs. | |
497c9a19 YL |
1342 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1343 | */ | |
c5b4712c | 1344 | if (attr->trigger) |
497c9a19 | 1345 | entry->mask = 1; |
c5b4712c | 1346 | |
497c9a19 YL |
1347 | return 0; |
1348 | } | |
1349 | ||
e4aff811 YL |
1350 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1351 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1352 | { |
1da177e4 | 1353 | struct IO_APIC_route_entry entry; |
22f65d31 | 1354 | unsigned int dest; |
497c9a19 YL |
1355 | |
1356 | if (!IO_APIC_IRQ(irq)) | |
1357 | return; | |
69c89efb | 1358 | |
f1c63001 SS |
1359 | /* |
1360 | * For legacy irqs, cfg->domain starts with cpu 0. Now that IO-APIC | |
1361 | * can handle this irq and the apic driver is finialized at this point, | |
1362 | * update the cfg->domain. | |
1363 | */ | |
1364 | if (irq < legacy_pic->nr_legacy_irqs && | |
1365 | cpumask_equal(cfg->domain, cpumask_of(0))) | |
1366 | apic->vector_allocation_domain(0, cfg->domain, | |
1367 | apic->target_cpus()); | |
1368 | ||
fe402e1f | 1369 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1370 | return; |
1371 | ||
ff164324 AG |
1372 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1373 | &dest)) { | |
1374 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1375 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
1376 | __clear_irq_vector(irq, cfg); | |
1377 | ||
1378 | return; | |
1379 | } | |
497c9a19 YL |
1380 | |
1381 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1382 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1383 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1384 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1385 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1386 | |
c5b4712c | 1387 | if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) { |
49d0c7a0 | 1388 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c5b4712c | 1389 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
3145e941 | 1390 | __clear_irq_vector(irq, cfg); |
c5b4712c | 1391 | |
497c9a19 YL |
1392 | return; |
1393 | } | |
1394 | ||
e4aff811 | 1395 | ioapic_register_intr(irq, cfg, attr->trigger); |
b81bb373 | 1396 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1397 | legacy_pic->mask(irq); |
497c9a19 | 1398 | |
e4aff811 | 1399 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1400 | } |
1401 | ||
6f50d45f | 1402 | static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) |
c8d6b8fe TG |
1403 | { |
1404 | if (idx != -1) | |
1405 | return false; | |
1406 | ||
1407 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
6f50d45f | 1408 | mpc_ioapic_id(ioapic_idx), pin); |
c8d6b8fe TG |
1409 | return true; |
1410 | } | |
1411 | ||
6f50d45f | 1412 | static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) |
497c9a19 | 1413 | { |
ed972ccf | 1414 | int idx, node = cpu_to_node(0); |
2d57e37d | 1415 | struct io_apic_irq_attr attr; |
ed972ccf | 1416 | unsigned int pin, irq; |
1da177e4 | 1417 | |
6f50d45f YL |
1418 | for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) { |
1419 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
1420 | if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) | |
b9c61b70 | 1421 | continue; |
33a201fa | 1422 | |
6f50d45f | 1423 | irq = pin_2_irq(idx, ioapic_idx, pin); |
33a201fa | 1424 | |
6f50d45f | 1425 | if ((ioapic_idx > 0) && (irq > 16)) |
fad53995 EB |
1426 | continue; |
1427 | ||
b9c61b70 YL |
1428 | /* |
1429 | * Skip the timer IRQ if there's a quirk handler | |
1430 | * installed and if it returns 1: | |
1431 | */ | |
1432 | if (apic->multi_timer_check && | |
6f50d45f | 1433 | apic->multi_timer_check(ioapic_idx, irq)) |
b9c61b70 | 1434 | continue; |
36062448 | 1435 | |
6f50d45f | 1436 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
2d57e37d | 1437 | irq_polarity(idx)); |
fbc6bff0 | 1438 | |
2d57e37d | 1439 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1440 | } |
1da177e4 LT |
1441 | } |
1442 | ||
ed972ccf TG |
1443 | static void __init setup_IO_APIC_irqs(void) |
1444 | { | |
6f50d45f | 1445 | unsigned int ioapic_idx; |
ed972ccf TG |
1446 | |
1447 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1448 | ||
6f50d45f YL |
1449 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1450 | __io_apic_setup_irqs(ioapic_idx); | |
ed972ccf TG |
1451 | } |
1452 | ||
18dce6ba YL |
1453 | /* |
1454 | * for the gsit that is not in first ioapic | |
1455 | * but could not use acpi_register_gsi() | |
1456 | * like some special sci in IBM x3330 | |
1457 | */ | |
1458 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1459 | { | |
6f50d45f | 1460 | int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1461 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1462 | |
1463 | /* | |
1464 | * Convert 'gsi' to 'ioapic.pin'. | |
1465 | */ | |
6f50d45f YL |
1466 | ioapic_idx = mp_find_ioapic(gsi); |
1467 | if (ioapic_idx < 0) | |
18dce6ba YL |
1468 | return; |
1469 | ||
6f50d45f YL |
1470 | pin = mp_find_ioapic_pin(ioapic_idx, gsi); |
1471 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
18dce6ba YL |
1472 | if (idx == -1) |
1473 | return; | |
1474 | ||
6f50d45f | 1475 | irq = pin_2_irq(idx, ioapic_idx, pin); |
fe6dab4e YL |
1476 | |
1477 | /* Only handle the non legacy irqs on secondary ioapics */ | |
6f50d45f | 1478 | if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY) |
18dce6ba | 1479 | return; |
fe6dab4e | 1480 | |
6f50d45f | 1481 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
da1ad9d7 TG |
1482 | irq_polarity(idx)); |
1483 | ||
710dcda6 | 1484 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1485 | } |
1486 | ||
1da177e4 | 1487 | /* |
f7633ce5 | 1488 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1489 | */ |
6f50d45f | 1490 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1491 | unsigned int pin, int vector) |
1da177e4 LT |
1492 | { |
1493 | struct IO_APIC_route_entry entry; | |
ff164324 | 1494 | unsigned int dest; |
1da177e4 | 1495 | |
95a02e97 | 1496 | if (irq_remapping_enabled) |
54168ed7 | 1497 | return; |
54168ed7 | 1498 | |
36062448 | 1499 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1500 | |
1501 | /* | |
1502 | * We use logical delivery to get the timer IRQ | |
1503 | * to the first CPU. | |
1504 | */ | |
a5a39156 AG |
1505 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1506 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1507 | dest = BAD_APICID; |
1508 | ||
9b5bc8dc | 1509 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1510 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1511 | entry.dest = dest; |
9b5bc8dc | 1512 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1513 | entry.polarity = 0; |
1514 | entry.trigger = 0; | |
1515 | entry.vector = vector; | |
1516 | ||
1517 | /* | |
1518 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1519 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1520 | */ |
2c778651 TG |
1521 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1522 | "edge"); | |
1da177e4 LT |
1523 | |
1524 | /* | |
1525 | * Add it to the IO-APIC irq-routing table: | |
1526 | */ | |
6f50d45f | 1527 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1528 | } |
1529 | ||
6f50d45f | 1530 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
1da177e4 | 1531 | { |
cda417dd | 1532 | int i; |
1da177e4 LT |
1533 | union IO_APIC_reg_00 reg_00; |
1534 | union IO_APIC_reg_01 reg_01; | |
1535 | union IO_APIC_reg_02 reg_02; | |
1536 | union IO_APIC_reg_03 reg_03; | |
1537 | unsigned long flags; | |
1da177e4 | 1538 | |
dade7716 | 1539 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1540 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1541 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1542 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1543 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1544 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1545 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1546 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1547 | |
6f50d45f | 1548 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1549 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1550 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1551 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1552 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1553 | |
54168ed7 | 1554 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1555 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1556 | reg_01.bits.entries); | |
1da177e4 LT |
1557 | |
1558 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1559 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1560 | reg_01.bits.version); | |
1da177e4 LT |
1561 | |
1562 | /* | |
1563 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1564 | * but the value of reg_02 is read as the previous read register | |
1565 | * value, so ignore it if reg_02 == reg_01. | |
1566 | */ | |
1567 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1568 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1569 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1570 | } |
1571 | ||
1572 | /* | |
1573 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1574 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1575 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1576 | */ | |
1577 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1578 | reg_03.raw != reg_01.raw) { | |
1579 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1580 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1581 | } |
1582 | ||
1583 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1584 | ||
95a02e97 | 1585 | if (irq_remapping_enabled) { |
42f0efc5 NC |
1586 | printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR" |
1587 | " Pol Stat Indx2 Zero Vect:\n"); | |
1588 | } else { | |
1589 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" | |
1590 | " Stat Dmod Deli Vect:\n"); | |
1591 | } | |
1da177e4 LT |
1592 | |
1593 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
95a02e97 | 1594 | if (irq_remapping_enabled) { |
42f0efc5 NC |
1595 | struct IO_APIC_route_entry entry; |
1596 | struct IR_IO_APIC_route_entry *ir_entry; | |
1597 | ||
6f50d45f | 1598 | entry = ioapic_read_entry(ioapic_idx, i); |
42f0efc5 NC |
1599 | ir_entry = (struct IR_IO_APIC_route_entry *) &entry; |
1600 | printk(KERN_DEBUG " %02x %04X ", | |
1601 | i, | |
1602 | ir_entry->index | |
1603 | ); | |
c767a54b | 1604 | pr_cont("%1d %1d %1d %1d %1d " |
42f0efc5 NC |
1605 | "%1d %1d %X %02X\n", |
1606 | ir_entry->format, | |
1607 | ir_entry->mask, | |
1608 | ir_entry->trigger, | |
1609 | ir_entry->irr, | |
1610 | ir_entry->polarity, | |
1611 | ir_entry->delivery_status, | |
1612 | ir_entry->index2, | |
1613 | ir_entry->zero, | |
1614 | ir_entry->vector | |
1615 | ); | |
1616 | } else { | |
1617 | struct IO_APIC_route_entry entry; | |
1618 | ||
6f50d45f | 1619 | entry = ioapic_read_entry(ioapic_idx, i); |
42f0efc5 NC |
1620 | printk(KERN_DEBUG " %02x %02X ", |
1621 | i, | |
1622 | entry.dest | |
1623 | ); | |
c767a54b | 1624 | pr_cont("%1d %1d %1d %1d %1d " |
42f0efc5 NC |
1625 | "%1d %1d %02X\n", |
1626 | entry.mask, | |
1627 | entry.trigger, | |
1628 | entry.irr, | |
1629 | entry.polarity, | |
1630 | entry.delivery_status, | |
1631 | entry.dest_mode, | |
1632 | entry.delivery_mode, | |
1633 | entry.vector | |
1634 | ); | |
1635 | } | |
1da177e4 | 1636 | } |
cda417dd YL |
1637 | } |
1638 | ||
1639 | __apicdebuginit(void) print_IO_APICs(void) | |
1640 | { | |
6f50d45f | 1641 | int ioapic_idx; |
cda417dd YL |
1642 | struct irq_cfg *cfg; |
1643 | unsigned int irq; | |
6fd36ba0 | 1644 | struct irq_chip *chip; |
cda417dd YL |
1645 | |
1646 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
6f50d45f | 1647 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
cda417dd | 1648 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1649 | mpc_ioapic_id(ioapic_idx), |
1650 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1651 | |
1652 | /* | |
1653 | * We are a bit conservative about what we expect. We have to | |
1654 | * know about every hardware change ASAP. | |
1655 | */ | |
1656 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1657 | ||
6f50d45f YL |
1658 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1659 | print_IO_APIC(ioapic_idx); | |
42f0efc5 | 1660 | |
1da177e4 | 1661 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1662 | for_each_active_irq(irq) { |
0b8f1efa YL |
1663 | struct irq_pin_list *entry; |
1664 | ||
6fd36ba0 MN |
1665 | chip = irq_get_chip(irq); |
1666 | if (chip != &ioapic_chip) | |
1667 | continue; | |
1668 | ||
2c778651 | 1669 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1670 | if (!cfg) |
1671 | continue; | |
0b8f1efa | 1672 | entry = cfg->irq_2_pin; |
0f978f45 | 1673 | if (!entry) |
1da177e4 | 1674 | continue; |
8f09cd20 | 1675 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1676 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1677 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1678 | pr_cont("\n"); | |
1da177e4 LT |
1679 | } |
1680 | ||
1681 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1682 | } |
1683 | ||
251e1e44 | 1684 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1685 | { |
251e1e44 | 1686 | int i; |
1da177e4 | 1687 | |
251e1e44 IM |
1688 | printk(KERN_DEBUG); |
1689 | ||
1690 | for (i = 0; i < 8; i++) | |
c767a54b | 1691 | pr_cont("%08x", apic_read(base + i*0x10)); |
251e1e44 | 1692 | |
c767a54b | 1693 | pr_cont("\n"); |
1da177e4 LT |
1694 | } |
1695 | ||
32f71aff | 1696 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1697 | { |
97a52714 | 1698 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1699 | u64 icr; |
1da177e4 | 1700 | |
251e1e44 | 1701 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1702 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1703 | v = apic_read(APIC_ID); |
54168ed7 | 1704 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1705 | v = apic_read(APIC_LVR); |
1706 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1707 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1708 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1709 | |
1710 | v = apic_read(APIC_TASKPRI); | |
1711 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1712 | ||
54168ed7 | 1713 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1714 | if (!APIC_XAPIC(ver)) { |
1715 | v = apic_read(APIC_ARBPRI); | |
1716 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1717 | v & APIC_ARBPRI_MASK); | |
1718 | } | |
1da177e4 LT |
1719 | v = apic_read(APIC_PROCPRI); |
1720 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1721 | } | |
1722 | ||
a11b5abe YL |
1723 | /* |
1724 | * Remote read supported only in the 82489DX and local APIC for | |
1725 | * Pentium processors. | |
1726 | */ | |
1727 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1728 | v = apic_read(APIC_RRR); | |
1729 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1730 | } | |
1731 | ||
1da177e4 LT |
1732 | v = apic_read(APIC_LDR); |
1733 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1734 | if (!x2apic_enabled()) { |
1735 | v = apic_read(APIC_DFR); | |
1736 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1737 | } | |
1da177e4 LT |
1738 | v = apic_read(APIC_SPIV); |
1739 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1740 | ||
1741 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1742 | print_APIC_field(APIC_ISR); |
1da177e4 | 1743 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1744 | print_APIC_field(APIC_TMR); |
1da177e4 | 1745 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1746 | print_APIC_field(APIC_IRR); |
1da177e4 | 1747 | |
54168ed7 IM |
1748 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1749 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1750 | apic_write(APIC_ESR, 0); |
54168ed7 | 1751 | |
1da177e4 LT |
1752 | v = apic_read(APIC_ESR); |
1753 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1754 | } | |
1755 | ||
7ab6af7a | 1756 | icr = apic_icr_read(); |
0c425cec IM |
1757 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1758 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1759 | |
1760 | v = apic_read(APIC_LVTT); | |
1761 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1762 | ||
1763 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1764 | v = apic_read(APIC_LVTPC); | |
1765 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1766 | } | |
1767 | v = apic_read(APIC_LVT0); | |
1768 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1769 | v = apic_read(APIC_LVT1); | |
1770 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1771 | ||
1772 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1773 | v = apic_read(APIC_LVTERR); | |
1774 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1775 | } | |
1776 | ||
1777 | v = apic_read(APIC_TMICT); | |
1778 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1779 | v = apic_read(APIC_TMCCT); | |
1780 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1781 | v = apic_read(APIC_TDCR); | |
1782 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1783 | |
1784 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1785 | v = apic_read(APIC_EFEAT); | |
1786 | maxlvt = (v >> 16) & 0xff; | |
1787 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1788 | v = apic_read(APIC_ECTRL); | |
1789 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1790 | for (i = 0; i < maxlvt; i++) { | |
1791 | v = apic_read(APIC_EILVTn(i)); | |
1792 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1793 | } | |
1794 | } | |
c767a54b | 1795 | pr_cont("\n"); |
1da177e4 LT |
1796 | } |
1797 | ||
2626eb2b | 1798 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1799 | { |
ffd5aae7 YL |
1800 | int cpu; |
1801 | ||
2626eb2b CG |
1802 | if (!maxcpu) |
1803 | return; | |
1804 | ||
ffd5aae7 | 1805 | preempt_disable(); |
2626eb2b CG |
1806 | for_each_online_cpu(cpu) { |
1807 | if (cpu >= maxcpu) | |
1808 | break; | |
ffd5aae7 | 1809 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1810 | } |
ffd5aae7 | 1811 | preempt_enable(); |
1da177e4 LT |
1812 | } |
1813 | ||
32f71aff | 1814 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1815 | { |
1da177e4 LT |
1816 | unsigned int v; |
1817 | unsigned long flags; | |
1818 | ||
b81bb373 | 1819 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1820 | return; |
1821 | ||
1822 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1823 | ||
5619c280 | 1824 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1825 | |
1826 | v = inb(0xa1) << 8 | inb(0x21); | |
1827 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1828 | ||
1829 | v = inb(0xa0) << 8 | inb(0x20); | |
1830 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1831 | ||
54168ed7 IM |
1832 | outb(0x0b,0xa0); |
1833 | outb(0x0b,0x20); | |
1da177e4 | 1834 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1835 | outb(0x0a,0xa0); |
1836 | outb(0x0a,0x20); | |
1da177e4 | 1837 | |
5619c280 | 1838 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1839 | |
1840 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1841 | ||
1842 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1843 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1844 | } | |
1845 | ||
2626eb2b CG |
1846 | static int __initdata show_lapic = 1; |
1847 | static __init int setup_show_lapic(char *arg) | |
1848 | { | |
1849 | int num = -1; | |
1850 | ||
1851 | if (strcmp(arg, "all") == 0) { | |
1852 | show_lapic = CONFIG_NR_CPUS; | |
1853 | } else { | |
1854 | get_option(&arg, &num); | |
1855 | if (num >= 0) | |
1856 | show_lapic = num; | |
1857 | } | |
1858 | ||
1859 | return 1; | |
1860 | } | |
1861 | __setup("show_lapic=", setup_show_lapic); | |
1862 | ||
1863 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1864 | { |
2626eb2b CG |
1865 | if (apic_verbosity == APIC_QUIET) |
1866 | return 0; | |
1867 | ||
32f71aff | 1868 | print_PIC(); |
4797f6b0 YL |
1869 | |
1870 | /* don't print out if apic is not there */ | |
8312136f | 1871 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1872 | return 0; |
1873 | ||
2626eb2b | 1874 | print_local_APICs(show_lapic); |
cda417dd | 1875 | print_IO_APICs(); |
32f71aff MR |
1876 | |
1877 | return 0; | |
1878 | } | |
1879 | ||
ded1f6ab | 1880 | late_initcall(print_ICs); |
32f71aff | 1881 | |
1da177e4 | 1882 | |
efa2559f YL |
1883 | /* Where if anywhere is the i8259 connect in external int mode */ |
1884 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1885 | ||
54168ed7 | 1886 | void __init enable_IO_APIC(void) |
1da177e4 | 1887 | { |
fcfd636a | 1888 | int i8259_apic, i8259_pin; |
54168ed7 | 1889 | int apic; |
bc07844a | 1890 | |
b81bb373 | 1891 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1892 | return; |
1893 | ||
54168ed7 | 1894 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1895 | int pin; |
1896 | /* See if any of the pins is in ExtINT mode */ | |
b69c6c3b | 1897 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
fcfd636a | 1898 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1899 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1900 | |
fcfd636a EB |
1901 | /* If the interrupt line is enabled and in ExtInt mode |
1902 | * I have found the pin where the i8259 is connected. | |
1903 | */ | |
1904 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1905 | ioapic_i8259.apic = apic; | |
1906 | ioapic_i8259.pin = pin; | |
1907 | goto found_i8259; | |
1908 | } | |
1909 | } | |
1910 | } | |
1911 | found_i8259: | |
1912 | /* Look to see what if the MP table has reported the ExtINT */ | |
1913 | /* If we could not find the appropriate pin by looking at the ioapic | |
1914 | * the i8259 probably is not connected the ioapic but give the | |
1915 | * mptable a chance anyway. | |
1916 | */ | |
1917 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1918 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1919 | /* Trust the MP table if nothing is setup in the hardware */ | |
1920 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1921 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1922 | ioapic_i8259.pin = i8259_pin; | |
1923 | ioapic_i8259.apic = i8259_apic; | |
1924 | } | |
1925 | /* Complain if the MP table and the hardware disagree */ | |
1926 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1927 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1928 | { | |
1929 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1930 | } |
1931 | ||
1932 | /* | |
1933 | * Do not trust the IO-APIC being empty at bootup | |
1934 | */ | |
1935 | clear_IO_APIC(); | |
1936 | } | |
1937 | ||
1938 | /* | |
1939 | * Not an __init, needed by the reboot code | |
1940 | */ | |
1941 | void disable_IO_APIC(void) | |
1942 | { | |
1943 | /* | |
1944 | * Clear the IO-APIC before rebooting: | |
1945 | */ | |
1946 | clear_IO_APIC(); | |
1947 | ||
b81bb373 | 1948 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1949 | return; |
1950 | ||
650927ef | 1951 | /* |
0b968d23 | 1952 | * If the i8259 is routed through an IOAPIC |
650927ef | 1953 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1954 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1955 | * |
1956 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1957 | * as virtual wire B is little complex (need to configure both | |
0d2eb44f | 1958 | * IOAPIC RTE as well as interrupt-remapping table entry). |
7c6d9f97 | 1959 | * As this gets called during crash dump, keep this simple for now. |
650927ef | 1960 | */ |
95a02e97 | 1961 | if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) { |
650927ef | 1962 | struct IO_APIC_route_entry entry; |
650927ef EB |
1963 | |
1964 | memset(&entry, 0, sizeof(entry)); | |
1965 | entry.mask = 0; /* Enabled */ | |
1966 | entry.trigger = 0; /* Edge */ | |
1967 | entry.irr = 0; | |
1968 | entry.polarity = 0; /* High */ | |
1969 | entry.delivery_status = 0; | |
1970 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1971 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1972 | entry.vector = 0; |
54168ed7 | 1973 | entry.dest = read_apic_id(); |
650927ef EB |
1974 | |
1975 | /* | |
1976 | * Add it to the IO-APIC irq-routing table: | |
1977 | */ | |
cf4c6a2f | 1978 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1979 | } |
54168ed7 | 1980 | |
7c6d9f97 SS |
1981 | /* |
1982 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1983 | */ | |
8312136f | 1984 | if (cpu_has_apic || apic_from_smp_config()) |
95a02e97 | 1985 | disconnect_bsp_APIC(!irq_remapping_enabled && |
3f4c3955 | 1986 | ioapic_i8259.pin != -1); |
1da177e4 LT |
1987 | } |
1988 | ||
54168ed7 | 1989 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1990 | /* |
1991 | * function to set the IO-APIC physical IDs based on the | |
1992 | * values stored in the MPC table. | |
1993 | * | |
1994 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1995 | */ | |
a38c5380 | 1996 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1997 | { |
1998 | union IO_APIC_reg_00 reg_00; | |
1999 | physid_mask_t phys_id_present_map; | |
6f50d45f | 2000 | int ioapic_idx; |
1da177e4 LT |
2001 | int i; |
2002 | unsigned char old_id; | |
2003 | unsigned long flags; | |
2004 | ||
2005 | /* | |
2006 | * This is broken; anything with a real cpu count has to | |
2007 | * circumvent this idiocy regardless. | |
2008 | */ | |
7abc0753 | 2009 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2010 | |
2011 | /* | |
2012 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2013 | */ | |
6f50d45f | 2014 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { |
1da177e4 | 2015 | /* Read the register 0 value */ |
dade7716 | 2016 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2017 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2018 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2019 | |
6f50d45f | 2020 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 2021 | |
6f50d45f | 2022 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 2023 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 2024 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2025 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2026 | reg_00.bits.ID); | |
6f50d45f | 2027 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
2028 | } |
2029 | ||
1da177e4 LT |
2030 | /* |
2031 | * Sanity check, is the ID really free? Every APIC in a | |
2032 | * system must have a unique ID or we get lots of nice | |
2033 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2034 | */ | |
7abc0753 | 2035 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 2036 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 2037 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 2038 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2039 | for (i = 0; i < get_physical_broadcast(); i++) |
2040 | if (!physid_isset(i, phys_id_present_map)) | |
2041 | break; | |
2042 | if (i >= get_physical_broadcast()) | |
2043 | panic("Max APIC ID exceeded!\n"); | |
2044 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2045 | i); | |
2046 | physid_set(i, phys_id_present_map); | |
6f50d45f | 2047 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
2048 | } else { |
2049 | physid_mask_t tmp; | |
6f50d45f | 2050 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 2051 | &tmp); |
1da177e4 LT |
2052 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2053 | "phys_id_present_map\n", | |
6f50d45f | 2054 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2055 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2056 | } | |
2057 | ||
1da177e4 LT |
2058 | /* |
2059 | * We need to adjust the IRQ routing table | |
2060 | * if the ID changed. | |
2061 | */ | |
6f50d45f | 2062 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 2063 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2064 | if (mp_irqs[i].dstapic == old_id) |
2065 | mp_irqs[i].dstapic | |
6f50d45f | 2066 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
2067 | |
2068 | /* | |
60d79fd9 YL |
2069 | * Update the ID register according to the right value |
2070 | * from the MPC table if they are different. | |
36062448 | 2071 | */ |
6f50d45f | 2072 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
2073 | continue; |
2074 | ||
1da177e4 LT |
2075 | apic_printk(APIC_VERBOSE, KERN_INFO |
2076 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 2077 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 2078 | |
6f50d45f | 2079 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 2080 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2081 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 2082 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2083 | |
2084 | /* | |
2085 | * Sanity check | |
2086 | */ | |
dade7716 | 2087 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2088 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2089 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 2090 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 2091 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
2092 | else |
2093 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2094 | } | |
2095 | } | |
a38c5380 SAS |
2096 | |
2097 | void __init setup_ioapic_ids_from_mpc(void) | |
2098 | { | |
2099 | ||
2100 | if (acpi_ioapic) | |
2101 | return; | |
2102 | /* | |
2103 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2104 | * no meaning without the serial APIC bus. | |
2105 | */ | |
2106 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2107 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2108 | return; | |
2109 | setup_ioapic_ids_from_mpc_nocheck(); | |
2110 | } | |
54168ed7 | 2111 | #endif |
1da177e4 | 2112 | |
7ce0bcfd | 2113 | int no_timer_check __initdata; |
8542b200 ZA |
2114 | |
2115 | static int __init notimercheck(char *s) | |
2116 | { | |
2117 | no_timer_check = 1; | |
2118 | return 1; | |
2119 | } | |
2120 | __setup("no_timer_check", notimercheck); | |
2121 | ||
1da177e4 LT |
2122 | /* |
2123 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2124 | * about the timer IRQ. We do the following to work around the situation: | |
2125 | * | |
2126 | * - timer IRQ defaults to IO-APIC IRQ | |
2127 | * - if this function detects that timer IRQs are defunct, then we fall | |
2128 | * back to ISA timer IRQs | |
2129 | */ | |
f0a7a5c9 | 2130 | static int __init timer_irq_works(void) |
1da177e4 LT |
2131 | { |
2132 | unsigned long t1 = jiffies; | |
4aae0702 | 2133 | unsigned long flags; |
1da177e4 | 2134 | |
8542b200 ZA |
2135 | if (no_timer_check) |
2136 | return 1; | |
2137 | ||
4aae0702 | 2138 | local_save_flags(flags); |
1da177e4 LT |
2139 | local_irq_enable(); |
2140 | /* Let ten ticks pass... */ | |
2141 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2142 | local_irq_restore(flags); |
1da177e4 LT |
2143 | |
2144 | /* | |
2145 | * Expect a few ticks at least, to be sure some possible | |
2146 | * glue logic does not lock up after one or two first | |
2147 | * ticks in a non-ExtINT mode. Also the local APIC | |
2148 | * might have cached one ExtINT interrupt. Finally, at | |
2149 | * least one tick may be lost due to delays. | |
2150 | */ | |
54168ed7 IM |
2151 | |
2152 | /* jiffies wrap? */ | |
1d16b53e | 2153 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2154 | return 1; |
1da177e4 LT |
2155 | return 0; |
2156 | } | |
2157 | ||
2158 | /* | |
2159 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2160 | * number of pending IRQ events unhandled. These cases are very rare, | |
2161 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2162 | * better to do it this way as thus we do not have to be aware of | |
2163 | * 'pending' interrupts in the IRQ path, except at this point. | |
2164 | */ | |
2165 | /* | |
2166 | * Edge triggered needs to resend any interrupt | |
2167 | * that was delayed but this is now handled in the device | |
2168 | * independent code. | |
2169 | */ | |
2170 | ||
2171 | /* | |
2172 | * Starting up a edge-triggered IO-APIC interrupt is | |
2173 | * nasty - we need to make sure that we get the edge. | |
2174 | * If it is already asserted for some reason, we need | |
2175 | * return 1 to indicate that is was pending. | |
2176 | * | |
2177 | * This is not complete - we should be able to fake | |
2178 | * an edge even if it isn't on the 8259A... | |
2179 | */ | |
54168ed7 | 2180 | |
61a38ce3 | 2181 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2182 | { |
61a38ce3 | 2183 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2184 | unsigned long flags; |
2185 | ||
dade7716 | 2186 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2187 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2188 | legacy_pic->mask(irq); |
b81bb373 | 2189 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2190 | was_pending = 1; |
2191 | } | |
61a38ce3 | 2192 | __unmask_ioapic(data->chip_data); |
dade7716 | 2193 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2194 | |
2195 | return was_pending; | |
2196 | } | |
2197 | ||
90297c5f | 2198 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2199 | { |
90297c5f | 2200 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 | 2201 | unsigned long flags; |
8d966a04 | 2202 | int cpu; |
54168ed7 | 2203 | |
dade7716 | 2204 | raw_spin_lock_irqsave(&vector_lock, flags); |
8d966a04 FY |
2205 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); |
2206 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); | |
dade7716 | 2207 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2208 | |
2209 | return 1; | |
2210 | } | |
497c9a19 | 2211 | |
54168ed7 IM |
2212 | /* |
2213 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2214 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2215 | * handled with the level-triggered descriptor, but that one has slightly | |
2216 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2217 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2218 | * races. | |
2219 | */ | |
497c9a19 | 2220 | |
54168ed7 | 2221 | #ifdef CONFIG_SMP |
9338ad6f | 2222 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2223 | { |
2224 | cpumask_var_t cleanup_mask; | |
2225 | ||
2226 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2227 | unsigned int i; | |
e85abf8f GH |
2228 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2229 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2230 | } else { | |
2231 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2232 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2233 | free_cpumask_var(cleanup_mask); | |
2234 | } | |
2235 | cfg->move_in_progress = 0; | |
2236 | } | |
2237 | ||
54168ed7 IM |
2238 | asmlinkage void smp_irq_move_cleanup_interrupt(void) |
2239 | { | |
2240 | unsigned vector, me; | |
8f2466f4 | 2241 | |
54168ed7 | 2242 | ack_APIC_irq(); |
54168ed7 | 2243 | irq_enter(); |
98ad1cc1 | 2244 | exit_idle(); |
54168ed7 IM |
2245 | |
2246 | me = smp_processor_id(); | |
2247 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2248 | unsigned int irq; | |
68a8ca59 | 2249 | unsigned int irr; |
54168ed7 IM |
2250 | struct irq_desc *desc; |
2251 | struct irq_cfg *cfg; | |
0a3aee0d | 2252 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2253 | |
0b8f1efa YL |
2254 | if (irq == -1) |
2255 | continue; | |
2256 | ||
54168ed7 IM |
2257 | desc = irq_to_desc(irq); |
2258 | if (!desc) | |
2259 | continue; | |
2260 | ||
2261 | cfg = irq_cfg(irq); | |
94777fc5 DS |
2262 | if (!cfg) |
2263 | continue; | |
2264 | ||
239007b8 | 2265 | raw_spin_lock(&desc->lock); |
54168ed7 | 2266 | |
7f41c2e1 SS |
2267 | /* |
2268 | * Check if the irq migration is in progress. If so, we | |
2269 | * haven't received the cleanup request yet for this irq. | |
2270 | */ | |
2271 | if (cfg->move_in_progress) | |
2272 | goto unlock; | |
2273 | ||
22f65d31 | 2274 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2275 | goto unlock; |
2276 | ||
68a8ca59 SS |
2277 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2278 | /* | |
2279 | * Check if the vector that needs to be cleanedup is | |
2280 | * registered at the cpu's IRR. If so, then this is not | |
2281 | * the best time to clean it up. Lets clean it up in the | |
2282 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2283 | * to myself. | |
2284 | */ | |
2285 | if (irr & (1 << (vector % 32))) { | |
2286 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2287 | goto unlock; | |
2288 | } | |
0a3aee0d | 2289 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2290 | unlock: |
239007b8 | 2291 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2292 | } |
2293 | ||
2294 | irq_exit(); | |
2295 | } | |
2296 | ||
dd5f15e5 | 2297 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2298 | { |
a5e74b84 | 2299 | unsigned me; |
54168ed7 | 2300 | |
fcef5911 | 2301 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2302 | return; |
2303 | ||
54168ed7 | 2304 | me = smp_processor_id(); |
10b888d6 | 2305 | |
fcef5911 | 2306 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2307 | send_cleanup_vector(cfg); |
497c9a19 | 2308 | } |
a5e74b84 | 2309 | |
dd5f15e5 | 2310 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2311 | { |
dd5f15e5 | 2312 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2313 | } |
2314 | ||
2315 | void irq_force_complete_move(int irq) | |
2316 | { | |
2c778651 | 2317 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2318 | |
bbd391a1 PB |
2319 | if (!cfg) |
2320 | return; | |
2321 | ||
dd5f15e5 | 2322 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2323 | } |
497c9a19 | 2324 | #else |
dd5f15e5 | 2325 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2326 | #endif |
3145e941 | 2327 | |
7eb9ae07 SS |
2328 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
2329 | { | |
2330 | int apic, pin; | |
2331 | struct irq_pin_list *entry; | |
2332 | u8 vector = cfg->vector; | |
2333 | ||
2334 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2335 | unsigned int reg; | |
2336 | ||
2337 | apic = entry->apic; | |
2338 | pin = entry->pin; | |
2339 | /* | |
2340 | * With interrupt-remapping, destination information comes | |
2341 | * from interrupt-remapping table entry. | |
2342 | */ | |
2343 | if (!irq_remapped(cfg)) | |
2344 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2345 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2346 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2347 | reg |= vector; | |
2348 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2349 | } | |
2350 | } | |
2351 | ||
2352 | /* | |
2353 | * Either sets data->affinity to a valid value, and returns | |
2354 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | |
2355 | * leaves data->affinity untouched. | |
2356 | */ | |
2357 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2358 | unsigned int *dest_id) | |
2359 | { | |
2360 | struct irq_cfg *cfg = data->chip_data; | |
2361 | unsigned int irq = data->irq; | |
2362 | int err; | |
2363 | ||
2364 | if (!config_enabled(CONFIG_SMP)) | |
2365 | return -1; | |
2366 | ||
2367 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2368 | return -EINVAL; | |
2369 | ||
2370 | err = assign_irq_vector(irq, cfg, mask); | |
2371 | if (err) | |
2372 | return err; | |
2373 | ||
2374 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | |
2375 | if (err) { | |
2376 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
2377 | pr_err("Failed to recover vector for irq %d\n", irq); | |
2378 | return err; | |
2379 | } | |
2380 | ||
2381 | cpumask_copy(data->affinity, mask); | |
2382 | ||
2383 | return 0; | |
2384 | } | |
2385 | ||
2386 | static int | |
2387 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2388 | bool force) | |
2389 | { | |
2390 | unsigned int dest, irq = data->irq; | |
2391 | unsigned long flags; | |
2392 | int ret; | |
2393 | ||
2394 | if (!config_enabled(CONFIG_SMP)) | |
2395 | return -1; | |
2396 | ||
2397 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2398 | ret = __ioapic_set_affinity(data, mask, &dest); | |
2399 | if (!ret) { | |
2400 | /* Only the high 8 bits are valid. */ | |
2401 | dest = SET_APIC_LOGICAL_ID(dest); | |
2402 | __target_IO_APIC_irq(irq, dest, data->chip_data); | |
2403 | ret = IRQ_SET_MASK_OK_NOCOPY; | |
2404 | } | |
2405 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2406 | return ret; | |
2407 | } | |
2408 | ||
90297c5f | 2409 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2410 | { |
90297c5f | 2411 | irq_complete_move(data->chip_data); |
08221110 | 2412 | irq_move_irq(data); |
1d025192 YL |
2413 | ack_APIC_irq(); |
2414 | } | |
2415 | ||
3eb2cce8 | 2416 | atomic_t irq_mis_count; |
3eb2cce8 | 2417 | |
047c8fdb | 2418 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
2419 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
2420 | { | |
2421 | struct irq_pin_list *entry; | |
2422 | unsigned long flags; | |
2423 | ||
2424 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2425 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2426 | unsigned int reg; | |
2427 | int pin; | |
2428 | ||
2429 | pin = entry->pin; | |
2430 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
2431 | /* Is the remote IRR bit set? */ | |
2432 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
2433 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2434 | return true; | |
2435 | } | |
2436 | } | |
2437 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2438 | ||
2439 | return false; | |
2440 | } | |
2441 | ||
4da7072a AG |
2442 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
2443 | { | |
54168ed7 | 2444 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2445 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 2446 | mask_ioapic(cfg); |
4da7072a | 2447 | return true; |
54168ed7 | 2448 | } |
4da7072a AG |
2449 | return false; |
2450 | } | |
2451 | ||
2452 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2453 | struct irq_cfg *cfg, bool masked) | |
2454 | { | |
2455 | if (unlikely(masked)) { | |
2456 | /* Only migrate the irq if the ack has been received. | |
2457 | * | |
2458 | * On rare occasions the broadcast level triggered ack gets | |
2459 | * delayed going to ioapics, and if we reprogram the | |
2460 | * vector while Remote IRR is still set the irq will never | |
2461 | * fire again. | |
2462 | * | |
2463 | * To prevent this scenario we read the Remote IRR bit | |
2464 | * of the ioapic. This has two effects. | |
2465 | * - On any sane system the read of the ioapic will | |
2466 | * flush writes (and acks) going to the ioapic from | |
2467 | * this cpu. | |
2468 | * - We get to see if the ACK has actually been delivered. | |
2469 | * | |
2470 | * Based on failed experiments of reprogramming the | |
2471 | * ioapic entry from outside of irq context starting | |
2472 | * with masking the ioapic entry and then polling until | |
2473 | * Remote IRR was clear before reprogramming the | |
2474 | * ioapic I don't trust the Remote IRR bit to be | |
2475 | * completey accurate. | |
2476 | * | |
2477 | * However there appears to be no other way to plug | |
2478 | * this race, so if the Remote IRR bit is not | |
2479 | * accurate and is causing problems then it is a hardware bug | |
2480 | * and you can go talk to the chipset vendor about it. | |
2481 | */ | |
2482 | if (!io_apic_level_ack_pending(cfg)) | |
2483 | irq_move_masked_irq(data); | |
2484 | unmask_ioapic(cfg); | |
2485 | } | |
2486 | } | |
2487 | #else | |
2488 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
2489 | { | |
2490 | return false; | |
2491 | } | |
2492 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2493 | struct irq_cfg *cfg, bool masked) | |
2494 | { | |
2495 | } | |
047c8fdb YL |
2496 | #endif |
2497 | ||
4da7072a AG |
2498 | static void ack_apic_level(struct irq_data *data) |
2499 | { | |
2500 | struct irq_cfg *cfg = data->chip_data; | |
2501 | int i, irq = data->irq; | |
2502 | unsigned long v; | |
2503 | bool masked; | |
2504 | ||
2505 | irq_complete_move(cfg); | |
2506 | masked = ioapic_irqd_mask(data, cfg); | |
2507 | ||
3eb2cce8 | 2508 | /* |
916a0fe7 JF |
2509 | * It appears there is an erratum which affects at least version 0x11 |
2510 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2511 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2512 | * erroneously delivered as edge-triggered one but the respective IRR | |
2513 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2514 | * message but it will never arrive and further interrupts are blocked | |
2515 | * from the source. The exact reason is so far unknown, but the | |
2516 | * phenomenon was observed when two consecutive interrupt requests | |
2517 | * from a given source get delivered to the same CPU and the source is | |
2518 | * temporarily disabled in between. | |
2519 | * | |
2520 | * A workaround is to simulate an EOI message manually. We achieve it | |
2521 | * by setting the trigger mode to edge and then to level when the edge | |
2522 | * trigger mode gets detected in the TMR of a local APIC for a | |
2523 | * level-triggered interrupt. We mask the source for the time of the | |
2524 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2525 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2526 | * |
2527 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2528 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2529 | * destination that is handling the corresponding interrupt. This | |
2530 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2531 | * level-triggered io-apic interrupt will be seen as an edge | |
2532 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2533 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2534 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2535 | * supporting EOI register, we do an explicit EOI to clear the | |
2536 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2537 | * we use the above logic (mask+edge followed by unmask+level) from | |
2538 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2539 | */ |
3145e941 | 2540 | i = cfg->vector; |
3eb2cce8 | 2541 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2542 | |
54168ed7 IM |
2543 | /* |
2544 | * We must acknowledge the irq before we move it or the acknowledge will | |
2545 | * not propagate properly. | |
2546 | */ | |
2547 | ack_APIC_irq(); | |
2548 | ||
1c83995b SS |
2549 | /* |
2550 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2551 | * message via io-apic EOI register write or simulating it using | |
2552 | * mask+edge followed by unnask+level logic) manually when the | |
2553 | * level triggered interrupt is seen as the edge triggered interrupt | |
2554 | * at the cpu. | |
2555 | */ | |
ca64c47c MR |
2556 | if (!(v & (1 << (i & 0x1f)))) { |
2557 | atomic_inc(&irq_mis_count); | |
2558 | ||
dd5f15e5 | 2559 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2560 | } |
2561 | ||
4da7072a | 2562 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2563 | } |
1d025192 | 2564 | |
d3f13810 | 2565 | #ifdef CONFIG_IRQ_REMAP |
90297c5f | 2566 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2567 | { |
5d0ae2db | 2568 | ack_APIC_irq(); |
d0b03bd1 HW |
2569 | } |
2570 | ||
90297c5f | 2571 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2572 | { |
5d0ae2db | 2573 | ack_APIC_irq(); |
90297c5f | 2574 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 | 2575 | } |
c39d77ff SS |
2576 | |
2577 | static void ir_print_prefix(struct irq_data *data, struct seq_file *p) | |
2578 | { | |
2579 | seq_printf(p, " IR-%s", data->chip->name); | |
2580 | } | |
2581 | ||
2582 | static void irq_remap_modify_chip_defaults(struct irq_chip *chip) | |
2583 | { | |
2584 | chip->irq_print_chip = ir_print_prefix; | |
2585 | chip->irq_ack = ir_ack_apic_edge; | |
2586 | chip->irq_eoi = ir_ack_apic_level; | |
2587 | ||
95a02e97 | 2588 | chip->irq_set_affinity = set_remapped_irq_affinity; |
c39d77ff | 2589 | } |
d3f13810 | 2590 | #endif /* CONFIG_IRQ_REMAP */ |
d0b03bd1 | 2591 | |
f5b9ed7a | 2592 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2593 | .name = "IO-APIC", |
2594 | .irq_startup = startup_ioapic_irq, | |
2595 | .irq_mask = mask_ioapic_irq, | |
2596 | .irq_unmask = unmask_ioapic_irq, | |
2597 | .irq_ack = ack_apic_edge, | |
2598 | .irq_eoi = ack_apic_level, | |
f7e909ea | 2599 | .irq_set_affinity = ioapic_set_affinity, |
f7e909ea | 2600 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2601 | }; |
2602 | ||
1da177e4 LT |
2603 | static inline void init_IO_APIC_traps(void) |
2604 | { | |
da51a821 | 2605 | struct irq_cfg *cfg; |
ad9f4334 | 2606 | unsigned int irq; |
1da177e4 LT |
2607 | |
2608 | /* | |
2609 | * NOTE! The local APIC isn't very good at handling | |
2610 | * multiple interrupts at the same interrupt level. | |
2611 | * As the interrupt level is determined by taking the | |
2612 | * vector number and shifting that right by 4, we | |
2613 | * want to spread these out a bit so that they don't | |
2614 | * all fall in the same interrupt level. | |
2615 | * | |
2616 | * Also, we've got to be careful not to trash gate | |
2617 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2618 | */ | |
ad9f4334 | 2619 | for_each_active_irq(irq) { |
2c778651 | 2620 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2621 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2622 | /* |
2623 | * Hmm.. We don't have an entry for this, | |
2624 | * so default to an old-fashioned 8259 | |
2625 | * interrupt if we can.. | |
2626 | */ | |
b81bb373 JP |
2627 | if (irq < legacy_pic->nr_legacy_irqs) |
2628 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2629 | else |
1da177e4 | 2630 | /* Strange. Oh, well.. */ |
2c778651 | 2631 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2632 | } |
2633 | } | |
2634 | } | |
2635 | ||
f5b9ed7a IM |
2636 | /* |
2637 | * The local APIC irq-chip implementation: | |
2638 | */ | |
1da177e4 | 2639 | |
90297c5f | 2640 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2641 | { |
2642 | unsigned long v; | |
2643 | ||
2644 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2645 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2646 | } |
2647 | ||
90297c5f | 2648 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2649 | { |
f5b9ed7a | 2650 | unsigned long v; |
1da177e4 | 2651 | |
f5b9ed7a | 2652 | v = apic_read(APIC_LVT0); |
593f4a78 | 2653 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2654 | } |
1da177e4 | 2655 | |
90297c5f | 2656 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2657 | { |
2658 | ack_APIC_irq(); | |
2659 | } | |
2660 | ||
f5b9ed7a | 2661 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2662 | .name = "local-APIC", |
90297c5f TG |
2663 | .irq_mask = mask_lapic_irq, |
2664 | .irq_unmask = unmask_lapic_irq, | |
2665 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2666 | }; |
2667 | ||
60c69948 | 2668 | static void lapic_register_intr(int irq) |
c88ac1df | 2669 | { |
60c69948 | 2670 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2671 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2672 | "edge"); |
c88ac1df MR |
2673 | } |
2674 | ||
1da177e4 LT |
2675 | /* |
2676 | * This looks a bit hackish but it's about the only one way of sending | |
2677 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2678 | * not support the ExtINT mode, unfortunately. We need to send these | |
2679 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2680 | * 8259A interrupt line asserted until INTA. --macro | |
2681 | */ | |
28acf285 | 2682 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2683 | { |
fcfd636a | 2684 | int apic, pin, i; |
1da177e4 LT |
2685 | struct IO_APIC_route_entry entry0, entry1; |
2686 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2687 | |
fcfd636a | 2688 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2689 | if (pin == -1) { |
2690 | WARN_ON_ONCE(1); | |
2691 | return; | |
2692 | } | |
fcfd636a | 2693 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2694 | if (apic == -1) { |
2695 | WARN_ON_ONCE(1); | |
1da177e4 | 2696 | return; |
956fb531 | 2697 | } |
1da177e4 | 2698 | |
cf4c6a2f | 2699 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2700 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2701 | |
2702 | memset(&entry1, 0, sizeof(entry1)); | |
2703 | ||
2704 | entry1.dest_mode = 0; /* physical delivery */ | |
2705 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2706 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2707 | entry1.delivery_mode = dest_ExtINT; |
2708 | entry1.polarity = entry0.polarity; | |
2709 | entry1.trigger = 0; | |
2710 | entry1.vector = 0; | |
2711 | ||
cf4c6a2f | 2712 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2713 | |
2714 | save_control = CMOS_READ(RTC_CONTROL); | |
2715 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2716 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2717 | RTC_FREQ_SELECT); | |
2718 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2719 | ||
2720 | i = 100; | |
2721 | while (i-- > 0) { | |
2722 | mdelay(10); | |
2723 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2724 | i -= 10; | |
2725 | } | |
2726 | ||
2727 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2728 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2729 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2730 | |
cf4c6a2f | 2731 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2732 | } |
2733 | ||
efa2559f | 2734 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2735 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2736 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2737 | { |
2738 | disable_timer_pin_1 = 1; | |
2739 | return 0; | |
2740 | } | |
54168ed7 | 2741 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2742 | |
2743 | int timer_through_8259 __initdata; | |
2744 | ||
1da177e4 LT |
2745 | /* |
2746 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2747 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2748 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2749 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2750 | * |
2751 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2752 | */ |
8542b200 | 2753 | static inline void __init check_timer(void) |
1da177e4 | 2754 | { |
2c778651 | 2755 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2756 | int node = cpu_to_node(0); |
fcfd636a | 2757 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2758 | unsigned long flags; |
047c8fdb | 2759 | int no_pin1 = 0; |
4aae0702 IM |
2760 | |
2761 | local_irq_save(flags); | |
d4d25dec | 2762 | |
1da177e4 LT |
2763 | /* |
2764 | * get/set the timer IRQ vector: | |
2765 | */ | |
4305df94 | 2766 | legacy_pic->mask(0); |
fe402e1f | 2767 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2768 | |
2769 | /* | |
d11d5794 MR |
2770 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2771 | * wire has to be disabled in the local APIC. Also | |
2772 | * timer interrupts need to be acknowledged manually in | |
2773 | * the 8259A for the i82489DX when using the NMI | |
2774 | * watchdog as that APIC treats NMIs as level-triggered. | |
2775 | * The AEOI mode will finish them in the 8259A | |
2776 | * automatically. | |
1da177e4 | 2777 | */ |
593f4a78 | 2778 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2779 | legacy_pic->init(1); |
1da177e4 | 2780 | |
fcfd636a EB |
2781 | pin1 = find_isa_irq_pin(0, mp_INT); |
2782 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2783 | pin2 = ioapic_i8259.pin; | |
2784 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2785 | |
49a66a0b MR |
2786 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2787 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2788 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2789 | |
691874fa MR |
2790 | /* |
2791 | * Some BIOS writers are clueless and report the ExtINTA | |
2792 | * I/O APIC input from the cascaded 8259A as the timer | |
2793 | * interrupt input. So just in case, if only one pin | |
2794 | * was found above, try it both directly and through the | |
2795 | * 8259A. | |
2796 | */ | |
2797 | if (pin1 == -1) { | |
95a02e97 | 2798 | if (irq_remapping_enabled) |
54168ed7 | 2799 | panic("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2800 | pin1 = pin2; |
2801 | apic1 = apic2; | |
2802 | no_pin1 = 1; | |
2803 | } else if (pin2 == -1) { | |
2804 | pin2 = pin1; | |
2805 | apic2 = apic1; | |
2806 | } | |
2807 | ||
1da177e4 LT |
2808 | if (pin1 != -1) { |
2809 | /* | |
2810 | * Ok, does IRQ0 through the IOAPIC work? | |
2811 | */ | |
691874fa | 2812 | if (no_pin1) { |
85ac16d0 | 2813 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2814 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2815 | } else { |
60c69948 | 2816 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2817 | * leave it unmasked. |
2818 | * so only need to unmask if it is level-trigger | |
2819 | * do we really have level trigger timer? | |
2820 | */ | |
2821 | int idx; | |
2822 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2823 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2824 | unmask_ioapic(cfg); |
691874fa | 2825 | } |
1da177e4 | 2826 | if (timer_irq_works()) { |
66759a01 CE |
2827 | if (disable_timer_pin_1 > 0) |
2828 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2829 | goto out; |
1da177e4 | 2830 | } |
95a02e97 | 2831 | if (irq_remapping_enabled) |
54168ed7 | 2832 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2833 | local_irq_disable(); |
fcfd636a | 2834 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2835 | if (!no_pin1) |
49a66a0b MR |
2836 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2837 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2838 | |
49a66a0b MR |
2839 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2840 | "(IRQ0) through the 8259A ...\n"); | |
2841 | apic_printk(APIC_QUIET, KERN_INFO | |
2842 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2843 | /* |
2844 | * legacy devices should be connected to IO APIC #0 | |
2845 | */ | |
85ac16d0 | 2846 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2847 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2848 | legacy_pic->unmask(0); |
1da177e4 | 2849 | if (timer_irq_works()) { |
49a66a0b | 2850 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2851 | timer_through_8259 = 1; |
4aae0702 | 2852 | goto out; |
1da177e4 LT |
2853 | } |
2854 | /* | |
2855 | * Cleanup, just in case ... | |
2856 | */ | |
f72dccac | 2857 | local_irq_disable(); |
4305df94 | 2858 | legacy_pic->mask(0); |
fcfd636a | 2859 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2860 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2861 | } |
1da177e4 | 2862 | |
49a66a0b MR |
2863 | apic_printk(APIC_QUIET, KERN_INFO |
2864 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2865 | |
60c69948 | 2866 | lapic_register_intr(0); |
497c9a19 | 2867 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2868 | legacy_pic->unmask(0); |
1da177e4 LT |
2869 | |
2870 | if (timer_irq_works()) { | |
49a66a0b | 2871 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2872 | goto out; |
1da177e4 | 2873 | } |
f72dccac | 2874 | local_irq_disable(); |
4305df94 | 2875 | legacy_pic->mask(0); |
497c9a19 | 2876 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2877 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2878 | |
49a66a0b MR |
2879 | apic_printk(APIC_QUIET, KERN_INFO |
2880 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2881 | |
b81bb373 JP |
2882 | legacy_pic->init(0); |
2883 | legacy_pic->make_irq(0); | |
593f4a78 | 2884 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2885 | |
2886 | unlock_ExtINT_logic(); | |
2887 | ||
2888 | if (timer_irq_works()) { | |
49a66a0b | 2889 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2890 | goto out; |
1da177e4 | 2891 | } |
f72dccac | 2892 | local_irq_disable(); |
49a66a0b | 2893 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
fb209bd8 YL |
2894 | if (x2apic_preenabled) |
2895 | apic_printk(APIC_QUIET, KERN_INFO | |
2896 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2897 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2898 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2899 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2900 | out: |
2901 | local_irq_restore(flags); | |
1da177e4 LT |
2902 | } |
2903 | ||
2904 | /* | |
af174783 MR |
2905 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2906 | * to devices. However there may be an I/O APIC pin available for | |
2907 | * this interrupt regardless. The pin may be left unconnected, but | |
2908 | * typically it will be reused as an ExtINT cascade interrupt for | |
2909 | * the master 8259A. In the MPS case such a pin will normally be | |
2910 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2911 | * there is no provision for ExtINT interrupts, and in the absence | |
2912 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2913 | * interrupt, that is edge-triggered and unmasked by default. We | |
2914 | * used to do this, but it caused problems on some systems because | |
2915 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2916 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2917 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2918 | * the I/O APIC in all cases now. No actual device should request | |
2919 | * it anyway. --macro | |
1da177e4 | 2920 | */ |
bc07844a | 2921 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2922 | |
2923 | void __init setup_IO_APIC(void) | |
2924 | { | |
54168ed7 | 2925 | |
54168ed7 IM |
2926 | /* |
2927 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2928 | */ | |
b81bb373 | 2929 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2930 | |
54168ed7 | 2931 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2932 | /* |
54168ed7 IM |
2933 | * Set up IO-APIC IRQ routing. |
2934 | */ | |
de934103 TG |
2935 | x86_init.mpparse.setup_ioapic_ids(); |
2936 | ||
1da177e4 LT |
2937 | sync_Arb_IDs(); |
2938 | setup_IO_APIC_irqs(); | |
2939 | init_IO_APIC_traps(); | |
b81bb373 | 2940 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2941 | check_timer(); |
1da177e4 LT |
2942 | } |
2943 | ||
2944 | /* | |
0d2eb44f | 2945 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2946 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2947 | */ |
36062448 | 2948 | |
1da177e4 LT |
2949 | static int __init io_apic_bug_finalize(void) |
2950 | { | |
d6c88a50 TG |
2951 | if (sis_apic_bug == -1) |
2952 | sis_apic_bug = 0; | |
2953 | return 0; | |
1da177e4 LT |
2954 | } |
2955 | ||
2956 | late_initcall(io_apic_bug_finalize); | |
2957 | ||
6f50d45f | 2958 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2959 | { |
1da177e4 LT |
2960 | unsigned long flags; |
2961 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2962 | |
dade7716 | 2963 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2964 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2965 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2966 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2967 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2968 | } |
dade7716 | 2969 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2970 | } |
1da177e4 | 2971 | |
f3c6ea1b RW |
2972 | static void ioapic_resume(void) |
2973 | { | |
6f50d45f | 2974 | int ioapic_idx; |
f3c6ea1b | 2975 | |
6f50d45f YL |
2976 | for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--) |
2977 | resume_ioapic_id(ioapic_idx); | |
15bac20b SS |
2978 | |
2979 | restore_ioapic_entries(); | |
1da177e4 LT |
2980 | } |
2981 | ||
f3c6ea1b | 2982 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2983 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2984 | .resume = ioapic_resume, |
2985 | }; | |
2986 | ||
f3c6ea1b | 2987 | static int __init ioapic_init_ops(void) |
1da177e4 | 2988 | { |
f3c6ea1b RW |
2989 | register_syscore_ops(&ioapic_syscore_ops); |
2990 | ||
1da177e4 LT |
2991 | return 0; |
2992 | } | |
2993 | ||
f3c6ea1b | 2994 | device_initcall(ioapic_init_ops); |
1da177e4 | 2995 | |
3fc471ed | 2996 | /* |
95d77884 | 2997 | * Dynamic irq allocate and deallocation |
3fc471ed | 2998 | */ |
fbc6bff0 | 2999 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 3000 | { |
fbc6bff0 | 3001 | struct irq_cfg *cfg; |
3fc471ed | 3002 | unsigned long flags; |
fbc6bff0 TG |
3003 | unsigned int ret = 0; |
3004 | int irq; | |
d047f53a | 3005 | |
fbc6bff0 TG |
3006 | if (from < nr_irqs_gsi) |
3007 | from = nr_irqs_gsi; | |
d047f53a | 3008 | |
fbc6bff0 TG |
3009 | irq = alloc_irq_from(from, node); |
3010 | if (irq < 0) | |
3011 | return 0; | |
3012 | cfg = alloc_irq_cfg(irq, node); | |
3013 | if (!cfg) { | |
3014 | free_irq_at(irq, NULL); | |
3015 | return 0; | |
ace80ab7 | 3016 | } |
3fc471ed | 3017 | |
fbc6bff0 TG |
3018 | raw_spin_lock_irqsave(&vector_lock, flags); |
3019 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
3020 | ret = irq; | |
3021 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3022 | |
fbc6bff0 | 3023 | if (ret) { |
2c778651 | 3024 | irq_set_chip_data(irq, cfg); |
fbc6bff0 TG |
3025 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
3026 | } else { | |
3027 | free_irq_at(irq, cfg); | |
3028 | } | |
3029 | return ret; | |
3fc471ed EB |
3030 | } |
3031 | ||
199751d7 YL |
3032 | int create_irq(void) |
3033 | { | |
f6e9456c | 3034 | int node = cpu_to_node(0); |
be5d5350 | 3035 | unsigned int irq_want; |
54168ed7 IM |
3036 | int irq; |
3037 | ||
be5d5350 | 3038 | irq_want = nr_irqs_gsi; |
d047f53a | 3039 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3040 | |
3041 | if (irq == 0) | |
3042 | irq = -1; | |
3043 | ||
3044 | return irq; | |
199751d7 YL |
3045 | } |
3046 | ||
3fc471ed EB |
3047 | void destroy_irq(unsigned int irq) |
3048 | { | |
2c778651 | 3049 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 3050 | unsigned long flags; |
3fc471ed | 3051 | |
fbc6bff0 | 3052 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3053 | |
7b79462a | 3054 | if (irq_remapped(cfg)) |
95a02e97 | 3055 | free_remapped_irq(irq); |
dade7716 | 3056 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3057 | __clear_irq_vector(irq, cfg); |
dade7716 | 3058 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3059 | free_irq_at(irq, cfg); |
3fc471ed | 3060 | } |
3fc471ed | 3061 | |
2d3fcc1c | 3062 | /* |
27b46d76 | 3063 | * MSI message composition |
2d3fcc1c EB |
3064 | */ |
3065 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3066 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3067 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3068 | { |
497c9a19 YL |
3069 | struct irq_cfg *cfg; |
3070 | int err; | |
2d3fcc1c EB |
3071 | unsigned dest; |
3072 | ||
f1182638 JB |
3073 | if (disable_apic) |
3074 | return -ENXIO; | |
3075 | ||
3145e941 | 3076 | cfg = irq_cfg(irq); |
fe402e1f | 3077 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3078 | if (err) |
3079 | return err; | |
2d3fcc1c | 3080 | |
ff164324 AG |
3081 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3082 | apic->target_cpus(), &dest); | |
3083 | if (err) | |
3084 | return err; | |
497c9a19 | 3085 | |
1a0e62a4 | 3086 | if (irq_remapped(cfg)) { |
95a02e97 | 3087 | compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id); |
5e2b930b JR |
3088 | return err; |
3089 | } | |
54168ed7 | 3090 | |
5e2b930b JR |
3091 | if (x2apic_enabled()) |
3092 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3093 | MSI_ADDR_EXT_DEST_ID(dest); | |
3094 | else | |
3095 | msg->address_hi = MSI_ADDR_BASE_HI; | |
f007e99c | 3096 | |
5e2b930b JR |
3097 | msg->address_lo = |
3098 | MSI_ADDR_BASE_LO | | |
3099 | ((apic->irq_dest_mode == 0) ? | |
3100 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3101 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3102 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3103 | MSI_ADDR_REDIRECTION_CPU: | |
3104 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3105 | MSI_ADDR_DEST_ID(dest); | |
3106 | ||
3107 | msg->data = | |
3108 | MSI_DATA_TRIGGER_EDGE | | |
3109 | MSI_DATA_LEVEL_ASSERT | | |
3110 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3111 | MSI_DATA_DELIVERY_FIXED: | |
3112 | MSI_DATA_DELIVERY_LOWPRI) | | |
3113 | MSI_DATA_VECTOR(cfg->vector); | |
54168ed7 | 3114 | |
497c9a19 | 3115 | return err; |
2d3fcc1c EB |
3116 | } |
3117 | ||
5346b2a7 TG |
3118 | static int |
3119 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3120 | { |
5346b2a7 | 3121 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3122 | struct msi_msg msg; |
3123 | unsigned int dest; | |
3b7d1921 | 3124 | |
5346b2a7 | 3125 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3126 | return -1; |
2d3fcc1c | 3127 | |
5346b2a7 | 3128 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3129 | |
3130 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3131 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3132 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3133 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3134 | ||
5346b2a7 | 3135 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 | 3136 | |
f841d792 | 3137 | return IRQ_SET_MASK_OK_NOCOPY; |
2d3fcc1c EB |
3138 | } |
3139 | ||
3b7d1921 EB |
3140 | /* |
3141 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3142 | * which implement the MSI or MSI-X Capability Structure. | |
3143 | */ | |
3144 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3145 | .name = "PCI-MSI", |
3146 | .irq_unmask = unmask_msi_irq, | |
3147 | .irq_mask = mask_msi_irq, | |
3148 | .irq_ack = ack_apic_edge, | |
5346b2a7 | 3149 | .irq_set_affinity = msi_set_affinity, |
5346b2a7 | 3150 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3151 | }; |
3152 | ||
3145e941 | 3153 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3154 | { |
c60eaf25 | 3155 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3156 | struct msi_msg msg; |
60c69948 | 3157 | int ret; |
1d025192 | 3158 | |
c8bc6f3c | 3159 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3160 | if (ret < 0) |
3161 | return ret; | |
3162 | ||
2c778651 | 3163 | irq_set_msi_desc(irq, msidesc); |
1d025192 YL |
3164 | write_msi_msg(irq, &msg); |
3165 | ||
2c778651 | 3166 | if (irq_remapped(irq_get_chip_data(irq))) { |
60c69948 | 3167 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c39d77ff | 3168 | irq_remap_modify_chip_defaults(chip); |
c60eaf25 TG |
3169 | } |
3170 | ||
3171 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3172 | |
c81bba49 YL |
3173 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3174 | ||
1d025192 YL |
3175 | return 0; |
3176 | } | |
3177 | ||
294ee6f8 | 3178 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3179 | { |
60c69948 TG |
3180 | int node, ret, sub_handle, index = 0; |
3181 | unsigned int irq, irq_want; | |
0b8f1efa | 3182 | struct msi_desc *msidesc; |
54168ed7 | 3183 | |
1c8d7b0a MW |
3184 | /* x86 doesn't support multiple MSI yet */ |
3185 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3186 | return 1; | |
3187 | ||
d047f53a | 3188 | node = dev_to_node(&dev->dev); |
be5d5350 | 3189 | irq_want = nr_irqs_gsi; |
54168ed7 | 3190 | sub_handle = 0; |
0b8f1efa | 3191 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3192 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3193 | if (irq == 0) |
3194 | return -1; | |
f1ee5548 | 3195 | irq_want = irq + 1; |
95a02e97 | 3196 | if (!irq_remapping_enabled) |
54168ed7 IM |
3197 | goto no_ir; |
3198 | ||
3199 | if (!sub_handle) { | |
3200 | /* | |
3201 | * allocate the consecutive block of IRTE's | |
3202 | * for 'nvec' | |
3203 | */ | |
95a02e97 | 3204 | index = msi_alloc_remapped_irq(dev, irq, nvec); |
54168ed7 IM |
3205 | if (index < 0) { |
3206 | ret = index; | |
3207 | goto error; | |
3208 | } | |
3209 | } else { | |
95a02e97 SS |
3210 | ret = msi_setup_remapped_irq(dev, irq, index, |
3211 | sub_handle); | |
5e2b930b | 3212 | if (ret < 0) |
54168ed7 | 3213 | goto error; |
54168ed7 IM |
3214 | } |
3215 | no_ir: | |
0b8f1efa | 3216 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3217 | if (ret < 0) |
3218 | goto error; | |
3219 | sub_handle++; | |
3220 | } | |
3221 | return 0; | |
047c8fdb YL |
3222 | |
3223 | error: | |
54168ed7 IM |
3224 | destroy_irq(irq); |
3225 | return ret; | |
047c8fdb YL |
3226 | } |
3227 | ||
294ee6f8 | 3228 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3229 | { |
f7feaca7 | 3230 | destroy_irq(irq); |
3b7d1921 EB |
3231 | } |
3232 | ||
d3f13810 | 3233 | #ifdef CONFIG_DMAR_TABLE |
fe52b2d2 TG |
3234 | static int |
3235 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3236 | bool force) | |
54168ed7 | 3237 | { |
fe52b2d2 TG |
3238 | struct irq_cfg *cfg = data->chip_data; |
3239 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3240 | struct msi_msg msg; |
54168ed7 | 3241 | |
fe52b2d2 | 3242 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3243 | return -1; |
54168ed7 | 3244 | |
54168ed7 IM |
3245 | dmar_msi_read(irq, &msg); |
3246 | ||
3247 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3248 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3249 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3250 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3251 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3252 | |
3253 | dmar_msi_write(irq, &msg); | |
d5dedd45 | 3254 | |
f841d792 | 3255 | return IRQ_SET_MASK_OK_NOCOPY; |
54168ed7 | 3256 | } |
3145e941 | 3257 | |
8f7007aa | 3258 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3259 | .name = "DMAR_MSI", |
3260 | .irq_unmask = dmar_msi_unmask, | |
3261 | .irq_mask = dmar_msi_mask, | |
3262 | .irq_ack = ack_apic_edge, | |
fe52b2d2 | 3263 | .irq_set_affinity = dmar_msi_set_affinity, |
fe52b2d2 | 3264 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3265 | }; |
3266 | ||
3267 | int arch_setup_dmar_msi(unsigned int irq) | |
3268 | { | |
3269 | int ret; | |
3270 | struct msi_msg msg; | |
2d3fcc1c | 3271 | |
c8bc6f3c | 3272 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3273 | if (ret < 0) |
3274 | return ret; | |
3275 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3276 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3277 | "edge"); | |
54168ed7 IM |
3278 | return 0; |
3279 | } | |
3280 | #endif | |
3281 | ||
58ac1e76 | 3282 | #ifdef CONFIG_HPET_TIMER |
3283 | ||
d0fbca8f TG |
3284 | static int hpet_msi_set_affinity(struct irq_data *data, |
3285 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3286 | { |
d0fbca8f | 3287 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3288 | struct msi_msg msg; |
3289 | unsigned int dest; | |
58ac1e76 | 3290 | |
0e09ddf2 | 3291 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3292 | return -1; |
58ac1e76 | 3293 | |
d0fbca8f | 3294 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3295 | |
3296 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3297 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3298 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3299 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3300 | ||
d0fbca8f | 3301 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 | 3302 | |
f841d792 | 3303 | return IRQ_SET_MASK_OK_NOCOPY; |
58ac1e76 | 3304 | } |
3145e941 | 3305 | |
1cc18521 | 3306 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3307 | .name = "HPET_MSI", |
d0fbca8f TG |
3308 | .irq_unmask = hpet_msi_unmask, |
3309 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3310 | .irq_ack = ack_apic_edge, |
d0fbca8f | 3311 | .irq_set_affinity = hpet_msi_set_affinity, |
90297c5f | 3312 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3313 | }; |
3314 | ||
c8bc6f3c | 3315 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3316 | { |
c60eaf25 | 3317 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3318 | struct msi_msg msg; |
d0fbca8f | 3319 | int ret; |
58ac1e76 | 3320 | |
95a02e97 SS |
3321 | if (irq_remapping_enabled) { |
3322 | if (!setup_hpet_msi_remapped(irq, id)) | |
c8bc6f3c SS |
3323 | return -1; |
3324 | } | |
3325 | ||
3326 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3327 | if (ret < 0) |
3328 | return ret; | |
3329 | ||
2c778651 | 3330 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3331 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2c778651 | 3332 | if (irq_remapped(irq_get_chip_data(irq))) |
c39d77ff | 3333 | irq_remap_modify_chip_defaults(chip); |
c81bba49 | 3334 | |
c60eaf25 | 3335 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3336 | return 0; |
3337 | } | |
3338 | #endif | |
3339 | ||
54168ed7 | 3340 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3341 | /* |
3342 | * Hypertransport interrupt support | |
3343 | */ | |
3344 | #ifdef CONFIG_HT_IRQ | |
3345 | ||
497c9a19 | 3346 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3347 | { |
ec68307c EB |
3348 | struct ht_irq_msg msg; |
3349 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3350 | |
497c9a19 | 3351 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3352 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3353 | |
497c9a19 | 3354 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3355 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3356 | |
ec68307c | 3357 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3358 | } |
3359 | ||
be5b7bf7 TG |
3360 | static int |
3361 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3362 | { |
be5b7bf7 | 3363 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3364 | unsigned int dest; |
8b955b0d | 3365 | |
be5b7bf7 | 3366 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3367 | return -1; |
8b955b0d | 3368 | |
be5b7bf7 | 3369 | target_ht_irq(data->irq, dest, cfg->vector); |
f841d792 | 3370 | return IRQ_SET_MASK_OK_NOCOPY; |
8b955b0d | 3371 | } |
3145e941 | 3372 | |
c37e108d | 3373 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3374 | .name = "PCI-HT", |
3375 | .irq_mask = mask_ht_irq, | |
3376 | .irq_unmask = unmask_ht_irq, | |
3377 | .irq_ack = ack_apic_edge, | |
be5b7bf7 | 3378 | .irq_set_affinity = ht_set_affinity, |
be5b7bf7 | 3379 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3380 | }; |
3381 | ||
3382 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3383 | { | |
497c9a19 | 3384 | struct irq_cfg *cfg; |
ff164324 AG |
3385 | struct ht_irq_msg msg; |
3386 | unsigned dest; | |
497c9a19 | 3387 | int err; |
8b955b0d | 3388 | |
f1182638 JB |
3389 | if (disable_apic) |
3390 | return -ENXIO; | |
3391 | ||
3145e941 | 3392 | cfg = irq_cfg(irq); |
fe402e1f | 3393 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
ff164324 AG |
3394 | if (err) |
3395 | return err; | |
8b955b0d | 3396 | |
ff164324 AG |
3397 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3398 | apic->target_cpus(), &dest); | |
3399 | if (err) | |
3400 | return err; | |
8b955b0d | 3401 | |
ff164324 | 3402 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3403 | |
ff164324 AG |
3404 | msg.address_lo = |
3405 | HT_IRQ_LOW_BASE | | |
3406 | HT_IRQ_LOW_DEST_ID(dest) | | |
3407 | HT_IRQ_LOW_VECTOR(cfg->vector) | | |
3408 | ((apic->irq_dest_mode == 0) ? | |
3409 | HT_IRQ_LOW_DM_PHYSICAL : | |
3410 | HT_IRQ_LOW_DM_LOGICAL) | | |
3411 | HT_IRQ_LOW_RQEOI_EDGE | | |
3412 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3413 | HT_IRQ_LOW_MT_FIXED : | |
3414 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3415 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 3416 | |
ff164324 | 3417 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3418 | |
ff164324 AG |
3419 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
3420 | handle_edge_irq, "edge"); | |
8b955b0d | 3421 | |
ff164324 | 3422 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
c81bba49 | 3423 | |
ff164324 | 3424 | return 0; |
8b955b0d EB |
3425 | } |
3426 | #endif /* CONFIG_HT_IRQ */ | |
3427 | ||
20443598 | 3428 | static int |
ff973d04 TG |
3429 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3430 | { | |
3431 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3432 | int ret; | |
3433 | ||
3434 | if (!cfg) | |
3435 | return -EINVAL; | |
3436 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3437 | if (!ret) | |
e4aff811 | 3438 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
3439 | return ret; |
3440 | } | |
3441 | ||
20443598 SAS |
3442 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3443 | struct io_apic_irq_attr *attr) | |
710dcda6 | 3444 | { |
6f50d45f | 3445 | unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; |
710dcda6 TG |
3446 | int ret; |
3447 | ||
3448 | /* Avoid redundant programming */ | |
6f50d45f | 3449 | if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { |
710dcda6 | 3450 | pr_debug("Pin %d-%d already programmed\n", |
6f50d45f | 3451 | mpc_ioapic_id(ioapic_idx), pin); |
710dcda6 TG |
3452 | return 0; |
3453 | } | |
3454 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3455 | if (!ret) | |
6f50d45f | 3456 | set_bit(pin, ioapics[ioapic_idx].pin_programmed); |
710dcda6 TG |
3457 | return ret; |
3458 | } | |
3459 | ||
41098ffe | 3460 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3461 | { |
3462 | union IO_APIC_reg_01 reg_01; | |
3463 | unsigned long flags; | |
3464 | ||
dade7716 | 3465 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3466 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3467 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3468 | |
4b6b19a1 EB |
3469 | /* The register returns the maximum index redir index |
3470 | * supported, which is one less than the total number of redir | |
3471 | * entries. | |
3472 | */ | |
3473 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3474 | } |
3475 | ||
23f9b267 | 3476 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3477 | { |
4afc51a8 | 3478 | int nr; |
be5d5350 | 3479 | |
a4384df3 | 3480 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3481 | if (nr > nr_irqs_gsi) |
be5d5350 | 3482 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3483 | |
3484 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3485 | } |
3486 | ||
7b586d71 JF |
3487 | int get_nr_irqs_gsi(void) |
3488 | { | |
3489 | return nr_irqs_gsi; | |
3490 | } | |
3491 | ||
4a046d17 YL |
3492 | int __init arch_probe_nr_irqs(void) |
3493 | { | |
3494 | int nr; | |
3495 | ||
f1ee5548 YL |
3496 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3497 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3498 | |
f1ee5548 YL |
3499 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3500 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3501 | /* | |
3502 | * for MSI and HT dyn irq | |
3503 | */ | |
3504 | nr += nr_irqs_gsi * 16; | |
3505 | #endif | |
3506 | if (nr < nr_irqs) | |
4a046d17 YL |
3507 | nr_irqs = nr; |
3508 | ||
b683de2b | 3509 | return NR_IRQS_LEGACY; |
4a046d17 | 3510 | } |
4a046d17 | 3511 | |
710dcda6 TG |
3512 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3513 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3514 | { |
5ef21837 YL |
3515 | int node; |
3516 | ||
3517 | if (!IO_APIC_IRQ(irq)) { | |
3518 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3519 | irq_attr->ioapic); |
5ef21837 YL |
3520 | return -EINVAL; |
3521 | } | |
3522 | ||
e0799c04 | 3523 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3524 | |
710dcda6 | 3525 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3526 | } |
3527 | ||
54168ed7 | 3528 | #ifdef CONFIG_X86_32 |
41098ffe | 3529 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3530 | { |
3531 | union IO_APIC_reg_00 reg_00; | |
3532 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3533 | physid_mask_t tmp; | |
3534 | unsigned long flags; | |
3535 | int i = 0; | |
3536 | ||
3537 | /* | |
36062448 PC |
3538 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3539 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3540 | * supports up to 16 on one shared APIC bus. |
36062448 | 3541 | * |
1da177e4 LT |
3542 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3543 | * advantage of new APIC bus architecture. | |
3544 | */ | |
3545 | ||
3546 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3547 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3548 | |
dade7716 | 3549 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3550 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3551 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3552 | |
3553 | if (apic_id >= get_physical_broadcast()) { | |
3554 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3555 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3556 | apic_id = reg_00.bits.ID; | |
3557 | } | |
3558 | ||
3559 | /* | |
36062448 | 3560 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3561 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3562 | */ | |
7abc0753 | 3563 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3564 | |
3565 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3566 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3567 | break; |
3568 | } | |
3569 | ||
3570 | if (i == get_physical_broadcast()) | |
3571 | panic("Max apic_id exceeded!\n"); | |
3572 | ||
3573 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3574 | "trying %d\n", ioapic, apic_id, i); | |
3575 | ||
3576 | apic_id = i; | |
36062448 | 3577 | } |
1da177e4 | 3578 | |
7abc0753 | 3579 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3580 | physids_or(apic_id_map, apic_id_map, tmp); |
3581 | ||
3582 | if (reg_00.bits.ID != apic_id) { | |
3583 | reg_00.bits.ID = apic_id; | |
3584 | ||
dade7716 | 3585 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3586 | io_apic_write(ioapic, 0, reg_00.raw); |
3587 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3588 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3589 | |
3590 | /* Sanity check */ | |
6070f9ec | 3591 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
3592 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
3593 | ioapic); | |
6070f9ec AD |
3594 | return -1; |
3595 | } | |
1da177e4 LT |
3596 | } |
3597 | ||
3598 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3599 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3600 | ||
3601 | return apic_id; | |
3602 | } | |
41098ffe TG |
3603 | |
3604 | static u8 __init io_apic_unique_id(u8 id) | |
3605 | { | |
3606 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3607 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3608 | return io_apic_get_unique_id(nr_ioapics, id); | |
3609 | else | |
3610 | return id; | |
3611 | } | |
3612 | #else | |
3613 | static u8 __init io_apic_unique_id(u8 id) | |
3614 | { | |
3615 | int i; | |
3616 | DECLARE_BITMAP(used, 256); | |
3617 | ||
3618 | bitmap_zero(used, 256); | |
3619 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 3620 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3621 | } |
3622 | if (!test_bit(id, used)) | |
3623 | return id; | |
3624 | return find_first_zero_bit(used, 256); | |
3625 | } | |
58f892e0 | 3626 | #endif |
1da177e4 | 3627 | |
41098ffe | 3628 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3629 | { |
3630 | union IO_APIC_reg_01 reg_01; | |
3631 | unsigned long flags; | |
3632 | ||
dade7716 | 3633 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3634 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3635 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3636 | |
3637 | return reg_01.bits.version; | |
3638 | } | |
3639 | ||
9a0a91bb | 3640 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3641 | { |
9a0a91bb | 3642 | int ioapic, pin, idx; |
61fd47e0 SL |
3643 | |
3644 | if (skip_ioapic_setup) | |
3645 | return -1; | |
3646 | ||
9a0a91bb EB |
3647 | ioapic = mp_find_ioapic(gsi); |
3648 | if (ioapic < 0) | |
61fd47e0 SL |
3649 | return -1; |
3650 | ||
9a0a91bb EB |
3651 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3652 | if (pin < 0) | |
3653 | return -1; | |
3654 | ||
3655 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3656 | if (idx < 0) | |
61fd47e0 SL |
3657 | return -1; |
3658 | ||
9a0a91bb EB |
3659 | *trigger = irq_trigger(idx); |
3660 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3661 | return 0; |
3662 | } | |
3663 | ||
497c9a19 YL |
3664 | /* |
3665 | * This function currently is only a helper for the i386 smp boot process where | |
3666 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3667 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3668 | */ |
3669 | #ifdef CONFIG_SMP | |
3670 | void __init setup_ioapic_dest(void) | |
3671 | { | |
fad53995 | 3672 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3673 | const struct cpumask *mask; |
5451ddc5 | 3674 | struct irq_data *idata; |
497c9a19 YL |
3675 | |
3676 | if (skip_ioapic_setup == 1) | |
3677 | return; | |
3678 | ||
fad53995 | 3679 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b69c6c3b | 3680 | for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { |
b9c61b70 YL |
3681 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3682 | if (irq_entry == -1) | |
3683 | continue; | |
3684 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3685 | |
fad53995 EB |
3686 | if ((ioapic > 0) && (irq > 16)) |
3687 | continue; | |
3688 | ||
5451ddc5 | 3689 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3690 | |
b9c61b70 YL |
3691 | /* |
3692 | * Honour affinities which have been set in early boot | |
3693 | */ | |
5451ddc5 TG |
3694 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3695 | mask = idata->affinity; | |
b9c61b70 YL |
3696 | else |
3697 | mask = apic->target_cpus(); | |
497c9a19 | 3698 | |
95a02e97 SS |
3699 | if (irq_remapping_enabled) |
3700 | set_remapped_irq_affinity(idata, mask, false); | |
b9c61b70 | 3701 | else |
5451ddc5 | 3702 | ioapic_set_affinity(idata, mask, false); |
497c9a19 | 3703 | } |
b9c61b70 | 3704 | |
497c9a19 YL |
3705 | } |
3706 | #endif | |
3707 | ||
54168ed7 IM |
3708 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3709 | ||
3710 | static struct resource *ioapic_resources; | |
3711 | ||
ffc43836 | 3712 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3713 | { |
3714 | unsigned long n; | |
3715 | struct resource *res; | |
3716 | char *mem; | |
3717 | int i; | |
3718 | ||
3719 | if (nr_ioapics <= 0) | |
3720 | return NULL; | |
3721 | ||
3722 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3723 | n *= nr_ioapics; | |
3724 | ||
3725 | mem = alloc_bootmem(n); | |
3726 | res = (void *)mem; | |
3727 | ||
ffc43836 | 3728 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3729 | |
ffc43836 CG |
3730 | for (i = 0; i < nr_ioapics; i++) { |
3731 | res[i].name = mem; | |
3732 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3733 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3734 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3735 | } |
3736 | ||
3737 | ioapic_resources = res; | |
3738 | ||
3739 | return res; | |
3740 | } | |
54168ed7 | 3741 | |
4a8e2a31 | 3742 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
3743 | { |
3744 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3745 | struct resource *ioapic_res; |
d6c88a50 | 3746 | int i; |
f3294a33 | 3747 | |
ffc43836 | 3748 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3749 | for (i = 0; i < nr_ioapics; i++) { |
3750 | if (smp_found_config) { | |
d5371430 | 3751 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3752 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3753 | if (!ioapic_phys) { |
3754 | printk(KERN_ERR | |
3755 | "WARNING: bogus zero IO-APIC " | |
3756 | "address found in MPTABLE, " | |
3757 | "disabling IO/APIC support!\n"); | |
3758 | smp_found_config = 0; | |
3759 | skip_ioapic_setup = 1; | |
3760 | goto fake_ioapic_page; | |
3761 | } | |
54168ed7 | 3762 | #endif |
f3294a33 | 3763 | } else { |
54168ed7 | 3764 | #ifdef CONFIG_X86_32 |
f3294a33 | 3765 | fake_ioapic_page: |
54168ed7 | 3766 | #endif |
e79c65a9 | 3767 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3768 | ioapic_phys = __pa(ioapic_phys); |
3769 | } | |
3770 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3771 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3772 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3773 | ioapic_phys); | |
f3294a33 | 3774 | idx++; |
54168ed7 | 3775 | |
ffc43836 | 3776 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3777 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3778 | ioapic_res++; |
f3294a33 | 3779 | } |
23f9b267 TG |
3780 | |
3781 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3782 | } |
3783 | ||
857fdc53 | 3784 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3785 | { |
3786 | int i; | |
3787 | struct resource *r = ioapic_resources; | |
3788 | ||
3789 | if (!r) { | |
857fdc53 | 3790 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3791 | printk(KERN_ERR |
3792 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3793 | return; |
54168ed7 IM |
3794 | } |
3795 | ||
3796 | for (i = 0; i < nr_ioapics; i++) { | |
3797 | insert_resource(&iomem_resource, r); | |
3798 | r++; | |
3799 | } | |
54168ed7 | 3800 | } |
2a4ab640 | 3801 | |
eddb0c55 | 3802 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3803 | { |
3804 | int i = 0; | |
3805 | ||
678301ec PB |
3806 | if (nr_ioapics == 0) |
3807 | return -1; | |
3808 | ||
2a4ab640 FT |
3809 | /* Find the IOAPIC that manages this GSI. */ |
3810 | for (i = 0; i < nr_ioapics; i++) { | |
c040aaeb SS |
3811 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
3812 | if ((gsi >= gsi_cfg->gsi_base) | |
3813 | && (gsi <= gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3814 | return i; |
3815 | } | |
54168ed7 | 3816 | |
2a4ab640 FT |
3817 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3818 | return -1; | |
3819 | } | |
3820 | ||
eddb0c55 | 3821 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3822 | { |
c040aaeb SS |
3823 | struct mp_ioapic_gsi *gsi_cfg; |
3824 | ||
2a4ab640 FT |
3825 | if (WARN_ON(ioapic == -1)) |
3826 | return -1; | |
c040aaeb SS |
3827 | |
3828 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3829 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3830 | return -1; |
3831 | ||
c040aaeb | 3832 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3833 | } |
3834 | ||
41098ffe | 3835 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3836 | { |
3837 | if (nr_ioapics >= MAX_IO_APICS) { | |
73d63d03 SS |
3838 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
3839 | MAX_IO_APICS, nr_ioapics); | |
2a4ab640 FT |
3840 | return 1; |
3841 | } | |
3842 | if (!address) { | |
73d63d03 | 3843 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
2a4ab640 FT |
3844 | return 1; |
3845 | } | |
54168ed7 IM |
3846 | return 0; |
3847 | } | |
3848 | ||
73d63d03 SS |
3849 | static __init int bad_ioapic_register(int idx) |
3850 | { | |
3851 | union IO_APIC_reg_00 reg_00; | |
3852 | union IO_APIC_reg_01 reg_01; | |
3853 | union IO_APIC_reg_02 reg_02; | |
3854 | ||
3855 | reg_00.raw = io_apic_read(idx, 0); | |
3856 | reg_01.raw = io_apic_read(idx, 1); | |
3857 | reg_02.raw = io_apic_read(idx, 2); | |
3858 | ||
3859 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3860 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3861 | mpc_ioapic_addr(idx)); | |
3862 | return 1; | |
3863 | } | |
3864 | ||
3865 | return 0; | |
3866 | } | |
3867 | ||
2a4ab640 FT |
3868 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3869 | { | |
3870 | int idx = 0; | |
7716a5c4 | 3871 | int entries; |
c040aaeb | 3872 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
3873 | |
3874 | if (bad_ioapic(address)) | |
3875 | return; | |
3876 | ||
3877 | idx = nr_ioapics; | |
3878 | ||
d5371430 SS |
3879 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3880 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3881 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
3882 | |
3883 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
3884 | |
3885 | if (bad_ioapic_register(idx)) { | |
3886 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3887 | return; | |
3888 | } | |
3889 | ||
d5371430 SS |
3890 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
3891 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
3892 | |
3893 | /* | |
3894 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3895 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3896 | */ | |
7716a5c4 | 3897 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
3898 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3899 | gsi_cfg->gsi_base = gsi_base; | |
3900 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
3901 | |
3902 | /* | |
3903 | * The number of IO-APIC IRQ registers (== #pins): | |
3904 | */ | |
b69c6c3b | 3905 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3906 | |
c040aaeb SS |
3907 | if (gsi_cfg->gsi_end >= gsi_top) |
3908 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 | 3909 | |
73d63d03 SS |
3910 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
3911 | idx, mpc_ioapic_id(idx), | |
3912 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
3913 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 FT |
3914 | |
3915 | nr_ioapics++; | |
3916 | } | |
05ddafb1 JP |
3917 | |
3918 | /* Enable IOAPIC early just for system timer */ | |
3919 | void __init pre_init_apic_IRQ0(void) | |
3920 | { | |
f880ec78 | 3921 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
3922 | |
3923 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
3924 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
3925 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
3926 | &phys_cpu_present_map); | |
05ddafb1 | 3927 | #endif |
05ddafb1 JP |
3928 | setup_local_APIC(); |
3929 | ||
f880ec78 | 3930 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
3931 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
3932 | "edge"); | |
05ddafb1 | 3933 | } |