[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sys_soc.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <mach/cm.h>
#include <mach/lm.h>
#include <mach/irqs.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <asm/hardware/timer-sp.h>

#include <plat/clcd.h>
#include <plat/fpga-irq.h>
#include <plat/sched_clock.h>

#include "common.h"

/* Base address to the CP controller */
static void __iomem *intcp_con_base;

#define INTCP_PA_FLASH_BASE		0x24000000

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

/*
 * Flash handling.
 */
static int intcp_flash_init(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static struct physmap_flash_data intcp_flash_data = {
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(__io_address(0xca000000 + 4));
	writel(8, intcp_con_base + 8);

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static void __init intcp_init_early(void)
{
#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	versatile_sched_clock_init(REFCOUNTER, 24000000);
#endif
}

#ifdef CONFIG_OF

static void __init intcp_timer_init_of(void)
{
	struct device_node *node;
	const char *path;
	void __iomem *base;
	int err;
	int irq;

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	writel(0, base + TIMER_CTRL);
	sp804_clocksource_init(base, node->name);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	irq = irq_of_parse_and_map(node, 0);
	writel(0, base + TIMER_CTRL);
	sp804_clockevents_init(base, irq, node->name);
}

static struct sys_timer cp_of_timer = {
	.init		= intcp_timer_init_of,
};

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init intcp_init_irq_of(void)
{
	of_irq_init(fpga_irq_of_match);
	integrator_clk_init(true);
}

/*
 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 * and enforce the bus names since these are used for clock lookups.
 */
static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
		"mmci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
		"aaci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
		"clcd", &clcd_data),
	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
		"physmap-flash", &intcp_flash_data),
	{ /* sentinel */ },
};

static void __init intcp_init_of(void)
{
	struct device_node *root;
	struct device_node *cpcon;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 intcp_sc_id;
	int err;

	/* Here we create an SoC device for the root node */
	root = of_find_node_by_path("/");
	if (!root)
		return;
	cpcon = of_find_node_by_path("/cpcon");
	if (!cpcon)
		return;

	intcp_con_base = of_iomap(cpcon, 0);
	if (!intcp_con_base)
		return;

	intcp_sc_id = readl(intcp_con_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	err = of_property_read_string(root, "compatible",
				      &soc_dev_attr->soc_id);
	if (err)
		return;
	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	if (err)
		return;
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (intcp_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR_OR_NULL(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);

	if (!IS_ERR_OR_NULL(parent))
		integrator_init_sysfs(parent, intcp_sc_id);

	of_platform_populate(root, of_default_bus_match_table,
			intcp_auxdata_lookup, parent);
}

static const char * intcp_dt_board_compat[] = {
	"arm,integrator-cp",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.timer		= &cp_of_timer,
	.init_machine	= intcp_init_of,
	.restart	= integrator_restart,
	.dt_compat      = intcp_dt_board_compat,
MACHINE_END

#endif

#ifdef CONFIG_ATAGS

/*
 * For the ATAG boot some static mappings are needed. This will
 * go away with the ATAG support down the road.
 */

static struct map_desc intcp_io_desc_atag[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	},
};

static void __init intcp_map_io_atag(void)
{
	iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
	intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
	intcp_map_io();
}


/*
 * This is where non-devicetree initialization code is collected and stashed
 * for eventual deletion.
 */

#define INTCP_FLASH_SIZE		SZ_32M

static struct resource intcp_flash_resource = {
	.start		= INTCP_PA_FLASH_BASE,
	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device intcp_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &intcp_flash_data,
	},
	.num_resources	= 1,
	.resource	= &intcp_flash_resource,
};

#define INTCP_ETH_SIZE			0x10

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= INTEGRATOR_CP_ETH_BASE,
		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CP_ETHINT,
		.end	= IRQ_CP_ETHINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct platform_device *intcp_devs[] __initdata = {
	&intcp_flash_device,
	&smc91x_device,
};

#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)

static void __init intcp_init_irq(void)
{
	u32 pic_mask, cic_mask, sic_mask;

	/* These masks are for the HW IRQ registers */
	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	pic_mask |= (~((~0u) << (29 - 22))) << 22;
	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));

	/*
	 * Disable all interrupt sources
	 */
	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
		      -1, pic_mask, NULL);

	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
		      -1, cic_mask, NULL);

	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
		      IRQ_CP_CPPLDINT, sic_mask, NULL);

	integrator_clk_init(true);
}

#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static void __init intcp_timer_init(void)
{
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
}

static struct sys_timer cp_timer = {
	.init		= intcp_timer_init,
};

#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }

static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
	INTEGRATOR_CP_MMC_IRQS, &mmc_data);

static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
	INTEGRATOR_CP_AACI_IRQS, NULL);

static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
	{ IRQ_CP_CLCDCINT }, &clcd_data);

static struct amba_device *amba_devs[] __initdata = {
	&mmc_device,
	&aaci_device,
	&clcd_device,
};

static void __init intcp_init(void)
{
	int i;

	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
	integrator_init(true);
}

MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.atag_offset	= 0x100,
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io_atag,
	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq,
	.handle_irq	= fpga_handle_irq,
	.timer		= &cp_timer,
	.init_machine	= intcp_init,
	.restart	= integrator_restart,
MACHINE_END

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4	16	#include <linux/string.h>
edbaa603	17	#include <linux/device.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
6ef297f8	21	#include <linux/amba/mmci.h>
fced80c7	22	#include <linux/io.h>
5a0e3ad6	23	#include <linux/gfp.h>
046dfa0a	24	#include <linux/mtd/physmap.h>
a613163d	25	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	26	#include <linux/of_irq.h>
4980f9bc LW	27	#include <linux/of_address.h>
4672cddf	28	#include <linux/of_platform.h>
64100a03	29	#include <linux/sys_soc.h>
1da177e4	30
a09e64fb	31	#include <mach/hardware.h>
a285edcf	32	#include <mach/platform.h>
1da177e4 LT	33	#include <asm/setup.h>
1da177e4 LT	34	#include <asm/mach-types.h>
5a46334a	35	#include <asm/hardware/arm_timer.h>
c5a0adb5	36	#include <asm/hardware/icst.h>
1da177e4	37
a09e64fb RK	38	#include <mach/cm.h>
a09e64fb RK	39	#include <mach/lm.h>
695436e3	40	#include <mach/irqs.h>
1da177e4 LT	41
1da177e4 LT	42	#include <asm/mach/arch.h>
1da177e4	43	#include <asm/mach/irq.h>
1da177e4 LT	44	#include <asm/mach/map.h>
	45	#include <asm/mach/time.h>
	46
8a9618f5	47	#include <asm/hardware/timer-sp.h>
5a46334a	48
9dfec4fe	49	#include <plat/clcd.h>
c41b16f8	50	#include <plat/fpga-irq.h>
d77e270c	51	#include <plat/sched_clock.h>
9dfec4fe	52
98c672cf RK	53	#include "common.h"
98c672cf RK	54
e6fae083 LW	55	/* Base address to the CP controller */
	56	static void __iomem *intcp_con_base;
	57
1da177e4	58	#define INTCP_PA_FLASH_BASE 0x24000000
1da177e4 LT	59
	60	#define INTCP_PA_CLCD_BASE 0xc0000000
	61
1da177e4 LT	62	#define INTCP_FLASHPROG 0x04
	63	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	64	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	65
	66	/*
	67	* Logical Physical
	68	* f1000000 10000000 Core module registers
	69	* f1100000 11000000 System controller registers
	70	* f1200000 12000000 EBI registers
	71	* f1300000 13000000 Counter/Timer
	72	* f1400000 14000000 Interrupt controller
	73	* f1600000 16000000 UART 0
	74	* f1700000 17000000 UART 1
	75	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	76	* fc900000 c9000000 GPIO
	77	* fca00000 ca000000 SIC
	78	* fcb00000 cb000000 CP system control
1da177e4 LT	79	*/
	80
	81	static struct map_desc intcp_io_desc[] __initdata = {
c8d27298 DS	82	{
	83	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	84	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	85	.length = SZ_4K,
	86	.type = MT_DEVICE
c8d27298 DS	87	}, {
	88	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	89	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	90	.length = SZ_4K,
	91	.type = MT_DEVICE
	92	}, {
	93	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	94	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	95	.length = SZ_4K,
	96	.type = MT_DEVICE
	97	}, {
	98	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	99	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	100	.length = SZ_4K,
	101	.type = MT_DEVICE
	102	}, {
	103	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	104	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	105	.length = SZ_4K,
	106	.type = MT_DEVICE
c8d27298 DS	107	}, {
	108	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	109	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	110	.length = SZ_4K,
	111	.type = MT_DEVICE
	112	}, {
da7ba956 RK	113	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	114	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	115	.length = SZ_4K,
	116	.type = MT_DEVICE
	117	}, {
da7ba956 RK	118	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	119	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	120	.length = SZ_4K,
c8d27298 DS	121	.type = MT_DEVICE
c8d27298	122	}
1da177e4 LT	123	};
	124
	125	static void __init intcp_map_io(void)
	126	{
	127	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	128	}
	129
1da177e4 LT	130	/*
	131	* Flash handling.
	132	*/
046dfa0a	133	static int intcp_flash_init(struct platform_device *dev)
1da177e4 LT	134	{
	135	u32 val;
	136
e6fae083	137	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	138	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
e6fae083	139	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	140
	141	return 0;
	142	}
	143
046dfa0a	144	static void intcp_flash_exit(struct platform_device *dev)
1da177e4 LT	145	{
	146	u32 val;
	147
e6fae083	148	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	149	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
e6fae083	150	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	151	}
1da177e4 LT	152
667f390b	153	static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4 LT	154	{
	155	u32 val;
	156
e6fae083	157	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	158	if (on)
	159	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	160	else
	161	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
e6fae083	162	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	163	}
1da177e4 LT	164
046dfa0a	165	static struct physmap_flash_data intcp_flash_data = {
1da177e4 LT	166	.width = 4,
	167	.init = intcp_flash_init,
	168	.exit = intcp_flash_exit,
	169	.set_vpp = intcp_flash_set_vpp,
	170	};
	171
1da177e4 LT	172	/*
	173	* It seems that the card insertion interrupt remains active after
	174	* we've acknowledged it. We therefore ignore the interrupt, and
	175	* rely on reading it from the SIC. This also means that we must
	176	* clear the latched interrupt.
	177	*/
	178	static unsigned int mmc_status(struct device *dev)
	179	{
b7a3f8db	180	unsigned int status = readl(__io_address(0xca000000 + 4));
e6fae083	181	writel(8, intcp_con_base + 8);
1da177e4 LT	182
	183	return status & 8;
	184	}
	185
6ef297f8	186	static struct mmci_platform_data mmc_data = {
1da177e4 LT	187	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	188	.status = mmc_status,
7fb2bbf4 RK	189	.gpio_wp = -1,
7fb2bbf4 RK	190	.gpio_cd = -1,
1da177e4 LT	191	};
1da177e4 LT	192
1da177e4 LT	193	/*
	194	* CLCD support
	195	*/
1da177e4 LT	196	/*
	197	* Ensure VGA is selected.
	198	*/
	199	static void cp_clcd_enable(struct clcd_fb *fb)
	200	{
e6b9c1f8 RK	201	struct fb_var_screeninfo *var = &fb->fb.var;
e6b9c1f8 RK	202	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2;
4774e226	203
e6b9c1f8 RK	204	if (var->bits_per_pixel <= 8 \|\|
	205	(var->bits_per_pixel == 16 && var->green.length == 5))
	206	/* Pseudocolor, RGB555, BGR555 */
	207	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	208	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	209	/* truecolor RGB565 */
e6b9c1f8 RK	210	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	211	else
	212	val = 0; /* no idea for this, don't trust the docs */
	213
	214	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	215	CM_CTRL_LCDEN0\|
	216	CM_CTRL_LCDEN1\|
	217	CM_CTRL_STATIC1\|
	218	CM_CTRL_STATIC2\|
	219	CM_CTRL_STATIC\|
	220	CM_CTRL_n24BITEN, val);
1da177e4 LT	221	}
1da177e4 LT	222
1da177e4 LT	223	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	224	{
9dfec4fe RK	225	fb->panel = versatile_clcd_get_panel("VGA");
	226	if (!fb->panel)
	227	return -EINVAL;
1da177e4	228
9dfec4fe	229	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	230	}
	231
	232	static struct clcd_board clcd_data = {
	233	.name = "Integrator/CP",
9dfec4fe	234	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	235	.check = clcdfb_check,
	236	.decode = clcdfb_decode,
	237	.enable = cp_clcd_enable,
	238	.setup = cp_clcd_setup,
9dfec4fe RK	239	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	240	.remove = versatile_clcd_remove_dma,
1da177e4 LT	241	};
1da177e4 LT	242
d77e270c RK	243	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	244
c735c987 RK	245	static void __init intcp_init_early(void)
c735c987 RK	246	{
d77e270c RK	247	#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	248	versatile_sched_clock_init(REFCOUNTER, 24000000);
	249	#endif
c735c987 RK	250	}
c735c987 RK	251
6e3a78d9 OJ	252	#ifdef CONFIG_OF
6e3a78d9 OJ	253
4980f9bc	254	static void __init intcp_timer_init_of(void)
1da177e4	255	{
4980f9bc LW	256	struct device_node *node;
	257	const char *path;
	258	void __iomem *base;
	259	int err;
	260	int irq;
	261
	262	err = of_property_read_string(of_aliases,
	263	"arm,timer-primary", &path);
	264	if (WARN_ON(err))
	265	return;
	266	node = of_find_node_by_path(path);
	267	base = of_iomap(node, 0);
	268	if (WARN_ON(!base))
	269	return;
	270	writel(0, base + TIMER_CTRL);
	271	sp804_clocksource_init(base, node->name);
	272
	273	err = of_property_read_string(of_aliases,
	274	"arm,timer-secondary", &path);
	275	if (WARN_ON(err))
	276	return;
	277	node = of_find_node_by_path(path);
	278	base = of_iomap(node, 0);
	279	if (WARN_ON(!base))
	280	return;
	281	irq = irq_of_parse_and_map(node, 0);
	282	writel(0, base + TIMER_CTRL);
	283	sp804_clockevents_init(base, irq, node->name);
	284	}
1da177e4	285
4980f9bc LW	286	static struct sys_timer cp_of_timer = {
	287	.init = intcp_timer_init_of,
	288	};
1da177e4	289
4980f9bc LW	290	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	291	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	292	{ /* Sentinel */ }
	293	};
	294
	295	static void __init intcp_init_irq_of(void)
1da177e4	296	{
4980f9bc LW	297	of_irq_init(fpga_irq_of_match);
	298	integrator_clk_init(true);
	299	}
1da177e4	300
4672cddf LW	301	/*
	302	* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
	303	* and enforce the bus names since these are used for clock lookups.
	304	*/
	305	static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	306	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	307	"rtc", NULL),
	308	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	309	"uart0", NULL),
4672cddf	310	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	311	"uart1", NULL),
4672cddf LW	312	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	313	"kmi0", NULL),
	314	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	315	"kmi1", NULL),
	316	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
	317	"mmci", &mmc_data),
	318	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
	319	"aaci", &mmc_data),
	320	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
	321	"clcd", &clcd_data),
73efd530 LW	322	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
73efd530 LW	323	"physmap-flash", &intcp_flash_data),
4672cddf LW	324	{ /* sentinel */ },
	325	};
	326
	327	static void __init intcp_init_of(void)
	328	{
64100a03 LW	329	struct device_node *root;
	330	struct device_node *cpcon;
	331	struct device *parent;
	332	struct soc_device *soc_dev;
	333	struct soc_device_attribute *soc_dev_attr;
	334	u32 intcp_sc_id;
	335	int err;
	336
	337	/* Here we create an SoC device for the root node */
	338	root = of_find_node_by_path("/");
	339	if (!root)
	340	return;
	341	cpcon = of_find_node_by_path("/cpcon");
	342	if (!cpcon)
	343	return;
	344
	345	intcp_con_base = of_iomap(cpcon, 0);
	346	if (!intcp_con_base)
	347	return;
	348
	349	intcp_sc_id = readl(intcp_con_base);
	350
	351	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	352	if (!soc_dev_attr)
	353	return;
	354
	355	err = of_property_read_string(root, "compatible",
	356	&soc_dev_attr->soc_id);
	357	if (err)
	358	return;
	359	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	360	if (err)
	361	return;
	362	soc_dev_attr->family = "Integrator";
	363	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	364	'A' + (intcp_sc_id & 0x0f));
	365
	366	soc_dev = soc_device_register(soc_dev_attr);
	367	if (IS_ERR_OR_NULL(soc_dev)) {
	368	kfree(soc_dev_attr->revision);
	369	kfree(soc_dev_attr);
	370	return;
	371	}
	372
	373	parent = soc_device_to_device(soc_dev);
	374
	375	if (!IS_ERR_OR_NULL(parent))
	376	integrator_init_sysfs(parent, intcp_sc_id);
	377
	378	of_platform_populate(root, of_default_bus_match_table,
	379	intcp_auxdata_lookup, parent);
4672cddf LW	380	}
4672cddf LW	381
4980f9bc LW	382	static const char * intcp_dt_board_compat[] = {
	383	"arm,integrator-cp",
	384	NULL,
	385	};
1da177e4	386
4980f9bc LW	387	DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	388	.reserve = integrator_reserve,
	389	.map_io = intcp_map_io,
	390	.nr_irqs = NR_IRQS_INTEGRATOR_CP,
	391	.init_early = intcp_init_early,
	392	.init_irq = intcp_init_irq_of,
	393	.handle_irq = fpga_handle_irq,
	394	.timer = &cp_of_timer,
4672cddf	395	.init_machine = intcp_init_of,
4980f9bc LW	396	.restart = integrator_restart,
	397	.dt_compat = intcp_dt_board_compat,
	398	MACHINE_END
	399
	400	#endif
	401
	402	#ifdef CONFIG_ATAGS
	403
e6fae083 LW	404	/*
	405	* For the ATAG boot some static mappings are needed. This will
	406	* go away with the ATAG support down the road.
	407	*/
	408
	409	static struct map_desc intcp_io_desc_atag[] __initdata = {
	410	{
	411	.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
	412	.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
	413	.length = SZ_4K,
	414	.type = MT_DEVICE
	415	},
	416	};
	417
	418	static void __init intcp_map_io_atag(void)
	419	{
	420	iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
	421	intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
	422	intcp_map_io();
	423	}
	424
	425
4980f9bc LW	426	/*
	427	* This is where non-devicetree initialization code is collected and stashed
	428	* for eventual deletion.
	429	*/
	430
73efd530 LW	431	#define INTCP_FLASH_SIZE SZ_32M
	432
	433	static struct resource intcp_flash_resource = {
	434	.start = INTCP_PA_FLASH_BASE,
	435	.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	436	.flags = IORESOURCE_MEM,
	437	};
	438
	439	static struct platform_device intcp_flash_device = {
	440	.name = "physmap-flash",
	441	.id = 0,
	442	.dev = {
	443	.platform_data = &intcp_flash_data,
	444	},
	445	.num_resources = 1,
	446	.resource = &intcp_flash_resource,
	447	};
	448
	449	#define INTCP_ETH_SIZE 0x10
	450
	451	static struct resource smc91x_resources[] = {
	452	[0] = {
	453	.start = INTEGRATOR_CP_ETH_BASE,
	454	.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
	455	.flags = IORESOURCE_MEM,
	456	},
	457	[1] = {
	458	.start = IRQ_CP_ETHINT,
	459	.end = IRQ_CP_ETHINT,
	460	.flags = IORESOURCE_IRQ,
	461	},
	462	};
	463
	464	static struct platform_device smc91x_device = {
	465	.name = "smc91x",
	466	.id = 0,
	467	.num_resources = ARRAY_SIZE(smc91x_resources),
	468	.resource = smc91x_resources,
	469	};
	470
	471	static struct platform_device *intcp_devs[] __initdata = {
	472	&intcp_flash_device,
	473	&smc91x_device,
	474	};
	475
4980f9bc LW	476	#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
	477	#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
	478	#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
	479
	480	static void __init intcp_init_irq(void)
	481	{
	482	u32 pic_mask, cic_mask, sic_mask;
	483
	484	/* These masks are for the HW IRQ registers */
	485	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	486	pic_mask \|= (~((~0u) << (29 - 22))) << 22;
	487	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
	488	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
	489
	490	/*
	491	* Disable all interrupt sources
	492	*/
	493	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	494	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	495	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	496	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	497	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	498	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
	499
	500	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
	501	-1, pic_mask, NULL);
	502
	503	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
	504	-1, cic_mask, NULL);
	505
	506	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
	507	IRQ_CP_CPPLDINT, sic_mask, NULL);
	508
	509	integrator_clk_init(true);
1da177e4 LT	510	}
1da177e4 LT	511
5a46334a RK	512	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	513	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	514	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
1da177e4 LT	515
	516	static void __init intcp_timer_init(void)
	517	{
5a46334a RK	518	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	519	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	520	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	521
fb593cf3	522	sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
57cc4f7d	523	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
1da177e4 LT	524	}
	525
	526	static struct sys_timer cp_timer = {
	527	.init = intcp_timer_init,
1da177e4 LT	528	};
1da177e4 LT	529
4672cddf LW	530	#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
	531	#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
	532
	533	static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
	534	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
	535
	536	static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
	537	INTEGRATOR_CP_AACI_IRQS, NULL);
	538
	539	static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
	540	{ IRQ_CP_CLCDCINT }, &clcd_data);
	541
	542	static struct amba_device *amba_devs[] __initdata = {
	543	&mmc_device,
	544	&aaci_device,
	545	&clcd_device,
	546	};
	547
	548	static void __init intcp_init(void)
	549	{
	550	int i;
	551
	552	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
	553
	554	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	555	struct amba_device *d = amba_devs[i];
	556	amba_device_register(d, &iomem_resource);
	557	}
	558	integrator_init(true);
	559	}
	560
1da177e4	561	MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
e9dea0c6	562	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
c5e587a2	563	.atag_offset = 0x100,
98c672cf	564	.reserve = integrator_reserve,
e6fae083	565	.map_io = intcp_map_io_atag,
695436e3	566	.nr_irqs = NR_IRQS_INTEGRATOR_CP,
c735c987	567	.init_early = intcp_init_early,
e9dea0c6	568	.init_irq = intcp_init_irq,
3108e6ab	569	.handle_irq = fpga_handle_irq,
1da177e4	570	.timer = &cp_timer,
e9dea0c6	571	.init_machine = intcp_init,
6338b66f	572	.restart = integrator_restart,
1da177e4	573	MACHINE_END
4980f9bc LW	574
4980f9bc LW	575	#endif