[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-davinci / board-dm646x-evm.c

/*
 * TI DaVinci DM646X EVM board
 *
 * Derived from: arch/arm/mach-davinci/board-evm.c
 * Copyright (C) 2006 Texas Instruments.
 *
 * (C) 2007-2008, MontaVista Software, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 *
 */

/**************************************************************************
 * Included Files
 **************************************************************************/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/i2c/pcf857x.h>

#include <media/tvp514x.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/clk.h>
#include <linux/export.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include <mach/dm646x.h>
#include <mach/common.h>
#include <mach/serial.h>
#include <mach/i2c.h>
#include <mach/nand.h>
#include <mach/clock.h>
#include <mach/cdce949.h>
#include <mach/aemif.h>

#include "clock.h"

#define NAND_BLOCK_SIZE		SZ_128K

/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
 * and U-Boot environment this avoids dependency on any particular combination
 * of UBL, U-Boot or flashing tools etc.
 */
static struct mtd_partition davinci_nand_partitions[] = {
	{
		/* UBL, U-Boot with environment */
		.name		= "bootloader",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 16 * NAND_BLOCK_SIZE,
		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
	}, {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_4M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
};

static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
	.wsetup		= 29,
	.wstrobe	= 24,
	.whold		= 14,
	.rsetup		= 19,
	.rstrobe	= 33,
	.rhold		= 0,
	.ta		= 29,
};

static struct davinci_nand_pdata davinci_nand_data = {
	.mask_cle 		= 0x80000,
	.mask_ale 		= 0x40000,
	.parts			= davinci_nand_partitions,
	.nr_parts		= ARRAY_SIZE(davinci_nand_partitions),
	.ecc_mode		= NAND_ECC_HW,
	.options		= 0,
};

static struct resource davinci_nand_resources[] = {
	{
		.start		= DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
		.end		= DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= DM646X_ASYNC_EMIF_CONTROL_BASE,
		.end		= DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device davinci_nand_device = {
	.name			= "davinci_nand",
	.id			= 0,

	.num_resources		= ARRAY_SIZE(davinci_nand_resources),
	.resource		= davinci_nand_resources,

	.dev			= {
		.platform_data	= &davinci_nand_data,
	},
};

#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
#define HAS_ATA 1
#else
#define HAS_ATA 0
#endif

/* CPLD Register 0 bits to control ATA */
#define DM646X_EVM_ATA_RST		BIT(0)
#define DM646X_EVM_ATA_PWD		BIT(1)

/* CPLD Register 0 Client: used for I/O Control */
static int cpld_reg0_probe(struct i2c_client *client,
			   const struct i2c_device_id *id)
{
	if (HAS_ATA) {
		u8 data;
		struct i2c_msg msg[2] = {
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &data,
			},
			{
				.addr = client->addr,
				.flags = 0,
				.len = 1,
				.buf = &data,
			},
		};

		/* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
		i2c_transfer(client->adapter, msg, 1);
		data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
		i2c_transfer(client->adapter, msg + 1, 1);
	}

	return 0;
}

static const struct i2c_device_id cpld_reg_ids[] = {
	{ "cpld_reg0", 0, },
	{ },
};

static struct i2c_driver dm6467evm_cpld_driver = {
	.driver.name	= "cpld_reg0",
	.id_table	= cpld_reg_ids,
	.probe		= cpld_reg0_probe,
};

/* LEDS */

static struct gpio_led evm_leds[] = {
	{ .name = "DS1", .active_low = 1, },
	{ .name = "DS2", .active_low = 1, },
	{ .name = "DS3", .active_low = 1, },
	{ .name = "DS4", .active_low = 1, },
};

static const struct gpio_led_platform_data evm_led_data = {
	.num_leds = ARRAY_SIZE(evm_leds),
	.leds     = evm_leds,
};

static struct platform_device *evm_led_dev;

static int evm_led_setup(struct i2c_client *client, int gpio,
			unsigned int ngpio, void *c)
{
	struct gpio_led *leds = evm_leds;
	int status;

	while (ngpio--) {
		leds->gpio = gpio++;
		leds++;
	};

	evm_led_dev = platform_device_alloc("leds-gpio", 0);
	platform_device_add_data(evm_led_dev, &evm_led_data,
				sizeof(evm_led_data));

	evm_led_dev->dev.parent = &client->dev;
	status = platform_device_add(evm_led_dev);
	if (status < 0) {
		platform_device_put(evm_led_dev);
		evm_led_dev = NULL;
	}
	return status;
}

static int evm_led_teardown(struct i2c_client *client, int gpio,
				unsigned ngpio, void *c)
{
	if (evm_led_dev) {
		platform_device_unregister(evm_led_dev);
		evm_led_dev = NULL;
	}
	return 0;
}

static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };

static int evm_sw_setup(struct i2c_client *client, int gpio,
			unsigned ngpio, void *c)
{
	int status;
	int i;
	char label[10];

	for (i = 0; i < 4; ++i) {
		snprintf(label, 10, "user_sw%d", i);
		status = gpio_request(gpio, label);
		if (status)
			goto out_free;
		evm_sw_gpio[i] = gpio++;

		status = gpio_direction_input(evm_sw_gpio[i]);
		if (status) {
			gpio_free(evm_sw_gpio[i]);
			evm_sw_gpio[i] = -EINVAL;
			goto out_free;
		}

		status = gpio_export(evm_sw_gpio[i], 0);
		if (status) {
			gpio_free(evm_sw_gpio[i]);
			evm_sw_gpio[i] = -EINVAL;
			goto out_free;
		}
	}
	return status;
out_free:
	for (i = 0; i < 4; ++i) {
		if (evm_sw_gpio[i] != -EINVAL) {
			gpio_free(evm_sw_gpio[i]);
			evm_sw_gpio[i] = -EINVAL;
		}
	}
	return status;
}

static int evm_sw_teardown(struct i2c_client *client, int gpio,
			unsigned ngpio, void *c)
{
	int i;

	for (i = 0; i < 4; ++i) {
		if (evm_sw_gpio[i] != -EINVAL) {
			gpio_unexport(evm_sw_gpio[i]);
			gpio_free(evm_sw_gpio[i]);
			evm_sw_gpio[i] = -EINVAL;
		}
	}
	return 0;
}

static int evm_pcf_setup(struct i2c_client *client, int gpio,
			unsigned int ngpio, void *c)
{
	int status;

	if (ngpio < 8)
		return -EINVAL;

	status = evm_sw_setup(client, gpio, 4, c);
	if (status)
		return status;

	return evm_led_setup(client, gpio+4, 4, c);
}

static int evm_pcf_teardown(struct i2c_client *client, int gpio,
			unsigned int ngpio, void *c)
{
	BUG_ON(ngpio < 8);

	evm_sw_teardown(client, gpio, 4, c);
	evm_led_teardown(client, gpio+4, 4, c);

	return 0;
}

static struct pcf857x_platform_data pcf_data = {
	.gpio_base	= DAVINCI_N_GPIO+1,
	.setup		= evm_pcf_setup,
	.teardown	= evm_pcf_teardown,
};

/* Most of this EEPROM is unused, but U-Boot uses some data:
 *  - 0x7f00, 6 bytes Ethernet Address
 *  - ... newer boards may have more
 */

static struct at24_platform_data eeprom_info = {
	.byte_len       = (256*1024) / 8,
	.page_size      = 64,
	.flags          = AT24_FLAG_ADDR16,
	.setup          = davinci_get_mac_addr,
	.context	= (void *)0x7f00,
};

static u8 dm646x_iis_serializer_direction[] = {
       TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
};

static u8 dm646x_dit_serializer_direction[] = {
       TX_MODE,
};

static struct snd_platform_data dm646x_evm_snd_data[] = {
	{
		.tx_dma_offset  = 0x400,
		.rx_dma_offset  = 0x400,
		.op_mode        = DAVINCI_MCASP_IIS_MODE,
		.num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
		.tdm_slots      = 2,
		.serial_dir     = dm646x_iis_serializer_direction,
		.asp_chan_q     = EVENTQ_0,
	},
	{
		.tx_dma_offset  = 0x400,
		.rx_dma_offset  = 0,
		.op_mode        = DAVINCI_MCASP_DIT_MODE,
		.num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
		.tdm_slots      = 32,
		.serial_dir     = dm646x_dit_serializer_direction,
		.asp_chan_q     = EVENTQ_0,
	},
};

static struct i2c_client *cpld_client;

static int cpld_video_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	cpld_client = client;
	return 0;
}

static int __devexit cpld_video_remove(struct i2c_client *client)
{
	cpld_client = NULL;
	return 0;
}

static const struct i2c_device_id cpld_video_id[] = {
	{ "cpld_video", 0 },
	{ }
};

static struct i2c_driver cpld_video_driver = {
	.driver = {
		.name	= "cpld_video",
	},
	.probe		= cpld_video_probe,
	.remove		= cpld_video_remove,
	.id_table	= cpld_video_id,
};

static void evm_init_cpld(void)
{
	i2c_add_driver(&cpld_video_driver);
}

static struct i2c_board_info __initdata i2c_info[] =  {
	{
		I2C_BOARD_INFO("24c256", 0x50),
		.platform_data  = &eeprom_info,
	},
	{
		I2C_BOARD_INFO("pcf8574a", 0x38),
		.platform_data	= &pcf_data,
	},
	{
		I2C_BOARD_INFO("cpld_reg0", 0x3a),
	},
	{
		I2C_BOARD_INFO("tlv320aic33", 0x18),
	},
	{
		I2C_BOARD_INFO("cpld_video", 0x3b),
	},
	{
		I2C_BOARD_INFO("cdce949", 0x6c),
	},
};

static struct davinci_i2c_platform_data i2c_pdata = {
	.bus_freq       = 100 /* kHz */,
	.bus_delay      = 0 /* usec */,
};

#define VIDCLKCTL_OFFSET	(DAVINCI_SYSTEM_MODULE_BASE + 0x38)
#define VSCLKDIS_OFFSET		(DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
#define VCH2CLK_MASK		(BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
#define VCH2CLK_SYSCLK8		(BIT(9))
#define VCH2CLK_AUXCLK		(BIT(9) | BIT(8))
#define VCH3CLK_MASK		(BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
#define VCH3CLK_SYSCLK8		(BIT(13))
#define VCH3CLK_AUXCLK		(BIT(14) | BIT(13))

#define VIDCH2CLK		(BIT(10))
#define VIDCH3CLK		(BIT(11))
#define VIDCH1CLK		(BIT(4))
#define TVP7002_INPUT		(BIT(4))
#define TVP5147_INPUT		(~BIT(4))
#define VPIF_INPUT_ONE_CHANNEL	(BIT(5))
#define VPIF_INPUT_TWO_CHANNEL	(~BIT(5))
#define TVP5147_CH0		"tvp514x-0"
#define TVP5147_CH1		"tvp514x-1"

static void __iomem *vpif_vidclkctl_reg;
static void __iomem *vpif_vsclkdis_reg;
/* spin lock for updating above registers */
static spinlock_t vpif_reg_lock;

static int set_vpif_clock(int mux_mode, int hd)
{
	unsigned long flags;
	unsigned int value;
	int val = 0;
	int err = 0;

	if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
		return -ENXIO;

	/* disable the clock */
	spin_lock_irqsave(&vpif_reg_lock, flags);
	value = __raw_readl(vpif_vsclkdis_reg);
	value |= (VIDCH3CLK | VIDCH2CLK);
	__raw_writel(value, vpif_vsclkdis_reg);
	spin_unlock_irqrestore(&vpif_reg_lock, flags);

	val = i2c_smbus_read_byte(cpld_client);
	if (val < 0)
		return val;

	if (mux_mode == 1)
		val &= ~0x40;
	else
		val |= 0x40;

	err = i2c_smbus_write_byte(cpld_client, val);
	if (err)
		return err;

	value = __raw_readl(vpif_vidclkctl_reg);
	value &= ~(VCH2CLK_MASK);
	value &= ~(VCH3CLK_MASK);

	if (hd >= 1)
		value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
	else
		value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);

	__raw_writel(value, vpif_vidclkctl_reg);

	spin_lock_irqsave(&vpif_reg_lock, flags);
	value = __raw_readl(vpif_vsclkdis_reg);
	/* enable the clock */
	value &= ~(VIDCH3CLK | VIDCH2CLK);
	__raw_writel(value, vpif_vsclkdis_reg);
	spin_unlock_irqrestore(&vpif_reg_lock, flags);

	return 0;
}

static struct vpif_subdev_info dm646x_vpif_subdev[] = {
	{
		.name	= "adv7343",
		.board_info = {
			I2C_BOARD_INFO("adv7343", 0x2a),
		},
	},
	{
		.name	= "ths7303",
		.board_info = {
			I2C_BOARD_INFO("ths7303", 0x2c),
		},
	},
};

static const char *output[] = {
	"Composite",
	"Component",
	"S-Video",
};

static struct vpif_display_config dm646x_vpif_display_config = {
	.set_clock	= set_vpif_clock,
	.subdevinfo	= dm646x_vpif_subdev,
	.subdev_count	= ARRAY_SIZE(dm646x_vpif_subdev),
	.output		= output,
	.output_count	= ARRAY_SIZE(output),
	.card_name	= "DM646x EVM",
};

/**
 * setup_vpif_input_path()
 * @channel: channel id (0 - CH0, 1 - CH1)
 * @sub_dev_name: ptr sub device name
 *
 * This will set vpif input to capture data from tvp514x or
 * tvp7002.
 */
static int setup_vpif_input_path(int channel, const char *sub_dev_name)
{
	int err = 0;
	int val;

	/* for channel 1, we don't do anything */
	if (channel != 0)
		return 0;

	if (!cpld_client)
		return -ENXIO;

	val = i2c_smbus_read_byte(cpld_client);
	if (val < 0)
		return val;

	if (!strcmp(sub_dev_name, TVP5147_CH0) ||
	    !strcmp(sub_dev_name, TVP5147_CH1))
		val &= TVP5147_INPUT;
	else
		val |= TVP7002_INPUT;

	err = i2c_smbus_write_byte(cpld_client, val);
	if (err)
		return err;
	return 0;
}

/**
 * setup_vpif_input_channel_mode()
 * @mux_mode:  mux mode. 0 - 1 channel or (1) - 2 channel
 *
 * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
 */
static int setup_vpif_input_channel_mode(int mux_mode)
{
	unsigned long flags;
	int err = 0;
	int val;
	u32 value;

	if (!vpif_vidclkctl_reg || !cpld_client)
		return -ENXIO;

	val = i2c_smbus_read_byte(cpld_client);
	if (val < 0)
		return val;

	spin_lock_irqsave(&vpif_reg_lock, flags);
	value = __raw_readl(vpif_vidclkctl_reg);
	if (mux_mode) {
		val &= VPIF_INPUT_TWO_CHANNEL;
		value |= VIDCH1CLK;
	} else {
		val |= VPIF_INPUT_ONE_CHANNEL;
		value &= ~VIDCH1CLK;
	}
	__raw_writel(value, vpif_vidclkctl_reg);
	spin_unlock_irqrestore(&vpif_reg_lock, flags);

	err = i2c_smbus_write_byte(cpld_client, val);
	if (err)
		return err;

	return 0;
}

static struct tvp514x_platform_data tvp5146_pdata = {
	.clk_polarity = 0,
	.hs_polarity = 1,
	.vs_polarity = 1
};

#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)

static struct vpif_subdev_info vpif_capture_sdev_info[] = {
	{
		.name	= TVP5147_CH0,
		.board_info = {
			I2C_BOARD_INFO("tvp5146", 0x5d),
			.platform_data = &tvp5146_pdata,
		},
		.input = INPUT_CVBS_VI2B,
		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
		.can_route = 1,
		.vpif_if = {
			.if_type = VPIF_IF_BT656,
			.hd_pol = 1,
			.vd_pol = 1,
			.fid_pol = 0,
		},
	},
	{
		.name	= TVP5147_CH1,
		.board_info = {
			I2C_BOARD_INFO("tvp5146", 0x5c),
			.platform_data = &tvp5146_pdata,
		},
		.input = INPUT_SVIDEO_VI2C_VI1C,
		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
		.can_route = 1,
		.vpif_if = {
			.if_type = VPIF_IF_BT656,
			.hd_pol = 1,
			.vd_pol = 1,
			.fid_pol = 0,
		},
	},
};

static const struct vpif_input dm6467_ch0_inputs[] = {
	{
		.input = {
			.index = 0,
			.name = "Composite",
			.type = V4L2_INPUT_TYPE_CAMERA,
			.std = TVP514X_STD_ALL,
		},
		.subdev_name = TVP5147_CH0,
	},
};

static const struct vpif_input dm6467_ch1_inputs[] = {
       {
		.input = {
			.index = 0,
			.name = "S-Video",
			.type = V4L2_INPUT_TYPE_CAMERA,
			.std = TVP514X_STD_ALL,
		},
		.subdev_name = TVP5147_CH1,
	},
};

static struct vpif_capture_config dm646x_vpif_capture_cfg = {
	.setup_input_path = setup_vpif_input_path,
	.setup_input_channel_mode = setup_vpif_input_channel_mode,
	.subdev_info = vpif_capture_sdev_info,
	.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
	.chan_config[0] = {
		.inputs = dm6467_ch0_inputs,
		.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
	},
	.chan_config[1] = {
		.inputs = dm6467_ch1_inputs,
		.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
	},
};

static void __init evm_init_video(void)
{
	vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
	vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
	if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
		pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
		return;
	}
	spin_lock_init(&vpif_reg_lock);

	dm646x_setup_vpif(&dm646x_vpif_display_config,
			  &dm646x_vpif_capture_cfg);
}

static void __init evm_init_i2c(void)
{
	davinci_init_i2c(&i2c_pdata);
	i2c_add_driver(&dm6467evm_cpld_driver);
	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
	evm_init_cpld();
	evm_init_video();
}

#define CDCE949_XIN_RATE	27000000

/* CDCE949 support - "lpsc" field is overridden to work as clock number */
static struct clk cdce_clk_in = {
	.name	= "cdce_xin",
	.rate	= CDCE949_XIN_RATE,
};

static struct clk_lookup cdce_clks[] = {
	CLK(NULL, "xin", &cdce_clk_in),
	CLK(NULL, NULL, NULL),
};

static void __init cdce_clk_init(void)
{
	struct clk_lookup *c;
	struct clk *clk;

	for (c = cdce_clks; c->clk; c++) {
		clk = c->clk;
		clkdev_add(c);
		clk_register(clk);
	}
}

#define DM6467T_EVM_REF_FREQ		33000000

static void __init davinci_map_io(void)
{
	dm646x_init();

	if (machine_is_davinci_dm6467tevm())
		davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);

	cdce_clk_init();
}

static struct davinci_uart_config uart_config __initdata = {
	.enabled_uarts = (1 << 0),
};

#define DM646X_EVM_PHY_ID		"0:01"
/*
 * The following EDMA channels/slots are not being used by drivers (for
 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
 * reserved for codecs on the DSP side.
 */
static const s16 dm646x_dma_rsv_chans[][2] = {
	/* (offset, number) */
	{ 0,  4},
	{13,  3},
	{24,  4},
	{30,  2},
	{54,  3},
	{-1, -1}
};

static const s16 dm646x_dma_rsv_slots[][2] = {
	/* (offset, number) */
	{ 0,  4},
	{13,  3},
	{24,  4},
	{30,  2},
	{54,  3},
	{128, 384},
	{-1, -1}
};

static struct edma_rsv_info dm646x_edma_rsv[] = {
	{
		.rsv_chans	= dm646x_dma_rsv_chans,
		.rsv_slots	= dm646x_dma_rsv_slots,
	},
};

static __init void evm_init(void)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	evm_init_i2c();
	davinci_serial_init(&uart_config);
	dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
	dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);

	if (machine_is_davinci_dm6467tevm())
		davinci_nand_data.timing = &dm6467tevm_nandflash_timing;

	platform_device_register(&davinci_nand_device);

	dm646x_init_edma(dm646x_edma_rsv);

	if (HAS_ATA)
		davinci_init_ide();

	soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
}

MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
	.atag_offset  = 0x100,
	.map_io       = davinci_map_io,
	.init_irq     = davinci_irq_init,
	.timer        = &davinci_timer,
	.init_machine = evm_init,
	.dma_zone_size	= SZ_128M,
	.restart	= davinci_restart,
MACHINE_END

MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
	.atag_offset  = 0x100,
	.map_io       = davinci_map_io,
	.init_irq     = davinci_irq_init,
	.timer        = &davinci_timer,
	.init_machine = evm_init,
	.dma_zone_size	= SZ_128M,
	.restart	= davinci_restart,
MACHINE_END
Commit	Line	Data
e38d92fd KH	1	/*
	2	* TI DaVinci DM646X EVM board
	3	*
	4	* Derived from: arch/arm/mach-davinci/board-evm.c
	5	* Copyright (C) 2006 Texas Instruments.
	6	*
	7	* (C) 2007-2008, MontaVista Software, Inc.
	8	*
	9	* This file is licensed under the terms of the GNU General Public License
	10	* version 2. This program is licensed "as is" without any warranty of any
	11	* kind, whether express or implied.
	12	*
	13	*/
	14
	15	/**************************************************************************
	16	* Included Files
	17	**************************************************************************/
	18
	19	#include <linux/kernel.h>
e38d92fd	20	#include <linux/init.h>
e38d92fd KH	21	#include <linux/leds.h>
e38d92fd KH	22	#include <linux/gpio.h>
e38d92fd KH	23	#include <linux/platform_device.h>
	24	#include <linux/i2c.h>
	25	#include <linux/i2c/at24.h>
	26	#include <linux/i2c/pcf857x.h>
e38d92fd	27
85609c1c MK	28	#include <media/tvp514x.h>
85609c1c MK	29
50fbabfe HP	30	#include <linux/mtd/mtd.h>
	31	#include <linux/mtd/nand.h>
	32	#include <linux/mtd/partitions.h>
c1978e1d	33	#include <linux/clk.h>
dc28094b	34	#include <linux/export.h>
50fbabfe	35
e38d92fd KH	36	#include <asm/mach-types.h>
e38d92fd KH	37	#include <asm/mach/arch.h>
e38d92fd KH	38
	39	#include <mach/dm646x.h>
	40	#include <mach/common.h>
e38d92fd KH	41	#include <mach/serial.h>
e38d92fd KH	42	#include <mach/i2c.h>
50fbabfe	43	#include <mach/nand.h>
77a92c71 NS	44	#include <mach/clock.h>
77a92c71 NS	45	#include <mach/cdce949.h>
0b3fc7bb	46	#include <mach/aemif.h>
ac7b75b5	47
c1978e1d SN	48	#include "clock.h"
c1978e1d SN	49
50fbabfe HP	50	#define NAND_BLOCK_SIZE SZ_128K
50fbabfe HP	51
50fbabfe HP	52	/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
	53	* and U-Boot environment this avoids dependency on any particular combination
	54	* of UBL, U-Boot or flashing tools etc.
	55	*/
	56	static struct mtd_partition davinci_nand_partitions[] = {
	57	{
	58	/* UBL, U-Boot with environment */
	59	.name = "bootloader",
	60	.offset = MTDPART_OFS_APPEND,
	61	.size = 16 * NAND_BLOCK_SIZE,
	62	.mask_flags = MTD_WRITEABLE, /* force read-only */
	63	}, {
	64	.name = "kernel",
	65	.offset = MTDPART_OFS_APPEND,
	66	.size = SZ_4M,
	67	.mask_flags = 0,
	68	}, {
	69	.name = "filesystem",
	70	.offset = MTDPART_OFS_APPEND,
	71	.size = MTDPART_SIZ_FULL,
	72	.mask_flags = 0,
	73	}
	74	};
	75
0b3fc7bb SN	76	static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
	77	.wsetup = 29,
	78	.wstrobe = 24,
	79	.whold = 14,
	80	.rsetup = 19,
	81	.rstrobe = 33,
	82	.rhold = 0,
	83	.ta = 29,
	84	};
	85
50fbabfe HP	86	static struct davinci_nand_pdata davinci_nand_data = {
	87	.mask_cle = 0x80000,
	88	.mask_ale = 0x40000,
	89	.parts = davinci_nand_partitions,
	90	.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
	91	.ecc_mode = NAND_ECC_HW,
	92	.options = 0,
	93	};
	94
	95	static struct resource davinci_nand_resources[] = {
	96	{
70342174 SS	97	.start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
70342174 SS	98	.end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
50fbabfe HP	99	.flags = IORESOURCE_MEM,
50fbabfe HP	100	}, {
70342174 SS	101	.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
70342174 SS	102	.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
50fbabfe HP	103	.flags = IORESOURCE_MEM,
	104	},
	105	};
	106
	107	static struct platform_device davinci_nand_device = {
	108	.name = "davinci_nand",
	109	.id = 0,
	110
	111	.num_resources = ARRAY_SIZE(davinci_nand_resources),
	112	.resource = davinci_nand_resources,
	113
	114	.dev = {
	115	.platform_data = &davinci_nand_data,
	116	},
	117	};
	118
b73b526e SN	119	#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) \|\| \
	120	defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
	121	#define HAS_ATA 1
	122	#else
	123	#define HAS_ATA 0
	124	#endif
	125
	126	/* CPLD Register 0 bits to control ATA */
	127	#define DM646X_EVM_ATA_RST BIT(0)
	128	#define DM646X_EVM_ATA_PWD BIT(1)
	129
548197bd HP	130	/* CPLD Register 0 Client: used for I/O Control */
	131	static int cpld_reg0_probe(struct i2c_client *client,
	132	const struct i2c_device_id *id)
	133	{
	134	if (HAS_ATA) {
	135	u8 data;
	136	struct i2c_msg msg[2] = {
	137	{
	138	.addr = client->addr,
	139	.flags = I2C_M_RD,
	140	.len = 1,
	141	.buf = &data,
	142	},
	143	{
	144	.addr = client->addr,
	145	.flags = 0,
	146	.len = 1,
	147	.buf = &data,
	148	},
	149	};
	150
	151	/* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
	152	i2c_transfer(client->adapter, msg, 1);
	153	data &= ~(DM646X_EVM_ATA_RST \| DM646X_EVM_ATA_PWD);
	154	i2c_transfer(client->adapter, msg + 1, 1);
	155	}
	156
	157	return 0;
	158	}
	159
	160	static const struct i2c_device_id cpld_reg_ids[] = {
	161	{ "cpld_reg0", 0, },
	162	{ },
	163	};
	164
	165	static struct i2c_driver dm6467evm_cpld_driver = {
	166	.driver.name = "cpld_reg0",
	167	.id_table = cpld_reg_ids,
	168	.probe = cpld_reg0_probe,
	169	};
	170
e38d92fd KH	171	/* LEDS */
	172
	173	static struct gpio_led evm_leds[] = {
	174	{ .name = "DS1", .active_low = 1, },
	175	{ .name = "DS2", .active_low = 1, },
	176	{ .name = "DS3", .active_low = 1, },
	177	{ .name = "DS4", .active_low = 1, },
	178	};
	179
445094f9	180	static const struct gpio_led_platform_data evm_led_data = {
e38d92fd KH	181	.num_leds = ARRAY_SIZE(evm_leds),
	182	.leds = evm_leds,
	183	};
	184
	185	static struct platform_device *evm_led_dev;
	186
	187	static int evm_led_setup(struct i2c_client *client, int gpio,
	188	unsigned int ngpio, void *c)
	189	{
	190	struct gpio_led *leds = evm_leds;
	191	int status;
	192
	193	while (ngpio--) {
	194	leds->gpio = gpio++;
	195	leds++;
	196	};
	197
	198	evm_led_dev = platform_device_alloc("leds-gpio", 0);
	199	platform_device_add_data(evm_led_dev, &evm_led_data,
	200	sizeof(evm_led_data));
	201
	202	evm_led_dev->dev.parent = &client->dev;
	203	status = platform_device_add(evm_led_dev);
	204	if (status < 0) {
	205	platform_device_put(evm_led_dev);
	206	evm_led_dev = NULL;
	207	}
	208	return status;
	209	}
	210
	211	static int evm_led_teardown(struct i2c_client *client, int gpio,
	212	unsigned ngpio, void *c)
	213	{
	214	if (evm_led_dev) {
	215	platform_device_unregister(evm_led_dev);
	216	evm_led_dev = NULL;
	217	}
	218	return 0;
	219	}
	220
	221	static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
	222
	223	static int evm_sw_setup(struct i2c_client *client, int gpio,
	224	unsigned ngpio, void *c)
	225	{
	226	int status;
	227	int i;
	228	char label[10];
	229
	230	for (i = 0; i < 4; ++i) {
	231	snprintf(label, 10, "user_sw%d", i);
	232	status = gpio_request(gpio, label);
	233	if (status)
	234	goto out_free;
	235	evm_sw_gpio[i] = gpio++;
	236
	237	status = gpio_direction_input(evm_sw_gpio[i]);
	238	if (status) {
	239	gpio_free(evm_sw_gpio[i]);
	240	evm_sw_gpio[i] = -EINVAL;
	241	goto out_free;
	242	}
	243
	244	status = gpio_export(evm_sw_gpio[i], 0);
245	if (status) {
246	gpio_free(evm_sw_gpio[i]);
247	evm_sw_gpio[i] = -EINVAL;
248	goto out_free;
249	}
250	}
251	return status;
252	out_free:
253	for (i = 0; i < 4; ++i) {
254	if (evm_sw_gpio[i] != -EINVAL) {
255	gpio_free(evm_sw_gpio[i]);
256	evm_sw_gpio[i] = -EINVAL;
257	}
258	}
259	return status;
260	}
261
262	static int evm_sw_teardown(struct i2c_client *client, int gpio,
263	unsigned ngpio, void *c)
264	{
265	int i;
266
267	for (i = 0; i < 4; ++i) {
268	if (evm_sw_gpio[i] != -EINVAL) {
269	gpio_unexport(evm_sw_gpio[i]);
270	gpio_free(evm_sw_gpio[i]);
271	evm_sw_gpio[i] = -EINVAL;
272	}
273	}
274	return 0;
275	}
276
277	static int evm_pcf_setup(struct i2c_client *client, int gpio,
278	unsigned int ngpio, void *c)
279	{
280	int status;
281
282	if (ngpio < 8)
283	return -EINVAL;
284
285	status = evm_sw_setup(client, gpio, 4, c);
286	if (status)
287	return status;
288
289	return evm_led_setup(client, gpio+4, 4, c);
290	}
291
292	static int evm_pcf_teardown(struct i2c_client *client, int gpio,
293	unsigned int ngpio, void *c)
294	{
295	BUG_ON(ngpio < 8);
296
297	evm_sw_teardown(client, gpio, 4, c);
298	evm_led_teardown(client, gpio+4, 4, c);
299
300	return 0;
301	}
302
303	static struct pcf857x_platform_data pcf_data = {
304	.gpio_base = DAVINCI_N_GPIO+1,
305	.setup = evm_pcf_setup,
306	.teardown = evm_pcf_teardown,
307	};
308
309	/* Most of this EEPROM is unused, but U-Boot uses some data:
310	* - 0x7f00, 6 bytes Ethernet Address
311	* - ... newer boards may have more
312	*/
e38d92fd KH	313
	314	static struct at24_platform_data eeprom_info = {
	315	.byte_len = (256*1024) / 8,
	316	.page_size = 64,
	317	.flags = AT24_FLAG_ADDR16,
b14dc0f9 MG	318	.setup = davinci_get_mac_addr,
b14dc0f9 MG	319	.context = (void *)0x7f00,
e38d92fd KH	320	};
e38d92fd KH	321
25acf553 C	322	static u8 dm646x_iis_serializer_direction[] = {
	323	TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
	324	};
	325
	326	static u8 dm646x_dit_serializer_direction[] = {
	327	TX_MODE,
	328	};
	329
	330	static struct snd_platform_data dm646x_evm_snd_data[] = {
	331	{
25acf553 C	332	.tx_dma_offset = 0x400,
	333	.rx_dma_offset = 0x400,
	334	.op_mode = DAVINCI_MCASP_IIS_MODE,
	335	.num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
	336	.tdm_slots = 2,
	337	.serial_dir = dm646x_iis_serializer_direction,
48519f0a	338	.asp_chan_q = EVENTQ_0,
25acf553 C	339	},
25acf553 C	340	{
25acf553 C	341	.tx_dma_offset = 0x400,
	342	.rx_dma_offset = 0,
	343	.op_mode = DAVINCI_MCASP_DIT_MODE,
	344	.num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
	345	.tdm_slots = 32,
	346	.serial_dir = dm646x_dit_serializer_direction,
48519f0a	347	.asp_chan_q = EVENTQ_0,
25acf553 C	348	},
	349	};
	350
85609c1c MK	351	static struct i2c_client *cpld_client;
	352
	353	static int cpld_video_probe(struct i2c_client *client,
	354	const struct i2c_device_id *id)
	355	{
	356	cpld_client = client;
	357	return 0;
	358	}
	359
	360	static int __devexit cpld_video_remove(struct i2c_client *client)
	361	{
	362	cpld_client = NULL;
	363	return 0;
	364	}
	365
	366	static const struct i2c_device_id cpld_video_id[] = {
	367	{ "cpld_video", 0 },
	368	{ }
	369	};
	370
	371	static struct i2c_driver cpld_video_driver = {
	372	.driver = {
	373	.name = "cpld_video",
	374	},
	375	.probe = cpld_video_probe,
	376	.remove = cpld_video_remove,
	377	.id_table = cpld_video_id,
	378	};
	379
	380	static void evm_init_cpld(void)
	381	{
	382	i2c_add_driver(&cpld_video_driver);
	383	}
	384
e38d92fd KH	385	static struct i2c_board_info __initdata i2c_info[] = {
	386	{
	387	I2C_BOARD_INFO("24c256", 0x50),
	388	.platform_data = &eeprom_info,
	389	},
	390	{
	391	I2C_BOARD_INFO("pcf8574a", 0x38),
	392	.platform_data = &pcf_data,
	393	},
548197bd HP	394	{
	395	I2C_BOARD_INFO("cpld_reg0", 0x3a),
	396	},
1a7ff8ff C	397	{
1a7ff8ff C	398	I2C_BOARD_INFO("tlv320aic33", 0x18),
85609c1c MK	399	},
	400	{
	401	I2C_BOARD_INFO("cpld_video", 0x3b),
	402	},
77a92c71 NS	403	{
	404	I2C_BOARD_INFO("cdce949", 0x6c),
	405	},
e38d92fd KH	406	};
	407
	408	static struct davinci_i2c_platform_data i2c_pdata = {
	409	.bus_freq = 100 /* kHz */,
	410	.bus_delay = 0 /* usec */,
	411	};
	412
b73b526e SN	413	#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
	414	#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
	415	#define VCH2CLK_MASK (BIT_MASK(10) \| BIT_MASK(9) \| BIT_MASK(8))
	416	#define VCH2CLK_SYSCLK8 (BIT(9))
	417	#define VCH2CLK_AUXCLK (BIT(9) \| BIT(8))
	418	#define VCH3CLK_MASK (BIT_MASK(14) \| BIT_MASK(13) \| BIT_MASK(12))
	419	#define VCH3CLK_SYSCLK8 (BIT(13))
	420	#define VCH3CLK_AUXCLK (BIT(14) \| BIT(13))
	421
	422	#define VIDCH2CLK (BIT(10))
	423	#define VIDCH3CLK (BIT(11))
	424	#define VIDCH1CLK (BIT(4))
	425	#define TVP7002_INPUT (BIT(4))
	426	#define TVP5147_INPUT (~BIT(4))
	427	#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
	428	#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
	429	#define TVP5147_CH0 "tvp514x-0"
	430	#define TVP5147_CH1 "tvp514x-1"
	431
	432	static void __iomem *vpif_vidclkctl_reg;
	433	static void __iomem *vpif_vsclkdis_reg;
	434	/* spin lock for updating above registers */
	435	static spinlock_t vpif_reg_lock;
	436
85609c1c MK	437	static int set_vpif_clock(int mux_mode, int hd)
	438	{
	439	unsigned long flags;
	440	unsigned int value;
	441	int val = 0;
	442	int err = 0;
	443
	444	if (!vpif_vidclkctl_reg \|\| !vpif_vsclkdis_reg \|\| !cpld_client)
	445	return -ENXIO;
	446
	447	/* disable the clock */
	448	spin_lock_irqsave(&vpif_reg_lock, flags);
	449	value = __raw_readl(vpif_vsclkdis_reg);
	450	value \|= (VIDCH3CLK \| VIDCH2CLK);
	451	__raw_writel(value, vpif_vsclkdis_reg);
	452	spin_unlock_irqrestore(&vpif_reg_lock, flags);
	453
	454	val = i2c_smbus_read_byte(cpld_client);
	455	if (val < 0)
	456	return val;
	457
	458	if (mux_mode == 1)
	459	val &= ~0x40;
	460	else
	461	val \|= 0x40;
	462
	463	err = i2c_smbus_write_byte(cpld_client, val);
	464	if (err)
	465	return err;
	466
	467	value = __raw_readl(vpif_vidclkctl_reg);
	468	value &= ~(VCH2CLK_MASK);
	469	value &= ~(VCH3CLK_MASK);
	470
	471	if (hd >= 1)
	472	value \|= (VCH2CLK_SYSCLK8 \| VCH3CLK_SYSCLK8);
	473	else
	474	value \|= (VCH2CLK_AUXCLK \| VCH3CLK_AUXCLK);
	475
	476	__raw_writel(value, vpif_vidclkctl_reg);
	477
	478	spin_lock_irqsave(&vpif_reg_lock, flags);
	479	value = __raw_readl(vpif_vsclkdis_reg);
	480	/* enable the clock */
	481	value &= ~(VIDCH3CLK \| VIDCH2CLK);
	482	__raw_writel(value, vpif_vsclkdis_reg);
	483	spin_unlock_irqrestore(&vpif_reg_lock, flags);
	484
	485	return 0;
	486	}
	487
	488	static struct vpif_subdev_info dm646x_vpif_subdev[] = {
	489	{
	490	.name = "adv7343",
	491	.board_info = {
	492	I2C_BOARD_INFO("adv7343", 0x2a),
	493	},
	494	},
	495	{
	496	.name = "ths7303",
	497	.board_info = {
	498	I2C_BOARD_INFO("ths7303", 0x2c),
	499	},
	500	},
501	};
502
503	static const char *output[] = {
504	"Composite",
505	"Component",
506	"S-Video",
507	};
508
509	static struct vpif_display_config dm646x_vpif_display_config = {
510	.set_clock = set_vpif_clock,
511	.subdevinfo = dm646x_vpif_subdev,
512	.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
513	.output = output,
514	.output_count = ARRAY_SIZE(output),
515	.card_name = "DM646x EVM",
516	};
517
518	/**
519	* setup_vpif_input_path()
520	* @channel: channel id (0 - CH0, 1 - CH1)
521	* @sub_dev_name: ptr sub device name
522	*
523	* This will set vpif input to capture data from tvp514x or
524	* tvp7002.
525	*/
526	static int setup_vpif_input_path(int channel, const char *sub_dev_name)
527	{
528	int err = 0;
529	int val;
530
531	/* for channel 1, we don't do anything */
532	if (channel != 0)
533	return 0;
534
535	if (!cpld_client)
536	return -ENXIO;
537
538	val = i2c_smbus_read_byte(cpld_client);
539	if (val < 0)
540	return val;
541
542	if (!strcmp(sub_dev_name, TVP5147_CH0) \|\|
543	!strcmp(sub_dev_name, TVP5147_CH1))
544	val &= TVP5147_INPUT;
545	else
546	val \|= TVP7002_INPUT;
547
548	err = i2c_smbus_write_byte(cpld_client, val);
549	if (err)
550	return err;
551	return 0;
552	}
553
554	/**
555	* setup_vpif_input_channel_mode()
556	* @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
557	*
558	* This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
559	*/
560	static int setup_vpif_input_channel_mode(int mux_mode)
561	{
562	unsigned long flags;
563	int err = 0;
564	int val;
565	u32 value;
566
83713fc9	567	if (!vpif_vidclkctl_reg \|\| !cpld_client)
85609c1c MK	568	return -ENXIO;
	569
	570	val = i2c_smbus_read_byte(cpld_client);
	571	if (val < 0)
	572	return val;
	573
	574	spin_lock_irqsave(&vpif_reg_lock, flags);
83713fc9	575	value = __raw_readl(vpif_vidclkctl_reg);
85609c1c MK	576	if (mux_mode) {
	577	val &= VPIF_INPUT_TWO_CHANNEL;
	578	value \|= VIDCH1CLK;
	579	} else {
	580	val \|= VPIF_INPUT_ONE_CHANNEL;
	581	value &= ~VIDCH1CLK;
	582	}
83713fc9	583	__raw_writel(value, vpif_vidclkctl_reg);
85609c1c MK	584	spin_unlock_irqrestore(&vpif_reg_lock, flags);
	585
	586	err = i2c_smbus_write_byte(cpld_client, val);
	587	if (err)
	588	return err;
	589
	590	return 0;
	591	}
	592
	593	static struct tvp514x_platform_data tvp5146_pdata = {
	594	.clk_polarity = 0,
	595	.hs_polarity = 1,
	596	.vs_polarity = 1
	597	};
	598
	599	#define TVP514X_STD_ALL (V4L2_STD_NTSC \| V4L2_STD_PAL)
	600
	601	static struct vpif_subdev_info vpif_capture_sdev_info[] = {
	602	{
	603	.name = TVP5147_CH0,
	604	.board_info = {
	605	I2C_BOARD_INFO("tvp5146", 0x5d),
	606	.platform_data = &tvp5146_pdata,
	607	},
	608	.input = INPUT_CVBS_VI2B,
	609	.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	610	.can_route = 1,
	611	.vpif_if = {
	612	.if_type = VPIF_IF_BT656,
	613	.hd_pol = 1,
	614	.vd_pol = 1,
	615	.fid_pol = 0,
	616	},
	617	},
	618	{
	619	.name = TVP5147_CH1,
	620	.board_info = {
	621	I2C_BOARD_INFO("tvp5146", 0x5c),
	622	.platform_data = &tvp5146_pdata,
	623	},
	624	.input = INPUT_SVIDEO_VI2C_VI1C,
	625	.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	626	.can_route = 1,
	627	.vpif_if = {
	628	.if_type = VPIF_IF_BT656,
	629	.hd_pol = 1,
	630	.vd_pol = 1,
	631	.fid_pol = 0,
	632	},
	633	},
	634	};
	635
	636	static const struct vpif_input dm6467_ch0_inputs[] = {
	637	{
	638	.input = {
	639	.index = 0,
	640	.name = "Composite",
	641	.type = V4L2_INPUT_TYPE_CAMERA,
	642	.std = TVP514X_STD_ALL,
	643	},
	644	.subdev_name = TVP5147_CH0,
	645	},
	646	};
	647
648	static const struct vpif_input dm6467_ch1_inputs[] = {
649	{
650	.input = {
651	.index = 0,
652	.name = "S-Video",
653	.type = V4L2_INPUT_TYPE_CAMERA,
654	.std = TVP514X_STD_ALL,
655	},
656	.subdev_name = TVP5147_CH1,
657	},
658	};
659
660	static struct vpif_capture_config dm646x_vpif_capture_cfg = {
661	.setup_input_path = setup_vpif_input_path,
662	.setup_input_channel_mode = setup_vpif_input_channel_mode,
663	.subdev_info = vpif_capture_sdev_info,
664	.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
665	.chan_config[0] = {
666	.inputs = dm6467_ch0_inputs,
667	.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
668	},
669	.chan_config[1] = {
670	.inputs = dm6467_ch1_inputs,
671	.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
672	},
673	};
674
675	static void __init evm_init_video(void)
676	{
677	vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
678	vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
679	if (!vpif_vidclkctl_reg \|\| !vpif_vsclkdis_reg) {
680	pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
681	return;
682	}
683	spin_lock_init(&vpif_reg_lock);
684
685	dm646x_setup_vpif(&dm646x_vpif_display_config,
686	&dm646x_vpif_capture_cfg);
687	}
688
e38d92fd KH	689	static void __init evm_init_i2c(void)
	690	{
	691	davinci_init_i2c(&i2c_pdata);
548197bd	692	i2c_add_driver(&dm6467evm_cpld_driver);
e38d92fd	693	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
85609c1c MK	694	evm_init_cpld();
85609c1c MK	695	evm_init_video();
e38d92fd KH	696	}
e38d92fd KH	697
77a92c71 NS	698	#define CDCE949_XIN_RATE 27000000
	699
	700	/* CDCE949 support - "lpsc" field is overridden to work as clock number */
	701	static struct clk cdce_clk_in = {
	702	.name = "cdce_xin",
	703	.rate = CDCE949_XIN_RATE,
	704	};
	705
c564191b	706	static struct clk_lookup cdce_clks[] = {
77a92c71 NS	707	CLK(NULL, "xin", &cdce_clk_in),
	708	CLK(NULL, NULL, NULL),
	709	};
	710
	711	static void __init cdce_clk_init(void)
	712	{
c564191b	713	struct clk_lookup *c;
77a92c71 NS	714	struct clk *clk;
77a92c71 NS	715
c564191b KH	716	for (c = cdce_clks; c->clk; c++) {
	717	clk = c->clk;
	718	clkdev_add(c);
77a92c71 NS	719	clk_register(clk);
	720	}
	721	}
	722
56e580d7 SN	723	#define DM6467T_EVM_REF_FREQ 33000000
56e580d7 SN	724
e38d92fd KH	725	static void __init davinci_map_io(void)
e38d92fd KH	726	{
e38d92fd	727	dm646x_init();
56e580d7 SN	728
	729	if (machine_is_davinci_dm6467tevm())
	730	davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
	731
77a92c71	732	cdce_clk_init();
e38d92fd KH	733	}
e38d92fd KH	734
b73b526e SN	735	static struct davinci_uart_config uart_config __initdata = {
	736	.enabled_uarts = (1 << 0),
	737	};
	738
782f2d78	739	#define DM646X_EVM_PHY_ID "0:01"
cce3dddb RS	740	/*
	741	* The following EDMA channels/slots are not being used by drivers (for
	742	* example: Timer, GPIO, UART events etc) on dm646x, hence they are being
	743	* reserved for codecs on the DSP side.
	744	*/
	745	static const s16 dm646x_dma_rsv_chans[][2] = {
	746	/* (offset, number) */
	747	{ 0, 4},
	748	{13, 3},
	749	{24, 4},
	750	{30, 2},
	751	{54, 3},
	752	{-1, -1}
	753	};
	754
	755	static const s16 dm646x_dma_rsv_slots[][2] = {
	756	/* (offset, number) */
	757	{ 0, 4},
	758	{13, 3},
	759	{24, 4},
	760	{30, 2},
	761	{54, 3},
	762	{128, 384},
	763	{-1, -1}
	764	};
	765
	766	static struct edma_rsv_info dm646x_edma_rsv[] = {
	767	{
	768	.rsv_chans = dm646x_dma_rsv_chans,
	769	.rsv_slots = dm646x_dma_rsv_slots,
	770	},
	771	};
	772
e38d92fd KH	773	static __init void evm_init(void)
e38d92fd KH	774	{
972412b6 MG	775	struct davinci_soc_info *soc_info = &davinci_soc_info;
972412b6 MG	776
e38d92fd KH	777	evm_init_i2c();
e38d92fd KH	778	davinci_serial_init(&uart_config);
25acf553 C	779	dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
25acf553 C	780	dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
972412b6	781
0b3fc7bb SN	782	if (machine_is_davinci_dm6467tevm())
	783	davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
	784
50fbabfe HP	785	platform_device_register(&davinci_nand_device);
50fbabfe HP	786
cce3dddb RS	787	dm646x_init_edma(dm646x_edma_rsv);
cce3dddb RS	788
548197bd	789	if (HAS_ATA)
7a9978a1	790	davinci_init_ide();
548197bd	791
782f2d78	792	soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
e38d92fd KH	793	}
e38d92fd KH	794
e38d92fd	795	MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
e7e56014	796	.atag_offset = 0x100,
e38d92fd	797	.map_io = davinci_map_io,
bd808947	798	.init_irq = davinci_irq_init,
e38d92fd KH	799	.timer = &davinci_timer,
e38d92fd KH	800	.init_machine = evm_init,
f68deabf	801	.dma_zone_size = SZ_128M,
c6121ddd	802	.restart = davinci_restart,
e38d92fd KH	803	MACHINE_END
e38d92fd KH	804
c1978e1d	805	MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
e7e56014	806	.atag_offset = 0x100,
c1978e1d	807	.map_io = davinci_map_io,
bd808947	808	.init_irq = davinci_irq_init,
c1978e1d SN	809	.timer = &davinci_timer,
c1978e1d SN	810	.init_machine = evm_init,
f68deabf	811	.dma_zone_size = SZ_128M,
c6121ddd	812	.restart = davinci_restart,
c1978e1d SN	813	MACHINE_END
c1978e1d SN	814