Commit | Line | Data |
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e38d92fd KH |
1 | /* |
2 | * TI DaVinci DM646X EVM board | |
3 | * | |
4 | * Derived from: arch/arm/mach-davinci/board-evm.c | |
5 | * Copyright (C) 2006 Texas Instruments. | |
6 | * | |
7 | * (C) 2007-2008, MontaVista Software, Inc. | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public License | |
10 | * version 2. This program is licensed "as is" without any warranty of any | |
11 | * kind, whether express or implied. | |
12 | * | |
13 | */ | |
14 | ||
15 | /************************************************************************** | |
16 | * Included Files | |
17 | **************************************************************************/ | |
18 | ||
19 | #include <linux/kernel.h> | |
e38d92fd | 20 | #include <linux/init.h> |
e38d92fd KH |
21 | #include <linux/leds.h> |
22 | #include <linux/gpio.h> | |
e38d92fd KH |
23 | #include <linux/platform_device.h> |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c/at24.h> | |
26 | #include <linux/i2c/pcf857x.h> | |
e38d92fd | 27 | |
85609c1c MK |
28 | #include <media/tvp514x.h> |
29 | ||
50fbabfe HP |
30 | #include <linux/mtd/mtd.h> |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/partitions.h> | |
c1978e1d | 33 | #include <linux/clk.h> |
dc28094b | 34 | #include <linux/export.h> |
50fbabfe | 35 | |
e38d92fd KH |
36 | #include <asm/mach-types.h> |
37 | #include <asm/mach/arch.h> | |
e38d92fd | 38 | |
e38d92fd | 39 | #include <mach/common.h> |
e38d92fd KH |
40 | #include <mach/serial.h> |
41 | #include <mach/i2c.h> | |
50fbabfe | 42 | #include <mach/nand.h> |
77a92c71 NS |
43 | #include <mach/clock.h> |
44 | #include <mach/cdce949.h> | |
0b3fc7bb | 45 | #include <mach/aemif.h> |
ac7b75b5 | 46 | |
39c6d2d1 | 47 | #include "davinci.h" |
c1978e1d SN |
48 | #include "clock.h" |
49 | ||
50fbabfe HP |
50 | #define NAND_BLOCK_SIZE SZ_128K |
51 | ||
50fbabfe HP |
52 | /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot |
53 | * and U-Boot environment this avoids dependency on any particular combination | |
54 | * of UBL, U-Boot or flashing tools etc. | |
55 | */ | |
56 | static struct mtd_partition davinci_nand_partitions[] = { | |
57 | { | |
58 | /* UBL, U-Boot with environment */ | |
59 | .name = "bootloader", | |
60 | .offset = MTDPART_OFS_APPEND, | |
61 | .size = 16 * NAND_BLOCK_SIZE, | |
62 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
63 | }, { | |
64 | .name = "kernel", | |
65 | .offset = MTDPART_OFS_APPEND, | |
66 | .size = SZ_4M, | |
67 | .mask_flags = 0, | |
68 | }, { | |
69 | .name = "filesystem", | |
70 | .offset = MTDPART_OFS_APPEND, | |
71 | .size = MTDPART_SIZ_FULL, | |
72 | .mask_flags = 0, | |
73 | } | |
74 | }; | |
75 | ||
0b3fc7bb SN |
76 | static struct davinci_aemif_timing dm6467tevm_nandflash_timing = { |
77 | .wsetup = 29, | |
78 | .wstrobe = 24, | |
79 | .whold = 14, | |
80 | .rsetup = 19, | |
81 | .rstrobe = 33, | |
82 | .rhold = 0, | |
83 | .ta = 29, | |
84 | }; | |
85 | ||
50fbabfe HP |
86 | static struct davinci_nand_pdata davinci_nand_data = { |
87 | .mask_cle = 0x80000, | |
88 | .mask_ale = 0x40000, | |
89 | .parts = davinci_nand_partitions, | |
90 | .nr_parts = ARRAY_SIZE(davinci_nand_partitions), | |
91 | .ecc_mode = NAND_ECC_HW, | |
92 | .options = 0, | |
93 | }; | |
94 | ||
95 | static struct resource davinci_nand_resources[] = { | |
96 | { | |
70342174 SS |
97 | .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE, |
98 | .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1, | |
50fbabfe HP |
99 | .flags = IORESOURCE_MEM, |
100 | }, { | |
70342174 SS |
101 | .start = DM646X_ASYNC_EMIF_CONTROL_BASE, |
102 | .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, | |
50fbabfe HP |
103 | .flags = IORESOURCE_MEM, |
104 | }, | |
105 | }; | |
106 | ||
107 | static struct platform_device davinci_nand_device = { | |
108 | .name = "davinci_nand", | |
109 | .id = 0, | |
110 | ||
111 | .num_resources = ARRAY_SIZE(davinci_nand_resources), | |
112 | .resource = davinci_nand_resources, | |
113 | ||
114 | .dev = { | |
115 | .platform_data = &davinci_nand_data, | |
116 | }, | |
117 | }; | |
118 | ||
b73b526e SN |
119 | #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ |
120 | defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) | |
121 | #define HAS_ATA 1 | |
122 | #else | |
123 | #define HAS_ATA 0 | |
124 | #endif | |
125 | ||
126 | /* CPLD Register 0 bits to control ATA */ | |
127 | #define DM646X_EVM_ATA_RST BIT(0) | |
128 | #define DM646X_EVM_ATA_PWD BIT(1) | |
129 | ||
548197bd HP |
130 | /* CPLD Register 0 Client: used for I/O Control */ |
131 | static int cpld_reg0_probe(struct i2c_client *client, | |
132 | const struct i2c_device_id *id) | |
133 | { | |
134 | if (HAS_ATA) { | |
135 | u8 data; | |
136 | struct i2c_msg msg[2] = { | |
137 | { | |
138 | .addr = client->addr, | |
139 | .flags = I2C_M_RD, | |
140 | .len = 1, | |
141 | .buf = &data, | |
142 | }, | |
143 | { | |
144 | .addr = client->addr, | |
145 | .flags = 0, | |
146 | .len = 1, | |
147 | .buf = &data, | |
148 | }, | |
149 | }; | |
150 | ||
151 | /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */ | |
152 | i2c_transfer(client->adapter, msg, 1); | |
153 | data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD); | |
154 | i2c_transfer(client->adapter, msg + 1, 1); | |
155 | } | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static const struct i2c_device_id cpld_reg_ids[] = { | |
161 | { "cpld_reg0", 0, }, | |
162 | { }, | |
163 | }; | |
164 | ||
165 | static struct i2c_driver dm6467evm_cpld_driver = { | |
166 | .driver.name = "cpld_reg0", | |
167 | .id_table = cpld_reg_ids, | |
168 | .probe = cpld_reg0_probe, | |
169 | }; | |
170 | ||
e38d92fd KH |
171 | /* LEDS */ |
172 | ||
173 | static struct gpio_led evm_leds[] = { | |
174 | { .name = "DS1", .active_low = 1, }, | |
175 | { .name = "DS2", .active_low = 1, }, | |
176 | { .name = "DS3", .active_low = 1, }, | |
177 | { .name = "DS4", .active_low = 1, }, | |
178 | }; | |
179 | ||
445094f9 | 180 | static const struct gpio_led_platform_data evm_led_data = { |
e38d92fd KH |
181 | .num_leds = ARRAY_SIZE(evm_leds), |
182 | .leds = evm_leds, | |
183 | }; | |
184 | ||
185 | static struct platform_device *evm_led_dev; | |
186 | ||
187 | static int evm_led_setup(struct i2c_client *client, int gpio, | |
188 | unsigned int ngpio, void *c) | |
189 | { | |
190 | struct gpio_led *leds = evm_leds; | |
191 | int status; | |
192 | ||
193 | while (ngpio--) { | |
194 | leds->gpio = gpio++; | |
195 | leds++; | |
196 | }; | |
197 | ||
198 | evm_led_dev = platform_device_alloc("leds-gpio", 0); | |
199 | platform_device_add_data(evm_led_dev, &evm_led_data, | |
200 | sizeof(evm_led_data)); | |
201 | ||
202 | evm_led_dev->dev.parent = &client->dev; | |
203 | status = platform_device_add(evm_led_dev); | |
204 | if (status < 0) { | |
205 | platform_device_put(evm_led_dev); | |
206 | evm_led_dev = NULL; | |
207 | } | |
208 | return status; | |
209 | } | |
210 | ||
211 | static int evm_led_teardown(struct i2c_client *client, int gpio, | |
212 | unsigned ngpio, void *c) | |
213 | { | |
214 | if (evm_led_dev) { | |
215 | platform_device_unregister(evm_led_dev); | |
216 | evm_led_dev = NULL; | |
217 | } | |
218 | return 0; | |
219 | } | |
220 | ||
221 | static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL }; | |
222 | ||
223 | static int evm_sw_setup(struct i2c_client *client, int gpio, | |
224 | unsigned ngpio, void *c) | |
225 | { | |
226 | int status; | |
227 | int i; | |
228 | char label[10]; | |
229 | ||
230 | for (i = 0; i < 4; ++i) { | |
231 | snprintf(label, 10, "user_sw%d", i); | |
232 | status = gpio_request(gpio, label); | |
233 | if (status) | |
234 | goto out_free; | |
235 | evm_sw_gpio[i] = gpio++; | |
236 | ||
237 | status = gpio_direction_input(evm_sw_gpio[i]); | |
238 | if (status) { | |
239 | gpio_free(evm_sw_gpio[i]); | |
240 | evm_sw_gpio[i] = -EINVAL; | |
241 | goto out_free; | |
242 | } | |
243 | ||
244 | status = gpio_export(evm_sw_gpio[i], 0); | |
245 | if (status) { | |
246 | gpio_free(evm_sw_gpio[i]); | |
247 | evm_sw_gpio[i] = -EINVAL; | |
248 | goto out_free; | |
249 | } | |
250 | } | |
251 | return status; | |
252 | out_free: | |
253 | for (i = 0; i < 4; ++i) { | |
254 | if (evm_sw_gpio[i] != -EINVAL) { | |
255 | gpio_free(evm_sw_gpio[i]); | |
256 | evm_sw_gpio[i] = -EINVAL; | |
257 | } | |
258 | } | |
259 | return status; | |
260 | } | |
261 | ||
262 | static int evm_sw_teardown(struct i2c_client *client, int gpio, | |
263 | unsigned ngpio, void *c) | |
264 | { | |
265 | int i; | |
266 | ||
267 | for (i = 0; i < 4; ++i) { | |
268 | if (evm_sw_gpio[i] != -EINVAL) { | |
269 | gpio_unexport(evm_sw_gpio[i]); | |
270 | gpio_free(evm_sw_gpio[i]); | |
271 | evm_sw_gpio[i] = -EINVAL; | |
272 | } | |
273 | } | |
274 | return 0; | |
275 | } | |
276 | ||
277 | static int evm_pcf_setup(struct i2c_client *client, int gpio, | |
278 | unsigned int ngpio, void *c) | |
279 | { | |
280 | int status; | |
281 | ||
282 | if (ngpio < 8) | |
283 | return -EINVAL; | |
284 | ||
285 | status = evm_sw_setup(client, gpio, 4, c); | |
286 | if (status) | |
287 | return status; | |
288 | ||
289 | return evm_led_setup(client, gpio+4, 4, c); | |
290 | } | |
291 | ||
292 | static int evm_pcf_teardown(struct i2c_client *client, int gpio, | |
293 | unsigned int ngpio, void *c) | |
294 | { | |
295 | BUG_ON(ngpio < 8); | |
296 | ||
297 | evm_sw_teardown(client, gpio, 4, c); | |
298 | evm_led_teardown(client, gpio+4, 4, c); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static struct pcf857x_platform_data pcf_data = { | |
304 | .gpio_base = DAVINCI_N_GPIO+1, | |
305 | .setup = evm_pcf_setup, | |
306 | .teardown = evm_pcf_teardown, | |
307 | }; | |
308 | ||
309 | /* Most of this EEPROM is unused, but U-Boot uses some data: | |
310 | * - 0x7f00, 6 bytes Ethernet Address | |
311 | * - ... newer boards may have more | |
312 | */ | |
e38d92fd KH |
313 | |
314 | static struct at24_platform_data eeprom_info = { | |
315 | .byte_len = (256*1024) / 8, | |
316 | .page_size = 64, | |
317 | .flags = AT24_FLAG_ADDR16, | |
b14dc0f9 MG |
318 | .setup = davinci_get_mac_addr, |
319 | .context = (void *)0x7f00, | |
e38d92fd KH |
320 | }; |
321 | ||
25acf553 C |
322 | static u8 dm646x_iis_serializer_direction[] = { |
323 | TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, | |
324 | }; | |
325 | ||
326 | static u8 dm646x_dit_serializer_direction[] = { | |
327 | TX_MODE, | |
328 | }; | |
329 | ||
330 | static struct snd_platform_data dm646x_evm_snd_data[] = { | |
331 | { | |
25acf553 C |
332 | .tx_dma_offset = 0x400, |
333 | .rx_dma_offset = 0x400, | |
334 | .op_mode = DAVINCI_MCASP_IIS_MODE, | |
335 | .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), | |
336 | .tdm_slots = 2, | |
337 | .serial_dir = dm646x_iis_serializer_direction, | |
48519f0a | 338 | .asp_chan_q = EVENTQ_0, |
25acf553 C |
339 | }, |
340 | { | |
25acf553 C |
341 | .tx_dma_offset = 0x400, |
342 | .rx_dma_offset = 0, | |
343 | .op_mode = DAVINCI_MCASP_DIT_MODE, | |
344 | .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), | |
345 | .tdm_slots = 32, | |
346 | .serial_dir = dm646x_dit_serializer_direction, | |
48519f0a | 347 | .asp_chan_q = EVENTQ_0, |
25acf553 C |
348 | }, |
349 | }; | |
350 | ||
85609c1c MK |
351 | static struct i2c_client *cpld_client; |
352 | ||
353 | static int cpld_video_probe(struct i2c_client *client, | |
354 | const struct i2c_device_id *id) | |
355 | { | |
356 | cpld_client = client; | |
357 | return 0; | |
358 | } | |
359 | ||
360 | static int __devexit cpld_video_remove(struct i2c_client *client) | |
361 | { | |
362 | cpld_client = NULL; | |
363 | return 0; | |
364 | } | |
365 | ||
366 | static const struct i2c_device_id cpld_video_id[] = { | |
367 | { "cpld_video", 0 }, | |
368 | { } | |
369 | }; | |
370 | ||
371 | static struct i2c_driver cpld_video_driver = { | |
372 | .driver = { | |
373 | .name = "cpld_video", | |
374 | }, | |
375 | .probe = cpld_video_probe, | |
376 | .remove = cpld_video_remove, | |
377 | .id_table = cpld_video_id, | |
378 | }; | |
379 | ||
380 | static void evm_init_cpld(void) | |
381 | { | |
382 | i2c_add_driver(&cpld_video_driver); | |
383 | } | |
384 | ||
e38d92fd KH |
385 | static struct i2c_board_info __initdata i2c_info[] = { |
386 | { | |
387 | I2C_BOARD_INFO("24c256", 0x50), | |
388 | .platform_data = &eeprom_info, | |
389 | }, | |
390 | { | |
391 | I2C_BOARD_INFO("pcf8574a", 0x38), | |
392 | .platform_data = &pcf_data, | |
393 | }, | |
548197bd HP |
394 | { |
395 | I2C_BOARD_INFO("cpld_reg0", 0x3a), | |
396 | }, | |
1a7ff8ff C |
397 | { |
398 | I2C_BOARD_INFO("tlv320aic33", 0x18), | |
85609c1c MK |
399 | }, |
400 | { | |
401 | I2C_BOARD_INFO("cpld_video", 0x3b), | |
402 | }, | |
77a92c71 NS |
403 | { |
404 | I2C_BOARD_INFO("cdce949", 0x6c), | |
405 | }, | |
e38d92fd KH |
406 | }; |
407 | ||
408 | static struct davinci_i2c_platform_data i2c_pdata = { | |
409 | .bus_freq = 100 /* kHz */, | |
410 | .bus_delay = 0 /* usec */, | |
411 | }; | |
412 | ||
b73b526e SN |
413 | #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) |
414 | #define VCH2CLK_SYSCLK8 (BIT(9)) | |
415 | #define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) | |
416 | #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12)) | |
417 | #define VCH3CLK_SYSCLK8 (BIT(13)) | |
418 | #define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) | |
419 | ||
420 | #define VIDCH2CLK (BIT(10)) | |
421 | #define VIDCH3CLK (BIT(11)) | |
422 | #define VIDCH1CLK (BIT(4)) | |
423 | #define TVP7002_INPUT (BIT(4)) | |
424 | #define TVP5147_INPUT (~BIT(4)) | |
425 | #define VPIF_INPUT_ONE_CHANNEL (BIT(5)) | |
426 | #define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) | |
427 | #define TVP5147_CH0 "tvp514x-0" | |
428 | #define TVP5147_CH1 "tvp514x-1" | |
429 | ||
b73b526e SN |
430 | /* spin lock for updating above registers */ |
431 | static spinlock_t vpif_reg_lock; | |
432 | ||
85609c1c MK |
433 | static int set_vpif_clock(int mux_mode, int hd) |
434 | { | |
435 | unsigned long flags; | |
436 | unsigned int value; | |
437 | int val = 0; | |
438 | int err = 0; | |
439 | ||
5cfb19ac | 440 | if (!cpld_client) |
85609c1c MK |
441 | return -ENXIO; |
442 | ||
443 | /* disable the clock */ | |
444 | spin_lock_irqsave(&vpif_reg_lock, flags); | |
5cfb19ac | 445 | value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); |
85609c1c | 446 | value |= (VIDCH3CLK | VIDCH2CLK); |
5cfb19ac | 447 | __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); |
85609c1c MK |
448 | spin_unlock_irqrestore(&vpif_reg_lock, flags); |
449 | ||
450 | val = i2c_smbus_read_byte(cpld_client); | |
451 | if (val < 0) | |
452 | return val; | |
453 | ||
454 | if (mux_mode == 1) | |
455 | val &= ~0x40; | |
456 | else | |
457 | val |= 0x40; | |
458 | ||
459 | err = i2c_smbus_write_byte(cpld_client, val); | |
460 | if (err) | |
461 | return err; | |
462 | ||
5cfb19ac | 463 | value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); |
85609c1c MK |
464 | value &= ~(VCH2CLK_MASK); |
465 | value &= ~(VCH3CLK_MASK); | |
466 | ||
467 | if (hd >= 1) | |
468 | value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8); | |
469 | else | |
470 | value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); | |
471 | ||
5cfb19ac | 472 | __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); |
85609c1c MK |
473 | |
474 | spin_lock_irqsave(&vpif_reg_lock, flags); | |
5cfb19ac | 475 | value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); |
85609c1c MK |
476 | /* enable the clock */ |
477 | value &= ~(VIDCH3CLK | VIDCH2CLK); | |
5cfb19ac | 478 | __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); |
85609c1c MK |
479 | spin_unlock_irqrestore(&vpif_reg_lock, flags); |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static struct vpif_subdev_info dm646x_vpif_subdev[] = { | |
485 | { | |
486 | .name = "adv7343", | |
487 | .board_info = { | |
488 | I2C_BOARD_INFO("adv7343", 0x2a), | |
489 | }, | |
490 | }, | |
491 | { | |
492 | .name = "ths7303", | |
493 | .board_info = { | |
494 | I2C_BOARD_INFO("ths7303", 0x2c), | |
495 | }, | |
496 | }, | |
497 | }; | |
498 | ||
499 | static const char *output[] = { | |
500 | "Composite", | |
501 | "Component", | |
502 | "S-Video", | |
503 | }; | |
504 | ||
505 | static struct vpif_display_config dm646x_vpif_display_config = { | |
506 | .set_clock = set_vpif_clock, | |
507 | .subdevinfo = dm646x_vpif_subdev, | |
508 | .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), | |
509 | .output = output, | |
510 | .output_count = ARRAY_SIZE(output), | |
511 | .card_name = "DM646x EVM", | |
512 | }; | |
513 | ||
514 | /** | |
515 | * setup_vpif_input_path() | |
516 | * @channel: channel id (0 - CH0, 1 - CH1) | |
517 | * @sub_dev_name: ptr sub device name | |
518 | * | |
519 | * This will set vpif input to capture data from tvp514x or | |
520 | * tvp7002. | |
521 | */ | |
522 | static int setup_vpif_input_path(int channel, const char *sub_dev_name) | |
523 | { | |
524 | int err = 0; | |
525 | int val; | |
526 | ||
527 | /* for channel 1, we don't do anything */ | |
528 | if (channel != 0) | |
529 | return 0; | |
530 | ||
531 | if (!cpld_client) | |
532 | return -ENXIO; | |
533 | ||
534 | val = i2c_smbus_read_byte(cpld_client); | |
535 | if (val < 0) | |
536 | return val; | |
537 | ||
538 | if (!strcmp(sub_dev_name, TVP5147_CH0) || | |
539 | !strcmp(sub_dev_name, TVP5147_CH1)) | |
540 | val &= TVP5147_INPUT; | |
541 | else | |
542 | val |= TVP7002_INPUT; | |
543 | ||
544 | err = i2c_smbus_write_byte(cpld_client, val); | |
545 | if (err) | |
546 | return err; | |
547 | return 0; | |
548 | } | |
549 | ||
550 | /** | |
551 | * setup_vpif_input_channel_mode() | |
552 | * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel | |
553 | * | |
554 | * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147) | |
555 | */ | |
556 | static int setup_vpif_input_channel_mode(int mux_mode) | |
557 | { | |
558 | unsigned long flags; | |
559 | int err = 0; | |
560 | int val; | |
561 | u32 value; | |
562 | ||
5cfb19ac | 563 | if (!cpld_client) |
85609c1c MK |
564 | return -ENXIO; |
565 | ||
566 | val = i2c_smbus_read_byte(cpld_client); | |
567 | if (val < 0) | |
568 | return val; | |
569 | ||
570 | spin_lock_irqsave(&vpif_reg_lock, flags); | |
5cfb19ac | 571 | value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); |
85609c1c MK |
572 | if (mux_mode) { |
573 | val &= VPIF_INPUT_TWO_CHANNEL; | |
574 | value |= VIDCH1CLK; | |
575 | } else { | |
576 | val |= VPIF_INPUT_ONE_CHANNEL; | |
577 | value &= ~VIDCH1CLK; | |
578 | } | |
5cfb19ac | 579 | __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); |
85609c1c MK |
580 | spin_unlock_irqrestore(&vpif_reg_lock, flags); |
581 | ||
582 | err = i2c_smbus_write_byte(cpld_client, val); | |
583 | if (err) | |
584 | return err; | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | static struct tvp514x_platform_data tvp5146_pdata = { | |
590 | .clk_polarity = 0, | |
591 | .hs_polarity = 1, | |
592 | .vs_polarity = 1 | |
593 | }; | |
594 | ||
595 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) | |
596 | ||
597 | static struct vpif_subdev_info vpif_capture_sdev_info[] = { | |
598 | { | |
599 | .name = TVP5147_CH0, | |
600 | .board_info = { | |
601 | I2C_BOARD_INFO("tvp5146", 0x5d), | |
602 | .platform_data = &tvp5146_pdata, | |
603 | }, | |
604 | .input = INPUT_CVBS_VI2B, | |
605 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | |
85609c1c MK |
606 | .vpif_if = { |
607 | .if_type = VPIF_IF_BT656, | |
608 | .hd_pol = 1, | |
609 | .vd_pol = 1, | |
610 | .fid_pol = 0, | |
611 | }, | |
612 | }, | |
613 | { | |
614 | .name = TVP5147_CH1, | |
615 | .board_info = { | |
616 | I2C_BOARD_INFO("tvp5146", 0x5c), | |
617 | .platform_data = &tvp5146_pdata, | |
618 | }, | |
619 | .input = INPUT_SVIDEO_VI2C_VI1C, | |
620 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | |
85609c1c MK |
621 | .vpif_if = { |
622 | .if_type = VPIF_IF_BT656, | |
623 | .hd_pol = 1, | |
624 | .vd_pol = 1, | |
625 | .fid_pol = 0, | |
626 | }, | |
627 | }, | |
628 | }; | |
629 | ||
630 | static const struct vpif_input dm6467_ch0_inputs[] = { | |
631 | { | |
632 | .input = { | |
633 | .index = 0, | |
634 | .name = "Composite", | |
635 | .type = V4L2_INPUT_TYPE_CAMERA, | |
636 | .std = TVP514X_STD_ALL, | |
637 | }, | |
638 | .subdev_name = TVP5147_CH0, | |
639 | }, | |
640 | }; | |
641 | ||
642 | static const struct vpif_input dm6467_ch1_inputs[] = { | |
643 | { | |
644 | .input = { | |
645 | .index = 0, | |
646 | .name = "S-Video", | |
647 | .type = V4L2_INPUT_TYPE_CAMERA, | |
648 | .std = TVP514X_STD_ALL, | |
649 | }, | |
650 | .subdev_name = TVP5147_CH1, | |
651 | }, | |
652 | }; | |
653 | ||
654 | static struct vpif_capture_config dm646x_vpif_capture_cfg = { | |
655 | .setup_input_path = setup_vpif_input_path, | |
656 | .setup_input_channel_mode = setup_vpif_input_channel_mode, | |
657 | .subdev_info = vpif_capture_sdev_info, | |
658 | .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info), | |
659 | .chan_config[0] = { | |
660 | .inputs = dm6467_ch0_inputs, | |
661 | .input_count = ARRAY_SIZE(dm6467_ch0_inputs), | |
662 | }, | |
663 | .chan_config[1] = { | |
664 | .inputs = dm6467_ch1_inputs, | |
665 | .input_count = ARRAY_SIZE(dm6467_ch1_inputs), | |
666 | }, | |
667 | }; | |
668 | ||
669 | static void __init evm_init_video(void) | |
670 | { | |
85609c1c MK |
671 | spin_lock_init(&vpif_reg_lock); |
672 | ||
673 | dm646x_setup_vpif(&dm646x_vpif_display_config, | |
674 | &dm646x_vpif_capture_cfg); | |
675 | } | |
676 | ||
e38d92fd KH |
677 | static void __init evm_init_i2c(void) |
678 | { | |
679 | davinci_init_i2c(&i2c_pdata); | |
548197bd | 680 | i2c_add_driver(&dm6467evm_cpld_driver); |
e38d92fd | 681 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); |
85609c1c MK |
682 | evm_init_cpld(); |
683 | evm_init_video(); | |
e38d92fd KH |
684 | } |
685 | ||
77a92c71 NS |
686 | #define CDCE949_XIN_RATE 27000000 |
687 | ||
688 | /* CDCE949 support - "lpsc" field is overridden to work as clock number */ | |
689 | static struct clk cdce_clk_in = { | |
690 | .name = "cdce_xin", | |
691 | .rate = CDCE949_XIN_RATE, | |
692 | }; | |
693 | ||
c564191b | 694 | static struct clk_lookup cdce_clks[] = { |
77a92c71 NS |
695 | CLK(NULL, "xin", &cdce_clk_in), |
696 | CLK(NULL, NULL, NULL), | |
697 | }; | |
698 | ||
699 | static void __init cdce_clk_init(void) | |
700 | { | |
c564191b | 701 | struct clk_lookup *c; |
77a92c71 NS |
702 | struct clk *clk; |
703 | ||
c564191b KH |
704 | for (c = cdce_clks; c->clk; c++) { |
705 | clk = c->clk; | |
706 | clkdev_add(c); | |
77a92c71 NS |
707 | clk_register(clk); |
708 | } | |
709 | } | |
710 | ||
56e580d7 SN |
711 | #define DM6467T_EVM_REF_FREQ 33000000 |
712 | ||
e38d92fd KH |
713 | static void __init davinci_map_io(void) |
714 | { | |
e38d92fd | 715 | dm646x_init(); |
56e580d7 SN |
716 | |
717 | if (machine_is_davinci_dm6467tevm()) | |
718 | davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ); | |
719 | ||
77a92c71 | 720 | cdce_clk_init(); |
e38d92fd KH |
721 | } |
722 | ||
b73b526e SN |
723 | static struct davinci_uart_config uart_config __initdata = { |
724 | .enabled_uarts = (1 << 0), | |
725 | }; | |
726 | ||
f6f97588 | 727 | #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" |
cce3dddb RS |
728 | /* |
729 | * The following EDMA channels/slots are not being used by drivers (for | |
730 | * example: Timer, GPIO, UART events etc) on dm646x, hence they are being | |
731 | * reserved for codecs on the DSP side. | |
732 | */ | |
733 | static const s16 dm646x_dma_rsv_chans[][2] = { | |
734 | /* (offset, number) */ | |
735 | { 0, 4}, | |
736 | {13, 3}, | |
737 | {24, 4}, | |
738 | {30, 2}, | |
739 | {54, 3}, | |
740 | {-1, -1} | |
741 | }; | |
742 | ||
743 | static const s16 dm646x_dma_rsv_slots[][2] = { | |
744 | /* (offset, number) */ | |
745 | { 0, 4}, | |
746 | {13, 3}, | |
747 | {24, 4}, | |
748 | {30, 2}, | |
749 | {54, 3}, | |
750 | {128, 384}, | |
751 | {-1, -1} | |
752 | }; | |
753 | ||
754 | static struct edma_rsv_info dm646x_edma_rsv[] = { | |
755 | { | |
756 | .rsv_chans = dm646x_dma_rsv_chans, | |
757 | .rsv_slots = dm646x_dma_rsv_slots, | |
758 | }, | |
759 | }; | |
760 | ||
e38d92fd KH |
761 | static __init void evm_init(void) |
762 | { | |
972412b6 MG |
763 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
764 | ||
e38d92fd KH |
765 | evm_init_i2c(); |
766 | davinci_serial_init(&uart_config); | |
25acf553 C |
767 | dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); |
768 | dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); | |
972412b6 | 769 | |
0b3fc7bb SN |
770 | if (machine_is_davinci_dm6467tevm()) |
771 | davinci_nand_data.timing = &dm6467tevm_nandflash_timing; | |
772 | ||
50fbabfe HP |
773 | platform_device_register(&davinci_nand_device); |
774 | ||
cce3dddb RS |
775 | dm646x_init_edma(dm646x_edma_rsv); |
776 | ||
548197bd | 777 | if (HAS_ATA) |
7a9978a1 | 778 | davinci_init_ide(); |
548197bd | 779 | |
782f2d78 | 780 | soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; |
e38d92fd KH |
781 | } |
782 | ||
e38d92fd | 783 | MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") |
e7e56014 | 784 | .atag_offset = 0x100, |
e38d92fd | 785 | .map_io = davinci_map_io, |
bd808947 | 786 | .init_irq = davinci_irq_init, |
e38d92fd KH |
787 | .timer = &davinci_timer, |
788 | .init_machine = evm_init, | |
3aa3e840 | 789 | .init_late = davinci_init_late, |
f68deabf | 790 | .dma_zone_size = SZ_128M, |
c6121ddd | 791 | .restart = davinci_restart, |
e38d92fd KH |
792 | MACHINE_END |
793 | ||
c1978e1d | 794 | MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") |
e7e56014 | 795 | .atag_offset = 0x100, |
c1978e1d | 796 | .map_io = davinci_map_io, |
bd808947 | 797 | .init_irq = davinci_irq_init, |
c1978e1d SN |
798 | .timer = &davinci_timer, |
799 | .init_machine = evm_init, | |
3aa3e840 | 800 | .init_late = davinci_init_late, |
f68deabf | 801 | .dma_zone_size = SZ_128M, |
c6121ddd | 802 | .restart = davinci_restart, |
c1978e1d SN |
803 | MACHINE_END |
804 |