[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arc / kernel / setup.c

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/seq_file.h>
#include <linux/fs.h>
#include <linux/delay.h>
#include <linux/root_dev.h>
#include <linux/console.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <linux/of_fdt.h>
#include <linux/cache.h>
#include <asm/sections.h>
#include <asm/arcregs.h>
#include <asm/tlb.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/unwind.h>
#include <asm/clk.h>
#include <asm/mach_desc.h>

#define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))

int running_on_hw = 1;	/* vs. on ISS */

char __initdata command_line[COMMAND_LINE_SIZE];
struct machine_desc *machine_desc __cpuinitdata;

struct task_struct *_current_task[NR_CPUS];	/* For stack switching */

struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];


void __cpuinit read_arc_build_cfg_regs(void)
{
	struct bcr_perip uncached_space;
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	FIX_PTR(cpu);

	READ_BCR(AUX_IDENTITY, cpu->core);

	cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR);
	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);

	READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
	cpu->uncached_base = uncached_space.start << 24;

	cpu->extn.mul = read_aux_reg(ARC_REG_MUL_BCR);
	cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR);
	cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR);
	cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR);
	cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR);
	READ_BCR(ARC_REG_MAC_BCR, cpu->extn_mac_mul);

	cpu->extn.ext_arith = read_aux_reg(ARC_REG_EXTARITH_BCR);
	cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR);

	/* Note that we read the CCM BCRs independent of kernel config
	 * This is to catch the cases where user doesn't know that
	 * CCMs are present in hardware build
	 */
	{
		struct bcr_iccm iccm;
		struct bcr_dccm dccm;
		struct bcr_dccm_base dccm_base;
		unsigned int bcr_32bit_val;

		bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR);
		if (bcr_32bit_val) {
			iccm = *((struct bcr_iccm *)&bcr_32bit_val);
			cpu->iccm.base_addr = iccm.base << 16;
			cpu->iccm.sz = 0x2000 << (iccm.sz - 1);
		}

		bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR);
		if (bcr_32bit_val) {
			dccm = *((struct bcr_dccm *)&bcr_32bit_val);
			cpu->dccm.sz = 0x800 << (dccm.sz);

			READ_BCR(ARC_REG_DCCMBASE_BCR, dccm_base);
			cpu->dccm.base_addr = dccm_base.addr << 8;
		}
	}

	READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);

	read_decode_mmu_bcr();
	read_decode_cache_bcr();

	READ_BCR(ARC_REG_FP_BCR, cpu->fp);
	READ_BCR(ARC_REG_DPFP_BCR, cpu->dpfp);
}

static const struct cpuinfo_data arc_cpu_tbl[] = {
	{ {0x10, "ARCTangent A5"}, 0x1F},
	{ {0x20, "ARC 600"      }, 0x2F},
	{ {0x30, "ARC 700"      }, 0x33},
	{ {0x34, "ARC 700 R4.10"}, 0x34},
	{ {0x00, NULL		} }
};

char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
{
	int n = 0;
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
	struct bcr_identity *core = &cpu->core;
	const struct cpuinfo_data *tbl;
	int be = 0;
#ifdef CONFIG_CPU_BIG_ENDIAN
	be = 1;
#endif
	FIX_PTR(cpu);

	n += scnprintf(buf + n, len - n,
		       "\nARC IDENTITY\t: Family [%#02x]"
		       " Cpu-id [%#02x] Chip-id [%#4x]\n",
		       core->family, core->cpu_id,
		       core->chip_id);

	for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
		if ((core->family >= tbl->info.id) &&
		    (core->family <= tbl->up_range)) {
			n += scnprintf(buf + n, len - n,
				       "processor\t: %s %s\n",
				       tbl->info.str,
				       be ? "[Big Endian]" : "");
			break;
		}
	}

	if (tbl->info.id == 0)
		n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");

	n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
		       (unsigned int)(arc_get_core_freq() / 1000000),
		       (unsigned int)(arc_get_core_freq() / 10000) % 100);

	n += scnprintf(buf + n, len - n, "Timers\t\t: %s %s\n",
		       (cpu->timers & 0x200) ? "TIMER1" : "",
		       (cpu->timers & 0x100) ? "TIMER0" : "");

	n += scnprintf(buf + n, len - n, "Vect Tbl Base\t: %#x\n",
		       cpu->vec_base);

	n += scnprintf(buf + n, len - n, "UNCACHED Base\t: %#x\n",
		       cpu->uncached_base);

	return buf;
}

static const struct id_to_str mul_type_nm[] = {
	{ 0x0, "N/A"},
	{ 0x1, "32x32 (spl Result Reg)" },
	{ 0x2, "32x32 (ANY Result Reg)" }
};

static const struct id_to_str mac_mul_nm[] = {
	{0x0, "N/A"},
	{0x1, "N/A"},
	{0x2, "Dual 16 x 16"},
	{0x3, "N/A"},
	{0x4, "32x16"},
	{0x5, "N/A"},
	{0x6, "Dual 16x16 and 32x16"}
};

char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
{
	int n = 0;
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];

	FIX_PTR(cpu);
#define IS_AVAIL1(var, str)	((var) ? str : "")
#define IS_AVAIL2(var, str)	((var == 0x2) ? str : "")
#define IS_USED(var)		((var) ? "(in-use)" : "(not used)")

	n += scnprintf(buf + n, len - n,
		       "Extn [700-Base]\t: %s %s %s %s %s %s\n",
		       IS_AVAIL2(cpu->extn.norm, "norm,"),
		       IS_AVAIL2(cpu->extn.barrel, "barrel-shift,"),
		       IS_AVAIL1(cpu->extn.swap, "swap,"),
		       IS_AVAIL2(cpu->extn.minmax, "minmax,"),
		       IS_AVAIL1(cpu->extn.crc, "crc,"),
		       IS_AVAIL2(cpu->extn.ext_arith, "ext-arith"));

	n += scnprintf(buf + n, len - n, "Extn [700-MPY]\t: %s",
		       mul_type_nm[cpu->extn.mul].str);

	n += scnprintf(buf + n, len - n, "   MAC MPY: %s\n",
		       mac_mul_nm[cpu->extn_mac_mul.type].str);

	if (cpu->core.family == 0x34) {
		n += scnprintf(buf + n, len - n,
		"Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n",
			       IS_USED(__CONFIG_ARC_HAS_LLSC_VAL),
			       IS_USED(__CONFIG_ARC_HAS_SWAPE_VAL),
			       IS_USED(__CONFIG_ARC_HAS_RTSC_VAL));
	}

	n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
		       !(cpu->dccm.sz || cpu->iccm.sz) ? "N/A" : "");

	if (cpu->dccm.sz)
		n += scnprintf(buf + n, len - n, "DCCM: @ %x, %d KB ",
			       cpu->dccm.base_addr, TO_KB(cpu->dccm.sz));

	if (cpu->iccm.sz)
		n += scnprintf(buf + n, len - n, "ICCM: @ %x, %d KB",
			       cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));

	n += scnprintf(buf + n, len - n, "\nExtn [FPU]\t: %s",
		       !(cpu->fp.ver || cpu->dpfp.ver) ? "N/A" : "");

	if (cpu->fp.ver)
		n += scnprintf(buf + n, len - n, "SP [v%d] %s",
			       cpu->fp.ver, cpu->fp.fast ? "(fast)" : "");

	if (cpu->dpfp.ver)
		n += scnprintf(buf + n, len - n, "DP [v%d] %s",
			       cpu->dpfp.ver, cpu->dpfp.fast ? "(fast)" : "");

	n += scnprintf(buf + n, len - n, "\n");

	n += scnprintf(buf + n, len - n,
		       "OS ABI [v3]\t: no-legacy-syscalls\n");

	return buf;
}

void __cpuinit arc_chk_ccms(void)
{
#if defined(CONFIG_ARC_HAS_DCCM) || defined(CONFIG_ARC_HAS_ICCM)
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];

#ifdef CONFIG_ARC_HAS_DCCM
	/*
	 * DCCM can be arbit placed in hardware.
	 * Make sure it's placement/sz matches what Linux is built with
	 */
	if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
		panic("Linux built with incorrect DCCM Base address\n");

	if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
		panic("Linux built with incorrect DCCM Size\n");
#endif

#ifdef CONFIG_ARC_HAS_ICCM
	if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
		panic("Linux built with incorrect ICCM Size\n");
#endif
#endif
}

/*
 * Ensure that FP hardware and kernel config match
 * -If hardware contains DPFP, kernel needs to save/restore FPU state
 *  across context switches
 * -If hardware lacks DPFP, but kernel configured to save FPU state then
 *  kernel trying to access non-existant DPFP regs will crash
 *
 * We only check for Dbl precision Floating Point, because only DPFP
 * hardware has dedicated regs which need to be saved/restored on ctx-sw
 * (Single Precision uses core regs), thus kernel is kind of oblivious to it
 */
void __cpuinit arc_chk_fpu(void)
{
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];

	if (cpu->dpfp.ver) {
#ifndef CONFIG_ARC_FPU_SAVE_RESTORE
		pr_warn("DPFP support broken in this kernel...\n");
#endif
	} else {
#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
		panic("H/w lacks DPFP support, apps won't work\n");
#endif
	}
}

/*
 * Initialize and setup the processor core
 * This is called by all the CPUs thus should not do special case stuff
 *    such as only for boot CPU etc
 */

void __cpuinit setup_processor(void)
{
	char str[512];
	int cpu_id = smp_processor_id();

	read_arc_build_cfg_regs();
	arc_init_IRQ();

	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));

	arc_mmu_init();
	arc_cache_init();
	arc_chk_ccms();

	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));

#ifdef CONFIG_SMP
	printk(arc_platform_smp_cpuinfo());
#endif

	arc_chk_fpu();
}

void __init setup_arch(char **cmdline_p)
{
	/* This also populates @boot_command_line from /bootargs */
	machine_desc = setup_machine_fdt(__dtb_start);
	if (!machine_desc)
		panic("Embedded DT invalid\n");

	/* Append any u-boot provided cmdline */
#ifdef CONFIG_CMDLINE_UBOOT
	/* Add a whitespace seperator between the 2 cmdlines */
	strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
	strlcat(boot_command_line, command_line, COMMAND_LINE_SIZE);
#endif

	/* Save unparsed command line copy for /proc/cmdline */
	*cmdline_p = boot_command_line;

	/* To force early parsing of things like mem=xxx */
	parse_early_param();

	/* Platform/board specific: e.g. early console registration */
	if (machine_desc->init_early)
		machine_desc->init_early();

	setup_processor();

#ifdef CONFIG_SMP
	smp_init_cpus();
#endif

	setup_arch_memory();

	/* copy flat DT out of .init and then unflatten it */
	copy_devtree();
	unflatten_device_tree();

	/* Can be issue if someone passes cmd line arg "ro"
	 * But that is unlikely so keeping it as it is
	 */
	root_mountflags &= ~MS_RDONLY;

	console_verbose();

#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
#endif

	arc_unwind_init();
	arc_unwind_setup();
}

static int __init customize_machine(void)
{
	/* Add platform devices */
	if (machine_desc->init_machine)
		machine_desc->init_machine();

	return 0;
}
arch_initcall(customize_machine);

static int __init init_late_machine(void)
{
	if (machine_desc->init_late)
		machine_desc->init_late();

	return 0;
}
late_initcall(init_late_machine);
/*
 *  Get CPU information for use by the procfs.
 */

#define cpu_to_ptr(c)	((void *)(0xFFFF0000 | (unsigned int)(c)))
#define ptr_to_cpu(p)	(~0xFFFF0000UL & (unsigned int)(p))

static int show_cpuinfo(struct seq_file *m, void *v)
{
	char *str;
	int cpu_id = ptr_to_cpu(v);

	str = (char *)__get_free_page(GFP_TEMPORARY);
	if (!str)
		goto done;

	seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));

	seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n",
		   loops_per_jiffy / (500000 / HZ),
		   (loops_per_jiffy / (5000 / HZ)) % 100);

	seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));

	seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));

	seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));

#ifdef CONFIG_SMP
	seq_printf(m, arc_platform_smp_cpuinfo());
#endif

	free_page((unsigned long)str);
done:
	seq_printf(m, "\n\n");

	return 0;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	/*
	 * Callback returns cpu-id to iterator for show routine, NULL to stop.
	 * However since NULL is also a valid cpu-id (0), we use a round-about
	 * way to pass it w/o having to kmalloc/free a 2 byte string.
	 * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
	 */
	return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return c_start(m, pos);
}

static void c_stop(struct seq_file *m, void *v)
{
}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= show_cpuinfo
};

static DEFINE_PER_CPU(struct cpu, cpu_topology);

static int __init topology_init(void)
{
	int cpu;

	for_each_present_cpu(cpu)
	    register_cpu(&per_cpu(cpu_topology, cpu), cpu);

	return 0;
}

subsys_initcall(topology_init);
Commit	Line	Data
c121c506 VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/seq_file.h>
	10	#include <linux/fs.h>
	11	#include <linux/delay.h>
	12	#include <linux/root_dev.h>
	13	#include <linux/console.h>
	14	#include <linux/module.h>
	15	#include <linux/cpu.h>
999159a5	16	#include <linux/of_fdt.h>
1ec9db10	17	#include <linux/cache.h>
999159a5	18	#include <asm/sections.h>
c121c506 VG	19	#include <asm/arcregs.h>
c121c506 VG	20	#include <asm/tlb.h>
c121c506 VG	21	#include <asm/setup.h>
	22	#include <asm/page.h>
	23	#include <asm/irq.h>
999159a5	24	#include <asm/prom.h>
854a0d95	25	#include <asm/unwind.h>
af617428	26	#include <asm/clk.h>
03a6d28c	27	#include <asm/mach_desc.h>
c121c506 VG	28
	29	#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
	30
	31	int running_on_hw = 1; /* vs. on ISS */
	32
	33	char __initdata command_line[COMMAND_LINE_SIZE];
30ecee8c	34	struct machine_desc *machine_desc __cpuinitdata;
c121c506 VG	35
	36	struct task_struct _current_task[NR_CPUS]; / For stack switching */
	37
	38	struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
	39
af617428	40
30ecee8c	41	void __cpuinit read_arc_build_cfg_regs(void)
c121c506	42	{
af617428 VG	43	struct bcr_perip uncached_space;
	44	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	45	FIX_PTR(cpu);
	46
	47	READ_BCR(AUX_IDENTITY, cpu->core);
	48
	49	cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR);
af617428	50	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
af617428 VG	51
	52	READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
	53	cpu->uncached_base = uncached_space.start << 24;
	54
	55	cpu->extn.mul = read_aux_reg(ARC_REG_MUL_BCR);
	56	cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR);
	57	cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR);
	58	cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR);
	59	cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR);
	60	READ_BCR(ARC_REG_MAC_BCR, cpu->extn_mac_mul);
	61
	62	cpu->extn.ext_arith = read_aux_reg(ARC_REG_EXTARITH_BCR);
	63	cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR);
	64
8b5850f8 VG	65	/* Note that we read the CCM BCRs independent of kernel config
	66	* This is to catch the cases where user doesn't know that
	67	* CCMs are present in hardware build
	68	*/
	69	{
	70	struct bcr_iccm iccm;
	71	struct bcr_dccm dccm;
	72	struct bcr_dccm_base dccm_base;
	73	unsigned int bcr_32bit_val;
	74
	75	bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR);
	76	if (bcr_32bit_val) {
	77	iccm = ((struct bcr_iccm )&bcr_32bit_val);
	78	cpu->iccm.base_addr = iccm.base << 16;
	79	cpu->iccm.sz = 0x2000 << (iccm.sz - 1);
	80	}
	81
	82	bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR);
	83	if (bcr_32bit_val) {
	84	dccm = ((struct bcr_dccm )&bcr_32bit_val);
	85	cpu->dccm.sz = 0x800 << (dccm.sz);
	86
	87	READ_BCR(ARC_REG_DCCMBASE_BCR, dccm_base);
	88	cpu->dccm.base_addr = dccm_base.addr << 8;
	89	}
	90	}
	91
af617428 VG	92	READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
af617428 VG	93
c121c506 VG	94	read_decode_mmu_bcr();
c121c506 VG	95	read_decode_cache_bcr();
af617428 VG	96
	97	READ_BCR(ARC_REG_FP_BCR, cpu->fp);
	98	READ_BCR(ARC_REG_DPFP_BCR, cpu->dpfp);
	99	}
	100
	101	static const struct cpuinfo_data arc_cpu_tbl[] = {
	102	{ {0x10, "ARCTangent A5"}, 0x1F},
	103	{ {0x20, "ARC 600" }, 0x2F},
	104	{ {0x30, "ARC 700" }, 0x33},
	105	{ {0x34, "ARC 700 R4.10"}, 0x34},
	106	{ {0x00, NULL } }
	107	};
	108
	109	char arc_cpu_mumbojumbo(int cpu_id, char buf, int len)
	110	{
	111	int n = 0;
	112	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
	113	struct bcr_identity *core = &cpu->core;
	114	const struct cpuinfo_data *tbl;
	115	int be = 0;
	116	#ifdef CONFIG_CPU_BIG_ENDIAN
	117	be = 1;
	118	#endif
	119	FIX_PTR(cpu);
	120
	121	n += scnprintf(buf + n, len - n,
	122	"\nARC IDENTITY\t: Family [%#02x]"
	123	" Cpu-id [%#02x] Chip-id [%#4x]\n",
	124	core->family, core->cpu_id,
	125	core->chip_id);
	126
	127	for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
	128	if ((core->family >= tbl->info.id) &&
	129	(core->family <= tbl->up_range)) {
	130	n += scnprintf(buf + n, len - n,
	131	"processor\t: %s %s\n",
	132	tbl->info.str,
	133	be ? "[Big Endian]" : "");
	134	break;
	135	}
	136	}
	137
	138	if (tbl->info.id == 0)
	139	n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
	140
	141	n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
	142	(unsigned int)(arc_get_core_freq() / 1000000),
	143	(unsigned int)(arc_get_core_freq() / 10000) % 100);
	144
	145	n += scnprintf(buf + n, len - n, "Timers\t\t: %s %s\n",
	146	(cpu->timers & 0x200) ? "TIMER1" : "",
	147	(cpu->timers & 0x100) ? "TIMER0" : "");
	148
	149	n += scnprintf(buf + n, len - n, "Vect Tbl Base\t: %#x\n",
	150	cpu->vec_base);
	151
	152	n += scnprintf(buf + n, len - n, "UNCACHED Base\t: %#x\n",
	153	cpu->uncached_base);
	154
	155	return buf;
	156	}
	157
	158	static const struct id_to_str mul_type_nm[] = {
	159	{ 0x0, "N/A"},
160	{ 0x1, "32x32 (spl Result Reg)" },
161	{ 0x2, "32x32 (ANY Result Reg)" }
162	};
163
164	static const struct id_to_str mac_mul_nm[] = {
165	{0x0, "N/A"},
166	{0x1, "N/A"},
167	{0x2, "Dual 16 x 16"},
168	{0x3, "N/A"},
169	{0x4, "32x16"},
170	{0x5, "N/A"},
171	{0x6, "Dual 16x16 and 32x16"}
172	};
173
174	char arc_extn_mumbojumbo(int cpu_id, char buf, int len)
175	{
176	int n = 0;
177	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
178
179	FIX_PTR(cpu);
180	#define IS_AVAIL1(var, str) ((var) ? str : "")
181	#define IS_AVAIL2(var, str) ((var == 0x2) ? str : "")
182	#define IS_USED(var) ((var) ? "(in-use)" : "(not used)")
183
184	n += scnprintf(buf + n, len - n,
185	"Extn [700-Base]\t: %s %s %s %s %s %s\n",
186	IS_AVAIL2(cpu->extn.norm, "norm,"),
187	IS_AVAIL2(cpu->extn.barrel, "barrel-shift,"),
188	IS_AVAIL1(cpu->extn.swap, "swap,"),
189	IS_AVAIL2(cpu->extn.minmax, "minmax,"),
190	IS_AVAIL1(cpu->extn.crc, "crc,"),
191	IS_AVAIL2(cpu->extn.ext_arith, "ext-arith"));
192
193	n += scnprintf(buf + n, len - n, "Extn [700-MPY]\t: %s",
194	mul_type_nm[cpu->extn.mul].str);
195
196	n += scnprintf(buf + n, len - n, " MAC MPY: %s\n",
197	mac_mul_nm[cpu->extn_mac_mul.type].str);
198
199	if (cpu->core.family == 0x34) {
200	n += scnprintf(buf + n, len - n,
201	"Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n",
202	IS_USED(__CONFIG_ARC_HAS_LLSC_VAL),
203	IS_USED(__CONFIG_ARC_HAS_SWAPE_VAL),
204	IS_USED(__CONFIG_ARC_HAS_RTSC_VAL));
205	}
206
207	n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
208	!(cpu->dccm.sz \|\| cpu->iccm.sz) ? "N/A" : "");
209
210	if (cpu->dccm.sz)
211	n += scnprintf(buf + n, len - n, "DCCM: @ %x, %d KB ",
212	cpu->dccm.base_addr, TO_KB(cpu->dccm.sz));
213
214	if (cpu->iccm.sz)
215	n += scnprintf(buf + n, len - n, "ICCM: @ %x, %d KB",
216	cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
217
218	n += scnprintf(buf + n, len - n, "\nExtn [FPU]\t: %s",
219	!(cpu->fp.ver \|\| cpu->dpfp.ver) ? "N/A" : "");
220
221	if (cpu->fp.ver)
222	n += scnprintf(buf + n, len - n, "SP [v%d] %s",
223	cpu->fp.ver, cpu->fp.fast ? "(fast)" : "");
224
225	if (cpu->dpfp.ver)
226	n += scnprintf(buf + n, len - n, "DP [v%d] %s",
227	cpu->dpfp.ver, cpu->dpfp.fast ? "(fast)" : "");
228
229	n += scnprintf(buf + n, len - n, "\n");
230
af617428	231	n += scnprintf(buf + n, len - n,
8ff14bbc	232	"OS ABI [v3]\t: no-legacy-syscalls\n");
af617428 VG	233
	234	return buf;
	235	}
	236
30ecee8c	237	void __cpuinit arc_chk_ccms(void)
8b5850f8 VG	238	{
	239	#if defined(CONFIG_ARC_HAS_DCCM) \|\| defined(CONFIG_ARC_HAS_ICCM)
	240	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	241
	242	#ifdef CONFIG_ARC_HAS_DCCM
	243	/*
	244	* DCCM can be arbit placed in hardware.
	245	* Make sure it's placement/sz matches what Linux is built with
	246	*/
	247	if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
	248	panic("Linux built with incorrect DCCM Base address\n");
	249
	250	if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
	251	panic("Linux built with incorrect DCCM Size\n");
	252	#endif
	253
	254	#ifdef CONFIG_ARC_HAS_ICCM
	255	if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
	256	panic("Linux built with incorrect ICCM Size\n");
	257	#endif
	258	#endif
	259	}
	260
af617428 VG	261	/*
	262	* Ensure that FP hardware and kernel config match
	263	* -If hardware contains DPFP, kernel needs to save/restore FPU state
	264	* across context switches
	265	* -If hardware lacks DPFP, but kernel configured to save FPU state then
	266	* kernel trying to access non-existant DPFP regs will crash
	267	*
	268	* We only check for Dbl precision Floating Point, because only DPFP
	269	* hardware has dedicated regs which need to be saved/restored on ctx-sw
	270	* (Single Precision uses core regs), thus kernel is kind of oblivious to it
	271	*/
30ecee8c	272	void __cpuinit arc_chk_fpu(void)
af617428 VG	273	{
	274	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	275
	276	if (cpu->dpfp.ver) {
	277	#ifndef CONFIG_ARC_FPU_SAVE_RESTORE
	278	pr_warn("DPFP support broken in this kernel...\n");
	279	#endif
	280	} else {
	281	#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
	282	panic("H/w lacks DPFP support, apps won't work\n");
	283	#endif
	284	}
c121c506 VG	285	}
	286
	287	/*
	288	* Initialize and setup the processor core
	289	* This is called by all the CPUs thus should not do special case stuff
	290	* such as only for boot CPU etc
	291	*/
	292
30ecee8c	293	void __cpuinit setup_processor(void)
c121c506	294	{
af617428 VG	295	char str[512];
	296	int cpu_id = smp_processor_id();
	297
c121c506 VG	298	read_arc_build_cfg_regs();
c121c506 VG	299	arc_init_IRQ();
af617428 VG	300
	301	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
	302
c121c506 VG	303	arc_mmu_init();
c121c506 VG	304	arc_cache_init();
8b5850f8	305	arc_chk_ccms();
af617428 VG	306
	307	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
	308
	309	#ifdef CONFIG_SMP
	310	printk(arc_platform_smp_cpuinfo());
	311	#endif
	312
	313	arc_chk_fpu();
c121c506 VG	314	}
c121c506 VG	315
c121c506 VG	316	void __init setup_arch(char **cmdline_p)
c121c506 VG	317	{
9593a933 VG	318	/* This also populates @boot_command_line from /bootargs */
	319	machine_desc = setup_machine_fdt(__dtb_start);
	320	if (!machine_desc)
	321	panic("Embedded DT invalid\n");
	322
	323	/* Append any u-boot provided cmdline */
c121c506	324	#ifdef CONFIG_CMDLINE_UBOOT
9593a933 VG	325	/* Add a whitespace seperator between the 2 cmdlines */
	326	strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
	327	strlcat(boot_command_line, command_line, COMMAND_LINE_SIZE);
c121c506	328	#endif
c121c506 VG	329
c121c506 VG	330	/* Save unparsed command line copy for /proc/cmdline */
9593a933	331	*cmdline_p = boot_command_line;
999159a5	332
c121c506 VG	333	/* To force early parsing of things like mem=xxx */
	334	parse_early_param();
	335
	336	/* Platform/board specific: e.g. early console registration */
03a6d28c VG	337	if (machine_desc->init_early)
03a6d28c VG	338	machine_desc->init_early();
c121c506 VG	339
	340	setup_processor();
	341
41195d23 VG	342	#ifdef CONFIG_SMP
	343	smp_init_cpus();
	344	#endif
	345
c121c506 VG	346	setup_arch_memory();
c121c506 VG	347
eab6a08c VG	348	/* copy flat DT out of .init and then unflatten it */
eab6a08c VG	349	copy_devtree();
999159a5 VG	350	unflatten_device_tree();
999159a5 VG	351
c121c506 VG	352	/* Can be issue if someone passes cmd line arg "ro"
	353	* But that is unlikely so keeping it as it is
	354	*/
	355	root_mountflags &= ~MS_RDONLY;
	356
	357	console_verbose();
	358
	359	#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
	360	conswitchp = &dummy_con;
	361	#endif
	362
854a0d95 VG	363	arc_unwind_init();
854a0d95 VG	364	arc_unwind_setup();
c121c506 VG	365	}
c121c506 VG	366
03a6d28c VG	367	static int __init customize_machine(void)
	368	{
	369	/* Add platform devices */
	370	if (machine_desc->init_machine)
	371	machine_desc->init_machine();
	372
	373	return 0;
	374	}
	375	arch_initcall(customize_machine);
	376
	377	static int __init init_late_machine(void)
	378	{
	379	if (machine_desc->init_late)
	380	machine_desc->init_late();
	381
	382	return 0;
	383	}
	384	late_initcall(init_late_machine);
c121c506 VG	385	/*
	386	* Get CPU information for use by the procfs.
	387	*/
	388
	389	#define cpu_to_ptr(c) ((void *)(0xFFFF0000 \| (unsigned int)(c)))
	390	#define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
	391
	392	static int show_cpuinfo(struct seq_file m, void v)
	393	{
	394	char *str;
	395	int cpu_id = ptr_to_cpu(v);
	396
	397	str = (char *)__get_free_page(GFP_TEMPORARY);
	398	if (!str)
	399	goto done;
	400
af617428	401	seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
c121c506 VG	402
	403	seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n",
	404	loops_per_jiffy / (500000 / HZ),
	405	(loops_per_jiffy / (5000 / HZ)) % 100);
	406
af617428 VG	407	seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
	408
	409	seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
	410
	411	seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
	412
	413	#ifdef CONFIG_SMP
	414	seq_printf(m, arc_platform_smp_cpuinfo());
	415	#endif
	416
c121c506 VG	417	free_page((unsigned long)str);
	418	done:
	419	seq_printf(m, "\n\n");
	420
	421	return 0;
	422	}
	423
	424	static void c_start(struct seq_file m, loff_t *pos)
	425	{
	426	/*
	427	* Callback returns cpu-id to iterator for show routine, NULL to stop.
	428	* However since NULL is also a valid cpu-id (0), we use a round-about
	429	* way to pass it w/o having to kmalloc/free a 2 byte string.
	430	* Encode cpu-id as 0xFFcccc, which is decoded by show routine.
	431	*/
	432	return pos < num_possible_cpus() ? cpu_to_ptr(pos) : NULL;
	433	}
	434
	435	static void c_next(struct seq_file m, void v, loff_t pos)
	436	{
	437	++*pos;
	438	return c_start(m, pos);
	439	}
	440
	441	static void c_stop(struct seq_file m, void v)
	442	{
	443	}
	444
	445	const struct seq_operations cpuinfo_op = {
	446	.start = c_start,
	447	.next = c_next,
	448	.stop = c_stop,
	449	.show = show_cpuinfo
	450	};
	451
	452	static DEFINE_PER_CPU(struct cpu, cpu_topology);
	453
	454	static int __init topology_init(void)
	455	{
	456	int cpu;
	457
	458	for_each_present_cpu(cpu)
	459	register_cpu(&per_cpu(cpu_topology, cpu), cpu);
	460
	461	return 0;
	462	}
	463
	464	subsys_initcall(topology_init);