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ac4c244d VG |
1 | /* |
2 | * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/interrupt.h> | |
11 | #include <linux/module.h> | |
abe11dde VG |
12 | #include <linux/of.h> |
13 | #include <linux/irqdomain.h> | |
c93d8b8c VG |
14 | #include <linux/irqchip.h> |
15 | #include "../../drivers/irqchip/irqchip.h" | |
bacdf480 VG |
16 | #include <asm/sections.h> |
17 | #include <asm/irq.h> | |
03a6d28c | 18 | #include <asm/mach_desc.h> |
bacdf480 VG |
19 | |
20 | /* | |
21 | * Early Hardware specific Interrupt setup | |
22 | * -Called very early (start_kernel -> setup_arch -> setup_processor) | |
23 | * -Platform Independent (must for any ARC700) | |
24 | * -Needed for each CPU (hence not foldable into init_IRQ) | |
25 | * | |
26 | * what it does ? | |
27 | * -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000 | |
28 | * -Disable all IRQs (on CPU side) | |
4788a594 | 29 | * -Optionally, setup the High priority Interrupts as Level 2 IRQs |
bacdf480 | 30 | */ |
30ecee8c | 31 | void __cpuinit arc_init_IRQ(void) |
bacdf480 | 32 | { |
4788a594 | 33 | int level_mask = 0; |
bacdf480 | 34 | |
bacdf480 VG |
35 | /* Disable all IRQs: enable them as devices request */ |
36 | write_aux_reg(AUX_IENABLE, 0); | |
4788a594 VG |
37 | |
38 | /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ | |
39 | #ifdef CONFIG_ARC_IRQ3_LV2 | |
40 | level_mask |= (1 << 3); | |
41 | #endif | |
42 | #ifdef CONFIG_ARC_IRQ5_LV2 | |
43 | level_mask |= (1 << 5); | |
44 | #endif | |
45 | #ifdef CONFIG_ARC_IRQ6_LV2 | |
46 | level_mask |= (1 << 6); | |
47 | #endif | |
48 | ||
49 | if (level_mask) { | |
50 | pr_info("Level-2 interrupts bitset %x\n", level_mask); | |
51 | write_aux_reg(AUX_IRQ_LEV, level_mask); | |
52 | } | |
bacdf480 VG |
53 | } |
54 | ||
55 | /* | |
56 | * ARC700 core includes a simple on-chip intc supporting | |
57 | * -per IRQ enable/disable | |
58 | * -2 levels of interrupts (high/low) | |
59 | * -all interrupts being level triggered | |
60 | * | |
61 | * To reduce platform code, we assume all IRQs directly hooked-up into intc. | |
62 | * Platforms with external intc, hence cascaded IRQs, are free to over-ride | |
63 | * below, per IRQ. | |
64 | */ | |
65 | ||
66 | static void arc_mask_irq(struct irq_data *data) | |
67 | { | |
68 | arch_mask_irq(data->irq); | |
69 | } | |
70 | ||
71 | static void arc_unmask_irq(struct irq_data *data) | |
72 | { | |
73 | arch_unmask_irq(data->irq); | |
74 | } | |
75 | ||
76 | static struct irq_chip onchip_intc = { | |
77 | .name = "ARC In-core Intc", | |
78 | .irq_mask = arc_mask_irq, | |
79 | .irq_unmask = arc_unmask_irq, | |
80 | }; | |
81 | ||
abe11dde VG |
82 | static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, |
83 | irq_hw_number_t hw) | |
84 | { | |
85 | if (irq == TIMER0_IRQ) | |
86 | irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); | |
87 | else | |
88 | irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | static const struct irq_domain_ops arc_intc_domain_ops = { | |
94 | .xlate = irq_domain_xlate_onecell, | |
95 | .map = arc_intc_domain_map, | |
96 | }; | |
97 | ||
98 | static struct irq_domain *root_domain; | |
99 | ||
c93d8b8c VG |
100 | static int __init |
101 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) | |
bacdf480 | 102 | { |
c93d8b8c VG |
103 | if (parent) |
104 | panic("DeviceTree incore intc not a root irq controller\n"); | |
abe11dde | 105 | |
a37cdacc | 106 | root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, |
abe11dde | 107 | &arc_intc_domain_ops, NULL); |
bacdf480 | 108 | |
abe11dde VG |
109 | if (!root_domain) |
110 | panic("root irq domain not avail\n"); | |
bacdf480 | 111 | |
abe11dde VG |
112 | /* with this we don't need to export root_domain */ |
113 | irq_set_default_host(root_domain); | |
c93d8b8c VG |
114 | |
115 | return 0; | |
bacdf480 VG |
116 | } |
117 | ||
c93d8b8c VG |
118 | IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); |
119 | ||
bacdf480 VG |
120 | /* |
121 | * Late Interrupt system init called from start_kernel for Boot CPU only | |
122 | * | |
123 | * Since slab must already be initialized, platforms can start doing any | |
124 | * needed request_irq( )s | |
125 | */ | |
126 | void __init init_IRQ(void) | |
127 | { | |
03a6d28c VG |
128 | /* Any external intc can be setup here */ |
129 | if (machine_desc->init_irq) | |
130 | machine_desc->init_irq(); | |
131 | ||
c93d8b8c VG |
132 | /* process the entire interrupt tree in one go */ |
133 | irqchip_init(); | |
134 | ||
41195d23 VG |
135 | #ifdef CONFIG_SMP |
136 | /* Master CPU can initialize it's side of IPI */ | |
03a6d28c VG |
137 | if (machine_desc->init_smp) |
138 | machine_desc->init_smp(smp_processor_id()); | |
41195d23 | 139 | #endif |
bacdf480 VG |
140 | } |
141 | ||
142 | /* | |
143 | * "C" Entry point for any ARC ISR, called from low level vector handler | |
144 | * @irq is the vector number read from ICAUSE reg of on-chip intc | |
145 | */ | |
146 | void arch_do_IRQ(unsigned int irq, struct pt_regs *regs) | |
147 | { | |
148 | struct pt_regs *old_regs = set_irq_regs(regs); | |
149 | ||
150 | irq_enter(); | |
151 | generic_handle_irq(irq); | |
152 | irq_exit(); | |
153 | set_irq_regs(old_regs); | |
154 | } | |
155 | ||
156 | int __init get_hw_config_num_irq(void) | |
157 | { | |
158 | uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR); | |
159 | ||
160 | switch (val & 0x03) { | |
161 | case 0: | |
162 | return 16; | |
163 | case 1: | |
164 | return 32; | |
165 | case 2: | |
166 | return 8; | |
167 | default: | |
168 | return 0; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
ac4c244d | 173 | |
4788a594 VG |
174 | /* |
175 | * arch_local_irq_enable - Enable interrupts. | |
176 | * | |
177 | * 1. Explicitly called to re-enable interrupts | |
178 | * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc | |
179 | * which maybe in hard ISR itself | |
180 | * | |
181 | * Semantics of this function change depending on where it is called from: | |
182 | * | |
183 | * -If called from hard-ISR, it must not invert interrupt priorities | |
184 | * e.g. suppose TIMER is high priority (Level 2) IRQ | |
185 | * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. | |
186 | * Here local_irq_enable( ) shd not re-enable lower priority interrupts | |
187 | * -If called from soft-ISR, it must re-enable all interrupts | |
188 | * soft ISR are low prioity jobs which can be very slow, thus all IRQs | |
189 | * must be enabled while they run. | |
190 | * Now hardware context wise we may still be in L2 ISR (not done rtie) | |
191 | * still we must re-enable both L1 and L2 IRQs | |
192 | * Another twist is prev scenario with flow being | |
193 | * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR | |
194 | * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get | |
195 | * over-written (this is deficiency in ARC700 Interrupt mechanism) | |
196 | */ | |
197 | ||
198 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ | |
199 | ||
200 | void arch_local_irq_enable(void) | |
201 | { | |
202 | ||
203 | unsigned long flags; | |
204 | flags = arch_local_save_flags(); | |
205 | ||
206 | /* Allow both L1 and L2 at the onset */ | |
207 | flags |= (STATUS_E1_MASK | STATUS_E2_MASK); | |
208 | ||
209 | /* Called from hard ISR (between irq_enter and irq_exit) */ | |
210 | if (in_irq()) { | |
211 | ||
212 | /* If in L2 ISR, don't re-enable any further IRQs as this can | |
213 | * cause IRQ priorities to get upside down. e.g. it could allow | |
214 | * L1 be taken while in L2 hard ISR which is wrong not only in | |
215 | * theory, it can also cause the dreaded L1-L2-L1 scenario | |
216 | */ | |
217 | if (flags & STATUS_A2_MASK) | |
218 | flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); | |
219 | ||
220 | /* Even if in L1 ISR, allowe Higher prio L2 IRQs */ | |
221 | else if (flags & STATUS_A1_MASK) | |
222 | flags &= ~(STATUS_E1_MASK); | |
223 | } | |
224 | ||
225 | /* called from soft IRQ, ideally we want to re-enable all levels */ | |
226 | ||
227 | else if (in_softirq()) { | |
228 | ||
229 | /* However if this is case of L1 interrupted by L2, | |
230 | * re-enabling both may cause whaco L1-L2-L1 scenario | |
231 | * because ARC700 allows level 1 to interrupt an active L2 ISR | |
232 | * Thus we disable both | |
233 | * However some code, executing in soft ISR wants some IRQs | |
234 | * to be enabled so we re-enable L2 only | |
235 | * | |
236 | * How do we determine L1 intr by L2 | |
237 | * -A2 is set (means in L2 ISR) | |
238 | * -E1 is set in this ISR's pt_regs->status32 which is | |
239 | * saved copy of status32_l2 when l2 ISR happened | |
240 | */ | |
241 | struct pt_regs *pt = get_irq_regs(); | |
242 | if ((flags & STATUS_A2_MASK) && pt && | |
243 | (pt->status32 & STATUS_A1_MASK)) { | |
244 | /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */ | |
245 | flags &= ~(STATUS_E1_MASK); | |
246 | } | |
247 | } | |
248 | ||
249 | arch_local_irq_restore(flags); | |
250 | } | |
251 | ||
252 | #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */ | |
253 | ||
254 | /* | |
255 | * Simpler version for only 1 level of interrupt | |
256 | * Here we only Worry about Level 1 Bits | |
257 | */ | |
ac4c244d VG |
258 | void arch_local_irq_enable(void) |
259 | { | |
260 | unsigned long flags; | |
261 | ||
262 | /* | |
263 | * ARC IDE Drivers tries to re-enable interrupts from hard-isr | |
264 | * context which is simply wrong | |
265 | */ | |
266 | if (in_irq()) { | |
267 | WARN_ONCE(1, "IRQ enabled from hard-isr"); | |
268 | return; | |
269 | } | |
270 | ||
271 | flags = arch_local_save_flags(); | |
272 | flags |= (STATUS_E1_MASK | STATUS_E2_MASK); | |
273 | arch_local_irq_restore(flags); | |
274 | } | |
4788a594 | 275 | #endif |
ac4c244d | 276 | EXPORT_SYMBOL(arch_local_irq_enable); |